xref: /linux/drivers/i2c/busses/i2c-riic.c (revision d27bb0246e5356dbef4d923e72c680bf893885a8) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Renesas RIIC driver
4  *
5  * Copyright (C) 2013 Wolfram Sang <wsa@sang-engineering.com>
6  * Copyright (C) 2013 Renesas Solutions Corp.
7  */
8 
9 /*
10  * This i2c core has a lot of interrupts, namely 8. We use their chaining as
11  * some kind of state machine.
12  *
13  * 1) The main xfer routine kicks off a transmission by putting the start bit
14  * (or repeated start) on the bus and enabling the transmit interrupt (TIE)
15  * since we need to send the slave address + RW bit in every case.
16  *
17  * 2) TIE sends slave address + RW bit and selects how to continue.
18  *
19  * 3a) Write case: We keep utilizing TIE as long as we have data to send. If we
20  * are done, we switch over to the transmission done interrupt (TEIE) and mark
21  * the message as completed (includes sending STOP) there.
22  *
23  * 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is
24  * needed to start clocking, then we keep receiving until we are done. Note
25  * that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by
26  * writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a
27  * message to create the final NACK as sketched in the datasheet. This caused
28  * some subtle races (when byte n was processed and byte n+1 was already
29  * waiting), though, and I started with the safe approach.
30  *
31  * 4) If we got a NACK somewhere, we flag the error and stop the transmission
32  * via NAKIE.
33  *
34  * Also check the comments in the interrupt routines for some gory details.
35  */
36 
37 #include <linux/clk.h>
38 #include <linux/completion.h>
39 #include <linux/err.h>
40 #include <linux/i2c.h>
41 #include <linux/interrupt.h>
42 #include <linux/io.h>
43 #include <linux/module.h>
44 #include <linux/of.h>
45 #include <linux/platform_device.h>
46 #include <linux/pm_runtime.h>
47 #include <linux/reset.h>
48 
49 #define RIIC_ICCR1	0x00
50 #define RIIC_ICCR2	0x04
51 #define RIIC_ICMR1	0x08
52 #define RIIC_ICMR3	0x10
53 #define RIIC_ICSER	0x18
54 #define RIIC_ICIER	0x1c
55 #define RIIC_ICSR2	0x24
56 #define RIIC_ICBRL	0x34
57 #define RIIC_ICBRH	0x38
58 #define RIIC_ICDRT	0x3c
59 #define RIIC_ICDRR	0x40
60 
61 #define ICCR1_ICE	0x80
62 #define ICCR1_IICRST	0x40
63 #define ICCR1_SOWP	0x10
64 
65 #define ICCR2_BBSY	0x80
66 #define ICCR2_SP	0x08
67 #define ICCR2_RS	0x04
68 #define ICCR2_ST	0x02
69 
70 #define ICMR1_CKS_MASK	0x70
71 #define ICMR1_BCWP	0x08
72 #define ICMR1_CKS(_x)	((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP)
73 
74 #define ICMR3_RDRFS	0x20
75 #define ICMR3_ACKWP	0x10
76 #define ICMR3_ACKBT	0x08
77 
78 #define ICIER_TIE	0x80
79 #define ICIER_TEIE	0x40
80 #define ICIER_RIE	0x20
81 #define ICIER_NAKIE	0x10
82 #define ICIER_SPIE	0x08
83 
84 #define ICSR2_NACKF	0x10
85 
86 #define ICBR_RESERVED	0xe0 /* Should be 1 on writes */
87 
88 #define RIIC_INIT_MSG	-1
89 
90 struct riic_dev {
91 	void __iomem *base;
92 	u8 *buf;
93 	struct i2c_msg *msg;
94 	int bytes_left;
95 	int err;
96 	int is_last;
97 	struct completion msg_done;
98 	struct i2c_adapter adapter;
99 	struct clk *clk;
100 };
101 
102 struct riic_irq_desc {
103 	int res_num;
104 	irq_handler_t isr;
105 	char *name;
106 };
107 
108 static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg)
109 {
110 	writeb((readb(riic->base + reg) & ~clear) | set, riic->base + reg);
111 }
112 
113 static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
114 {
115 	struct riic_dev *riic = i2c_get_adapdata(adap);
116 	unsigned long time_left;
117 	int i;
118 	u8 start_bit;
119 
120 	pm_runtime_get_sync(adap->dev.parent);
121 
122 	if (readb(riic->base + RIIC_ICCR2) & ICCR2_BBSY) {
123 		riic->err = -EBUSY;
124 		goto out;
125 	}
126 
127 	reinit_completion(&riic->msg_done);
128 	riic->err = 0;
129 
130 	writeb(0, riic->base + RIIC_ICSR2);
131 
132 	for (i = 0, start_bit = ICCR2_ST; i < num; i++) {
133 		riic->bytes_left = RIIC_INIT_MSG;
134 		riic->buf = msgs[i].buf;
135 		riic->msg = &msgs[i];
136 		riic->is_last = (i == num - 1);
137 
138 		writeb(ICIER_NAKIE | ICIER_TIE, riic->base + RIIC_ICIER);
139 
140 		writeb(start_bit, riic->base + RIIC_ICCR2);
141 
142 		time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout);
143 		if (time_left == 0)
144 			riic->err = -ETIMEDOUT;
145 
146 		if (riic->err)
147 			break;
148 
149 		start_bit = ICCR2_RS;
150 	}
151 
152  out:
153 	pm_runtime_put(adap->dev.parent);
154 
155 	return riic->err ?: num;
156 }
157 
158 static irqreturn_t riic_tdre_isr(int irq, void *data)
159 {
160 	struct riic_dev *riic = data;
161 	u8 val;
162 
163 	if (!riic->bytes_left)
164 		return IRQ_NONE;
165 
166 	if (riic->bytes_left == RIIC_INIT_MSG) {
167 		if (riic->msg->flags & I2C_M_RD)
168 			/* On read, switch over to receive interrupt */
169 			riic_clear_set_bit(riic, ICIER_TIE, ICIER_RIE, RIIC_ICIER);
170 		else
171 			/* On write, initialize length */
172 			riic->bytes_left = riic->msg->len;
173 
174 		val = i2c_8bit_addr_from_msg(riic->msg);
175 	} else {
176 		val = *riic->buf;
177 		riic->buf++;
178 		riic->bytes_left--;
179 	}
180 
181 	/*
182 	 * Switch to transmission ended interrupt when done. Do check here
183 	 * after bytes_left was initialized to support SMBUS_QUICK (new msg has
184 	 * 0 length then)
185 	 */
186 	if (riic->bytes_left == 0)
187 		riic_clear_set_bit(riic, ICIER_TIE, ICIER_TEIE, RIIC_ICIER);
188 
189 	/*
190 	 * This acks the TIE interrupt. We get another TIE immediately if our
191 	 * value could be moved to the shadow shift register right away. So
192 	 * this must be after updates to ICIER (where we want to disable TIE)!
193 	 */
194 	writeb(val, riic->base + RIIC_ICDRT);
195 
196 	return IRQ_HANDLED;
197 }
198 
199 static irqreturn_t riic_tend_isr(int irq, void *data)
200 {
201 	struct riic_dev *riic = data;
202 
203 	if (readb(riic->base + RIIC_ICSR2) & ICSR2_NACKF) {
204 		/* We got a NACKIE */
205 		readb(riic->base + RIIC_ICDRR);	/* dummy read */
206 		riic_clear_set_bit(riic, ICSR2_NACKF, 0, RIIC_ICSR2);
207 		riic->err = -ENXIO;
208 	} else if (riic->bytes_left) {
209 		return IRQ_NONE;
210 	}
211 
212 	if (riic->is_last || riic->err) {
213 		riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER);
214 		writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
215 	} else {
216 		/* Transfer is complete, but do not send STOP */
217 		riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER);
218 		complete(&riic->msg_done);
219 	}
220 
221 	return IRQ_HANDLED;
222 }
223 
224 static irqreturn_t riic_rdrf_isr(int irq, void *data)
225 {
226 	struct riic_dev *riic = data;
227 
228 	if (!riic->bytes_left)
229 		return IRQ_NONE;
230 
231 	if (riic->bytes_left == RIIC_INIT_MSG) {
232 		riic->bytes_left = riic->msg->len;
233 		readb(riic->base + RIIC_ICDRR);	/* dummy read */
234 		return IRQ_HANDLED;
235 	}
236 
237 	if (riic->bytes_left == 1) {
238 		/* STOP must come before we set ACKBT! */
239 		if (riic->is_last) {
240 			riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER);
241 			writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
242 		}
243 
244 		riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3);
245 
246 	} else {
247 		riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3);
248 	}
249 
250 	/* Reading acks the RIE interrupt */
251 	*riic->buf = readb(riic->base + RIIC_ICDRR);
252 	riic->buf++;
253 	riic->bytes_left--;
254 
255 	return IRQ_HANDLED;
256 }
257 
258 static irqreturn_t riic_stop_isr(int irq, void *data)
259 {
260 	struct riic_dev *riic = data;
261 
262 	/* read back registers to confirm writes have fully propagated */
263 	writeb(0, riic->base + RIIC_ICSR2);
264 	readb(riic->base + RIIC_ICSR2);
265 	writeb(0, riic->base + RIIC_ICIER);
266 	readb(riic->base + RIIC_ICIER);
267 
268 	complete(&riic->msg_done);
269 
270 	return IRQ_HANDLED;
271 }
272 
273 static u32 riic_func(struct i2c_adapter *adap)
274 {
275 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
276 }
277 
278 static const struct i2c_algorithm riic_algo = {
279 	.master_xfer	= riic_xfer,
280 	.functionality	= riic_func,
281 };
282 
283 static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
284 {
285 	int ret = 0;
286 	unsigned long rate;
287 	int total_ticks, cks, brl, brh;
288 
289 	pm_runtime_get_sync(riic->adapter.dev.parent);
290 
291 	if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) {
292 		dev_err(&riic->adapter.dev,
293 			"unsupported bus speed (%dHz). %d max\n",
294 			t->bus_freq_hz, I2C_MAX_FAST_MODE_FREQ);
295 		ret = -EINVAL;
296 		goto out;
297 	}
298 
299 	rate = clk_get_rate(riic->clk);
300 
301 	/*
302 	 * Assume the default register settings:
303 	 *  FER.SCLE = 1 (SCL sync circuit enabled, adds 2 or 3 cycles)
304 	 *  FER.NFE = 1 (noise circuit enabled)
305 	 *  MR3.NF = 0 (1 cycle of noise filtered out)
306 	 *
307 	 * Freq (CKS=000) = (I2CCLK + tr + tf)/ (BRH + 3 + 1) + (BRL + 3 + 1)
308 	 * Freq (CKS!=000) = (I2CCLK + tr + tf)/ (BRH + 2 + 1) + (BRL + 2 + 1)
309 	 */
310 
311 	/*
312 	 * Determine reference clock rate. We must be able to get the desired
313 	 * frequency with only 62 clock ticks max (31 high, 31 low).
314 	 * Aim for a duty of 60% LOW, 40% HIGH.
315 	 */
316 	total_ticks = DIV_ROUND_UP(rate, t->bus_freq_hz);
317 
318 	for (cks = 0; cks < 7; cks++) {
319 		/*
320 		 * 60% low time must be less than BRL + 2 + 1
321 		 * BRL max register value is 0x1F.
322 		 */
323 		brl = ((total_ticks * 6) / 10);
324 		if (brl <= (0x1F + 3))
325 			break;
326 
327 		total_ticks /= 2;
328 		rate /= 2;
329 	}
330 
331 	if (brl > (0x1F + 3)) {
332 		dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n",
333 			(unsigned long)t->bus_freq_hz);
334 		ret = -EINVAL;
335 		goto out;
336 	}
337 
338 	brh = total_ticks - brl;
339 
340 	/* Remove automatic clock ticks for sync circuit and NF */
341 	if (cks == 0) {
342 		brl -= 4;
343 		brh -= 4;
344 	} else {
345 		brl -= 3;
346 		brh -= 3;
347 	}
348 
349 	/*
350 	 * Remove clock ticks for rise and fall times. Convert ns to clock
351 	 * ticks.
352 	 */
353 	brl -= t->scl_fall_ns / (1000000000 / rate);
354 	brh -= t->scl_rise_ns / (1000000000 / rate);
355 
356 	/* Adjust for min register values for when SCLE=1 and NFE=1 */
357 	if (brl < 1)
358 		brl = 1;
359 	if (brh < 1)
360 		brh = 1;
361 
362 	pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n",
363 		 rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6),
364 		 t->scl_fall_ns / (1000000000 / rate),
365 		 t->scl_rise_ns / (1000000000 / rate), cks, brl, brh);
366 
367 	/* Changing the order of accessing IICRST and ICE may break things! */
368 	writeb(ICCR1_IICRST | ICCR1_SOWP, riic->base + RIIC_ICCR1);
369 	riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1);
370 
371 	writeb(ICMR1_CKS(cks), riic->base + RIIC_ICMR1);
372 	writeb(brh | ICBR_RESERVED, riic->base + RIIC_ICBRH);
373 	writeb(brl | ICBR_RESERVED, riic->base + RIIC_ICBRL);
374 
375 	writeb(0, riic->base + RIIC_ICSER);
376 	writeb(ICMR3_ACKWP | ICMR3_RDRFS, riic->base + RIIC_ICMR3);
377 
378 	riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);
379 
380 out:
381 	pm_runtime_put(riic->adapter.dev.parent);
382 	return ret;
383 }
384 
385 static struct riic_irq_desc riic_irqs[] = {
386 	{ .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" },
387 	{ .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" },
388 	{ .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" },
389 	{ .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" },
390 	{ .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },
391 };
392 
393 static void riic_reset_control_assert(void *data)
394 {
395 	reset_control_assert(data);
396 }
397 
398 static int riic_i2c_probe(struct platform_device *pdev)
399 {
400 	struct riic_dev *riic;
401 	struct i2c_adapter *adap;
402 	struct i2c_timings i2c_t;
403 	struct reset_control *rstc;
404 	int i, ret;
405 
406 	riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL);
407 	if (!riic)
408 		return -ENOMEM;
409 
410 	riic->base = devm_platform_ioremap_resource(pdev, 0);
411 	if (IS_ERR(riic->base))
412 		return PTR_ERR(riic->base);
413 
414 	riic->clk = devm_clk_get(&pdev->dev, NULL);
415 	if (IS_ERR(riic->clk)) {
416 		dev_err(&pdev->dev, "missing controller clock");
417 		return PTR_ERR(riic->clk);
418 	}
419 
420 	rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
421 	if (IS_ERR(rstc))
422 		return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
423 				     "Error: missing reset ctrl\n");
424 
425 	ret = reset_control_deassert(rstc);
426 	if (ret)
427 		return ret;
428 
429 	ret = devm_add_action_or_reset(&pdev->dev, riic_reset_control_assert, rstc);
430 	if (ret)
431 		return ret;
432 
433 	for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) {
434 		ret = platform_get_irq(pdev, riic_irqs[i].res_num);
435 		if (ret < 0)
436 			return ret;
437 
438 		ret = devm_request_irq(&pdev->dev, ret, riic_irqs[i].isr,
439 				       0, riic_irqs[i].name, riic);
440 		if (ret) {
441 			dev_err(&pdev->dev, "failed to request irq %s\n", riic_irqs[i].name);
442 			return ret;
443 		}
444 	}
445 
446 	adap = &riic->adapter;
447 	i2c_set_adapdata(adap, riic);
448 	strscpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
449 	adap->owner = THIS_MODULE;
450 	adap->algo = &riic_algo;
451 	adap->dev.parent = &pdev->dev;
452 	adap->dev.of_node = pdev->dev.of_node;
453 
454 	init_completion(&riic->msg_done);
455 
456 	i2c_parse_fw_timings(&pdev->dev, &i2c_t, true);
457 
458 	pm_runtime_enable(&pdev->dev);
459 
460 	ret = riic_init_hw(riic, &i2c_t);
461 	if (ret)
462 		goto out;
463 
464 	ret = i2c_add_adapter(adap);
465 	if (ret)
466 		goto out;
467 
468 	platform_set_drvdata(pdev, riic);
469 
470 	dev_info(&pdev->dev, "registered with %dHz bus speed\n",
471 		 i2c_t.bus_freq_hz);
472 	return 0;
473 
474 out:
475 	pm_runtime_disable(&pdev->dev);
476 	return ret;
477 }
478 
479 static void riic_i2c_remove(struct platform_device *pdev)
480 {
481 	struct riic_dev *riic = platform_get_drvdata(pdev);
482 
483 	pm_runtime_get_sync(&pdev->dev);
484 	writeb(0, riic->base + RIIC_ICIER);
485 	pm_runtime_put(&pdev->dev);
486 	i2c_del_adapter(&riic->adapter);
487 	pm_runtime_disable(&pdev->dev);
488 }
489 
490 static const struct of_device_id riic_i2c_dt_ids[] = {
491 	{ .compatible = "renesas,riic-rz", },
492 	{ /* Sentinel */ },
493 };
494 
495 static struct platform_driver riic_i2c_driver = {
496 	.probe		= riic_i2c_probe,
497 	.remove_new	= riic_i2c_remove,
498 	.driver		= {
499 		.name	= "i2c-riic",
500 		.of_match_table = riic_i2c_dt_ids,
501 	},
502 };
503 
504 module_platform_driver(riic_i2c_driver);
505 
506 MODULE_DESCRIPTION("Renesas RIIC adapter");
507 MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
508 MODULE_LICENSE("GPL v2");
509 MODULE_DEVICE_TABLE(of, riic_i2c_dt_ids);
510