1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RIIC driver 4 * 5 * Copyright (C) 2013 Wolfram Sang <wsa@sang-engineering.com> 6 * Copyright (C) 2013 Renesas Solutions Corp. 7 */ 8 9 /* 10 * This i2c core has a lot of interrupts, namely 8. We use their chaining as 11 * some kind of state machine. 12 * 13 * 1) The main xfer routine kicks off a transmission by putting the start bit 14 * (or repeated start) on the bus and enabling the transmit interrupt (TIE) 15 * since we need to send the target address + RW bit in every case. 16 * 17 * 2) TIE sends target address + RW bit and selects how to continue. 18 * 19 * 3a) Write case: We keep utilizing TIE as long as we have data to send. If we 20 * are done, we switch over to the transmission done interrupt (TEIE) and mark 21 * the message as completed (includes sending STOP) there. 22 * 23 * 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is 24 * needed to start clocking, then we keep receiving until we are done. Note 25 * that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by 26 * writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a 27 * message to create the final NACK as sketched in the datasheet. This caused 28 * some subtle races (when byte n was processed and byte n+1 was already 29 * waiting), though, and I started with the safe approach. 30 * 31 * 4) If we got a NACK somewhere, we flag the error and stop the transmission 32 * via NAKIE. 33 * 34 * Also check the comments in the interrupt routines for some gory details. 35 */ 36 37 #include <linux/bits.h> 38 #include <linux/clk.h> 39 #include <linux/completion.h> 40 #include <linux/err.h> 41 #include <linux/i2c.h> 42 #include <linux/interrupt.h> 43 #include <linux/io.h> 44 #include <linux/iopoll.h> 45 #include <linux/module.h> 46 #include <linux/of.h> 47 #include <linux/platform_device.h> 48 #include <linux/pm_runtime.h> 49 #include <linux/reset.h> 50 #include <linux/time.h> 51 52 #define ICCR1_ICE BIT(7) 53 #define ICCR1_IICRST BIT(6) 54 #define ICCR1_SOWP BIT(4) 55 #define ICCR1_SCLO BIT(3) 56 #define ICCR1_SDAO BIT(2) 57 #define ICCR1_SCLI BIT(1) 58 #define ICCR1_SDAI BIT(0) 59 60 #define ICCR2_BBSY BIT(7) 61 #define ICCR2_SP BIT(3) 62 #define ICCR2_RS BIT(2) 63 #define ICCR2_ST BIT(1) 64 65 #define ICMR1_CKS_MASK GENMASK(6, 4) 66 #define ICMR1_BCWP BIT(3) 67 #define ICMR1_CKS(_x) ((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP) 68 69 #define ICMR3_RDRFS BIT(5) 70 #define ICMR3_ACKWP BIT(4) 71 #define ICMR3_ACKBT BIT(3) 72 73 #define ICFER_FMPE BIT(7) 74 75 #define ICIER_TIE BIT(7) 76 #define ICIER_TEIE BIT(6) 77 #define ICIER_RIE BIT(5) 78 #define ICIER_NAKIE BIT(4) 79 #define ICIER_SPIE BIT(3) 80 81 #define ICSR2_NACKF BIT(4) 82 #define ICSR2_STOP BIT(3) 83 84 #define ICBR_RESERVED GENMASK(7, 5) /* Should be 1 on writes */ 85 86 #define RIIC_INIT_MSG -1 87 88 enum riic_reg_list { 89 RIIC_ICCR1 = 0, 90 RIIC_ICCR2, 91 RIIC_ICMR1, 92 RIIC_ICMR3, 93 RIIC_ICFER, 94 RIIC_ICSER, 95 RIIC_ICIER, 96 RIIC_ICSR2, 97 RIIC_ICBRL, 98 RIIC_ICBRH, 99 RIIC_ICDRT, 100 RIIC_ICDRR, 101 RIIC_REG_END, 102 }; 103 104 struct riic_of_data { 105 const u8 *regs; 106 const struct riic_irq_desc *irqs; 107 u8 num_irqs; 108 bool fast_mode_plus; 109 }; 110 111 struct riic_dev { 112 void __iomem *base; 113 u8 *buf; 114 struct i2c_msg *msg; 115 int bytes_left; 116 int err; 117 int is_last; 118 const struct riic_of_data *info; 119 struct completion msg_done; 120 struct i2c_adapter adapter; 121 struct clk *clk; 122 struct reset_control *rstc; 123 struct i2c_timings i2c_t; 124 }; 125 126 struct riic_irq_desc { 127 int res_num; 128 irq_handler_t isr; 129 char *name; 130 }; 131 132 static inline void riic_writeb(struct riic_dev *riic, u8 val, u8 offset) 133 { 134 writeb(val, riic->base + riic->info->regs[offset]); 135 } 136 137 static inline u8 riic_readb(struct riic_dev *riic, u8 offset) 138 { 139 return readb(riic->base + riic->info->regs[offset]); 140 } 141 142 static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg) 143 { 144 riic_writeb(riic, (riic_readb(riic, reg) & ~clear) | set, reg); 145 } 146 147 static int riic_bus_barrier(struct riic_dev *riic) 148 { 149 int ret; 150 u8 val; 151 152 /* 153 * The SDA line can still be low even when BBSY = 0. Therefore, after checking 154 * the BBSY flag, also verify that the SDA and SCL lines are not being held low. 155 */ 156 ret = readb_poll_timeout(riic->base + riic->info->regs[RIIC_ICCR2], val, 157 !(val & ICCR2_BBSY), 10, riic->adapter.timeout); 158 if (ret) 159 return i2c_recover_bus(&riic->adapter); 160 161 if ((riic_readb(riic, RIIC_ICCR1) & (ICCR1_SDAI | ICCR1_SCLI)) != 162 (ICCR1_SDAI | ICCR1_SCLI)) 163 return i2c_recover_bus(&riic->adapter); 164 165 return 0; 166 } 167 168 static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 169 { 170 struct riic_dev *riic = i2c_get_adapdata(adap); 171 struct device *dev = adap->dev.parent; 172 unsigned long time_left; 173 int i, ret; 174 u8 start_bit; 175 176 ret = pm_runtime_resume_and_get(dev); 177 if (ret) 178 return ret; 179 180 riic->err = riic_bus_barrier(riic); 181 if (riic->err) 182 goto out; 183 184 reinit_completion(&riic->msg_done); 185 186 riic_writeb(riic, 0, RIIC_ICSR2); 187 188 for (i = 0, start_bit = ICCR2_ST; i < num; i++) { 189 riic->bytes_left = RIIC_INIT_MSG; 190 riic->buf = msgs[i].buf; 191 riic->msg = &msgs[i]; 192 riic->is_last = (i == num - 1); 193 194 riic_writeb(riic, ICIER_NAKIE | ICIER_TIE, RIIC_ICIER); 195 196 riic_writeb(riic, start_bit, RIIC_ICCR2); 197 198 time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout); 199 if (time_left == 0) 200 riic->err = -ETIMEDOUT; 201 202 if (riic->err) 203 break; 204 205 start_bit = ICCR2_RS; 206 } 207 208 out: 209 pm_runtime_put_autosuspend(dev); 210 211 return riic->err ?: num; 212 } 213 214 static irqreturn_t riic_tdre_isr(int irq, void *data) 215 { 216 struct riic_dev *riic = data; 217 u8 val; 218 219 if (!riic->bytes_left) 220 return IRQ_NONE; 221 222 if (riic->bytes_left == RIIC_INIT_MSG) { 223 if (riic->msg->flags & I2C_M_RD) 224 /* On read, switch over to receive interrupt */ 225 riic_clear_set_bit(riic, ICIER_TIE, ICIER_RIE, RIIC_ICIER); 226 else 227 /* On write, initialize length */ 228 riic->bytes_left = riic->msg->len; 229 230 val = i2c_8bit_addr_from_msg(riic->msg); 231 } else { 232 val = *riic->buf; 233 riic->buf++; 234 riic->bytes_left--; 235 } 236 237 /* 238 * Switch to transmission ended interrupt when done. Do check here 239 * after bytes_left was initialized to support SMBUS_QUICK (new msg has 240 * 0 length then) 241 */ 242 if (riic->bytes_left == 0) 243 riic_clear_set_bit(riic, ICIER_TIE, ICIER_TEIE, RIIC_ICIER); 244 245 /* 246 * This acks the TIE interrupt. We get another TIE immediately if our 247 * value could be moved to the shadow shift register right away. So 248 * this must be after updates to ICIER (where we want to disable TIE)! 249 */ 250 riic_writeb(riic, val, RIIC_ICDRT); 251 252 return IRQ_HANDLED; 253 } 254 255 static irqreturn_t riic_tend_isr(int irq, void *data) 256 { 257 struct riic_dev *riic = data; 258 259 if (riic_readb(riic, RIIC_ICSR2) & ICSR2_NACKF) { 260 /* We got a NACKIE */ 261 riic_readb(riic, RIIC_ICDRR); /* dummy read */ 262 riic_clear_set_bit(riic, ICSR2_NACKF, 0, RIIC_ICSR2); 263 riic->err = -ENXIO; 264 } else if (riic->bytes_left) { 265 return IRQ_NONE; 266 } 267 268 if (riic->is_last || riic->err) { 269 riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER); 270 riic_writeb(riic, ICCR2_SP, RIIC_ICCR2); 271 } else { 272 /* Transfer is complete, but do not send STOP */ 273 riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER); 274 complete(&riic->msg_done); 275 } 276 277 return IRQ_HANDLED; 278 } 279 280 static irqreturn_t riic_rdrf_isr(int irq, void *data) 281 { 282 struct riic_dev *riic = data; 283 284 if (!riic->bytes_left) 285 return IRQ_NONE; 286 287 if (riic->bytes_left == RIIC_INIT_MSG) { 288 riic->bytes_left = riic->msg->len; 289 riic_readb(riic, RIIC_ICDRR); /* dummy read */ 290 return IRQ_HANDLED; 291 } 292 293 if (riic->bytes_left == 1) { 294 /* STOP must come before we set ACKBT! */ 295 if (riic->is_last) { 296 riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER); 297 riic_writeb(riic, ICCR2_SP, RIIC_ICCR2); 298 } 299 300 riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3); 301 302 } else { 303 riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3); 304 } 305 306 /* Reading acks the RIE interrupt */ 307 *riic->buf = riic_readb(riic, RIIC_ICDRR); 308 riic->buf++; 309 riic->bytes_left--; 310 311 return IRQ_HANDLED; 312 } 313 314 static irqreturn_t riic_stop_isr(int irq, void *data) 315 { 316 struct riic_dev *riic = data; 317 318 /* read back registers to confirm writes have fully propagated */ 319 riic_writeb(riic, 0, RIIC_ICSR2); 320 riic_readb(riic, RIIC_ICSR2); 321 riic_writeb(riic, 0, RIIC_ICIER); 322 riic_readb(riic, RIIC_ICIER); 323 324 complete(&riic->msg_done); 325 326 return IRQ_HANDLED; 327 } 328 329 static irqreturn_t riic_eei_isr(int irq, void *data) 330 { 331 u8 icsr2 = riic_readb(data, RIIC_ICSR2); 332 333 if (icsr2 & ICSR2_NACKF) 334 return riic_tend_isr(irq, data); 335 336 if (icsr2 & ICSR2_STOP) 337 return riic_stop_isr(irq, data); 338 339 return IRQ_NONE; 340 } 341 342 static u32 riic_func(struct i2c_adapter *adap) 343 { 344 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 345 } 346 347 static const struct i2c_algorithm riic_algo = { 348 .xfer = riic_xfer, 349 .functionality = riic_func, 350 }; 351 352 static int riic_init_hw(struct riic_dev *riic) 353 { 354 int ret; 355 unsigned long rate; 356 unsigned long ns_per_tick; 357 int total_ticks, cks, brl, brh; 358 struct i2c_timings *t = &riic->i2c_t; 359 struct device *dev = riic->adapter.dev.parent; 360 bool fast_mode_plus = riic->info->fast_mode_plus; 361 u32 max_freq = fast_mode_plus ? I2C_MAX_FAST_MODE_PLUS_FREQ 362 : I2C_MAX_FAST_MODE_FREQ; 363 364 if (t->bus_freq_hz > max_freq) 365 return dev_err_probe(dev, -EINVAL, 366 "unsupported bus speed %uHz (%u max)\n", 367 t->bus_freq_hz, max_freq); 368 369 rate = clk_get_rate(riic->clk); 370 371 /* 372 * Assume the default register settings: 373 * FER.SCLE = 1 (SCL sync circuit enabled, adds 2 or 3 cycles) 374 * FER.NFE = 1 (noise circuit enabled) 375 * MR3.NF = 0 (1 cycle of noise filtered out) 376 * 377 * Freq (CKS=000) = (I2CCLK + tr + tf)/ (BRH + 3 + 1) + (BRL + 3 + 1) 378 * Freq (CKS!=000) = (I2CCLK + tr + tf)/ (BRH + 2 + 1) + (BRL + 2 + 1) 379 */ 380 381 /* 382 * Determine reference clock rate. We must be able to get the desired 383 * frequency with only 62 clock ticks max (31 high, 31 low). 384 * Aim for a duty of 60% LOW, 40% HIGH. 385 */ 386 total_ticks = DIV_ROUND_UP(rate, t->bus_freq_hz ?: 1); 387 388 for (cks = 0; cks <= 7; cks++) { 389 /* 390 * 60% low time must be less than BRL + 2 + 1 391 * BRL max register value is 0x1F. 392 */ 393 brl = ((total_ticks * 6) / 10); 394 if (brl <= (0x1F + 3)) 395 break; 396 397 total_ticks = DIV_ROUND_UP(total_ticks, 2); 398 rate /= 2; 399 } 400 401 if (brl > (0x1F + 3)) 402 return dev_err_probe(dev, -EINVAL, "invalid speed (%uHz). Too slow.\n", 403 t->bus_freq_hz); 404 405 brh = total_ticks - brl; 406 407 /* Remove automatic clock ticks for sync circuit and NF */ 408 if (cks == 0) { 409 brl -= 4; 410 brh -= 4; 411 } else { 412 brl -= 3; 413 brh -= 3; 414 } 415 416 /* 417 * Remove clock ticks for rise and fall times. Convert ns to clock 418 * ticks. 419 */ 420 ns_per_tick = NSEC_PER_SEC / rate; 421 brl -= t->scl_fall_ns / ns_per_tick; 422 brh -= t->scl_rise_ns / ns_per_tick; 423 424 /* Adjust for min register values for when SCLE=1 and NFE=1 */ 425 if (brl < 1) 426 brl = 1; 427 if (brh < 1) 428 brh = 1; 429 430 pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n", 431 rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6), 432 t->scl_fall_ns / ns_per_tick, t->scl_rise_ns / ns_per_tick, cks, brl, brh); 433 434 ret = pm_runtime_resume_and_get(dev); 435 if (ret) 436 return ret; 437 438 /* Changing the order of accessing IICRST and ICE may break things! */ 439 riic_writeb(riic, ICCR1_IICRST | ICCR1_SOWP, RIIC_ICCR1); 440 riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1); 441 442 riic_writeb(riic, ICMR1_CKS(cks), RIIC_ICMR1); 443 riic_writeb(riic, brh | ICBR_RESERVED, RIIC_ICBRH); 444 riic_writeb(riic, brl | ICBR_RESERVED, RIIC_ICBRL); 445 446 riic_writeb(riic, 0, RIIC_ICSER); 447 riic_writeb(riic, ICMR3_ACKWP | ICMR3_RDRFS, RIIC_ICMR3); 448 449 if (fast_mode_plus && t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) 450 riic_clear_set_bit(riic, 0, ICFER_FMPE, RIIC_ICFER); 451 452 riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1); 453 454 pm_runtime_put_autosuspend(dev); 455 return 0; 456 } 457 458 static int riic_get_scl(struct i2c_adapter *adap) 459 { 460 struct riic_dev *riic = i2c_get_adapdata(adap); 461 462 return !!(riic_readb(riic, RIIC_ICCR1) & ICCR1_SCLI); 463 } 464 465 static int riic_get_sda(struct i2c_adapter *adap) 466 { 467 struct riic_dev *riic = i2c_get_adapdata(adap); 468 469 return !!(riic_readb(riic, RIIC_ICCR1) & ICCR1_SDAI); 470 } 471 472 static void riic_set_scl(struct i2c_adapter *adap, int val) 473 { 474 struct riic_dev *riic = i2c_get_adapdata(adap); 475 476 if (val) 477 riic_clear_set_bit(riic, ICCR1_SOWP, ICCR1_SCLO, RIIC_ICCR1); 478 else 479 riic_clear_set_bit(riic, ICCR1_SOWP | ICCR1_SCLO, 0, RIIC_ICCR1); 480 481 riic_clear_set_bit(riic, 0, ICCR1_SOWP, RIIC_ICCR1); 482 } 483 484 static void riic_set_sda(struct i2c_adapter *adap, int val) 485 { 486 struct riic_dev *riic = i2c_get_adapdata(adap); 487 488 if (val) 489 riic_clear_set_bit(riic, ICCR1_SOWP, ICCR1_SDAO, RIIC_ICCR1); 490 else 491 riic_clear_set_bit(riic, ICCR1_SOWP | ICCR1_SDAO, 0, RIIC_ICCR1); 492 493 riic_clear_set_bit(riic, 0, ICCR1_SOWP, RIIC_ICCR1); 494 } 495 496 static struct i2c_bus_recovery_info riic_bri = { 497 .recover_bus = i2c_generic_scl_recovery, 498 .get_scl = riic_get_scl, 499 .set_scl = riic_set_scl, 500 .get_sda = riic_get_sda, 501 .set_sda = riic_set_sda, 502 }; 503 504 static const struct riic_irq_desc riic_irqs[] = { 505 { .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" }, 506 { .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" }, 507 { .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" }, 508 { .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" }, 509 { .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" }, 510 }; 511 512 static const struct riic_irq_desc riic_rzt2h_irqs[] = { 513 { .res_num = 0, .isr = riic_eei_isr, .name = "riic-eei" }, 514 { .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rxi" }, 515 { .res_num = 2, .isr = riic_tdre_isr, .name = "riic-txi" }, 516 { .res_num = 3, .isr = riic_tend_isr, .name = "riic-tei" }, 517 }; 518 519 static int riic_i2c_probe(struct platform_device *pdev) 520 { 521 struct device *dev = &pdev->dev; 522 struct riic_dev *riic; 523 struct i2c_adapter *adap; 524 int i, ret; 525 526 riic = devm_kzalloc(dev, sizeof(*riic), GFP_KERNEL); 527 if (!riic) 528 return -ENOMEM; 529 530 riic->base = devm_platform_ioremap_resource(pdev, 0); 531 if (IS_ERR(riic->base)) 532 return PTR_ERR(riic->base); 533 534 riic->clk = devm_clk_get(dev, NULL); 535 if (IS_ERR(riic->clk)) 536 return dev_err_probe(dev, PTR_ERR(riic->clk), 537 "missing controller clock"); 538 539 riic->rstc = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL); 540 if (IS_ERR(riic->rstc)) 541 return dev_err_probe(dev, PTR_ERR(riic->rstc), 542 "failed to acquire deasserted reset\n"); 543 544 riic->info = of_device_get_match_data(dev); 545 546 for (i = 0; i < riic->info->num_irqs; i++) { 547 const struct riic_irq_desc *irq_desc; 548 int irq; 549 550 irq_desc = &riic->info->irqs[i]; 551 irq = platform_get_irq(pdev, irq_desc->res_num); 552 if (irq < 0) 553 return irq; 554 555 ret = devm_request_irq(dev, irq, irq_desc->isr, 0, irq_desc->name, riic); 556 if (ret) 557 return dev_err_probe(dev, ret, "failed to request irq %s\n", 558 irq_desc->name); 559 } 560 561 562 adap = &riic->adapter; 563 i2c_set_adapdata(adap, riic); 564 strscpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name)); 565 adap->owner = THIS_MODULE; 566 adap->algo = &riic_algo; 567 adap->dev.parent = dev; 568 adap->dev.of_node = dev->of_node; 569 adap->bus_recovery_info = &riic_bri; 570 571 init_completion(&riic->msg_done); 572 573 i2c_parse_fw_timings(dev, &riic->i2c_t, true); 574 575 /* Default 0 to save power. Can be overridden via sysfs for lower latency. */ 576 pm_runtime_set_autosuspend_delay(dev, 0); 577 pm_runtime_use_autosuspend(dev); 578 pm_runtime_enable(dev); 579 580 ret = riic_init_hw(riic); 581 if (ret) 582 goto out; 583 584 ret = i2c_add_adapter(adap); 585 if (ret) 586 goto out; 587 588 platform_set_drvdata(pdev, riic); 589 590 dev_info(dev, "registered with %dHz bus speed\n", riic->i2c_t.bus_freq_hz); 591 return 0; 592 593 out: 594 pm_runtime_disable(dev); 595 pm_runtime_dont_use_autosuspend(dev); 596 return ret; 597 } 598 599 static void riic_i2c_remove(struct platform_device *pdev) 600 { 601 struct riic_dev *riic = platform_get_drvdata(pdev); 602 struct device *dev = &pdev->dev; 603 int ret; 604 605 ret = pm_runtime_resume_and_get(dev); 606 if (!ret) { 607 riic_writeb(riic, 0, RIIC_ICIER); 608 pm_runtime_put(dev); 609 } 610 i2c_del_adapter(&riic->adapter); 611 pm_runtime_disable(dev); 612 pm_runtime_dont_use_autosuspend(dev); 613 } 614 615 static const u8 riic_rz_a_regs[RIIC_REG_END] = { 616 [RIIC_ICCR1] = 0x00, 617 [RIIC_ICCR2] = 0x04, 618 [RIIC_ICMR1] = 0x08, 619 [RIIC_ICMR3] = 0x10, 620 [RIIC_ICFER] = 0x14, 621 [RIIC_ICSER] = 0x18, 622 [RIIC_ICIER] = 0x1c, 623 [RIIC_ICSR2] = 0x24, 624 [RIIC_ICBRL] = 0x34, 625 [RIIC_ICBRH] = 0x38, 626 [RIIC_ICDRT] = 0x3c, 627 [RIIC_ICDRR] = 0x40, 628 }; 629 630 static const struct riic_of_data riic_rz_a_info = { 631 .regs = riic_rz_a_regs, 632 .irqs = riic_irqs, 633 .num_irqs = ARRAY_SIZE(riic_irqs), 634 .fast_mode_plus = true, 635 }; 636 637 static const struct riic_of_data riic_rz_a1h_info = { 638 .regs = riic_rz_a_regs, 639 .irqs = riic_irqs, 640 .num_irqs = ARRAY_SIZE(riic_irqs), 641 }; 642 643 static const u8 riic_rz_v2h_regs[RIIC_REG_END] = { 644 [RIIC_ICCR1] = 0x00, 645 [RIIC_ICCR2] = 0x01, 646 [RIIC_ICMR1] = 0x02, 647 [RIIC_ICMR3] = 0x04, 648 [RIIC_ICFER] = 0x05, 649 [RIIC_ICSER] = 0x06, 650 [RIIC_ICIER] = 0x07, 651 [RIIC_ICSR2] = 0x09, 652 [RIIC_ICBRL] = 0x10, 653 [RIIC_ICBRH] = 0x11, 654 [RIIC_ICDRT] = 0x12, 655 [RIIC_ICDRR] = 0x13, 656 }; 657 658 static const struct riic_of_data riic_rz_v2h_info = { 659 .regs = riic_rz_v2h_regs, 660 .irqs = riic_irqs, 661 .num_irqs = ARRAY_SIZE(riic_irqs), 662 .fast_mode_plus = true, 663 }; 664 665 static const struct riic_of_data riic_rz_t2h_info = { 666 .regs = riic_rz_v2h_regs, 667 .irqs = riic_rzt2h_irqs, 668 .num_irqs = ARRAY_SIZE(riic_rzt2h_irqs), 669 }; 670 671 static int riic_i2c_suspend(struct device *dev) 672 { 673 struct riic_dev *riic = dev_get_drvdata(dev); 674 int ret; 675 676 ret = pm_runtime_resume_and_get(dev); 677 if (ret) 678 return ret; 679 680 i2c_mark_adapter_suspended(&riic->adapter); 681 682 /* Disable output on SDA, SCL pins. */ 683 riic_clear_set_bit(riic, ICCR1_ICE, 0, RIIC_ICCR1); 684 685 pm_runtime_mark_last_busy(dev); 686 pm_runtime_put_sync(dev); 687 688 return reset_control_assert(riic->rstc); 689 } 690 691 static int riic_i2c_resume(struct device *dev) 692 { 693 struct riic_dev *riic = dev_get_drvdata(dev); 694 int ret; 695 696 ret = reset_control_deassert(riic->rstc); 697 if (ret) 698 return ret; 699 700 ret = riic_init_hw(riic); 701 if (ret) { 702 /* 703 * In case this happens there is no way to recover from this 704 * state. The driver will remain loaded. We want to avoid 705 * keeping the reset line de-asserted for no reason. 706 */ 707 reset_control_assert(riic->rstc); 708 return ret; 709 } 710 711 i2c_mark_adapter_resumed(&riic->adapter); 712 713 return 0; 714 } 715 716 static const struct dev_pm_ops riic_i2c_pm_ops = { 717 SYSTEM_SLEEP_PM_OPS(riic_i2c_suspend, riic_i2c_resume) 718 }; 719 720 static const struct of_device_id riic_i2c_dt_ids[] = { 721 { .compatible = "renesas,riic-r7s72100", .data = &riic_rz_a1h_info, }, 722 { .compatible = "renesas,riic-r9a09g057", .data = &riic_rz_v2h_info }, 723 { .compatible = "renesas,riic-r9a09g077", .data = &riic_rz_t2h_info }, 724 { .compatible = "renesas,riic-rz", .data = &riic_rz_a_info }, 725 { /* Sentinel */ } 726 }; 727 728 static struct platform_driver riic_i2c_driver = { 729 .probe = riic_i2c_probe, 730 .remove = riic_i2c_remove, 731 .driver = { 732 .name = "i2c-riic", 733 .of_match_table = riic_i2c_dt_ids, 734 .pm = pm_ptr(&riic_i2c_pm_ops), 735 }, 736 }; 737 738 module_platform_driver(riic_i2c_driver); 739 740 MODULE_DESCRIPTION("Renesas RIIC adapter"); 741 MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>"); 742 MODULE_LICENSE("GPL v2"); 743 MODULE_DEVICE_TABLE(of, riic_i2c_dt_ids); 744