1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Renesas R-Car I2C unit 4 * 5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com> 6 * Copyright (C) 2011-2019 Renesas Electronics Corporation 7 * 8 * Copyright (C) 2012-14 Renesas Solutions Corp. 9 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 10 * 11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c 12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> 13 */ 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dmaengine.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/i2c.h> 24 #include <linux/i2c-smbus.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/of.h> 28 #include <linux/platform_device.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/reset.h> 31 #include <linux/slab.h> 32 33 /* register offsets */ 34 #define ICSCR 0x00 /* slave ctrl */ 35 #define ICMCR 0x04 /* master ctrl */ 36 #define ICSSR 0x08 /* slave status */ 37 #define ICMSR 0x0C /* master status */ 38 #define ICSIER 0x10 /* slave irq enable */ 39 #define ICMIER 0x14 /* master irq enable */ 40 #define ICCCR 0x18 /* clock dividers */ 41 #define ICSAR 0x1C /* slave address */ 42 #define ICMAR 0x20 /* master address */ 43 #define ICRXTX 0x24 /* data port */ 44 #define ICCCR2 0x28 /* Clock control 2 */ 45 #define ICMPR 0x2C /* SCL mask control */ 46 #define ICHPR 0x30 /* SCL HIGH control */ 47 #define ICLPR 0x34 /* SCL LOW control */ 48 #define ICFBSCR 0x38 /* first bit setup cycle (Gen3) */ 49 #define ICDMAER 0x3c /* DMA enable (Gen3) */ 50 51 /* ICSCR */ 52 #define SDBS BIT(3) /* slave data buffer select */ 53 #define SIE BIT(2) /* slave interface enable */ 54 #define GCAE BIT(1) /* general call address enable */ 55 #define FNA BIT(0) /* forced non acknowledgment */ 56 57 /* ICMCR */ 58 #define MDBS BIT(7) /* non-fifo mode switch */ 59 #define FSCL BIT(6) /* override SCL pin */ 60 #define FSDA BIT(5) /* override SDA pin */ 61 #define OBPC BIT(4) /* override pins */ 62 #define MIE BIT(3) /* master if enable */ 63 #define TSBE BIT(2) 64 #define FSB BIT(1) /* force stop bit */ 65 #define ESG BIT(0) /* enable start bit gen */ 66 67 /* ICSSR (also for ICSIER) */ 68 #define GCAR BIT(6) /* general call received */ 69 #define STM BIT(5) /* slave transmit mode */ 70 #define SSR BIT(4) /* stop received */ 71 #define SDE BIT(3) /* slave data empty */ 72 #define SDT BIT(2) /* slave data transmitted */ 73 #define SDR BIT(1) /* slave data received */ 74 #define SAR BIT(0) /* slave addr received */ 75 76 /* ICMSR (also for ICMIE) */ 77 #define MNR BIT(6) /* nack received */ 78 #define MAL BIT(5) /* arbitration lost */ 79 #define MST BIT(4) /* sent a stop */ 80 #define MDE BIT(3) 81 #define MDT BIT(2) 82 #define MDR BIT(1) 83 #define MAT BIT(0) /* slave addr xfer done */ 84 85 /* ICDMAER */ 86 #define RSDMAE BIT(3) /* DMA Slave Received Enable */ 87 #define TSDMAE BIT(2) /* DMA Slave Transmitted Enable */ 88 #define RMDMAE BIT(1) /* DMA Master Received Enable */ 89 #define TMDMAE BIT(0) /* DMA Master Transmitted Enable */ 90 91 /* ICCCR2 */ 92 #define FMPE BIT(7) /* Fast Mode Plus Enable */ 93 #define CDFD BIT(2) /* CDF Disable */ 94 #define HLSE BIT(1) /* HIGH/LOW Separate Control Enable */ 95 #define SME BIT(0) /* SCL Mask Enable */ 96 97 /* ICFBSCR */ 98 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ 99 100 #define RCAR_MIN_DMA_LEN 8 101 102 /* SCL low/high ratio 5:4 to meet all I2C timing specs (incl safety margin) */ 103 #define RCAR_SCLD_RATIO 5 104 #define RCAR_SCHD_RATIO 4 105 /* 106 * SMD should be smaller than SCLD/SCHD and is always around 20 in the docs. 107 * Thus, we simply use 20 which works for low and high speeds. 108 */ 109 #define RCAR_DEFAULT_SMD 20 110 111 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) 112 #define RCAR_BUS_PHASE_DATA (MDBS | MIE) 113 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) 114 115 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) 116 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) 117 #define RCAR_IRQ_STOP (MST) 118 119 #define ID_LAST_MSG BIT(0) 120 #define ID_REP_AFTER_RD BIT(1) 121 #define ID_DONE BIT(2) 122 #define ID_ARBLOST BIT(3) 123 #define ID_NACK BIT(4) 124 #define ID_EPROTO BIT(5) 125 /* persistent flags */ 126 #define ID_P_FMPLUS BIT(27) 127 #define ID_P_NOT_ATOMIC BIT(28) 128 #define ID_P_HOST_NOTIFY BIT(29) 129 #define ID_P_NO_RXDMA BIT(30) /* HW forbids RXDMA sometimes */ 130 #define ID_P_PM_BLOCKED BIT(31) 131 #define ID_P_MASK GENMASK(31, 27) 132 133 enum rcar_i2c_type { 134 I2C_RCAR_GEN1, 135 I2C_RCAR_GEN2, 136 I2C_RCAR_GEN3, 137 I2C_RCAR_GEN4, 138 }; 139 140 struct rcar_i2c_priv { 141 u32 flags; 142 void __iomem *io; 143 struct i2c_adapter adap; 144 struct i2c_msg *msg; 145 int msgs_left; 146 struct clk *clk; 147 148 wait_queue_head_t wait; 149 150 int pos; 151 u32 icccr; 152 u16 schd; 153 u16 scld; 154 u8 smd; 155 u8 recovery_icmcr; /* protected by adapter lock */ 156 enum rcar_i2c_type devtype; 157 struct i2c_client *slave; 158 159 struct resource *res; 160 struct dma_chan *dma_tx; 161 struct dma_chan *dma_rx; 162 struct scatterlist sg; 163 enum dma_data_direction dma_direction; 164 165 struct reset_control *rstc; 166 int irq; 167 168 struct i2c_client *host_notify_client; 169 }; 170 171 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) 172 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) 173 174 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) 175 { 176 writel(val, priv->io + reg); 177 } 178 179 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) 180 { 181 return readl(priv->io + reg); 182 } 183 184 static void rcar_i2c_clear_irq(struct rcar_i2c_priv *priv, u32 val) 185 { 186 writel(~val & 0x7f, priv->io + ICMSR); 187 } 188 189 static int rcar_i2c_get_scl(struct i2c_adapter *adap) 190 { 191 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 192 193 return !!(rcar_i2c_read(priv, ICMCR) & FSCL); 194 195 }; 196 197 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val) 198 { 199 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 200 201 if (val) 202 priv->recovery_icmcr |= FSCL; 203 else 204 priv->recovery_icmcr &= ~FSCL; 205 206 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 207 }; 208 209 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val) 210 { 211 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 212 213 if (val) 214 priv->recovery_icmcr |= FSDA; 215 else 216 priv->recovery_icmcr &= ~FSDA; 217 218 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 219 }; 220 221 static int rcar_i2c_get_bus_free(struct i2c_adapter *adap) 222 { 223 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 224 225 return !(rcar_i2c_read(priv, ICMCR) & FSDA); 226 227 }; 228 229 static struct i2c_bus_recovery_info rcar_i2c_bri = { 230 .get_scl = rcar_i2c_get_scl, 231 .set_scl = rcar_i2c_set_scl, 232 .set_sda = rcar_i2c_set_sda, 233 .get_bus_free = rcar_i2c_get_bus_free, 234 .recover_bus = i2c_generic_scl_recovery, 235 }; 236 static void rcar_i2c_init(struct rcar_i2c_priv *priv) 237 { 238 /* reset master mode */ 239 rcar_i2c_write(priv, ICMIER, 0); 240 rcar_i2c_write(priv, ICMCR, MDBS); 241 rcar_i2c_write(priv, ICMSR, 0); 242 /* start clock */ 243 if (priv->devtype < I2C_RCAR_GEN3) { 244 rcar_i2c_write(priv, ICCCR, priv->icccr); 245 } else { 246 u32 icccr2 = CDFD | HLSE | SME; 247 248 if (priv->flags & ID_P_FMPLUS) 249 icccr2 |= FMPE; 250 251 rcar_i2c_write(priv, ICCCR2, icccr2); 252 rcar_i2c_write(priv, ICCCR, priv->icccr); 253 rcar_i2c_write(priv, ICMPR, priv->smd); 254 rcar_i2c_write(priv, ICHPR, priv->schd); 255 rcar_i2c_write(priv, ICLPR, priv->scld); 256 rcar_i2c_write(priv, ICFBSCR, TCYC17); 257 } 258 } 259 260 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) 261 { 262 int ret; 263 u32 val; 264 265 ret = readl_poll_timeout(priv->io + ICMCR, val, !(val & FSDA), 10, 266 priv->adap.timeout); 267 if (ret) { 268 /* Waiting did not help, try to recover */ 269 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL; 270 ret = i2c_recover_bus(&priv->adap); 271 } 272 273 return ret; 274 } 275 276 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv) 277 { 278 u32 cdf, round, ick, sum, scl, cdf_width; 279 unsigned long rate; 280 struct device *dev = rcar_i2c_priv_to_dev(priv); 281 struct i2c_timings t = { 282 .bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ, 283 .scl_fall_ns = 35, 284 .scl_rise_ns = 200, 285 .scl_int_delay_ns = 50, 286 }; 287 288 /* Fall back to previously used values if not supplied */ 289 i2c_parse_fw_timings(dev, &t, false); 290 priv->smd = RCAR_DEFAULT_SMD; 291 292 /* 293 * calculate SCL clock 294 * see 295 * ICCCR (and ICCCR2 for Gen3+) 296 * 297 * ick = clkp / (1 + CDF) 298 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 299 * 300 * for Gen3+: 301 * SCL = clkp / (8 + SMD * 2 + SCLD + SCHD +F[(ticf + tr + intd) * clkp]) 302 * 303 * ick : I2C internal clock < 20 MHz 304 * ticf : I2C SCL falling time 305 * tr : I2C SCL rising time 306 * intd : LSI internal delay 307 * clkp : peripheral_clk 308 * F[] : integer up-valuation 309 */ 310 rate = clk_get_rate(priv->clk); 311 cdf = rate / 20000000; 312 cdf_width = (priv->devtype == I2C_RCAR_GEN1) ? 2 : 3; 313 if (cdf >= 1U << cdf_width) 314 goto err_no_val; 315 316 if (t.bus_freq_hz > I2C_MAX_FAST_MODE_FREQ && priv->devtype >= I2C_RCAR_GEN4) 317 priv->flags |= ID_P_FMPLUS; 318 else 319 priv->flags &= ~ID_P_FMPLUS; 320 321 /* On Gen3+, we use cdf only for the filters, not as a SCL divider */ 322 ick = rate / (priv->devtype < I2C_RCAR_GEN3 ? (cdf + 1) : 1); 323 324 /* 325 * It is impossible to calculate a large scale number on u32. Separate it. 326 * 327 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd) 328 * = F[sum * ick / 1000000000] 329 * = F[(ick / 1000000) * sum / 1000] 330 */ 331 sum = t.scl_fall_ns + t.scl_rise_ns + t.scl_int_delay_ns; 332 round = DIV_ROUND_CLOSEST(ick, 1000000); 333 round = DIV_ROUND_CLOSEST(round * sum, 1000); 334 335 if (priv->devtype < I2C_RCAR_GEN3) { 336 u32 scgd; 337 /* 338 * SCL = ick / (20 + 8 * SCGD + F[(ticf + tr + intd) * ick]) 339 * 20 + 8 * SCGD + F[...] = ick / SCL 340 * SCGD = ((ick / SCL) - 20 - F[...]) / 8 341 * Result (= SCL) should be less than bus_speed for hardware safety 342 */ 343 scgd = DIV_ROUND_UP(ick, t.bus_freq_hz ?: 1); 344 scgd = DIV_ROUND_UP(scgd - 20 - round, 8); 345 scl = ick / (20 + 8 * scgd + round); 346 347 if (scgd > 0x3f) 348 goto err_no_val; 349 350 dev_dbg(dev, "clk %u/%u(%lu), round %u, CDF: %u, SCGD: %u\n", 351 scl, t.bus_freq_hz, rate, round, cdf, scgd); 352 353 priv->icccr = scgd << cdf_width | cdf; 354 } else { 355 u32 x, sum_ratio = RCAR_SCHD_RATIO + RCAR_SCLD_RATIO; 356 /* 357 * SCLD/SCHD ratio and SMD default value are explained above 358 * where they are defined. With these definitions, we can compute 359 * x as a base value for the SCLD/SCHD ratio: 360 * 361 * SCL = clkp / (8 + 2 * SMD + SCLD + SCHD + F[(ticf + tr + intd) * clkp]) 362 * SCL = clkp / (8 + 2 * SMD + RCAR_SCLD_RATIO * x 363 * + RCAR_SCHD_RATIO * x + F[...]) 364 * 365 * with: sum_ratio = RCAR_SCLD_RATIO + RCAR_SCHD_RATIO 366 * 367 * SCL = clkp / (8 + 2 * smd + sum_ratio * x + F[...]) 368 * 8 + 2 * smd + sum_ratio * x + F[...] = clkp / SCL 369 * x = ((clkp / SCL) - 8 - 2 * smd - F[...]) / sum_ratio 370 */ 371 x = DIV_ROUND_UP(rate, t.bus_freq_hz ?: 1); 372 x = DIV_ROUND_UP(x - 8 - 2 * priv->smd - round, sum_ratio); 373 scl = rate / (8 + 2 * priv->smd + sum_ratio * x + round); 374 375 if (x == 0 || x * RCAR_SCLD_RATIO > 0xffff) 376 goto err_no_val; 377 378 priv->icccr = cdf; 379 priv->schd = RCAR_SCHD_RATIO * x; 380 priv->scld = RCAR_SCLD_RATIO * x; 381 if (priv->smd >= priv->schd) 382 priv->smd = priv->schd - 1; 383 384 dev_dbg(dev, "clk %u/%u(%lu), round %u, CDF: %u SCHD %u SCLD %u SMD %u\n", 385 scl, t.bus_freq_hz, rate, round, cdf, priv->schd, priv->scld, priv->smd); 386 } 387 388 return 0; 389 390 err_no_val: 391 dev_err(dev, "it is impossible to calculate best SCL\n"); 392 return -EINVAL; 393 } 394 395 /* 396 * We don't have a test case but the HW engineers say that the write order of 397 * ICMSR and ICMCR depends on whether we issue START or REP_START. So, ICMSR 398 * handling is outside of this function. First messages clear ICMSR before this 399 * function, interrupt handlers clear the relevant bits after this function. 400 */ 401 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) 402 { 403 int read = !!rcar_i2c_is_recv(priv); 404 bool rep_start = !(priv->flags & ID_REP_AFTER_RD); 405 406 priv->pos = 0; 407 priv->flags &= ID_P_MASK; 408 409 if (priv->msgs_left == 1) 410 priv->flags |= ID_LAST_MSG; 411 412 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg)); 413 if (priv->flags & ID_P_NOT_ATOMIC) 414 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); 415 416 if (rep_start) 417 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 418 } 419 420 static void rcar_i2c_first_msg(struct rcar_i2c_priv *priv, 421 struct i2c_msg *msgs, int num) 422 { 423 priv->msg = msgs; 424 priv->msgs_left = num; 425 rcar_i2c_write(priv, ICMSR, 0); /* must be before preparing msg */ 426 rcar_i2c_prepare_msg(priv); 427 } 428 429 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) 430 { 431 priv->msg++; 432 priv->msgs_left--; 433 rcar_i2c_prepare_msg(priv); 434 /* ICMSR handling must come afterwards in the irq handler */ 435 } 436 437 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv, bool terminate) 438 { 439 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE 440 ? priv->dma_rx : priv->dma_tx; 441 442 /* only allowed from thread context! */ 443 if (terminate) 444 dmaengine_terminate_sync(chan); 445 446 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), 447 sg_dma_len(&priv->sg), priv->dma_direction); 448 449 /* Gen3+ can only do one RXDMA per transfer and we just completed it */ 450 if (priv->devtype >= I2C_RCAR_GEN3 && 451 priv->dma_direction == DMA_FROM_DEVICE) 452 priv->flags |= ID_P_NO_RXDMA; 453 454 priv->dma_direction = DMA_NONE; 455 456 /* Disable DMA Master Received/Transmitted, must be last! */ 457 rcar_i2c_write(priv, ICDMAER, 0); 458 } 459 460 static void rcar_i2c_dma_callback(void *data) 461 { 462 struct rcar_i2c_priv *priv = data; 463 464 priv->pos += sg_dma_len(&priv->sg); 465 466 rcar_i2c_cleanup_dma(priv, false); 467 } 468 469 static bool rcar_i2c_dma(struct rcar_i2c_priv *priv) 470 { 471 struct device *dev = rcar_i2c_priv_to_dev(priv); 472 struct i2c_msg *msg = priv->msg; 473 bool read = msg->flags & I2C_M_RD; 474 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 475 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx; 476 struct dma_async_tx_descriptor *txdesc; 477 dma_addr_t dma_addr; 478 dma_cookie_t cookie; 479 unsigned char *buf; 480 int len; 481 482 /* Do various checks to see if DMA is feasible at all */ 483 if (!(priv->flags & ID_P_NOT_ATOMIC) || IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN || 484 !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA)) 485 return false; 486 487 if (read) { 488 /* 489 * The last two bytes needs to be fetched using PIO in 490 * order for the STOP phase to work. 491 */ 492 buf = priv->msg->buf; 493 len = priv->msg->len - 2; 494 } else { 495 /* 496 * First byte in message was sent using PIO. 497 */ 498 buf = priv->msg->buf + 1; 499 len = priv->msg->len - 1; 500 } 501 502 dma_addr = dma_map_single(chan->device->dev, buf, len, dir); 503 if (dma_mapping_error(chan->device->dev, dma_addr)) { 504 dev_dbg(dev, "dma map failed, using PIO\n"); 505 return false; 506 } 507 508 sg_dma_len(&priv->sg) = len; 509 sg_dma_address(&priv->sg) = dma_addr; 510 511 priv->dma_direction = dir; 512 513 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1, 514 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 515 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 516 if (!txdesc) { 517 dev_dbg(dev, "dma prep slave sg failed, using PIO\n"); 518 rcar_i2c_cleanup_dma(priv, false); 519 return false; 520 } 521 522 txdesc->callback = rcar_i2c_dma_callback; 523 txdesc->callback_param = priv; 524 525 cookie = dmaengine_submit(txdesc); 526 if (dma_submit_error(cookie)) { 527 dev_dbg(dev, "submitting dma failed, using PIO\n"); 528 rcar_i2c_cleanup_dma(priv, false); 529 return false; 530 } 531 532 /* Enable DMA Master Received/Transmitted */ 533 if (read) 534 rcar_i2c_write(priv, ICDMAER, RMDMAE); 535 else 536 rcar_i2c_write(priv, ICDMAER, TMDMAE); 537 538 dma_async_issue_pending(chan); 539 return true; 540 } 541 542 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) 543 { 544 struct i2c_msg *msg = priv->msg; 545 u32 irqs_to_clear = MDE; 546 547 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 548 if (!(msr & MDE)) 549 return; 550 551 if (msr & MAT) 552 irqs_to_clear |= MAT; 553 554 /* Check if DMA can be enabled and take over */ 555 if (priv->pos == 1 && rcar_i2c_dma(priv)) 556 return; 557 558 if (priv->pos < msg->len) { 559 /* 560 * Prepare next data to ICRXTX register. 561 * This data will go to _SHIFT_ register. 562 * 563 * * 564 * [ICRXTX] -> [SHIFT] -> [I2C bus] 565 */ 566 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); 567 priv->pos++; 568 } else { 569 /* 570 * The last data was pushed to ICRXTX on _PREV_ empty irq. 571 * It is on _SHIFT_ register, and will sent to I2C bus. 572 * 573 * * 574 * [ICRXTX] -> [SHIFT] -> [I2C bus] 575 */ 576 577 if (priv->flags & ID_LAST_MSG) 578 /* 579 * If current msg is the _LAST_ msg, 580 * prepare stop condition here. 581 * ID_DONE will be set on STOP irq. 582 */ 583 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 584 else 585 rcar_i2c_next_msg(priv); 586 } 587 588 rcar_i2c_clear_irq(priv, irqs_to_clear); 589 } 590 591 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) 592 { 593 struct i2c_msg *msg = priv->msg; 594 bool recv_len_init = priv->pos == 0 && msg->flags & I2C_M_RECV_LEN; 595 u32 irqs_to_clear = MDR; 596 597 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 598 if (!(msr & MDR)) 599 return; 600 601 if (msr & MAT) { 602 irqs_to_clear |= MAT; 603 /* 604 * Address transfer phase finished, but no data at this point. 605 * Try to use DMA to receive data. 606 */ 607 rcar_i2c_dma(priv); 608 } else if (priv->pos < msg->len) { 609 /* get received data */ 610 u8 data = rcar_i2c_read(priv, ICRXTX); 611 612 msg->buf[priv->pos] = data; 613 if (recv_len_init) { 614 if (data == 0 || data > I2C_SMBUS_BLOCK_MAX) { 615 priv->flags |= ID_DONE | ID_EPROTO; 616 return; 617 } 618 msg->len += msg->buf[0]; 619 /* Enough data for DMA? */ 620 if (rcar_i2c_dma(priv)) 621 return; 622 /* new length after RECV_LEN now properly initialized */ 623 recv_len_init = false; 624 } 625 priv->pos++; 626 } 627 628 /* 629 * If next received data is the _LAST_ and we are not waiting for a new 630 * length because of RECV_LEN, then go to a new phase. 631 */ 632 if (priv->pos + 1 == msg->len && !recv_len_init) { 633 if (priv->flags & ID_LAST_MSG) { 634 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 635 } else { 636 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 637 priv->flags |= ID_REP_AFTER_RD; 638 } 639 } 640 641 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG)) 642 rcar_i2c_next_msg(priv); 643 644 rcar_i2c_clear_irq(priv, irqs_to_clear); 645 } 646 647 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) 648 { 649 u32 ssr_raw, ssr_filtered; 650 u8 value; 651 652 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; 653 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); 654 655 if (!ssr_filtered) 656 return false; 657 658 /* address detected */ 659 if (ssr_filtered & SAR) { 660 /* read or write request */ 661 if (ssr_raw & STM) { 662 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); 663 rcar_i2c_write(priv, ICRXTX, value); 664 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); 665 } else { 666 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); 667 rcar_i2c_read(priv, ICRXTX); /* dummy read */ 668 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); 669 } 670 671 /* Clear SSR, too, because of old STOPs to other clients than us */ 672 rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff); 673 } 674 675 /* master sent stop */ 676 if (ssr_filtered & SSR) { 677 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); 678 rcar_i2c_write(priv, ICSCR, SIE | SDBS); /* clear our NACK */ 679 rcar_i2c_write(priv, ICSIER, SAR); 680 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); 681 } 682 683 /* master wants to write to us */ 684 if (ssr_filtered & SDR) { 685 int ret; 686 687 value = rcar_i2c_read(priv, ICRXTX); 688 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); 689 /* Send NACK in case of error */ 690 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); 691 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); 692 } 693 694 /* master wants to read from us */ 695 if (ssr_filtered & SDE) { 696 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); 697 rcar_i2c_write(priv, ICRXTX, value); 698 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); 699 } 700 701 return true; 702 } 703 704 /* 705 * This driver has a lock-free design because there are IP cores (at least 706 * R-Car Gen2) which have an inherent race condition in their hardware design. 707 * There, we need to switch to RCAR_BUS_PHASE_DATA as soon as possible after 708 * the interrupt was generated, otherwise an unwanted repeated message gets 709 * generated. It turned out that taking a spinlock at the beginning of the ISR 710 * was already causing repeated messages. Thus, this driver was converted to 711 * the now lockless behaviour. Please keep this in mind when hacking the driver. 712 * R-Car Gen3 seems to have this fixed but earlier versions than R-Car Gen2 are 713 * likely affected. Therefore, we have different interrupt handler entries. 714 */ 715 static irqreturn_t rcar_i2c_irq(int irq, struct rcar_i2c_priv *priv, u32 msr) 716 { 717 if (!msr) { 718 if (rcar_i2c_slave_irq(priv)) 719 return IRQ_HANDLED; 720 721 return IRQ_NONE; 722 } 723 724 /* Arbitration lost */ 725 if (msr & MAL) { 726 priv->flags |= ID_DONE | ID_ARBLOST; 727 goto out; 728 } 729 730 /* Nack */ 731 if (msr & MNR) { 732 /* HW automatically sends STOP after received NACK */ 733 if (priv->flags & ID_P_NOT_ATOMIC) 734 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); 735 priv->flags |= ID_NACK; 736 goto out; 737 } 738 739 /* Stop */ 740 if (msr & MST) { 741 priv->msgs_left--; /* The last message also made it */ 742 priv->flags |= ID_DONE; 743 goto out; 744 } 745 746 if (rcar_i2c_is_recv(priv)) 747 rcar_i2c_irq_recv(priv, msr); 748 else 749 rcar_i2c_irq_send(priv, msr); 750 751 out: 752 if (priv->flags & ID_DONE) { 753 rcar_i2c_write(priv, ICMIER, 0); 754 rcar_i2c_write(priv, ICMSR, 0); 755 if (priv->flags & ID_P_NOT_ATOMIC) 756 wake_up(&priv->wait); 757 } 758 759 return IRQ_HANDLED; 760 } 761 762 static irqreturn_t rcar_i2c_gen2_irq(int irq, void *ptr) 763 { 764 struct rcar_i2c_priv *priv = ptr; 765 u32 msr; 766 767 /* Clear START or STOP immediately, except for REPSTART after read */ 768 if (likely(!(priv->flags & ID_REP_AFTER_RD))) 769 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); 770 771 /* Only handle interrupts that are currently enabled */ 772 msr = rcar_i2c_read(priv, ICMSR); 773 if (priv->flags & ID_P_NOT_ATOMIC) 774 msr &= rcar_i2c_read(priv, ICMIER); 775 776 return rcar_i2c_irq(irq, priv, msr); 777 } 778 779 static irqreturn_t rcar_i2c_gen3_irq(int irq, void *ptr) 780 { 781 struct rcar_i2c_priv *priv = ptr; 782 u32 msr; 783 784 /* Only handle interrupts that are currently enabled */ 785 msr = rcar_i2c_read(priv, ICMSR); 786 if (priv->flags & ID_P_NOT_ATOMIC) 787 msr &= rcar_i2c_read(priv, ICMIER); 788 789 /* 790 * Clear START or STOP immediately, except for REPSTART after read or 791 * if a spurious interrupt was detected. 792 */ 793 if (likely(!(priv->flags & ID_REP_AFTER_RD) && msr)) 794 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); 795 796 return rcar_i2c_irq(irq, priv, msr); 797 } 798 799 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev, 800 enum dma_transfer_direction dir, 801 dma_addr_t port_addr) 802 { 803 struct dma_chan *chan; 804 struct dma_slave_config cfg; 805 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; 806 int ret; 807 808 chan = dma_request_chan(dev, chan_name); 809 if (IS_ERR(chan)) { 810 dev_dbg(dev, "request_channel failed for %s (%ld)\n", 811 chan_name, PTR_ERR(chan)); 812 return chan; 813 } 814 815 memset(&cfg, 0, sizeof(cfg)); 816 cfg.direction = dir; 817 if (dir == DMA_MEM_TO_DEV) { 818 cfg.dst_addr = port_addr; 819 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 820 } else { 821 cfg.src_addr = port_addr; 822 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 823 } 824 825 ret = dmaengine_slave_config(chan, &cfg); 826 if (ret) { 827 dev_dbg(dev, "slave_config failed for %s (%d)\n", 828 chan_name, ret); 829 dma_release_channel(chan); 830 return ERR_PTR(ret); 831 } 832 833 dev_dbg(dev, "got DMA channel for %s\n", chan_name); 834 return chan; 835 } 836 837 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv, 838 struct i2c_msg *msg) 839 { 840 struct device *dev = rcar_i2c_priv_to_dev(priv); 841 bool read; 842 struct dma_chan *chan; 843 enum dma_transfer_direction dir; 844 845 read = msg->flags & I2C_M_RD; 846 847 chan = read ? priv->dma_rx : priv->dma_tx; 848 if (PTR_ERR(chan) != -EPROBE_DEFER) 849 return; 850 851 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 852 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX); 853 854 if (read) 855 priv->dma_rx = chan; 856 else 857 priv->dma_tx = chan; 858 } 859 860 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv) 861 { 862 if (!IS_ERR(priv->dma_tx)) { 863 dma_release_channel(priv->dma_tx); 864 priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 865 } 866 867 if (!IS_ERR(priv->dma_rx)) { 868 dma_release_channel(priv->dma_rx); 869 priv->dma_rx = ERR_PTR(-EPROBE_DEFER); 870 } 871 } 872 873 /* I2C is a special case, we need to poll the status of a reset */ 874 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv) 875 { 876 int ret; 877 878 ret = reset_control_reset(priv->rstc); 879 if (ret) 880 return ret; 881 882 return read_poll_timeout_atomic(reset_control_status, ret, ret == 0, 1, 883 100, false, priv->rstc); 884 } 885 886 static int rcar_i2c_master_xfer(struct i2c_adapter *adap, 887 struct i2c_msg *msgs, 888 int num) 889 { 890 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 891 struct device *dev = rcar_i2c_priv_to_dev(priv); 892 int i, ret; 893 long time_left; 894 895 priv->flags |= ID_P_NOT_ATOMIC; 896 897 pm_runtime_get_sync(dev); 898 899 /* Check bus state before init otherwise bus busy info will be lost */ 900 ret = rcar_i2c_bus_barrier(priv); 901 if (ret < 0) 902 goto out; 903 904 /* Gen3+ needs a reset. That also allows RXDMA once */ 905 if (priv->devtype >= I2C_RCAR_GEN3) { 906 priv->flags &= ~ID_P_NO_RXDMA; 907 ret = rcar_i2c_do_reset(priv); 908 if (ret) 909 goto out; 910 } 911 912 rcar_i2c_init(priv); 913 914 for (i = 0; i < num; i++) 915 rcar_i2c_request_dma(priv, msgs + i); 916 917 rcar_i2c_first_msg(priv, msgs, num); 918 919 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE, 920 num * adap->timeout); 921 922 /* cleanup DMA if it couldn't complete properly due to an error */ 923 if (priv->dma_direction != DMA_NONE) 924 rcar_i2c_cleanup_dma(priv, true); 925 926 if (!time_left) { 927 rcar_i2c_init(priv); 928 ret = -ETIMEDOUT; 929 } else if (priv->flags & ID_NACK) { 930 ret = -ENXIO; 931 } else if (priv->flags & ID_ARBLOST) { 932 ret = -EAGAIN; 933 } else if (priv->flags & ID_EPROTO) { 934 ret = -EPROTO; 935 } else { 936 ret = num - priv->msgs_left; /* The number of transfer */ 937 } 938 out: 939 pm_runtime_put(dev); 940 941 if (ret < 0 && ret != -ENXIO) 942 dev_err(dev, "error %d : %x\n", ret, priv->flags); 943 944 return ret; 945 } 946 947 static int rcar_i2c_master_xfer_atomic(struct i2c_adapter *adap, 948 struct i2c_msg *msgs, 949 int num) 950 { 951 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 952 struct device *dev = rcar_i2c_priv_to_dev(priv); 953 unsigned long j; 954 bool time_left; 955 int ret; 956 957 priv->flags &= ~ID_P_NOT_ATOMIC; 958 959 pm_runtime_get_sync(dev); 960 961 /* Check bus state before init otherwise bus busy info will be lost */ 962 ret = rcar_i2c_bus_barrier(priv); 963 if (ret < 0) 964 goto out; 965 966 rcar_i2c_init(priv); 967 rcar_i2c_first_msg(priv, msgs, num); 968 969 j = jiffies + num * adap->timeout; 970 do { 971 u32 msr = rcar_i2c_read(priv, ICMSR); 972 973 msr &= (rcar_i2c_is_recv(priv) ? RCAR_IRQ_RECV : RCAR_IRQ_SEND) | RCAR_IRQ_STOP; 974 975 if (msr) { 976 if (priv->devtype < I2C_RCAR_GEN3) 977 rcar_i2c_gen2_irq(0, priv); 978 else 979 rcar_i2c_gen3_irq(0, priv); 980 } 981 982 time_left = time_before_eq(jiffies, j); 983 } while (!(priv->flags & ID_DONE) && time_left); 984 985 if (!time_left) { 986 rcar_i2c_init(priv); 987 ret = -ETIMEDOUT; 988 } else if (priv->flags & ID_NACK) { 989 ret = -ENXIO; 990 } else if (priv->flags & ID_ARBLOST) { 991 ret = -EAGAIN; 992 } else if (priv->flags & ID_EPROTO) { 993 ret = -EPROTO; 994 } else { 995 ret = num - priv->msgs_left; /* The number of transfer */ 996 } 997 out: 998 pm_runtime_put(dev); 999 1000 if (ret < 0 && ret != -ENXIO) 1001 dev_err(dev, "error %d : %x\n", ret, priv->flags); 1002 1003 return ret; 1004 } 1005 1006 static int rcar_reg_slave(struct i2c_client *slave) 1007 { 1008 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 1009 1010 if (priv->slave) 1011 return -EBUSY; 1012 1013 if (slave->flags & I2C_CLIENT_TEN) 1014 return -EAFNOSUPPORT; 1015 1016 /* Keep device active for slave address detection logic */ 1017 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv)); 1018 1019 priv->slave = slave; 1020 rcar_i2c_write(priv, ICSAR, slave->addr); 1021 rcar_i2c_write(priv, ICSSR, 0); 1022 rcar_i2c_write(priv, ICSIER, SAR); 1023 rcar_i2c_write(priv, ICSCR, SIE | SDBS); 1024 1025 return 0; 1026 } 1027 1028 static int rcar_unreg_slave(struct i2c_client *slave) 1029 { 1030 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 1031 1032 WARN_ON(!priv->slave); 1033 1034 /* ensure no irq is running before clearing ptr */ 1035 disable_irq(priv->irq); 1036 rcar_i2c_write(priv, ICSIER, 0); 1037 rcar_i2c_write(priv, ICSSR, 0); 1038 enable_irq(priv->irq); 1039 rcar_i2c_write(priv, ICSCR, SDBS); 1040 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */ 1041 1042 priv->slave = NULL; 1043 1044 pm_runtime_put(rcar_i2c_priv_to_dev(priv)); 1045 1046 return 0; 1047 } 1048 1049 static u32 rcar_i2c_func(struct i2c_adapter *adap) 1050 { 1051 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 1052 1053 /* 1054 * This HW can't do: 1055 * I2C_SMBUS_QUICK (setting FSB during START didn't work) 1056 * I2C_M_NOSTART (automatically sends address after START) 1057 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK) 1058 */ 1059 u32 func = I2C_FUNC_I2C | I2C_FUNC_SLAVE | 1060 (I2C_FUNC_SMBUS_EMUL_ALL & ~I2C_FUNC_SMBUS_QUICK); 1061 1062 if (priv->flags & ID_P_HOST_NOTIFY) 1063 func |= I2C_FUNC_SMBUS_HOST_NOTIFY; 1064 1065 return func; 1066 } 1067 1068 static const struct i2c_algorithm rcar_i2c_algo = { 1069 .master_xfer = rcar_i2c_master_xfer, 1070 .master_xfer_atomic = rcar_i2c_master_xfer_atomic, 1071 .functionality = rcar_i2c_func, 1072 .reg_slave = rcar_reg_slave, 1073 .unreg_slave = rcar_unreg_slave, 1074 }; 1075 1076 static const struct i2c_adapter_quirks rcar_i2c_quirks = { 1077 .flags = I2C_AQ_NO_ZERO_LEN, 1078 }; 1079 1080 static const struct of_device_id rcar_i2c_dt_ids[] = { 1081 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, 1082 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, 1083 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, 1084 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, 1085 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, 1086 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, 1087 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, 1088 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, 1089 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 }, 1090 /* S4 has no FM+ bit */ 1091 { .compatible = "renesas,i2c-r8a779f0", .data = (void *)I2C_RCAR_GEN3 }, 1092 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 }, 1093 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 }, 1094 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 }, 1095 { .compatible = "renesas,rcar-gen4-i2c", .data = (void *)I2C_RCAR_GEN4 }, 1096 {}, 1097 }; 1098 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); 1099 1100 static int rcar_i2c_probe(struct platform_device *pdev) 1101 { 1102 struct rcar_i2c_priv *priv; 1103 struct i2c_adapter *adap; 1104 struct device *dev = &pdev->dev; 1105 unsigned long irqflags = 0; 1106 irqreturn_t (*irqhandler)(int irq, void *ptr) = rcar_i2c_gen3_irq; 1107 int ret; 1108 1109 /* Otherwise logic will break because some bytes must always use PIO */ 1110 BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length"); 1111 1112 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); 1113 if (!priv) 1114 return -ENOMEM; 1115 1116 priv->clk = devm_clk_get(dev, NULL); 1117 if (IS_ERR(priv->clk)) { 1118 dev_err(dev, "cannot get clock\n"); 1119 return PTR_ERR(priv->clk); 1120 } 1121 1122 priv->io = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->res); 1123 if (IS_ERR(priv->io)) 1124 return PTR_ERR(priv->io); 1125 1126 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev); 1127 init_waitqueue_head(&priv->wait); 1128 1129 adap = &priv->adap; 1130 adap->nr = pdev->id; 1131 adap->algo = &rcar_i2c_algo; 1132 adap->class = I2C_CLASS_DEPRECATED; 1133 adap->retries = 3; 1134 adap->dev.parent = dev; 1135 adap->dev.of_node = dev->of_node; 1136 adap->bus_recovery_info = &rcar_i2c_bri; 1137 adap->quirks = &rcar_i2c_quirks; 1138 i2c_set_adapdata(adap, priv); 1139 strscpy(adap->name, pdev->name, sizeof(adap->name)); 1140 1141 /* Init DMA */ 1142 sg_init_table(&priv->sg, 1); 1143 priv->dma_direction = DMA_NONE; 1144 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 1145 1146 /* Activate device for clock calculation */ 1147 pm_runtime_enable(dev); 1148 pm_runtime_get_sync(dev); 1149 ret = rcar_i2c_clock_calculate(priv); 1150 if (ret < 0) { 1151 pm_runtime_put(dev); 1152 goto out_pm_disable; 1153 } 1154 1155 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */ 1156 1157 if (priv->devtype < I2C_RCAR_GEN3) { 1158 irqflags |= IRQF_NO_THREAD; 1159 irqhandler = rcar_i2c_gen2_irq; 1160 } 1161 1162 /* Stay always active when multi-master to keep arbitration working */ 1163 if (of_property_read_bool(dev->of_node, "multi-master")) 1164 priv->flags |= ID_P_PM_BLOCKED; 1165 else 1166 pm_runtime_put(dev); 1167 1168 if (of_property_read_bool(dev->of_node, "smbus")) 1169 priv->flags |= ID_P_HOST_NOTIFY; 1170 1171 if (priv->devtype >= I2C_RCAR_GEN3) { 1172 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1173 if (IS_ERR(priv->rstc)) { 1174 ret = PTR_ERR(priv->rstc); 1175 goto out_pm_put; 1176 } 1177 1178 ret = reset_control_status(priv->rstc); 1179 if (ret < 0) 1180 goto out_pm_put; 1181 } 1182 1183 ret = platform_get_irq(pdev, 0); 1184 if (ret < 0) 1185 goto out_pm_put; 1186 priv->irq = ret; 1187 ret = devm_request_irq(dev, priv->irq, irqhandler, irqflags, dev_name(dev), priv); 1188 if (ret < 0) { 1189 dev_err(dev, "cannot get irq %d\n", priv->irq); 1190 goto out_pm_put; 1191 } 1192 1193 platform_set_drvdata(pdev, priv); 1194 1195 ret = i2c_add_numbered_adapter(adap); 1196 if (ret < 0) 1197 goto out_pm_put; 1198 1199 if (priv->flags & ID_P_HOST_NOTIFY) { 1200 priv->host_notify_client = i2c_new_slave_host_notify_device(adap); 1201 if (IS_ERR(priv->host_notify_client)) { 1202 ret = PTR_ERR(priv->host_notify_client); 1203 goto out_del_device; 1204 } 1205 } 1206 1207 dev_info(dev, "probed\n"); 1208 1209 return 0; 1210 1211 out_del_device: 1212 i2c_del_adapter(&priv->adap); 1213 out_pm_put: 1214 if (priv->flags & ID_P_PM_BLOCKED) 1215 pm_runtime_put(dev); 1216 out_pm_disable: 1217 pm_runtime_disable(dev); 1218 return ret; 1219 } 1220 1221 static void rcar_i2c_remove(struct platform_device *pdev) 1222 { 1223 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); 1224 struct device *dev = &pdev->dev; 1225 1226 if (priv->host_notify_client) 1227 i2c_free_slave_host_notify_device(priv->host_notify_client); 1228 i2c_del_adapter(&priv->adap); 1229 rcar_i2c_release_dma(priv); 1230 if (priv->flags & ID_P_PM_BLOCKED) 1231 pm_runtime_put(dev); 1232 pm_runtime_disable(dev); 1233 } 1234 1235 static int rcar_i2c_suspend(struct device *dev) 1236 { 1237 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1238 1239 i2c_mark_adapter_suspended(&priv->adap); 1240 return 0; 1241 } 1242 1243 static int rcar_i2c_resume(struct device *dev) 1244 { 1245 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1246 1247 i2c_mark_adapter_resumed(&priv->adap); 1248 return 0; 1249 } 1250 1251 static const struct dev_pm_ops rcar_i2c_pm_ops = { 1252 NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume) 1253 }; 1254 1255 static struct platform_driver rcar_i2c_driver = { 1256 .driver = { 1257 .name = "i2c-rcar", 1258 .of_match_table = rcar_i2c_dt_ids, 1259 .pm = pm_sleep_ptr(&rcar_i2c_pm_ops), 1260 }, 1261 .probe = rcar_i2c_probe, 1262 .remove_new = rcar_i2c_remove, 1263 }; 1264 1265 module_platform_driver(rcar_i2c_driver); 1266 1267 MODULE_LICENSE("GPL v2"); 1268 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); 1269 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); 1270