1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Renesas R-Car I2C unit 4 * 5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com> 6 * Copyright (C) 2011-2019 Renesas Electronics Corporation 7 * 8 * Copyright (C) 2012-14 Renesas Solutions Corp. 9 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 10 * 11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c 12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> 13 */ 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dmaengine.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/i2c.h> 24 #include <linux/i2c-smbus.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/of.h> 28 #include <linux/platform_device.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/reset.h> 31 #include <linux/slab.h> 32 33 /* register offsets */ 34 #define ICSCR 0x00 /* slave ctrl */ 35 #define ICMCR 0x04 /* master ctrl */ 36 #define ICSSR 0x08 /* slave status */ 37 #define ICMSR 0x0C /* master status */ 38 #define ICSIER 0x10 /* slave irq enable */ 39 #define ICMIER 0x14 /* master irq enable */ 40 #define ICCCR 0x18 /* clock dividers */ 41 #define ICSAR 0x1C /* slave address */ 42 #define ICMAR 0x20 /* master address */ 43 #define ICRXTX 0x24 /* data port */ 44 #define ICCCR2 0x28 /* Clock control 2 */ 45 #define ICMPR 0x2C /* SCL mask control */ 46 #define ICHPR 0x30 /* SCL HIGH control */ 47 #define ICLPR 0x34 /* SCL LOW control */ 48 #define ICFBSCR 0x38 /* first bit setup cycle (Gen3) */ 49 #define ICDMAER 0x3c /* DMA enable (Gen3) */ 50 51 /* ICSCR */ 52 #define SDBS BIT(3) /* slave data buffer select */ 53 #define SIE BIT(2) /* slave interface enable */ 54 #define GCAE BIT(1) /* general call address enable */ 55 #define FNA BIT(0) /* forced non acknowledgment */ 56 57 /* ICMCR */ 58 #define MDBS BIT(7) /* non-fifo mode switch */ 59 #define FSCL BIT(6) /* override SCL pin */ 60 #define FSDA BIT(5) /* override SDA pin */ 61 #define OBPC BIT(4) /* override pins */ 62 #define MIE BIT(3) /* master if enable */ 63 #define TSBE BIT(2) 64 #define FSB BIT(1) /* force stop bit */ 65 #define ESG BIT(0) /* enable start bit gen */ 66 67 /* ICSSR (also for ICSIER) */ 68 #define GCAR BIT(6) /* general call received */ 69 #define STM BIT(5) /* slave transmit mode */ 70 #define SSR BIT(4) /* stop received */ 71 #define SDE BIT(3) /* slave data empty */ 72 #define SDT BIT(2) /* slave data transmitted */ 73 #define SDR BIT(1) /* slave data received */ 74 #define SAR BIT(0) /* slave addr received */ 75 76 /* ICMSR (also for ICMIE) */ 77 #define MNR BIT(6) /* nack received */ 78 #define MAL BIT(5) /* arbitration lost */ 79 #define MST BIT(4) /* sent a stop */ 80 #define MDE BIT(3) 81 #define MDT BIT(2) 82 #define MDR BIT(1) 83 #define MAT BIT(0) /* slave addr xfer done */ 84 85 /* ICDMAER */ 86 #define RSDMAE BIT(3) /* DMA Slave Received Enable */ 87 #define TSDMAE BIT(2) /* DMA Slave Transmitted Enable */ 88 #define RMDMAE BIT(1) /* DMA Master Received Enable */ 89 #define TMDMAE BIT(0) /* DMA Master Transmitted Enable */ 90 91 /* ICCCR2 */ 92 #define FMPE BIT(7) /* Fast Mode Plus Enable */ 93 #define CDFD BIT(2) /* CDF Disable */ 94 #define HLSE BIT(1) /* HIGH/LOW Separate Control Enable */ 95 #define SME BIT(0) /* SCL Mask Enable */ 96 97 /* ICFBSCR */ 98 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ 99 100 #define RCAR_MIN_DMA_LEN 8 101 102 /* SCL low/high ratio 5:4 to meet all I2C timing specs (incl safety margin) */ 103 #define RCAR_SCLD_RATIO 5 104 #define RCAR_SCHD_RATIO 4 105 /* 106 * SMD should be smaller than SCLD/SCHD and is always around 20 in the docs. 107 * Thus, we simply use 20 which works for low and high speeds. 108 */ 109 #define RCAR_DEFAULT_SMD 20 110 111 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) 112 #define RCAR_BUS_PHASE_DATA (MDBS | MIE) 113 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) 114 115 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) 116 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) 117 #define RCAR_IRQ_STOP (MST) 118 119 #define ID_LAST_MSG BIT(0) 120 #define ID_REP_AFTER_RD BIT(1) 121 #define ID_DONE BIT(2) 122 #define ID_ARBLOST BIT(3) 123 #define ID_NACK BIT(4) 124 #define ID_EPROTO BIT(5) 125 /* persistent flags */ 126 #define ID_P_FMPLUS BIT(27) 127 #define ID_P_NOT_ATOMIC BIT(28) 128 #define ID_P_HOST_NOTIFY BIT(29) 129 #define ID_P_NO_RXDMA BIT(30) /* HW forbids RXDMA sometimes */ 130 #define ID_P_PM_BLOCKED BIT(31) 131 #define ID_P_MASK GENMASK(31, 27) 132 133 enum rcar_i2c_type { 134 I2C_RCAR_GEN1, 135 I2C_RCAR_GEN2, 136 I2C_RCAR_GEN3, 137 I2C_RCAR_GEN4, 138 }; 139 140 struct rcar_i2c_priv { 141 u32 flags; 142 void __iomem *io; 143 struct i2c_adapter adap; 144 struct i2c_msg *msg; 145 int msgs_left; 146 struct clk *clk; 147 148 wait_queue_head_t wait; 149 150 int pos; 151 u32 icccr; 152 u16 schd; 153 u16 scld; 154 u8 smd; 155 u8 recovery_icmcr; /* protected by adapter lock */ 156 enum rcar_i2c_type devtype; 157 struct i2c_client *slave; 158 159 struct resource *res; 160 struct dma_chan *dma_tx; 161 struct dma_chan *dma_rx; 162 struct scatterlist sg; 163 enum dma_data_direction dma_direction; 164 165 struct reset_control *rstc; 166 int irq; 167 168 struct i2c_client *host_notify_client; 169 }; 170 171 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) 172 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) 173 174 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) 175 { 176 writel(val, priv->io + reg); 177 } 178 179 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) 180 { 181 return readl(priv->io + reg); 182 } 183 184 static void rcar_i2c_clear_irq(struct rcar_i2c_priv *priv, u32 val) 185 { 186 writel(~val & 0x7f, priv->io + ICMSR); 187 } 188 189 static int rcar_i2c_get_scl(struct i2c_adapter *adap) 190 { 191 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 192 193 return !!(rcar_i2c_read(priv, ICMCR) & FSCL); 194 195 }; 196 197 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val) 198 { 199 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 200 201 if (val) 202 priv->recovery_icmcr |= FSCL; 203 else 204 priv->recovery_icmcr &= ~FSCL; 205 206 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 207 }; 208 209 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val) 210 { 211 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 212 213 if (val) 214 priv->recovery_icmcr |= FSDA; 215 else 216 priv->recovery_icmcr &= ~FSDA; 217 218 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 219 }; 220 221 static int rcar_i2c_get_bus_free(struct i2c_adapter *adap) 222 { 223 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 224 225 return !(rcar_i2c_read(priv, ICMCR) & FSDA); 226 227 }; 228 229 static struct i2c_bus_recovery_info rcar_i2c_bri = { 230 .get_scl = rcar_i2c_get_scl, 231 .set_scl = rcar_i2c_set_scl, 232 .set_sda = rcar_i2c_set_sda, 233 .get_bus_free = rcar_i2c_get_bus_free, 234 .recover_bus = i2c_generic_scl_recovery, 235 }; 236 static void rcar_i2c_init(struct rcar_i2c_priv *priv) 237 { 238 /* reset master mode */ 239 rcar_i2c_write(priv, ICMIER, 0); 240 rcar_i2c_write(priv, ICMCR, MDBS); 241 rcar_i2c_write(priv, ICMSR, 0); 242 /* start clock */ 243 if (priv->devtype < I2C_RCAR_GEN3) { 244 rcar_i2c_write(priv, ICCCR, priv->icccr); 245 } else { 246 u32 icccr2 = CDFD | HLSE | SME; 247 248 if (priv->flags & ID_P_FMPLUS) 249 icccr2 |= FMPE; 250 251 rcar_i2c_write(priv, ICCCR2, icccr2); 252 rcar_i2c_write(priv, ICCCR, priv->icccr); 253 rcar_i2c_write(priv, ICMPR, priv->smd); 254 rcar_i2c_write(priv, ICHPR, priv->schd); 255 rcar_i2c_write(priv, ICLPR, priv->scld); 256 rcar_i2c_write(priv, ICFBSCR, TCYC17); 257 } 258 } 259 260 static void rcar_i2c_reset_slave(struct rcar_i2c_priv *priv) 261 { 262 rcar_i2c_write(priv, ICSIER, 0); 263 rcar_i2c_write(priv, ICSSR, 0); 264 rcar_i2c_write(priv, ICSCR, SDBS); 265 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */ 266 } 267 268 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) 269 { 270 int ret; 271 u32 val; 272 273 ret = readl_poll_timeout(priv->io + ICMCR, val, !(val & FSDA), 10, 274 priv->adap.timeout); 275 if (ret) { 276 /* Waiting did not help, try to recover */ 277 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL; 278 ret = i2c_recover_bus(&priv->adap); 279 } 280 281 return ret; 282 } 283 284 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv) 285 { 286 u32 cdf, round, ick, sum, scl, cdf_width; 287 unsigned long rate; 288 struct device *dev = rcar_i2c_priv_to_dev(priv); 289 struct i2c_timings t = { 290 .bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ, 291 .scl_fall_ns = 35, 292 .scl_rise_ns = 200, 293 .scl_int_delay_ns = 50, 294 }; 295 296 /* Fall back to previously used values if not supplied */ 297 i2c_parse_fw_timings(dev, &t, false); 298 priv->smd = RCAR_DEFAULT_SMD; 299 300 /* 301 * calculate SCL clock 302 * see 303 * ICCCR (and ICCCR2 for Gen3+) 304 * 305 * ick = clkp / (1 + CDF) 306 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 307 * 308 * for Gen3+: 309 * SCL = clkp / (8 + SMD * 2 + SCLD + SCHD +F[(ticf + tr + intd) * clkp]) 310 * 311 * ick : I2C internal clock < 20 MHz 312 * ticf : I2C SCL falling time 313 * tr : I2C SCL rising time 314 * intd : LSI internal delay 315 * clkp : peripheral_clk 316 * F[] : integer up-valuation 317 */ 318 rate = clk_get_rate(priv->clk); 319 cdf = rate / 20000000; 320 cdf_width = (priv->devtype == I2C_RCAR_GEN1) ? 2 : 3; 321 if (cdf >= 1U << cdf_width) 322 goto err_no_val; 323 324 if (t.bus_freq_hz > I2C_MAX_FAST_MODE_FREQ && priv->devtype >= I2C_RCAR_GEN4) 325 priv->flags |= ID_P_FMPLUS; 326 else 327 priv->flags &= ~ID_P_FMPLUS; 328 329 /* On Gen3+, we use cdf only for the filters, not as a SCL divider */ 330 ick = rate / (priv->devtype < I2C_RCAR_GEN3 ? (cdf + 1) : 1); 331 332 /* 333 * It is impossible to calculate a large scale number on u32. Separate it. 334 * 335 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd) 336 * = F[sum * ick / 1000000000] 337 * = F[(ick / 1000000) * sum / 1000] 338 */ 339 sum = t.scl_fall_ns + t.scl_rise_ns + t.scl_int_delay_ns; 340 round = DIV_ROUND_CLOSEST(ick, 1000000); 341 round = DIV_ROUND_CLOSEST(round * sum, 1000); 342 343 if (priv->devtype < I2C_RCAR_GEN3) { 344 u32 scgd; 345 /* 346 * SCL = ick / (20 + 8 * SCGD + F[(ticf + tr + intd) * ick]) 347 * 20 + 8 * SCGD + F[...] = ick / SCL 348 * SCGD = ((ick / SCL) - 20 - F[...]) / 8 349 * Result (= SCL) should be less than bus_speed for hardware safety 350 */ 351 scgd = DIV_ROUND_UP(ick, t.bus_freq_hz ?: 1); 352 scgd = DIV_ROUND_UP(scgd - 20 - round, 8); 353 scl = ick / (20 + 8 * scgd + round); 354 355 if (scgd > 0x3f) 356 goto err_no_val; 357 358 dev_dbg(dev, "clk %u/%u(%lu), round %u, CDF: %u, SCGD: %u\n", 359 scl, t.bus_freq_hz, rate, round, cdf, scgd); 360 361 priv->icccr = scgd << cdf_width | cdf; 362 } else { 363 u32 x, sum_ratio = RCAR_SCHD_RATIO + RCAR_SCLD_RATIO; 364 /* 365 * SCLD/SCHD ratio and SMD default value are explained above 366 * where they are defined. With these definitions, we can compute 367 * x as a base value for the SCLD/SCHD ratio: 368 * 369 * SCL = clkp / (8 + 2 * SMD + SCLD + SCHD + F[(ticf + tr + intd) * clkp]) 370 * SCL = clkp / (8 + 2 * SMD + RCAR_SCLD_RATIO * x 371 * + RCAR_SCHD_RATIO * x + F[...]) 372 * 373 * with: sum_ratio = RCAR_SCLD_RATIO + RCAR_SCHD_RATIO 374 * 375 * SCL = clkp / (8 + 2 * smd + sum_ratio * x + F[...]) 376 * 8 + 2 * smd + sum_ratio * x + F[...] = clkp / SCL 377 * x = ((clkp / SCL) - 8 - 2 * smd - F[...]) / sum_ratio 378 */ 379 x = DIV_ROUND_UP(rate, t.bus_freq_hz ?: 1); 380 x = DIV_ROUND_UP(x - 8 - 2 * priv->smd - round, sum_ratio); 381 scl = rate / (8 + 2 * priv->smd + sum_ratio * x + round); 382 383 if (x == 0 || x * RCAR_SCLD_RATIO > 0xffff) 384 goto err_no_val; 385 386 priv->icccr = cdf; 387 priv->schd = RCAR_SCHD_RATIO * x; 388 priv->scld = RCAR_SCLD_RATIO * x; 389 if (priv->smd >= priv->schd) 390 priv->smd = priv->schd - 1; 391 392 dev_dbg(dev, "clk %u/%u(%lu), round %u, CDF: %u SCHD %u SCLD %u SMD %u\n", 393 scl, t.bus_freq_hz, rate, round, cdf, priv->schd, priv->scld, priv->smd); 394 } 395 396 return 0; 397 398 err_no_val: 399 dev_err(dev, "it is impossible to calculate best SCL\n"); 400 return -EINVAL; 401 } 402 403 /* 404 * We don't have a test case but the HW engineers say that the write order of 405 * ICMSR and ICMCR depends on whether we issue START or REP_START. So, ICMSR 406 * handling is outside of this function. First messages clear ICMSR before this 407 * function, interrupt handlers clear the relevant bits after this function. 408 */ 409 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) 410 { 411 int read = !!rcar_i2c_is_recv(priv); 412 bool rep_start = !(priv->flags & ID_REP_AFTER_RD); 413 414 priv->pos = 0; 415 priv->flags &= ID_P_MASK; 416 417 if (priv->msgs_left == 1) 418 priv->flags |= ID_LAST_MSG; 419 420 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg)); 421 if (priv->flags & ID_P_NOT_ATOMIC) 422 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); 423 424 if (rep_start) 425 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 426 } 427 428 static void rcar_i2c_first_msg(struct rcar_i2c_priv *priv, 429 struct i2c_msg *msgs, int num) 430 { 431 priv->msg = msgs; 432 priv->msgs_left = num; 433 rcar_i2c_write(priv, ICMSR, 0); /* must be before preparing msg */ 434 rcar_i2c_prepare_msg(priv); 435 } 436 437 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) 438 { 439 priv->msg++; 440 priv->msgs_left--; 441 rcar_i2c_prepare_msg(priv); 442 /* ICMSR handling must come afterwards in the irq handler */ 443 } 444 445 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv, bool terminate) 446 { 447 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE 448 ? priv->dma_rx : priv->dma_tx; 449 450 /* only allowed from thread context! */ 451 if (terminate) 452 dmaengine_terminate_sync(chan); 453 454 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), 455 sg_dma_len(&priv->sg), priv->dma_direction); 456 457 /* Gen3+ can only do one RXDMA per transfer and we just completed it */ 458 if (priv->devtype >= I2C_RCAR_GEN3 && 459 priv->dma_direction == DMA_FROM_DEVICE) 460 priv->flags |= ID_P_NO_RXDMA; 461 462 priv->dma_direction = DMA_NONE; 463 464 /* Disable DMA Master Received/Transmitted, must be last! */ 465 rcar_i2c_write(priv, ICDMAER, 0); 466 } 467 468 static void rcar_i2c_dma_callback(void *data) 469 { 470 struct rcar_i2c_priv *priv = data; 471 472 priv->pos += sg_dma_len(&priv->sg); 473 474 rcar_i2c_cleanup_dma(priv, false); 475 } 476 477 static bool rcar_i2c_dma(struct rcar_i2c_priv *priv) 478 { 479 struct device *dev = rcar_i2c_priv_to_dev(priv); 480 struct i2c_msg *msg = priv->msg; 481 bool read = msg->flags & I2C_M_RD; 482 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 483 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx; 484 struct dma_async_tx_descriptor *txdesc; 485 dma_addr_t dma_addr; 486 dma_cookie_t cookie; 487 unsigned char *buf; 488 int len; 489 490 /* Do various checks to see if DMA is feasible at all */ 491 if (!(priv->flags & ID_P_NOT_ATOMIC) || IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN || 492 !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA)) 493 return false; 494 495 if (read) { 496 /* 497 * The last two bytes needs to be fetched using PIO in 498 * order for the STOP phase to work. 499 */ 500 buf = priv->msg->buf; 501 len = priv->msg->len - 2; 502 } else { 503 /* 504 * First byte in message was sent using PIO. 505 */ 506 buf = priv->msg->buf + 1; 507 len = priv->msg->len - 1; 508 } 509 510 dma_addr = dma_map_single(chan->device->dev, buf, len, dir); 511 if (dma_mapping_error(chan->device->dev, dma_addr)) { 512 dev_dbg(dev, "dma map failed, using PIO\n"); 513 return false; 514 } 515 516 sg_dma_len(&priv->sg) = len; 517 sg_dma_address(&priv->sg) = dma_addr; 518 519 priv->dma_direction = dir; 520 521 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1, 522 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 523 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 524 if (!txdesc) { 525 dev_dbg(dev, "dma prep slave sg failed, using PIO\n"); 526 rcar_i2c_cleanup_dma(priv, false); 527 return false; 528 } 529 530 txdesc->callback = rcar_i2c_dma_callback; 531 txdesc->callback_param = priv; 532 533 cookie = dmaengine_submit(txdesc); 534 if (dma_submit_error(cookie)) { 535 dev_dbg(dev, "submitting dma failed, using PIO\n"); 536 rcar_i2c_cleanup_dma(priv, false); 537 return false; 538 } 539 540 /* Enable DMA Master Received/Transmitted */ 541 if (read) 542 rcar_i2c_write(priv, ICDMAER, RMDMAE); 543 else 544 rcar_i2c_write(priv, ICDMAER, TMDMAE); 545 546 dma_async_issue_pending(chan); 547 return true; 548 } 549 550 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) 551 { 552 struct i2c_msg *msg = priv->msg; 553 u32 irqs_to_clear = MDE; 554 555 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 556 if (!(msr & MDE)) 557 return; 558 559 if (msr & MAT) 560 irqs_to_clear |= MAT; 561 562 /* Check if DMA can be enabled and take over */ 563 if (priv->pos == 1 && rcar_i2c_dma(priv)) 564 return; 565 566 if (priv->pos < msg->len) { 567 /* 568 * Prepare next data to ICRXTX register. 569 * This data will go to _SHIFT_ register. 570 * 571 * * 572 * [ICRXTX] -> [SHIFT] -> [I2C bus] 573 */ 574 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); 575 priv->pos++; 576 } else { 577 /* 578 * The last data was pushed to ICRXTX on _PREV_ empty irq. 579 * It is on _SHIFT_ register, and will sent to I2C bus. 580 * 581 * * 582 * [ICRXTX] -> [SHIFT] -> [I2C bus] 583 */ 584 585 if (priv->flags & ID_LAST_MSG) 586 /* 587 * If current msg is the _LAST_ msg, 588 * prepare stop condition here. 589 * ID_DONE will be set on STOP irq. 590 */ 591 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 592 else 593 rcar_i2c_next_msg(priv); 594 } 595 596 rcar_i2c_clear_irq(priv, irqs_to_clear); 597 } 598 599 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) 600 { 601 struct i2c_msg *msg = priv->msg; 602 bool recv_len_init = priv->pos == 0 && msg->flags & I2C_M_RECV_LEN; 603 u32 irqs_to_clear = MDR; 604 605 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 606 if (!(msr & MDR)) 607 return; 608 609 if (msr & MAT) { 610 irqs_to_clear |= MAT; 611 /* 612 * Address transfer phase finished, but no data at this point. 613 * Try to use DMA to receive data. 614 */ 615 rcar_i2c_dma(priv); 616 } else if (priv->pos < msg->len) { 617 /* get received data */ 618 u8 data = rcar_i2c_read(priv, ICRXTX); 619 620 msg->buf[priv->pos] = data; 621 if (recv_len_init) { 622 if (data == 0 || data > I2C_SMBUS_BLOCK_MAX) { 623 priv->flags |= ID_DONE | ID_EPROTO; 624 return; 625 } 626 msg->len += msg->buf[0]; 627 /* Enough data for DMA? */ 628 if (rcar_i2c_dma(priv)) 629 return; 630 /* new length after RECV_LEN now properly initialized */ 631 recv_len_init = false; 632 } 633 priv->pos++; 634 } 635 636 /* 637 * If next received data is the _LAST_ and we are not waiting for a new 638 * length because of RECV_LEN, then go to a new phase. 639 */ 640 if (priv->pos + 1 == msg->len && !recv_len_init) { 641 if (priv->flags & ID_LAST_MSG) { 642 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 643 } else { 644 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 645 priv->flags |= ID_REP_AFTER_RD; 646 } 647 } 648 649 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG)) 650 rcar_i2c_next_msg(priv); 651 652 rcar_i2c_clear_irq(priv, irqs_to_clear); 653 } 654 655 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) 656 { 657 u32 ssr_raw, ssr_filtered; 658 u8 value; 659 660 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; 661 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); 662 663 if (!ssr_filtered) 664 return false; 665 666 /* address detected */ 667 if (ssr_filtered & SAR) { 668 /* read or write request */ 669 if (ssr_raw & STM) { 670 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); 671 rcar_i2c_write(priv, ICRXTX, value); 672 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); 673 } else { 674 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); 675 rcar_i2c_read(priv, ICRXTX); /* dummy read */ 676 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); 677 } 678 679 /* Clear SSR, too, because of old STOPs to other clients than us */ 680 rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff); 681 } 682 683 /* master sent stop */ 684 if (ssr_filtered & SSR) { 685 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); 686 rcar_i2c_write(priv, ICSCR, SIE | SDBS); /* clear our NACK */ 687 rcar_i2c_write(priv, ICSIER, SAR); 688 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); 689 } 690 691 /* master wants to write to us */ 692 if (ssr_filtered & SDR) { 693 int ret; 694 695 value = rcar_i2c_read(priv, ICRXTX); 696 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); 697 /* Send NACK in case of error */ 698 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); 699 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); 700 } 701 702 /* master wants to read from us */ 703 if (ssr_filtered & SDE) { 704 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); 705 rcar_i2c_write(priv, ICRXTX, value); 706 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); 707 } 708 709 return true; 710 } 711 712 /* 713 * This driver has a lock-free design because there are IP cores (at least 714 * R-Car Gen2) which have an inherent race condition in their hardware design. 715 * There, we need to switch to RCAR_BUS_PHASE_DATA as soon as possible after 716 * the interrupt was generated, otherwise an unwanted repeated message gets 717 * generated. It turned out that taking a spinlock at the beginning of the ISR 718 * was already causing repeated messages. Thus, this driver was converted to 719 * the now lockless behaviour. Please keep this in mind when hacking the driver. 720 * R-Car Gen3 seems to have this fixed but earlier versions than R-Car Gen2 are 721 * likely affected. Therefore, we have different interrupt handler entries. 722 */ 723 static irqreturn_t rcar_i2c_irq(int irq, struct rcar_i2c_priv *priv, u32 msr) 724 { 725 if (!msr) { 726 if (rcar_i2c_slave_irq(priv)) 727 return IRQ_HANDLED; 728 729 return IRQ_NONE; 730 } 731 732 /* Arbitration lost */ 733 if (msr & MAL) { 734 priv->flags |= ID_DONE | ID_ARBLOST; 735 goto out; 736 } 737 738 /* Nack */ 739 if (msr & MNR) { 740 /* HW automatically sends STOP after received NACK */ 741 if (priv->flags & ID_P_NOT_ATOMIC) 742 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); 743 priv->flags |= ID_NACK; 744 goto out; 745 } 746 747 /* Stop */ 748 if (msr & MST) { 749 priv->msgs_left--; /* The last message also made it */ 750 priv->flags |= ID_DONE; 751 goto out; 752 } 753 754 if (rcar_i2c_is_recv(priv)) 755 rcar_i2c_irq_recv(priv, msr); 756 else 757 rcar_i2c_irq_send(priv, msr); 758 759 out: 760 if (priv->flags & ID_DONE) { 761 rcar_i2c_write(priv, ICMIER, 0); 762 rcar_i2c_write(priv, ICMSR, 0); 763 if (priv->flags & ID_P_NOT_ATOMIC) 764 wake_up(&priv->wait); 765 } 766 767 return IRQ_HANDLED; 768 } 769 770 static irqreturn_t rcar_i2c_gen2_irq(int irq, void *ptr) 771 { 772 struct rcar_i2c_priv *priv = ptr; 773 u32 msr; 774 775 /* Clear START or STOP immediately, except for REPSTART after read */ 776 if (likely(!(priv->flags & ID_REP_AFTER_RD))) 777 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); 778 779 /* Only handle interrupts that are currently enabled */ 780 msr = rcar_i2c_read(priv, ICMSR); 781 if (priv->flags & ID_P_NOT_ATOMIC) 782 msr &= rcar_i2c_read(priv, ICMIER); 783 784 return rcar_i2c_irq(irq, priv, msr); 785 } 786 787 static irqreturn_t rcar_i2c_gen3_irq(int irq, void *ptr) 788 { 789 struct rcar_i2c_priv *priv = ptr; 790 u32 msr; 791 792 /* Only handle interrupts that are currently enabled */ 793 msr = rcar_i2c_read(priv, ICMSR); 794 if (priv->flags & ID_P_NOT_ATOMIC) 795 msr &= rcar_i2c_read(priv, ICMIER); 796 797 /* 798 * Clear START or STOP immediately, except for REPSTART after read or 799 * if a spurious interrupt was detected. 800 */ 801 if (likely(!(priv->flags & ID_REP_AFTER_RD) && msr)) 802 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); 803 804 return rcar_i2c_irq(irq, priv, msr); 805 } 806 807 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev, 808 enum dma_transfer_direction dir, 809 dma_addr_t port_addr) 810 { 811 struct dma_chan *chan; 812 struct dma_slave_config cfg; 813 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; 814 int ret; 815 816 chan = dma_request_chan(dev, chan_name); 817 if (IS_ERR(chan)) { 818 dev_dbg(dev, "request_channel failed for %s (%ld)\n", 819 chan_name, PTR_ERR(chan)); 820 return chan; 821 } 822 823 memset(&cfg, 0, sizeof(cfg)); 824 cfg.direction = dir; 825 if (dir == DMA_MEM_TO_DEV) { 826 cfg.dst_addr = port_addr; 827 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 828 } else { 829 cfg.src_addr = port_addr; 830 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 831 } 832 833 ret = dmaengine_slave_config(chan, &cfg); 834 if (ret) { 835 dev_dbg(dev, "slave_config failed for %s (%d)\n", 836 chan_name, ret); 837 dma_release_channel(chan); 838 return ERR_PTR(ret); 839 } 840 841 dev_dbg(dev, "got DMA channel for %s\n", chan_name); 842 return chan; 843 } 844 845 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv, 846 struct i2c_msg *msg) 847 { 848 struct device *dev = rcar_i2c_priv_to_dev(priv); 849 bool read; 850 struct dma_chan *chan; 851 enum dma_transfer_direction dir; 852 853 read = msg->flags & I2C_M_RD; 854 855 chan = read ? priv->dma_rx : priv->dma_tx; 856 if (PTR_ERR(chan) != -EPROBE_DEFER) 857 return; 858 859 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 860 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX); 861 862 if (read) 863 priv->dma_rx = chan; 864 else 865 priv->dma_tx = chan; 866 } 867 868 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv) 869 { 870 if (!IS_ERR(priv->dma_tx)) { 871 dma_release_channel(priv->dma_tx); 872 priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 873 } 874 875 if (!IS_ERR(priv->dma_rx)) { 876 dma_release_channel(priv->dma_rx); 877 priv->dma_rx = ERR_PTR(-EPROBE_DEFER); 878 } 879 } 880 881 /* I2C is a special case, we need to poll the status of a reset */ 882 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv) 883 { 884 int ret; 885 886 /* Don't reset if a slave instance is currently running */ 887 if (priv->slave) 888 return -EISCONN; 889 890 ret = reset_control_reset(priv->rstc); 891 if (ret) 892 return ret; 893 894 return read_poll_timeout_atomic(reset_control_status, ret, ret == 0, 1, 895 100, false, priv->rstc); 896 } 897 898 static int rcar_i2c_master_xfer(struct i2c_adapter *adap, 899 struct i2c_msg *msgs, 900 int num) 901 { 902 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 903 struct device *dev = rcar_i2c_priv_to_dev(priv); 904 int i, ret; 905 long time_left; 906 907 priv->flags |= ID_P_NOT_ATOMIC; 908 909 pm_runtime_get_sync(dev); 910 911 /* Check bus state before init otherwise bus busy info will be lost */ 912 ret = rcar_i2c_bus_barrier(priv); 913 if (ret < 0) 914 goto out; 915 916 /* Gen3+ needs a reset. That also allows RXDMA once */ 917 if (priv->devtype >= I2C_RCAR_GEN3) { 918 ret = rcar_i2c_do_reset(priv); 919 if (ret) 920 goto out; 921 priv->flags &= ~ID_P_NO_RXDMA; 922 } 923 924 rcar_i2c_init(priv); 925 926 for (i = 0; i < num; i++) 927 rcar_i2c_request_dma(priv, msgs + i); 928 929 rcar_i2c_first_msg(priv, msgs, num); 930 931 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE, 932 num * adap->timeout); 933 934 /* cleanup DMA if it couldn't complete properly due to an error */ 935 if (priv->dma_direction != DMA_NONE) 936 rcar_i2c_cleanup_dma(priv, true); 937 938 if (!time_left) { 939 rcar_i2c_init(priv); 940 ret = -ETIMEDOUT; 941 } else if (priv->flags & ID_NACK) { 942 ret = -ENXIO; 943 } else if (priv->flags & ID_ARBLOST) { 944 ret = -EAGAIN; 945 } else if (priv->flags & ID_EPROTO) { 946 ret = -EPROTO; 947 } else { 948 ret = num - priv->msgs_left; /* The number of transfer */ 949 } 950 out: 951 pm_runtime_put(dev); 952 953 if (ret < 0 && ret != -ENXIO) 954 dev_err(dev, "error %d : %x\n", ret, priv->flags); 955 956 return ret; 957 } 958 959 static int rcar_i2c_master_xfer_atomic(struct i2c_adapter *adap, 960 struct i2c_msg *msgs, 961 int num) 962 { 963 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 964 struct device *dev = rcar_i2c_priv_to_dev(priv); 965 unsigned long j; 966 bool time_left; 967 int ret; 968 969 priv->flags &= ~ID_P_NOT_ATOMIC; 970 971 pm_runtime_get_sync(dev); 972 973 /* Check bus state before init otherwise bus busy info will be lost */ 974 ret = rcar_i2c_bus_barrier(priv); 975 if (ret < 0) 976 goto out; 977 978 rcar_i2c_init(priv); 979 rcar_i2c_first_msg(priv, msgs, num); 980 981 j = jiffies + num * adap->timeout; 982 do { 983 u32 msr = rcar_i2c_read(priv, ICMSR); 984 985 msr &= (rcar_i2c_is_recv(priv) ? RCAR_IRQ_RECV : RCAR_IRQ_SEND) | RCAR_IRQ_STOP; 986 987 if (msr) { 988 if (priv->devtype < I2C_RCAR_GEN3) 989 rcar_i2c_gen2_irq(0, priv); 990 else 991 rcar_i2c_gen3_irq(0, priv); 992 } 993 994 time_left = time_before_eq(jiffies, j); 995 } while (!(priv->flags & ID_DONE) && time_left); 996 997 if (!time_left) { 998 rcar_i2c_init(priv); 999 ret = -ETIMEDOUT; 1000 } else if (priv->flags & ID_NACK) { 1001 ret = -ENXIO; 1002 } else if (priv->flags & ID_ARBLOST) { 1003 ret = -EAGAIN; 1004 } else if (priv->flags & ID_EPROTO) { 1005 ret = -EPROTO; 1006 } else { 1007 ret = num - priv->msgs_left; /* The number of transfer */ 1008 } 1009 out: 1010 pm_runtime_put(dev); 1011 1012 if (ret < 0 && ret != -ENXIO) 1013 dev_err(dev, "error %d : %x\n", ret, priv->flags); 1014 1015 return ret; 1016 } 1017 1018 static int rcar_reg_slave(struct i2c_client *slave) 1019 { 1020 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 1021 1022 if (priv->slave) 1023 return -EBUSY; 1024 1025 if (slave->flags & I2C_CLIENT_TEN) 1026 return -EAFNOSUPPORT; 1027 1028 /* Keep device active for slave address detection logic */ 1029 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv)); 1030 1031 priv->slave = slave; 1032 rcar_i2c_write(priv, ICSAR, slave->addr); 1033 rcar_i2c_write(priv, ICSSR, 0); 1034 rcar_i2c_write(priv, ICSIER, SAR); 1035 rcar_i2c_write(priv, ICSCR, SIE | SDBS); 1036 1037 return 0; 1038 } 1039 1040 static int rcar_unreg_slave(struct i2c_client *slave) 1041 { 1042 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 1043 1044 WARN_ON(!priv->slave); 1045 1046 /* ensure no irq is running before clearing ptr */ 1047 disable_irq(priv->irq); 1048 rcar_i2c_reset_slave(priv); 1049 enable_irq(priv->irq); 1050 1051 priv->slave = NULL; 1052 1053 pm_runtime_put(rcar_i2c_priv_to_dev(priv)); 1054 1055 return 0; 1056 } 1057 1058 static u32 rcar_i2c_func(struct i2c_adapter *adap) 1059 { 1060 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 1061 1062 /* 1063 * This HW can't do: 1064 * I2C_SMBUS_QUICK (setting FSB during START didn't work) 1065 * I2C_M_NOSTART (automatically sends address after START) 1066 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK) 1067 */ 1068 u32 func = I2C_FUNC_I2C | I2C_FUNC_SLAVE | 1069 (I2C_FUNC_SMBUS_EMUL_ALL & ~I2C_FUNC_SMBUS_QUICK); 1070 1071 if (priv->flags & ID_P_HOST_NOTIFY) 1072 func |= I2C_FUNC_SMBUS_HOST_NOTIFY; 1073 1074 return func; 1075 } 1076 1077 static const struct i2c_algorithm rcar_i2c_algo = { 1078 .master_xfer = rcar_i2c_master_xfer, 1079 .master_xfer_atomic = rcar_i2c_master_xfer_atomic, 1080 .functionality = rcar_i2c_func, 1081 .reg_slave = rcar_reg_slave, 1082 .unreg_slave = rcar_unreg_slave, 1083 }; 1084 1085 static const struct i2c_adapter_quirks rcar_i2c_quirks = { 1086 .flags = I2C_AQ_NO_ZERO_LEN, 1087 }; 1088 1089 static const struct of_device_id rcar_i2c_dt_ids[] = { 1090 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, 1091 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, 1092 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, 1093 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, 1094 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, 1095 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, 1096 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, 1097 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, 1098 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 }, 1099 /* S4 has no FM+ bit */ 1100 { .compatible = "renesas,i2c-r8a779f0", .data = (void *)I2C_RCAR_GEN3 }, 1101 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 }, 1102 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 }, 1103 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 }, 1104 { .compatible = "renesas,rcar-gen4-i2c", .data = (void *)I2C_RCAR_GEN4 }, 1105 {}, 1106 }; 1107 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); 1108 1109 static int rcar_i2c_probe(struct platform_device *pdev) 1110 { 1111 struct rcar_i2c_priv *priv; 1112 struct i2c_adapter *adap; 1113 struct device *dev = &pdev->dev; 1114 unsigned long irqflags = 0; 1115 irqreturn_t (*irqhandler)(int irq, void *ptr) = rcar_i2c_gen3_irq; 1116 int ret; 1117 1118 /* Otherwise logic will break because some bytes must always use PIO */ 1119 BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length"); 1120 1121 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); 1122 if (!priv) 1123 return -ENOMEM; 1124 1125 priv->clk = devm_clk_get(dev, NULL); 1126 if (IS_ERR(priv->clk)) { 1127 dev_err(dev, "cannot get clock\n"); 1128 return PTR_ERR(priv->clk); 1129 } 1130 1131 priv->io = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->res); 1132 if (IS_ERR(priv->io)) 1133 return PTR_ERR(priv->io); 1134 1135 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev); 1136 init_waitqueue_head(&priv->wait); 1137 1138 adap = &priv->adap; 1139 adap->nr = pdev->id; 1140 adap->algo = &rcar_i2c_algo; 1141 adap->class = I2C_CLASS_DEPRECATED; 1142 adap->retries = 3; 1143 adap->dev.parent = dev; 1144 adap->dev.of_node = dev->of_node; 1145 adap->bus_recovery_info = &rcar_i2c_bri; 1146 adap->quirks = &rcar_i2c_quirks; 1147 i2c_set_adapdata(adap, priv); 1148 strscpy(adap->name, pdev->name, sizeof(adap->name)); 1149 1150 /* Init DMA */ 1151 sg_init_table(&priv->sg, 1); 1152 priv->dma_direction = DMA_NONE; 1153 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 1154 1155 /* Activate device for clock calculation */ 1156 pm_runtime_enable(dev); 1157 pm_runtime_get_sync(dev); 1158 ret = rcar_i2c_clock_calculate(priv); 1159 if (ret < 0) { 1160 pm_runtime_put(dev); 1161 goto out_pm_disable; 1162 } 1163 1164 /* Bring hardware to known state */ 1165 rcar_i2c_init(priv); 1166 rcar_i2c_reset_slave(priv); 1167 1168 if (priv->devtype < I2C_RCAR_GEN3) { 1169 irqflags |= IRQF_NO_THREAD; 1170 irqhandler = rcar_i2c_gen2_irq; 1171 } 1172 1173 /* Stay always active when multi-master to keep arbitration working */ 1174 if (of_property_read_bool(dev->of_node, "multi-master")) 1175 priv->flags |= ID_P_PM_BLOCKED; 1176 else 1177 pm_runtime_put(dev); 1178 1179 if (of_property_read_bool(dev->of_node, "smbus")) 1180 priv->flags |= ID_P_HOST_NOTIFY; 1181 1182 /* R-Car Gen3+ needs a reset before every transfer */ 1183 if (priv->devtype >= I2C_RCAR_GEN3) { 1184 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1185 if (IS_ERR(priv->rstc)) { 1186 ret = PTR_ERR(priv->rstc); 1187 goto out_pm_put; 1188 } 1189 1190 ret = reset_control_status(priv->rstc); 1191 if (ret < 0) 1192 goto out_pm_put; 1193 1194 /* hard reset disturbs HostNotify local target, so disable it */ 1195 priv->flags &= ~ID_P_HOST_NOTIFY; 1196 } 1197 1198 ret = platform_get_irq(pdev, 0); 1199 if (ret < 0) 1200 goto out_pm_put; 1201 priv->irq = ret; 1202 ret = devm_request_irq(dev, priv->irq, irqhandler, irqflags, dev_name(dev), priv); 1203 if (ret < 0) { 1204 dev_err(dev, "cannot get irq %d\n", priv->irq); 1205 goto out_pm_put; 1206 } 1207 1208 platform_set_drvdata(pdev, priv); 1209 1210 ret = i2c_add_numbered_adapter(adap); 1211 if (ret < 0) 1212 goto out_pm_put; 1213 1214 if (priv->flags & ID_P_HOST_NOTIFY) { 1215 priv->host_notify_client = i2c_new_slave_host_notify_device(adap); 1216 if (IS_ERR(priv->host_notify_client)) { 1217 ret = PTR_ERR(priv->host_notify_client); 1218 goto out_del_device; 1219 } 1220 } 1221 1222 dev_info(dev, "probed\n"); 1223 1224 return 0; 1225 1226 out_del_device: 1227 i2c_del_adapter(&priv->adap); 1228 out_pm_put: 1229 if (priv->flags & ID_P_PM_BLOCKED) 1230 pm_runtime_put(dev); 1231 out_pm_disable: 1232 pm_runtime_disable(dev); 1233 return ret; 1234 } 1235 1236 static void rcar_i2c_remove(struct platform_device *pdev) 1237 { 1238 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); 1239 struct device *dev = &pdev->dev; 1240 1241 if (priv->host_notify_client) 1242 i2c_free_slave_host_notify_device(priv->host_notify_client); 1243 i2c_del_adapter(&priv->adap); 1244 rcar_i2c_release_dma(priv); 1245 if (priv->flags & ID_P_PM_BLOCKED) 1246 pm_runtime_put(dev); 1247 pm_runtime_disable(dev); 1248 } 1249 1250 static int rcar_i2c_suspend(struct device *dev) 1251 { 1252 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1253 1254 i2c_mark_adapter_suspended(&priv->adap); 1255 return 0; 1256 } 1257 1258 static int rcar_i2c_resume(struct device *dev) 1259 { 1260 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1261 1262 i2c_mark_adapter_resumed(&priv->adap); 1263 return 0; 1264 } 1265 1266 static const struct dev_pm_ops rcar_i2c_pm_ops = { 1267 NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume) 1268 }; 1269 1270 static struct platform_driver rcar_i2c_driver = { 1271 .driver = { 1272 .name = "i2c-rcar", 1273 .of_match_table = rcar_i2c_dt_ids, 1274 .pm = pm_sleep_ptr(&rcar_i2c_pm_ops), 1275 }, 1276 .probe = rcar_i2c_probe, 1277 .remove_new = rcar_i2c_remove, 1278 }; 1279 1280 module_platform_driver(rcar_i2c_driver); 1281 1282 MODULE_LICENSE("GPL v2"); 1283 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); 1284 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); 1285