1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Renesas R-Car I2C unit 4 * 5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com> 6 * Copyright (C) 2011-2019 Renesas Electronics Corporation 7 * 8 * Copyright (C) 2012-14 Renesas Solutions Corp. 9 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 10 * 11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c 12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> 13 */ 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dmaengine.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/i2c.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/reset.h> 29 #include <linux/slab.h> 30 31 /* register offsets */ 32 #define ICSCR 0x00 /* slave ctrl */ 33 #define ICMCR 0x04 /* master ctrl */ 34 #define ICSSR 0x08 /* slave status */ 35 #define ICMSR 0x0C /* master status */ 36 #define ICSIER 0x10 /* slave irq enable */ 37 #define ICMIER 0x14 /* master irq enable */ 38 #define ICCCR 0x18 /* clock dividers */ 39 #define ICSAR 0x1C /* slave address */ 40 #define ICMAR 0x20 /* master address */ 41 #define ICRXTX 0x24 /* data port */ 42 #define ICFBSCR 0x38 /* first bit setup cycle (Gen3) */ 43 #define ICDMAER 0x3c /* DMA enable (Gen3) */ 44 45 /* ICSCR */ 46 #define SDBS (1 << 3) /* slave data buffer select */ 47 #define SIE (1 << 2) /* slave interface enable */ 48 #define GCAE (1 << 1) /* general call address enable */ 49 #define FNA (1 << 0) /* forced non acknowledgment */ 50 51 /* ICMCR */ 52 #define MDBS (1 << 7) /* non-fifo mode switch */ 53 #define FSCL (1 << 6) /* override SCL pin */ 54 #define FSDA (1 << 5) /* override SDA pin */ 55 #define OBPC (1 << 4) /* override pins */ 56 #define MIE (1 << 3) /* master if enable */ 57 #define TSBE (1 << 2) 58 #define FSB (1 << 1) /* force stop bit */ 59 #define ESG (1 << 0) /* enable start bit gen */ 60 61 /* ICSSR (also for ICSIER) */ 62 #define GCAR (1 << 6) /* general call received */ 63 #define STM (1 << 5) /* slave transmit mode */ 64 #define SSR (1 << 4) /* stop received */ 65 #define SDE (1 << 3) /* slave data empty */ 66 #define SDT (1 << 2) /* slave data transmitted */ 67 #define SDR (1 << 1) /* slave data received */ 68 #define SAR (1 << 0) /* slave addr received */ 69 70 /* ICMSR (also for ICMIE) */ 71 #define MNR (1 << 6) /* nack received */ 72 #define MAL (1 << 5) /* arbitration lost */ 73 #define MST (1 << 4) /* sent a stop */ 74 #define MDE (1 << 3) 75 #define MDT (1 << 2) 76 #define MDR (1 << 1) 77 #define MAT (1 << 0) /* slave addr xfer done */ 78 79 /* ICDMAER */ 80 #define RSDMAE (1 << 3) /* DMA Slave Received Enable */ 81 #define TSDMAE (1 << 2) /* DMA Slave Transmitted Enable */ 82 #define RMDMAE (1 << 1) /* DMA Master Received Enable */ 83 #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */ 84 85 /* ICFBSCR */ 86 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ 87 88 #define RCAR_MIN_DMA_LEN 8 89 90 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) 91 #define RCAR_BUS_PHASE_DATA (MDBS | MIE) 92 #define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF) 93 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) 94 95 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) 96 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) 97 #define RCAR_IRQ_STOP (MST) 98 99 #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0x7F) 100 #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0x7F) 101 102 #define ID_LAST_MSG (1 << 0) 103 #define ID_FIRST_MSG (1 << 1) 104 #define ID_DONE (1 << 2) 105 #define ID_ARBLOST (1 << 3) 106 #define ID_NACK (1 << 4) 107 /* persistent flags */ 108 #define ID_P_REP_AFTER_RD BIT(29) 109 #define ID_P_NO_RXDMA BIT(30) /* HW forbids RXDMA sometimes */ 110 #define ID_P_PM_BLOCKED BIT(31) 111 #define ID_P_MASK GENMASK(31, 29) 112 113 enum rcar_i2c_type { 114 I2C_RCAR_GEN1, 115 I2C_RCAR_GEN2, 116 I2C_RCAR_GEN3, 117 }; 118 119 struct rcar_i2c_priv { 120 void __iomem *io; 121 struct i2c_adapter adap; 122 struct i2c_msg *msg; 123 int msgs_left; 124 struct clk *clk; 125 126 wait_queue_head_t wait; 127 128 int pos; 129 u32 icccr; 130 u32 flags; 131 u8 recovery_icmcr; /* protected by adapter lock */ 132 enum rcar_i2c_type devtype; 133 struct i2c_client *slave; 134 135 struct resource *res; 136 struct dma_chan *dma_tx; 137 struct dma_chan *dma_rx; 138 struct scatterlist sg; 139 enum dma_data_direction dma_direction; 140 141 struct reset_control *rstc; 142 }; 143 144 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) 145 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) 146 147 #define LOOP_TIMEOUT 1024 148 149 150 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) 151 { 152 writel(val, priv->io + reg); 153 } 154 155 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) 156 { 157 return readl(priv->io + reg); 158 } 159 160 static int rcar_i2c_get_scl(struct i2c_adapter *adap) 161 { 162 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 163 164 return !!(rcar_i2c_read(priv, ICMCR) & FSCL); 165 166 }; 167 168 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val) 169 { 170 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 171 172 if (val) 173 priv->recovery_icmcr |= FSCL; 174 else 175 priv->recovery_icmcr &= ~FSCL; 176 177 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 178 }; 179 180 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val) 181 { 182 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 183 184 if (val) 185 priv->recovery_icmcr |= FSDA; 186 else 187 priv->recovery_icmcr &= ~FSDA; 188 189 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 190 }; 191 192 static int rcar_i2c_get_bus_free(struct i2c_adapter *adap) 193 { 194 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 195 196 return !(rcar_i2c_read(priv, ICMCR) & FSDA); 197 198 }; 199 200 static struct i2c_bus_recovery_info rcar_i2c_bri = { 201 .get_scl = rcar_i2c_get_scl, 202 .set_scl = rcar_i2c_set_scl, 203 .set_sda = rcar_i2c_set_sda, 204 .get_bus_free = rcar_i2c_get_bus_free, 205 .recover_bus = i2c_generic_scl_recovery, 206 }; 207 static void rcar_i2c_init(struct rcar_i2c_priv *priv) 208 { 209 /* reset master mode */ 210 rcar_i2c_write(priv, ICMIER, 0); 211 rcar_i2c_write(priv, ICMCR, MDBS); 212 rcar_i2c_write(priv, ICMSR, 0); 213 /* start clock */ 214 rcar_i2c_write(priv, ICCCR, priv->icccr); 215 216 if (priv->devtype == I2C_RCAR_GEN3) 217 rcar_i2c_write(priv, ICFBSCR, TCYC17); 218 219 } 220 221 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) 222 { 223 int i; 224 225 for (i = 0; i < LOOP_TIMEOUT; i++) { 226 /* make sure that bus is not busy */ 227 if (!(rcar_i2c_read(priv, ICMCR) & FSDA)) 228 return 0; 229 udelay(1); 230 } 231 232 /* Waiting did not help, try to recover */ 233 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL; 234 return i2c_recover_bus(&priv->adap); 235 } 236 237 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, struct i2c_timings *t) 238 { 239 u32 scgd, cdf, round, ick, sum, scl, cdf_width; 240 unsigned long rate; 241 struct device *dev = rcar_i2c_priv_to_dev(priv); 242 243 /* Fall back to previously used values if not supplied */ 244 t->bus_freq_hz = t->bus_freq_hz ?: 100000; 245 t->scl_fall_ns = t->scl_fall_ns ?: 35; 246 t->scl_rise_ns = t->scl_rise_ns ?: 200; 247 t->scl_int_delay_ns = t->scl_int_delay_ns ?: 50; 248 249 switch (priv->devtype) { 250 case I2C_RCAR_GEN1: 251 cdf_width = 2; 252 break; 253 case I2C_RCAR_GEN2: 254 case I2C_RCAR_GEN3: 255 cdf_width = 3; 256 break; 257 default: 258 dev_err(dev, "device type error\n"); 259 return -EIO; 260 } 261 262 /* 263 * calculate SCL clock 264 * see 265 * ICCCR 266 * 267 * ick = clkp / (1 + CDF) 268 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 269 * 270 * ick : I2C internal clock < 20 MHz 271 * ticf : I2C SCL falling time 272 * tr : I2C SCL rising time 273 * intd : LSI internal delay 274 * clkp : peripheral_clk 275 * F[] : integer up-valuation 276 */ 277 rate = clk_get_rate(priv->clk); 278 cdf = rate / 20000000; 279 if (cdf >= 1U << cdf_width) { 280 dev_err(dev, "Input clock %lu too high\n", rate); 281 return -EIO; 282 } 283 ick = rate / (cdf + 1); 284 285 /* 286 * it is impossible to calculate large scale 287 * number on u32. separate it 288 * 289 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd) 290 * = F[sum * ick / 1000000000] 291 * = F[(ick / 1000000) * sum / 1000] 292 */ 293 sum = t->scl_fall_ns + t->scl_rise_ns + t->scl_int_delay_ns; 294 round = (ick + 500000) / 1000000 * sum; 295 round = (round + 500) / 1000; 296 297 /* 298 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 299 * 300 * Calculation result (= SCL) should be less than 301 * bus_speed for hardware safety 302 * 303 * We could use something along the lines of 304 * div = ick / (bus_speed + 1) + 1; 305 * scgd = (div - 20 - round + 7) / 8; 306 * scl = ick / (20 + (scgd * 8) + round); 307 * (not fully verified) but that would get pretty involved 308 */ 309 for (scgd = 0; scgd < 0x40; scgd++) { 310 scl = ick / (20 + (scgd * 8) + round); 311 if (scl <= t->bus_freq_hz) 312 goto scgd_find; 313 } 314 dev_err(dev, "it is impossible to calculate best SCL\n"); 315 return -EIO; 316 317 scgd_find: 318 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", 319 scl, t->bus_freq_hz, clk_get_rate(priv->clk), round, cdf, scgd); 320 321 /* keep icccr value */ 322 priv->icccr = scgd << cdf_width | cdf; 323 324 return 0; 325 } 326 327 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) 328 { 329 int read = !!rcar_i2c_is_recv(priv); 330 331 priv->pos = 0; 332 if (priv->msgs_left == 1) 333 priv->flags |= ID_LAST_MSG; 334 335 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg)); 336 /* 337 * We don't have a test case but the HW engineers say that the write order 338 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since 339 * it didn't cause a drawback for me, let's rather be safe than sorry. 340 */ 341 if (priv->flags & ID_FIRST_MSG) { 342 rcar_i2c_write(priv, ICMSR, 0); 343 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 344 } else { 345 if (priv->flags & ID_P_REP_AFTER_RD) 346 priv->flags &= ~ID_P_REP_AFTER_RD; 347 else 348 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 349 rcar_i2c_write(priv, ICMSR, 0); 350 } 351 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); 352 } 353 354 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) 355 { 356 priv->msg++; 357 priv->msgs_left--; 358 priv->flags &= ID_P_MASK; 359 rcar_i2c_prepare_msg(priv); 360 } 361 362 static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv) 363 { 364 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE 365 ? priv->dma_rx : priv->dma_tx; 366 367 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), 368 sg_dma_len(&priv->sg), priv->dma_direction); 369 370 /* Gen3 can only do one RXDMA per transfer and we just completed it */ 371 if (priv->devtype == I2C_RCAR_GEN3 && 372 priv->dma_direction == DMA_FROM_DEVICE) 373 priv->flags |= ID_P_NO_RXDMA; 374 375 priv->dma_direction = DMA_NONE; 376 377 /* Disable DMA Master Received/Transmitted, must be last! */ 378 rcar_i2c_write(priv, ICDMAER, 0); 379 } 380 381 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv) 382 { 383 if (priv->dma_direction == DMA_NONE) 384 return; 385 else if (priv->dma_direction == DMA_FROM_DEVICE) 386 dmaengine_terminate_all(priv->dma_rx); 387 else if (priv->dma_direction == DMA_TO_DEVICE) 388 dmaengine_terminate_all(priv->dma_tx); 389 390 rcar_i2c_dma_unmap(priv); 391 } 392 393 static void rcar_i2c_dma_callback(void *data) 394 { 395 struct rcar_i2c_priv *priv = data; 396 397 priv->pos += sg_dma_len(&priv->sg); 398 399 rcar_i2c_dma_unmap(priv); 400 } 401 402 static bool rcar_i2c_dma(struct rcar_i2c_priv *priv) 403 { 404 struct device *dev = rcar_i2c_priv_to_dev(priv); 405 struct i2c_msg *msg = priv->msg; 406 bool read = msg->flags & I2C_M_RD; 407 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 408 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx; 409 struct dma_async_tx_descriptor *txdesc; 410 dma_addr_t dma_addr; 411 dma_cookie_t cookie; 412 unsigned char *buf; 413 int len; 414 415 /* Do various checks to see if DMA is feasible at all */ 416 if (IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN || 417 !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA)) 418 return false; 419 420 if (read) { 421 /* 422 * The last two bytes needs to be fetched using PIO in 423 * order for the STOP phase to work. 424 */ 425 buf = priv->msg->buf; 426 len = priv->msg->len - 2; 427 } else { 428 /* 429 * First byte in message was sent using PIO. 430 */ 431 buf = priv->msg->buf + 1; 432 len = priv->msg->len - 1; 433 } 434 435 dma_addr = dma_map_single(chan->device->dev, buf, len, dir); 436 if (dma_mapping_error(chan->device->dev, dma_addr)) { 437 dev_dbg(dev, "dma map failed, using PIO\n"); 438 return false; 439 } 440 441 sg_dma_len(&priv->sg) = len; 442 sg_dma_address(&priv->sg) = dma_addr; 443 444 priv->dma_direction = dir; 445 446 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1, 447 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 448 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 449 if (!txdesc) { 450 dev_dbg(dev, "dma prep slave sg failed, using PIO\n"); 451 rcar_i2c_cleanup_dma(priv); 452 return false; 453 } 454 455 txdesc->callback = rcar_i2c_dma_callback; 456 txdesc->callback_param = priv; 457 458 cookie = dmaengine_submit(txdesc); 459 if (dma_submit_error(cookie)) { 460 dev_dbg(dev, "submitting dma failed, using PIO\n"); 461 rcar_i2c_cleanup_dma(priv); 462 return false; 463 } 464 465 /* Enable DMA Master Received/Transmitted */ 466 if (read) 467 rcar_i2c_write(priv, ICDMAER, RMDMAE); 468 else 469 rcar_i2c_write(priv, ICDMAER, TMDMAE); 470 471 dma_async_issue_pending(chan); 472 return true; 473 } 474 475 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) 476 { 477 struct i2c_msg *msg = priv->msg; 478 479 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 480 if (!(msr & MDE)) 481 return; 482 483 /* Check if DMA can be enabled and take over */ 484 if (priv->pos == 1 && rcar_i2c_dma(priv)) 485 return; 486 487 if (priv->pos < msg->len) { 488 /* 489 * Prepare next data to ICRXTX register. 490 * This data will go to _SHIFT_ register. 491 * 492 * * 493 * [ICRXTX] -> [SHIFT] -> [I2C bus] 494 */ 495 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); 496 priv->pos++; 497 } else { 498 /* 499 * The last data was pushed to ICRXTX on _PREV_ empty irq. 500 * It is on _SHIFT_ register, and will sent to I2C bus. 501 * 502 * * 503 * [ICRXTX] -> [SHIFT] -> [I2C bus] 504 */ 505 506 if (priv->flags & ID_LAST_MSG) { 507 /* 508 * If current msg is the _LAST_ msg, 509 * prepare stop condition here. 510 * ID_DONE will be set on STOP irq. 511 */ 512 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 513 } else { 514 rcar_i2c_next_msg(priv); 515 return; 516 } 517 } 518 519 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND); 520 } 521 522 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) 523 { 524 struct i2c_msg *msg = priv->msg; 525 526 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 527 if (!(msr & MDR)) 528 return; 529 530 if (msr & MAT) { 531 /* 532 * Address transfer phase finished, but no data at this point. 533 * Try to use DMA to receive data. 534 */ 535 rcar_i2c_dma(priv); 536 } else if (priv->pos < msg->len) { 537 /* get received data */ 538 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); 539 priv->pos++; 540 } 541 542 /* If next received data is the _LAST_, go to new phase. */ 543 if (priv->pos + 1 == msg->len) { 544 if (priv->flags & ID_LAST_MSG) { 545 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 546 } else { 547 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 548 priv->flags |= ID_P_REP_AFTER_RD; 549 } 550 } 551 552 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG)) 553 rcar_i2c_next_msg(priv); 554 else 555 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV); 556 } 557 558 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) 559 { 560 u32 ssr_raw, ssr_filtered; 561 u8 value; 562 563 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; 564 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); 565 566 if (!ssr_filtered) 567 return false; 568 569 /* address detected */ 570 if (ssr_filtered & SAR) { 571 /* read or write request */ 572 if (ssr_raw & STM) { 573 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); 574 rcar_i2c_write(priv, ICRXTX, value); 575 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); 576 } else { 577 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); 578 rcar_i2c_read(priv, ICRXTX); /* dummy read */ 579 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); 580 } 581 582 rcar_i2c_write(priv, ICSSR, ~SAR & 0xff); 583 } 584 585 /* master sent stop */ 586 if (ssr_filtered & SSR) { 587 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); 588 rcar_i2c_write(priv, ICSIER, SAR | SSR); 589 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); 590 } 591 592 /* master wants to write to us */ 593 if (ssr_filtered & SDR) { 594 int ret; 595 596 value = rcar_i2c_read(priv, ICRXTX); 597 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); 598 /* Send NACK in case of error */ 599 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); 600 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); 601 } 602 603 /* master wants to read from us */ 604 if (ssr_filtered & SDE) { 605 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); 606 rcar_i2c_write(priv, ICRXTX, value); 607 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); 608 } 609 610 return true; 611 } 612 613 /* 614 * This driver has a lock-free design because there are IP cores (at least 615 * R-Car Gen2) which have an inherent race condition in their hardware design. 616 * There, we need to clear RCAR_BUS_MASK_DATA bits as soon as possible after 617 * the interrupt was generated, otherwise an unwanted repeated message gets 618 * generated. It turned out that taking a spinlock at the beginning of the ISR 619 * was already causing repeated messages. Thus, this driver was converted to 620 * the now lockless behaviour. Please keep this in mind when hacking the driver. 621 */ 622 static irqreturn_t rcar_i2c_irq(int irq, void *ptr) 623 { 624 struct rcar_i2c_priv *priv = ptr; 625 u32 msr, val; 626 627 /* Clear START or STOP immediately, except for REPSTART after read */ 628 if (likely(!(priv->flags & ID_P_REP_AFTER_RD))) { 629 val = rcar_i2c_read(priv, ICMCR); 630 rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA); 631 } 632 633 msr = rcar_i2c_read(priv, ICMSR); 634 635 /* Only handle interrupts that are currently enabled */ 636 msr &= rcar_i2c_read(priv, ICMIER); 637 if (!msr) { 638 if (rcar_i2c_slave_irq(priv)) 639 return IRQ_HANDLED; 640 641 return IRQ_NONE; 642 } 643 644 /* Arbitration lost */ 645 if (msr & MAL) { 646 priv->flags |= ID_DONE | ID_ARBLOST; 647 goto out; 648 } 649 650 /* Nack */ 651 if (msr & MNR) { 652 /* HW automatically sends STOP after received NACK */ 653 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); 654 priv->flags |= ID_NACK; 655 goto out; 656 } 657 658 /* Stop */ 659 if (msr & MST) { 660 priv->msgs_left--; /* The last message also made it */ 661 priv->flags |= ID_DONE; 662 goto out; 663 } 664 665 if (rcar_i2c_is_recv(priv)) 666 rcar_i2c_irq_recv(priv, msr); 667 else 668 rcar_i2c_irq_send(priv, msr); 669 670 out: 671 if (priv->flags & ID_DONE) { 672 rcar_i2c_write(priv, ICMIER, 0); 673 rcar_i2c_write(priv, ICMSR, 0); 674 wake_up(&priv->wait); 675 } 676 677 return IRQ_HANDLED; 678 } 679 680 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev, 681 enum dma_transfer_direction dir, 682 dma_addr_t port_addr) 683 { 684 struct dma_chan *chan; 685 struct dma_slave_config cfg; 686 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; 687 int ret; 688 689 chan = dma_request_chan(dev, chan_name); 690 if (IS_ERR(chan)) { 691 dev_dbg(dev, "request_channel failed for %s (%ld)\n", 692 chan_name, PTR_ERR(chan)); 693 return chan; 694 } 695 696 memset(&cfg, 0, sizeof(cfg)); 697 cfg.direction = dir; 698 if (dir == DMA_MEM_TO_DEV) { 699 cfg.dst_addr = port_addr; 700 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 701 } else { 702 cfg.src_addr = port_addr; 703 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 704 } 705 706 ret = dmaengine_slave_config(chan, &cfg); 707 if (ret) { 708 dev_dbg(dev, "slave_config failed for %s (%d)\n", 709 chan_name, ret); 710 dma_release_channel(chan); 711 return ERR_PTR(ret); 712 } 713 714 dev_dbg(dev, "got DMA channel for %s\n", chan_name); 715 return chan; 716 } 717 718 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv, 719 struct i2c_msg *msg) 720 { 721 struct device *dev = rcar_i2c_priv_to_dev(priv); 722 bool read; 723 struct dma_chan *chan; 724 enum dma_transfer_direction dir; 725 726 read = msg->flags & I2C_M_RD; 727 728 chan = read ? priv->dma_rx : priv->dma_tx; 729 if (PTR_ERR(chan) != -EPROBE_DEFER) 730 return; 731 732 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 733 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX); 734 735 if (read) 736 priv->dma_rx = chan; 737 else 738 priv->dma_tx = chan; 739 } 740 741 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv) 742 { 743 if (!IS_ERR(priv->dma_tx)) { 744 dma_release_channel(priv->dma_tx); 745 priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 746 } 747 748 if (!IS_ERR(priv->dma_rx)) { 749 dma_release_channel(priv->dma_rx); 750 priv->dma_rx = ERR_PTR(-EPROBE_DEFER); 751 } 752 } 753 754 /* I2C is a special case, we need to poll the status of a reset */ 755 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv) 756 { 757 int i, ret; 758 759 ret = reset_control_reset(priv->rstc); 760 if (ret) 761 return ret; 762 763 for (i = 0; i < LOOP_TIMEOUT; i++) { 764 ret = reset_control_status(priv->rstc); 765 if (ret == 0) 766 return 0; 767 udelay(1); 768 } 769 770 return -ETIMEDOUT; 771 } 772 773 static int rcar_i2c_master_xfer(struct i2c_adapter *adap, 774 struct i2c_msg *msgs, 775 int num) 776 { 777 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 778 struct device *dev = rcar_i2c_priv_to_dev(priv); 779 int i, ret; 780 long time_left; 781 782 pm_runtime_get_sync(dev); 783 784 /* Check bus state before init otherwise bus busy info will be lost */ 785 ret = rcar_i2c_bus_barrier(priv); 786 if (ret < 0) 787 goto out; 788 789 /* Gen3 needs a reset before allowing RXDMA once */ 790 if (priv->devtype == I2C_RCAR_GEN3) { 791 priv->flags |= ID_P_NO_RXDMA; 792 if (!IS_ERR(priv->rstc)) { 793 ret = rcar_i2c_do_reset(priv); 794 if (ret == 0) 795 priv->flags &= ~ID_P_NO_RXDMA; 796 } 797 } 798 799 rcar_i2c_init(priv); 800 801 for (i = 0; i < num; i++) 802 rcar_i2c_request_dma(priv, msgs + i); 803 804 /* init first message */ 805 priv->msg = msgs; 806 priv->msgs_left = num; 807 priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG; 808 rcar_i2c_prepare_msg(priv); 809 810 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE, 811 num * adap->timeout); 812 813 /* cleanup DMA if it couldn't complete properly due to an error */ 814 if (priv->dma_direction != DMA_NONE) 815 rcar_i2c_cleanup_dma(priv); 816 817 if (!time_left) { 818 rcar_i2c_init(priv); 819 ret = -ETIMEDOUT; 820 } else if (priv->flags & ID_NACK) { 821 ret = -ENXIO; 822 } else if (priv->flags & ID_ARBLOST) { 823 ret = -EAGAIN; 824 } else { 825 ret = num - priv->msgs_left; /* The number of transfer */ 826 } 827 out: 828 pm_runtime_put(dev); 829 830 if (ret < 0 && ret != -ENXIO) 831 dev_err(dev, "error %d : %x\n", ret, priv->flags); 832 833 return ret; 834 } 835 836 static int rcar_reg_slave(struct i2c_client *slave) 837 { 838 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 839 840 if (priv->slave) 841 return -EBUSY; 842 843 if (slave->flags & I2C_CLIENT_TEN) 844 return -EAFNOSUPPORT; 845 846 /* Keep device active for slave address detection logic */ 847 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv)); 848 849 priv->slave = slave; 850 rcar_i2c_write(priv, ICSAR, slave->addr); 851 rcar_i2c_write(priv, ICSSR, 0); 852 rcar_i2c_write(priv, ICSIER, SAR | SSR); 853 rcar_i2c_write(priv, ICSCR, SIE | SDBS); 854 855 return 0; 856 } 857 858 static int rcar_unreg_slave(struct i2c_client *slave) 859 { 860 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 861 862 WARN_ON(!priv->slave); 863 864 rcar_i2c_write(priv, ICSIER, 0); 865 rcar_i2c_write(priv, ICSCR, 0); 866 867 priv->slave = NULL; 868 869 pm_runtime_put(rcar_i2c_priv_to_dev(priv)); 870 871 return 0; 872 } 873 874 static u32 rcar_i2c_func(struct i2c_adapter *adap) 875 { 876 /* 877 * This HW can't do: 878 * I2C_SMBUS_QUICK (setting FSB during START didn't work) 879 * I2C_M_NOSTART (automatically sends address after START) 880 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK) 881 */ 882 return I2C_FUNC_I2C | I2C_FUNC_SLAVE | 883 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 884 } 885 886 static const struct i2c_algorithm rcar_i2c_algo = { 887 .master_xfer = rcar_i2c_master_xfer, 888 .functionality = rcar_i2c_func, 889 .reg_slave = rcar_reg_slave, 890 .unreg_slave = rcar_unreg_slave, 891 }; 892 893 static const struct i2c_adapter_quirks rcar_i2c_quirks = { 894 .flags = I2C_AQ_NO_ZERO_LEN, 895 }; 896 897 static const struct of_device_id rcar_i2c_dt_ids[] = { 898 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, 899 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, 900 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, 901 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, 902 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, 903 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, 904 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, 905 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, 906 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 }, 907 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, /* Deprecated */ 908 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 }, 909 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 }, 910 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 }, 911 {}, 912 }; 913 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); 914 915 static int rcar_i2c_probe(struct platform_device *pdev) 916 { 917 struct rcar_i2c_priv *priv; 918 struct i2c_adapter *adap; 919 struct device *dev = &pdev->dev; 920 struct i2c_timings i2c_t; 921 int irq, ret; 922 923 /* Otherwise logic will break because some bytes must always use PIO */ 924 BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length"); 925 926 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); 927 if (!priv) 928 return -ENOMEM; 929 930 priv->clk = devm_clk_get(dev, NULL); 931 if (IS_ERR(priv->clk)) { 932 dev_err(dev, "cannot get clock\n"); 933 return PTR_ERR(priv->clk); 934 } 935 936 priv->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 937 938 priv->io = devm_ioremap_resource(dev, priv->res); 939 if (IS_ERR(priv->io)) 940 return PTR_ERR(priv->io); 941 942 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev); 943 init_waitqueue_head(&priv->wait); 944 945 adap = &priv->adap; 946 adap->nr = pdev->id; 947 adap->algo = &rcar_i2c_algo; 948 adap->class = I2C_CLASS_DEPRECATED; 949 adap->retries = 3; 950 adap->dev.parent = dev; 951 adap->dev.of_node = dev->of_node; 952 adap->bus_recovery_info = &rcar_i2c_bri; 953 adap->quirks = &rcar_i2c_quirks; 954 i2c_set_adapdata(adap, priv); 955 strlcpy(adap->name, pdev->name, sizeof(adap->name)); 956 957 i2c_parse_fw_timings(dev, &i2c_t, false); 958 959 /* Init DMA */ 960 sg_init_table(&priv->sg, 1); 961 priv->dma_direction = DMA_NONE; 962 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 963 964 /* Activate device for clock calculation */ 965 pm_runtime_enable(dev); 966 pm_runtime_get_sync(dev); 967 ret = rcar_i2c_clock_calculate(priv, &i2c_t); 968 if (ret < 0) 969 goto out_pm_put; 970 971 if (priv->devtype == I2C_RCAR_GEN3) { 972 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 973 if (!IS_ERR(priv->rstc)) { 974 ret = reset_control_status(priv->rstc); 975 if (ret < 0) 976 priv->rstc = ERR_PTR(-ENOTSUPP); 977 } 978 } 979 980 /* Stay always active when multi-master to keep arbitration working */ 981 if (of_property_read_bool(dev->of_node, "multi-master")) 982 priv->flags |= ID_P_PM_BLOCKED; 983 else 984 pm_runtime_put(dev); 985 986 987 irq = platform_get_irq(pdev, 0); 988 ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0, dev_name(dev), priv); 989 if (ret < 0) { 990 dev_err(dev, "cannot get irq %d\n", irq); 991 goto out_pm_disable; 992 } 993 994 platform_set_drvdata(pdev, priv); 995 996 ret = i2c_add_numbered_adapter(adap); 997 if (ret < 0) 998 goto out_pm_disable; 999 1000 dev_info(dev, "probed\n"); 1001 1002 return 0; 1003 1004 out_pm_put: 1005 pm_runtime_put(dev); 1006 out_pm_disable: 1007 pm_runtime_disable(dev); 1008 return ret; 1009 } 1010 1011 static int rcar_i2c_remove(struct platform_device *pdev) 1012 { 1013 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); 1014 struct device *dev = &pdev->dev; 1015 1016 i2c_del_adapter(&priv->adap); 1017 rcar_i2c_release_dma(priv); 1018 if (priv->flags & ID_P_PM_BLOCKED) 1019 pm_runtime_put(dev); 1020 pm_runtime_disable(dev); 1021 1022 return 0; 1023 } 1024 1025 #ifdef CONFIG_PM_SLEEP 1026 static int rcar_i2c_suspend(struct device *dev) 1027 { 1028 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1029 1030 i2c_mark_adapter_suspended(&priv->adap); 1031 return 0; 1032 } 1033 1034 static int rcar_i2c_resume(struct device *dev) 1035 { 1036 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1037 1038 i2c_mark_adapter_resumed(&priv->adap); 1039 return 0; 1040 } 1041 1042 static const struct dev_pm_ops rcar_i2c_pm_ops = { 1043 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume) 1044 }; 1045 1046 #define DEV_PM_OPS (&rcar_i2c_pm_ops) 1047 #else 1048 #define DEV_PM_OPS NULL 1049 #endif /* CONFIG_PM_SLEEP */ 1050 1051 static struct platform_driver rcar_i2c_driver = { 1052 .driver = { 1053 .name = "i2c-rcar", 1054 .of_match_table = rcar_i2c_dt_ids, 1055 .pm = DEV_PM_OPS, 1056 }, 1057 .probe = rcar_i2c_probe, 1058 .remove = rcar_i2c_remove, 1059 }; 1060 1061 module_platform_driver(rcar_i2c_driver); 1062 1063 MODULE_LICENSE("GPL v2"); 1064 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); 1065 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); 1066