1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Renesas R-Car I2C unit 4 * 5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com> 6 * Copyright (C) 2011-2019 Renesas Electronics Corporation 7 * 8 * Copyright (C) 2012-14 Renesas Solutions Corp. 9 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 10 * 11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c 12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> 13 */ 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dmaengine.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/i2c.h> 24 #include <linux/i2c-smbus.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/of.h> 28 #include <linux/platform_device.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/reset.h> 31 #include <linux/slab.h> 32 33 /* register offsets */ 34 #define ICSCR 0x00 /* slave ctrl */ 35 #define ICMCR 0x04 /* master ctrl */ 36 #define ICSSR 0x08 /* slave status */ 37 #define ICMSR 0x0C /* master status */ 38 #define ICSIER 0x10 /* slave irq enable */ 39 #define ICMIER 0x14 /* master irq enable */ 40 #define ICCCR 0x18 /* clock dividers */ 41 #define ICSAR 0x1C /* slave address */ 42 #define ICMAR 0x20 /* master address */ 43 #define ICRXTX 0x24 /* data port */ 44 #define ICCCR2 0x28 /* Clock control 2 */ 45 #define ICMPR 0x2C /* SCL mask control */ 46 #define ICHPR 0x30 /* SCL HIGH control */ 47 #define ICLPR 0x34 /* SCL LOW control */ 48 #define ICFBSCR 0x38 /* first bit setup cycle (Gen3) */ 49 #define ICDMAER 0x3c /* DMA enable (Gen3) */ 50 51 /* ICSCR */ 52 #define SDBS BIT(3) /* slave data buffer select */ 53 #define SIE BIT(2) /* slave interface enable */ 54 #define GCAE BIT(1) /* general call address enable */ 55 #define FNA BIT(0) /* forced non acknowledgment */ 56 57 /* ICMCR */ 58 #define MDBS BIT(7) /* non-fifo mode switch */ 59 #define FSCL BIT(6) /* override SCL pin */ 60 #define FSDA BIT(5) /* override SDA pin */ 61 #define OBPC BIT(4) /* override pins */ 62 #define MIE BIT(3) /* master if enable */ 63 #define TSBE BIT(2) 64 #define FSB BIT(1) /* force stop bit */ 65 #define ESG BIT(0) /* enable start bit gen */ 66 67 /* ICSSR (also for ICSIER) */ 68 #define GCAR BIT(6) /* general call received */ 69 #define STM BIT(5) /* slave transmit mode */ 70 #define SSR BIT(4) /* stop received */ 71 #define SDE BIT(3) /* slave data empty */ 72 #define SDT BIT(2) /* slave data transmitted */ 73 #define SDR BIT(1) /* slave data received */ 74 #define SAR BIT(0) /* slave addr received */ 75 76 /* ICMSR (also for ICMIE) */ 77 #define MNR BIT(6) /* nack received */ 78 #define MAL BIT(5) /* arbitration lost */ 79 #define MST BIT(4) /* sent a stop */ 80 #define MDE BIT(3) 81 #define MDT BIT(2) 82 #define MDR BIT(1) 83 #define MAT BIT(0) /* slave addr xfer done */ 84 85 /* ICDMAER */ 86 #define RSDMAE BIT(3) /* DMA Slave Received Enable */ 87 #define TSDMAE BIT(2) /* DMA Slave Transmitted Enable */ 88 #define RMDMAE BIT(1) /* DMA Master Received Enable */ 89 #define TMDMAE BIT(0) /* DMA Master Transmitted Enable */ 90 91 /* ICCCR2 */ 92 #define CDFD BIT(2) /* CDF Disable */ 93 #define HLSE BIT(1) /* HIGH/LOW Separate Control Enable */ 94 #define SME BIT(0) /* SCL Mask Enable */ 95 96 /* ICFBSCR */ 97 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ 98 99 #define RCAR_MIN_DMA_LEN 8 100 101 /* SCL low/high ratio 5:4 to meet all I2C timing specs (incl safety margin) */ 102 #define RCAR_SCLD_RATIO 5 103 #define RCAR_SCHD_RATIO 4 104 /* 105 * SMD should be smaller than SCLD/SCHD and is always around 20 in the docs. 106 * Thus, we simply use 20 which works for low and high speeds. 107 */ 108 #define RCAR_DEFAULT_SMD 20 109 110 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) 111 #define RCAR_BUS_PHASE_DATA (MDBS | MIE) 112 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) 113 114 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) 115 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) 116 #define RCAR_IRQ_STOP (MST) 117 118 #define ID_LAST_MSG BIT(0) 119 #define ID_REP_AFTER_RD BIT(1) 120 #define ID_DONE BIT(2) 121 #define ID_ARBLOST BIT(3) 122 #define ID_NACK BIT(4) 123 #define ID_EPROTO BIT(5) 124 /* persistent flags */ 125 #define ID_P_NOT_ATOMIC BIT(28) 126 #define ID_P_HOST_NOTIFY BIT(29) 127 #define ID_P_NO_RXDMA BIT(30) /* HW forbids RXDMA sometimes */ 128 #define ID_P_PM_BLOCKED BIT(31) 129 #define ID_P_MASK GENMASK(31, 28) 130 131 enum rcar_i2c_type { 132 I2C_RCAR_GEN1, 133 I2C_RCAR_GEN2, 134 I2C_RCAR_GEN3, 135 }; 136 137 struct rcar_i2c_priv { 138 u32 flags; 139 void __iomem *io; 140 struct i2c_adapter adap; 141 struct i2c_msg *msg; 142 int msgs_left; 143 struct clk *clk; 144 145 wait_queue_head_t wait; 146 147 int pos; 148 u32 icccr; 149 u16 schd; 150 u16 scld; 151 u8 recovery_icmcr; /* protected by adapter lock */ 152 enum rcar_i2c_type devtype; 153 struct i2c_client *slave; 154 155 struct resource *res; 156 struct dma_chan *dma_tx; 157 struct dma_chan *dma_rx; 158 struct scatterlist sg; 159 enum dma_data_direction dma_direction; 160 161 struct reset_control *rstc; 162 int irq; 163 164 struct i2c_client *host_notify_client; 165 }; 166 167 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) 168 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) 169 170 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) 171 { 172 writel(val, priv->io + reg); 173 } 174 175 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) 176 { 177 return readl(priv->io + reg); 178 } 179 180 static void rcar_i2c_clear_irq(struct rcar_i2c_priv *priv, u32 val) 181 { 182 writel(~val & 0x7f, priv->io + ICMSR); 183 } 184 185 static int rcar_i2c_get_scl(struct i2c_adapter *adap) 186 { 187 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 188 189 return !!(rcar_i2c_read(priv, ICMCR) & FSCL); 190 191 }; 192 193 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val) 194 { 195 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 196 197 if (val) 198 priv->recovery_icmcr |= FSCL; 199 else 200 priv->recovery_icmcr &= ~FSCL; 201 202 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 203 }; 204 205 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val) 206 { 207 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 208 209 if (val) 210 priv->recovery_icmcr |= FSDA; 211 else 212 priv->recovery_icmcr &= ~FSDA; 213 214 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 215 }; 216 217 static int rcar_i2c_get_bus_free(struct i2c_adapter *adap) 218 { 219 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 220 221 return !(rcar_i2c_read(priv, ICMCR) & FSDA); 222 223 }; 224 225 static struct i2c_bus_recovery_info rcar_i2c_bri = { 226 .get_scl = rcar_i2c_get_scl, 227 .set_scl = rcar_i2c_set_scl, 228 .set_sda = rcar_i2c_set_sda, 229 .get_bus_free = rcar_i2c_get_bus_free, 230 .recover_bus = i2c_generic_scl_recovery, 231 }; 232 static void rcar_i2c_init(struct rcar_i2c_priv *priv) 233 { 234 /* reset master mode */ 235 rcar_i2c_write(priv, ICMIER, 0); 236 rcar_i2c_write(priv, ICMCR, MDBS); 237 rcar_i2c_write(priv, ICMSR, 0); 238 /* start clock */ 239 if (priv->devtype < I2C_RCAR_GEN3) { 240 rcar_i2c_write(priv, ICCCR, priv->icccr); 241 } else { 242 rcar_i2c_write(priv, ICCCR2, CDFD | HLSE | SME); 243 rcar_i2c_write(priv, ICCCR, priv->icccr); 244 rcar_i2c_write(priv, ICMPR, RCAR_DEFAULT_SMD); 245 rcar_i2c_write(priv, ICHPR, priv->schd); 246 rcar_i2c_write(priv, ICLPR, priv->scld); 247 rcar_i2c_write(priv, ICFBSCR, TCYC17); 248 } 249 } 250 251 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) 252 { 253 int ret; 254 u32 val; 255 256 ret = readl_poll_timeout(priv->io + ICMCR, val, !(val & FSDA), 10, 257 priv->adap.timeout); 258 if (ret) { 259 /* Waiting did not help, try to recover */ 260 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL; 261 ret = i2c_recover_bus(&priv->adap); 262 } 263 264 return ret; 265 } 266 267 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv) 268 { 269 u32 cdf, round, ick, sum, scl, cdf_width; 270 unsigned long rate; 271 struct device *dev = rcar_i2c_priv_to_dev(priv); 272 struct i2c_timings t = { 273 .bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ, 274 .scl_fall_ns = 35, 275 .scl_rise_ns = 200, 276 .scl_int_delay_ns = 50, 277 }; 278 279 /* Fall back to previously used values if not supplied */ 280 i2c_parse_fw_timings(dev, &t, false); 281 282 /* 283 * calculate SCL clock 284 * see 285 * ICCCR (and ICCCR2 for Gen3+) 286 * 287 * ick = clkp / (1 + CDF) 288 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 289 * 290 * for Gen3+: 291 * SCL = clkp / (8 + SMD * 2 + SCLD + SCHD +F[(ticf + tr + intd) * clkp]) 292 * 293 * ick : I2C internal clock < 20 MHz 294 * ticf : I2C SCL falling time 295 * tr : I2C SCL rising time 296 * intd : LSI internal delay 297 * clkp : peripheral_clk 298 * F[] : integer up-valuation 299 */ 300 rate = clk_get_rate(priv->clk); 301 cdf = rate / 20000000; 302 cdf_width = (priv->devtype == I2C_RCAR_GEN1) ? 2 : 3; 303 if (cdf >= 1U << cdf_width) 304 goto err_no_val; 305 306 /* On Gen3+, we use cdf only for the filters, not as a SCL divider */ 307 ick = rate / (priv->devtype < I2C_RCAR_GEN3 ? (cdf + 1) : 1); 308 309 /* 310 * It is impossible to calculate a large scale number on u32. Separate it. 311 * 312 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd) 313 * = F[sum * ick / 1000000000] 314 * = F[(ick / 1000000) * sum / 1000] 315 */ 316 sum = t.scl_fall_ns + t.scl_rise_ns + t.scl_int_delay_ns; 317 round = DIV_ROUND_CLOSEST(ick, 1000000); 318 round = DIV_ROUND_CLOSEST(round * sum, 1000); 319 320 if (priv->devtype < I2C_RCAR_GEN3) { 321 u32 scgd; 322 /* 323 * SCL = ick / (20 + 8 * SCGD + F[(ticf + tr + intd) * ick]) 324 * 20 + 8 * SCGD + F[...] = ick / SCL 325 * SCGD = ((ick / SCL) - 20 - F[...]) / 8 326 * Result (= SCL) should be less than bus_speed for hardware safety 327 */ 328 scgd = DIV_ROUND_UP(ick, t.bus_freq_hz ?: 1); 329 scgd = DIV_ROUND_UP(scgd - 20 - round, 8); 330 scl = ick / (20 + 8 * scgd + round); 331 332 if (scgd > 0x3f) 333 goto err_no_val; 334 335 dev_dbg(dev, "clk %u/%u(%lu), round %u, CDF: %u, SCGD: %u\n", 336 scl, t.bus_freq_hz, rate, round, cdf, scgd); 337 338 priv->icccr = scgd << cdf_width | cdf; 339 } else { 340 u32 x, sum_ratio = RCAR_SCHD_RATIO + RCAR_SCLD_RATIO; 341 /* 342 * SCLD/SCHD ratio and SMD default value are explained above 343 * where they are defined. With these definitions, we can compute 344 * x as a base value for the SCLD/SCHD ratio: 345 * 346 * SCL = clkp / (8 + 2 * SMD + SCLD + SCHD + F[(ticf + tr + intd) * clkp]) 347 * SCL = clkp / (8 + 2 * RCAR_DEFAULT_SMD + RCAR_SCLD_RATIO * x 348 * + RCAR_SCHD_RATIO * x + F[...]) 349 * 350 * with: sum_ratio = RCAR_SCLD_RATIO + RCAR_SCHD_RATIO 351 * and: smd = RCAR_DEFAULT_SMD 352 * 353 * SCL = clkp / (8 + 2 * smd + sum_ratio * x + F[...]) 354 * 8 + 2 * smd + sum_ratio * x + F[...] = clkp / SCL 355 * x = ((clkp / SCL) - 8 - 2 * smd - F[...]) / sum_ratio 356 */ 357 x = DIV_ROUND_UP(rate, t.bus_freq_hz ?: 1); 358 x = DIV_ROUND_UP(x - 8 - 2 * RCAR_DEFAULT_SMD - round, sum_ratio); 359 scl = rate / (8 + 2 * RCAR_DEFAULT_SMD + sum_ratio * x + round); 360 361 /* Bail out if values don't fit into 16 bit or SMD became too large */ 362 if (x * RCAR_SCLD_RATIO > 0xffff || RCAR_DEFAULT_SMD > x * RCAR_SCHD_RATIO) 363 goto err_no_val; 364 365 priv->icccr = cdf; 366 priv->schd = RCAR_SCHD_RATIO * x; 367 priv->scld = RCAR_SCLD_RATIO * x; 368 369 dev_dbg(dev, "clk %u/%u(%lu), round %u, CDF: %u SCHD %u SCLD %u\n", 370 scl, t.bus_freq_hz, rate, round, cdf, priv->schd, priv->scld); 371 } 372 373 return 0; 374 375 err_no_val: 376 dev_err(dev, "it is impossible to calculate best SCL\n"); 377 return -EINVAL; 378 } 379 380 /* 381 * We don't have a test case but the HW engineers say that the write order of 382 * ICMSR and ICMCR depends on whether we issue START or REP_START. So, ICMSR 383 * handling is outside of this function. First messages clear ICMSR before this 384 * function, interrupt handlers clear the relevant bits after this function. 385 */ 386 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) 387 { 388 int read = !!rcar_i2c_is_recv(priv); 389 bool rep_start = !(priv->flags & ID_REP_AFTER_RD); 390 391 priv->pos = 0; 392 priv->flags &= ID_P_MASK; 393 394 if (priv->msgs_left == 1) 395 priv->flags |= ID_LAST_MSG; 396 397 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg)); 398 if (priv->flags & ID_P_NOT_ATOMIC) 399 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); 400 401 if (rep_start) 402 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 403 } 404 405 static void rcar_i2c_first_msg(struct rcar_i2c_priv *priv, 406 struct i2c_msg *msgs, int num) 407 { 408 priv->msg = msgs; 409 priv->msgs_left = num; 410 rcar_i2c_write(priv, ICMSR, 0); /* must be before preparing msg */ 411 rcar_i2c_prepare_msg(priv); 412 } 413 414 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) 415 { 416 priv->msg++; 417 priv->msgs_left--; 418 rcar_i2c_prepare_msg(priv); 419 /* ICMSR handling must come afterwards in the irq handler */ 420 } 421 422 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv, bool terminate) 423 { 424 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE 425 ? priv->dma_rx : priv->dma_tx; 426 427 /* only allowed from thread context! */ 428 if (terminate) 429 dmaengine_terminate_sync(chan); 430 431 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), 432 sg_dma_len(&priv->sg), priv->dma_direction); 433 434 /* Gen3 can only do one RXDMA per transfer and we just completed it */ 435 if (priv->devtype == I2C_RCAR_GEN3 && 436 priv->dma_direction == DMA_FROM_DEVICE) 437 priv->flags |= ID_P_NO_RXDMA; 438 439 priv->dma_direction = DMA_NONE; 440 441 /* Disable DMA Master Received/Transmitted, must be last! */ 442 rcar_i2c_write(priv, ICDMAER, 0); 443 } 444 445 static void rcar_i2c_dma_callback(void *data) 446 { 447 struct rcar_i2c_priv *priv = data; 448 449 priv->pos += sg_dma_len(&priv->sg); 450 451 rcar_i2c_cleanup_dma(priv, false); 452 } 453 454 static bool rcar_i2c_dma(struct rcar_i2c_priv *priv) 455 { 456 struct device *dev = rcar_i2c_priv_to_dev(priv); 457 struct i2c_msg *msg = priv->msg; 458 bool read = msg->flags & I2C_M_RD; 459 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 460 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx; 461 struct dma_async_tx_descriptor *txdesc; 462 dma_addr_t dma_addr; 463 dma_cookie_t cookie; 464 unsigned char *buf; 465 int len; 466 467 /* Do various checks to see if DMA is feasible at all */ 468 if (!(priv->flags & ID_P_NOT_ATOMIC) || IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN || 469 !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA)) 470 return false; 471 472 if (read) { 473 /* 474 * The last two bytes needs to be fetched using PIO in 475 * order for the STOP phase to work. 476 */ 477 buf = priv->msg->buf; 478 len = priv->msg->len - 2; 479 } else { 480 /* 481 * First byte in message was sent using PIO. 482 */ 483 buf = priv->msg->buf + 1; 484 len = priv->msg->len - 1; 485 } 486 487 dma_addr = dma_map_single(chan->device->dev, buf, len, dir); 488 if (dma_mapping_error(chan->device->dev, dma_addr)) { 489 dev_dbg(dev, "dma map failed, using PIO\n"); 490 return false; 491 } 492 493 sg_dma_len(&priv->sg) = len; 494 sg_dma_address(&priv->sg) = dma_addr; 495 496 priv->dma_direction = dir; 497 498 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1, 499 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 500 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 501 if (!txdesc) { 502 dev_dbg(dev, "dma prep slave sg failed, using PIO\n"); 503 rcar_i2c_cleanup_dma(priv, false); 504 return false; 505 } 506 507 txdesc->callback = rcar_i2c_dma_callback; 508 txdesc->callback_param = priv; 509 510 cookie = dmaengine_submit(txdesc); 511 if (dma_submit_error(cookie)) { 512 dev_dbg(dev, "submitting dma failed, using PIO\n"); 513 rcar_i2c_cleanup_dma(priv, false); 514 return false; 515 } 516 517 /* Enable DMA Master Received/Transmitted */ 518 if (read) 519 rcar_i2c_write(priv, ICDMAER, RMDMAE); 520 else 521 rcar_i2c_write(priv, ICDMAER, TMDMAE); 522 523 dma_async_issue_pending(chan); 524 return true; 525 } 526 527 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) 528 { 529 struct i2c_msg *msg = priv->msg; 530 u32 irqs_to_clear = MDE; 531 532 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 533 if (!(msr & MDE)) 534 return; 535 536 if (msr & MAT) 537 irqs_to_clear |= MAT; 538 539 /* Check if DMA can be enabled and take over */ 540 if (priv->pos == 1 && rcar_i2c_dma(priv)) 541 return; 542 543 if (priv->pos < msg->len) { 544 /* 545 * Prepare next data to ICRXTX register. 546 * This data will go to _SHIFT_ register. 547 * 548 * * 549 * [ICRXTX] -> [SHIFT] -> [I2C bus] 550 */ 551 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); 552 priv->pos++; 553 } else { 554 /* 555 * The last data was pushed to ICRXTX on _PREV_ empty irq. 556 * It is on _SHIFT_ register, and will sent to I2C bus. 557 * 558 * * 559 * [ICRXTX] -> [SHIFT] -> [I2C bus] 560 */ 561 562 if (priv->flags & ID_LAST_MSG) 563 /* 564 * If current msg is the _LAST_ msg, 565 * prepare stop condition here. 566 * ID_DONE will be set on STOP irq. 567 */ 568 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 569 else 570 rcar_i2c_next_msg(priv); 571 } 572 573 rcar_i2c_clear_irq(priv, irqs_to_clear); 574 } 575 576 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) 577 { 578 struct i2c_msg *msg = priv->msg; 579 bool recv_len_init = priv->pos == 0 && msg->flags & I2C_M_RECV_LEN; 580 u32 irqs_to_clear = MDR; 581 582 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 583 if (!(msr & MDR)) 584 return; 585 586 if (msr & MAT) { 587 irqs_to_clear |= MAT; 588 /* 589 * Address transfer phase finished, but no data at this point. 590 * Try to use DMA to receive data. 591 */ 592 rcar_i2c_dma(priv); 593 } else if (priv->pos < msg->len) { 594 /* get received data */ 595 u8 data = rcar_i2c_read(priv, ICRXTX); 596 597 msg->buf[priv->pos] = data; 598 if (recv_len_init) { 599 if (data == 0 || data > I2C_SMBUS_BLOCK_MAX) { 600 priv->flags |= ID_DONE | ID_EPROTO; 601 return; 602 } 603 msg->len += msg->buf[0]; 604 /* Enough data for DMA? */ 605 if (rcar_i2c_dma(priv)) 606 return; 607 /* new length after RECV_LEN now properly initialized */ 608 recv_len_init = false; 609 } 610 priv->pos++; 611 } 612 613 /* 614 * If next received data is the _LAST_ and we are not waiting for a new 615 * length because of RECV_LEN, then go to a new phase. 616 */ 617 if (priv->pos + 1 == msg->len && !recv_len_init) { 618 if (priv->flags & ID_LAST_MSG) { 619 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 620 } else { 621 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 622 priv->flags |= ID_REP_AFTER_RD; 623 } 624 } 625 626 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG)) 627 rcar_i2c_next_msg(priv); 628 629 rcar_i2c_clear_irq(priv, irqs_to_clear); 630 } 631 632 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) 633 { 634 u32 ssr_raw, ssr_filtered; 635 u8 value; 636 637 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; 638 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); 639 640 if (!ssr_filtered) 641 return false; 642 643 /* address detected */ 644 if (ssr_filtered & SAR) { 645 /* read or write request */ 646 if (ssr_raw & STM) { 647 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); 648 rcar_i2c_write(priv, ICRXTX, value); 649 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); 650 } else { 651 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); 652 rcar_i2c_read(priv, ICRXTX); /* dummy read */ 653 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); 654 } 655 656 /* Clear SSR, too, because of old STOPs to other clients than us */ 657 rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff); 658 } 659 660 /* master sent stop */ 661 if (ssr_filtered & SSR) { 662 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); 663 rcar_i2c_write(priv, ICSCR, SIE | SDBS); /* clear our NACK */ 664 rcar_i2c_write(priv, ICSIER, SAR); 665 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); 666 } 667 668 /* master wants to write to us */ 669 if (ssr_filtered & SDR) { 670 int ret; 671 672 value = rcar_i2c_read(priv, ICRXTX); 673 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); 674 /* Send NACK in case of error */ 675 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); 676 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); 677 } 678 679 /* master wants to read from us */ 680 if (ssr_filtered & SDE) { 681 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); 682 rcar_i2c_write(priv, ICRXTX, value); 683 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); 684 } 685 686 return true; 687 } 688 689 /* 690 * This driver has a lock-free design because there are IP cores (at least 691 * R-Car Gen2) which have an inherent race condition in their hardware design. 692 * There, we need to switch to RCAR_BUS_PHASE_DATA as soon as possible after 693 * the interrupt was generated, otherwise an unwanted repeated message gets 694 * generated. It turned out that taking a spinlock at the beginning of the ISR 695 * was already causing repeated messages. Thus, this driver was converted to 696 * the now lockless behaviour. Please keep this in mind when hacking the driver. 697 * R-Car Gen3 seems to have this fixed but earlier versions than R-Car Gen2 are 698 * likely affected. Therefore, we have different interrupt handler entries. 699 */ 700 static irqreturn_t rcar_i2c_irq(int irq, struct rcar_i2c_priv *priv, u32 msr) 701 { 702 if (!msr) { 703 if (rcar_i2c_slave_irq(priv)) 704 return IRQ_HANDLED; 705 706 return IRQ_NONE; 707 } 708 709 /* Arbitration lost */ 710 if (msr & MAL) { 711 priv->flags |= ID_DONE | ID_ARBLOST; 712 goto out; 713 } 714 715 /* Nack */ 716 if (msr & MNR) { 717 /* HW automatically sends STOP after received NACK */ 718 if (priv->flags & ID_P_NOT_ATOMIC) 719 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); 720 priv->flags |= ID_NACK; 721 goto out; 722 } 723 724 /* Stop */ 725 if (msr & MST) { 726 priv->msgs_left--; /* The last message also made it */ 727 priv->flags |= ID_DONE; 728 goto out; 729 } 730 731 if (rcar_i2c_is_recv(priv)) 732 rcar_i2c_irq_recv(priv, msr); 733 else 734 rcar_i2c_irq_send(priv, msr); 735 736 out: 737 if (priv->flags & ID_DONE) { 738 rcar_i2c_write(priv, ICMIER, 0); 739 rcar_i2c_write(priv, ICMSR, 0); 740 if (priv->flags & ID_P_NOT_ATOMIC) 741 wake_up(&priv->wait); 742 } 743 744 return IRQ_HANDLED; 745 } 746 747 static irqreturn_t rcar_i2c_gen2_irq(int irq, void *ptr) 748 { 749 struct rcar_i2c_priv *priv = ptr; 750 u32 msr; 751 752 /* Clear START or STOP immediately, except for REPSTART after read */ 753 if (likely(!(priv->flags & ID_REP_AFTER_RD))) 754 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); 755 756 /* Only handle interrupts that are currently enabled */ 757 msr = rcar_i2c_read(priv, ICMSR); 758 if (priv->flags & ID_P_NOT_ATOMIC) 759 msr &= rcar_i2c_read(priv, ICMIER); 760 761 return rcar_i2c_irq(irq, priv, msr); 762 } 763 764 static irqreturn_t rcar_i2c_gen3_irq(int irq, void *ptr) 765 { 766 struct rcar_i2c_priv *priv = ptr; 767 u32 msr; 768 769 /* Only handle interrupts that are currently enabled */ 770 msr = rcar_i2c_read(priv, ICMSR); 771 if (priv->flags & ID_P_NOT_ATOMIC) 772 msr &= rcar_i2c_read(priv, ICMIER); 773 774 /* 775 * Clear START or STOP immediately, except for REPSTART after read or 776 * if a spurious interrupt was detected. 777 */ 778 if (likely(!(priv->flags & ID_REP_AFTER_RD) && msr)) 779 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); 780 781 return rcar_i2c_irq(irq, priv, msr); 782 } 783 784 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev, 785 enum dma_transfer_direction dir, 786 dma_addr_t port_addr) 787 { 788 struct dma_chan *chan; 789 struct dma_slave_config cfg; 790 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; 791 int ret; 792 793 chan = dma_request_chan(dev, chan_name); 794 if (IS_ERR(chan)) { 795 dev_dbg(dev, "request_channel failed for %s (%ld)\n", 796 chan_name, PTR_ERR(chan)); 797 return chan; 798 } 799 800 memset(&cfg, 0, sizeof(cfg)); 801 cfg.direction = dir; 802 if (dir == DMA_MEM_TO_DEV) { 803 cfg.dst_addr = port_addr; 804 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 805 } else { 806 cfg.src_addr = port_addr; 807 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 808 } 809 810 ret = dmaengine_slave_config(chan, &cfg); 811 if (ret) { 812 dev_dbg(dev, "slave_config failed for %s (%d)\n", 813 chan_name, ret); 814 dma_release_channel(chan); 815 return ERR_PTR(ret); 816 } 817 818 dev_dbg(dev, "got DMA channel for %s\n", chan_name); 819 return chan; 820 } 821 822 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv, 823 struct i2c_msg *msg) 824 { 825 struct device *dev = rcar_i2c_priv_to_dev(priv); 826 bool read; 827 struct dma_chan *chan; 828 enum dma_transfer_direction dir; 829 830 read = msg->flags & I2C_M_RD; 831 832 chan = read ? priv->dma_rx : priv->dma_tx; 833 if (PTR_ERR(chan) != -EPROBE_DEFER) 834 return; 835 836 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 837 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX); 838 839 if (read) 840 priv->dma_rx = chan; 841 else 842 priv->dma_tx = chan; 843 } 844 845 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv) 846 { 847 if (!IS_ERR(priv->dma_tx)) { 848 dma_release_channel(priv->dma_tx); 849 priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 850 } 851 852 if (!IS_ERR(priv->dma_rx)) { 853 dma_release_channel(priv->dma_rx); 854 priv->dma_rx = ERR_PTR(-EPROBE_DEFER); 855 } 856 } 857 858 /* I2C is a special case, we need to poll the status of a reset */ 859 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv) 860 { 861 int ret; 862 863 ret = reset_control_reset(priv->rstc); 864 if (ret) 865 return ret; 866 867 return read_poll_timeout_atomic(reset_control_status, ret, ret == 0, 1, 868 100, false, priv->rstc); 869 } 870 871 static int rcar_i2c_master_xfer(struct i2c_adapter *adap, 872 struct i2c_msg *msgs, 873 int num) 874 { 875 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 876 struct device *dev = rcar_i2c_priv_to_dev(priv); 877 int i, ret; 878 long time_left; 879 880 priv->flags |= ID_P_NOT_ATOMIC; 881 882 pm_runtime_get_sync(dev); 883 884 /* Check bus state before init otherwise bus busy info will be lost */ 885 ret = rcar_i2c_bus_barrier(priv); 886 if (ret < 0) 887 goto out; 888 889 /* Gen3 needs a reset before allowing RXDMA once */ 890 if (priv->devtype == I2C_RCAR_GEN3) { 891 priv->flags &= ~ID_P_NO_RXDMA; 892 ret = rcar_i2c_do_reset(priv); 893 if (ret) 894 goto out; 895 } 896 897 rcar_i2c_init(priv); 898 899 for (i = 0; i < num; i++) 900 rcar_i2c_request_dma(priv, msgs + i); 901 902 rcar_i2c_first_msg(priv, msgs, num); 903 904 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE, 905 num * adap->timeout); 906 907 /* cleanup DMA if it couldn't complete properly due to an error */ 908 if (priv->dma_direction != DMA_NONE) 909 rcar_i2c_cleanup_dma(priv, true); 910 911 if (!time_left) { 912 rcar_i2c_init(priv); 913 ret = -ETIMEDOUT; 914 } else if (priv->flags & ID_NACK) { 915 ret = -ENXIO; 916 } else if (priv->flags & ID_ARBLOST) { 917 ret = -EAGAIN; 918 } else if (priv->flags & ID_EPROTO) { 919 ret = -EPROTO; 920 } else { 921 ret = num - priv->msgs_left; /* The number of transfer */ 922 } 923 out: 924 pm_runtime_put(dev); 925 926 if (ret < 0 && ret != -ENXIO) 927 dev_err(dev, "error %d : %x\n", ret, priv->flags); 928 929 return ret; 930 } 931 932 static int rcar_i2c_master_xfer_atomic(struct i2c_adapter *adap, 933 struct i2c_msg *msgs, 934 int num) 935 { 936 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 937 struct device *dev = rcar_i2c_priv_to_dev(priv); 938 unsigned long j; 939 bool time_left; 940 int ret; 941 942 priv->flags &= ~ID_P_NOT_ATOMIC; 943 944 pm_runtime_get_sync(dev); 945 946 /* Check bus state before init otherwise bus busy info will be lost */ 947 ret = rcar_i2c_bus_barrier(priv); 948 if (ret < 0) 949 goto out; 950 951 rcar_i2c_init(priv); 952 rcar_i2c_first_msg(priv, msgs, num); 953 954 j = jiffies + num * adap->timeout; 955 do { 956 u32 msr = rcar_i2c_read(priv, ICMSR); 957 958 msr &= (rcar_i2c_is_recv(priv) ? RCAR_IRQ_RECV : RCAR_IRQ_SEND) | RCAR_IRQ_STOP; 959 960 if (msr) { 961 if (priv->devtype < I2C_RCAR_GEN3) 962 rcar_i2c_gen2_irq(0, priv); 963 else 964 rcar_i2c_gen3_irq(0, priv); 965 } 966 967 time_left = time_before_eq(jiffies, j); 968 } while (!(priv->flags & ID_DONE) && time_left); 969 970 if (!time_left) { 971 rcar_i2c_init(priv); 972 ret = -ETIMEDOUT; 973 } else if (priv->flags & ID_NACK) { 974 ret = -ENXIO; 975 } else if (priv->flags & ID_ARBLOST) { 976 ret = -EAGAIN; 977 } else if (priv->flags & ID_EPROTO) { 978 ret = -EPROTO; 979 } else { 980 ret = num - priv->msgs_left; /* The number of transfer */ 981 } 982 out: 983 pm_runtime_put(dev); 984 985 if (ret < 0 && ret != -ENXIO) 986 dev_err(dev, "error %d : %x\n", ret, priv->flags); 987 988 return ret; 989 } 990 991 static int rcar_reg_slave(struct i2c_client *slave) 992 { 993 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 994 995 if (priv->slave) 996 return -EBUSY; 997 998 if (slave->flags & I2C_CLIENT_TEN) 999 return -EAFNOSUPPORT; 1000 1001 /* Keep device active for slave address detection logic */ 1002 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv)); 1003 1004 priv->slave = slave; 1005 rcar_i2c_write(priv, ICSAR, slave->addr); 1006 rcar_i2c_write(priv, ICSSR, 0); 1007 rcar_i2c_write(priv, ICSIER, SAR); 1008 rcar_i2c_write(priv, ICSCR, SIE | SDBS); 1009 1010 return 0; 1011 } 1012 1013 static int rcar_unreg_slave(struct i2c_client *slave) 1014 { 1015 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 1016 1017 WARN_ON(!priv->slave); 1018 1019 /* ensure no irq is running before clearing ptr */ 1020 disable_irq(priv->irq); 1021 rcar_i2c_write(priv, ICSIER, 0); 1022 rcar_i2c_write(priv, ICSSR, 0); 1023 enable_irq(priv->irq); 1024 rcar_i2c_write(priv, ICSCR, SDBS); 1025 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */ 1026 1027 priv->slave = NULL; 1028 1029 pm_runtime_put(rcar_i2c_priv_to_dev(priv)); 1030 1031 return 0; 1032 } 1033 1034 static u32 rcar_i2c_func(struct i2c_adapter *adap) 1035 { 1036 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 1037 1038 /* 1039 * This HW can't do: 1040 * I2C_SMBUS_QUICK (setting FSB during START didn't work) 1041 * I2C_M_NOSTART (automatically sends address after START) 1042 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK) 1043 */ 1044 u32 func = I2C_FUNC_I2C | I2C_FUNC_SLAVE | 1045 (I2C_FUNC_SMBUS_EMUL_ALL & ~I2C_FUNC_SMBUS_QUICK); 1046 1047 if (priv->flags & ID_P_HOST_NOTIFY) 1048 func |= I2C_FUNC_SMBUS_HOST_NOTIFY; 1049 1050 return func; 1051 } 1052 1053 static const struct i2c_algorithm rcar_i2c_algo = { 1054 .master_xfer = rcar_i2c_master_xfer, 1055 .master_xfer_atomic = rcar_i2c_master_xfer_atomic, 1056 .functionality = rcar_i2c_func, 1057 .reg_slave = rcar_reg_slave, 1058 .unreg_slave = rcar_unreg_slave, 1059 }; 1060 1061 static const struct i2c_adapter_quirks rcar_i2c_quirks = { 1062 .flags = I2C_AQ_NO_ZERO_LEN, 1063 }; 1064 1065 static const struct of_device_id rcar_i2c_dt_ids[] = { 1066 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, 1067 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, 1068 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, 1069 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, 1070 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, 1071 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, 1072 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, 1073 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, 1074 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 }, 1075 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 }, 1076 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 }, 1077 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 }, 1078 { .compatible = "renesas,rcar-gen4-i2c", .data = (void *)I2C_RCAR_GEN3 }, 1079 {}, 1080 }; 1081 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); 1082 1083 static int rcar_i2c_probe(struct platform_device *pdev) 1084 { 1085 struct rcar_i2c_priv *priv; 1086 struct i2c_adapter *adap; 1087 struct device *dev = &pdev->dev; 1088 unsigned long irqflags = 0; 1089 irqreturn_t (*irqhandler)(int irq, void *ptr) = rcar_i2c_gen3_irq; 1090 int ret; 1091 1092 /* Otherwise logic will break because some bytes must always use PIO */ 1093 BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length"); 1094 1095 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); 1096 if (!priv) 1097 return -ENOMEM; 1098 1099 priv->clk = devm_clk_get(dev, NULL); 1100 if (IS_ERR(priv->clk)) { 1101 dev_err(dev, "cannot get clock\n"); 1102 return PTR_ERR(priv->clk); 1103 } 1104 1105 priv->io = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->res); 1106 if (IS_ERR(priv->io)) 1107 return PTR_ERR(priv->io); 1108 1109 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev); 1110 init_waitqueue_head(&priv->wait); 1111 1112 adap = &priv->adap; 1113 adap->nr = pdev->id; 1114 adap->algo = &rcar_i2c_algo; 1115 adap->class = I2C_CLASS_DEPRECATED; 1116 adap->retries = 3; 1117 adap->dev.parent = dev; 1118 adap->dev.of_node = dev->of_node; 1119 adap->bus_recovery_info = &rcar_i2c_bri; 1120 adap->quirks = &rcar_i2c_quirks; 1121 i2c_set_adapdata(adap, priv); 1122 strscpy(adap->name, pdev->name, sizeof(adap->name)); 1123 1124 /* Init DMA */ 1125 sg_init_table(&priv->sg, 1); 1126 priv->dma_direction = DMA_NONE; 1127 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 1128 1129 /* Activate device for clock calculation */ 1130 pm_runtime_enable(dev); 1131 pm_runtime_get_sync(dev); 1132 ret = rcar_i2c_clock_calculate(priv); 1133 if (ret < 0) { 1134 pm_runtime_put(dev); 1135 goto out_pm_disable; 1136 } 1137 1138 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */ 1139 1140 if (priv->devtype < I2C_RCAR_GEN3) { 1141 irqflags |= IRQF_NO_THREAD; 1142 irqhandler = rcar_i2c_gen2_irq; 1143 } 1144 1145 /* Stay always active when multi-master to keep arbitration working */ 1146 if (of_property_read_bool(dev->of_node, "multi-master")) 1147 priv->flags |= ID_P_PM_BLOCKED; 1148 else 1149 pm_runtime_put(dev); 1150 1151 if (of_property_read_bool(dev->of_node, "smbus")) 1152 priv->flags |= ID_P_HOST_NOTIFY; 1153 1154 if (priv->devtype == I2C_RCAR_GEN3) { 1155 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1156 if (IS_ERR(priv->rstc)) { 1157 ret = PTR_ERR(priv->rstc); 1158 goto out_pm_put; 1159 } 1160 1161 ret = reset_control_status(priv->rstc); 1162 if (ret < 0) 1163 goto out_pm_put; 1164 } 1165 1166 ret = platform_get_irq(pdev, 0); 1167 if (ret < 0) 1168 goto out_pm_put; 1169 priv->irq = ret; 1170 ret = devm_request_irq(dev, priv->irq, irqhandler, irqflags, dev_name(dev), priv); 1171 if (ret < 0) { 1172 dev_err(dev, "cannot get irq %d\n", priv->irq); 1173 goto out_pm_put; 1174 } 1175 1176 platform_set_drvdata(pdev, priv); 1177 1178 ret = i2c_add_numbered_adapter(adap); 1179 if (ret < 0) 1180 goto out_pm_put; 1181 1182 if (priv->flags & ID_P_HOST_NOTIFY) { 1183 priv->host_notify_client = i2c_new_slave_host_notify_device(adap); 1184 if (IS_ERR(priv->host_notify_client)) { 1185 ret = PTR_ERR(priv->host_notify_client); 1186 goto out_del_device; 1187 } 1188 } 1189 1190 dev_info(dev, "probed\n"); 1191 1192 return 0; 1193 1194 out_del_device: 1195 i2c_del_adapter(&priv->adap); 1196 out_pm_put: 1197 if (priv->flags & ID_P_PM_BLOCKED) 1198 pm_runtime_put(dev); 1199 out_pm_disable: 1200 pm_runtime_disable(dev); 1201 return ret; 1202 } 1203 1204 static void rcar_i2c_remove(struct platform_device *pdev) 1205 { 1206 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); 1207 struct device *dev = &pdev->dev; 1208 1209 if (priv->host_notify_client) 1210 i2c_free_slave_host_notify_device(priv->host_notify_client); 1211 i2c_del_adapter(&priv->adap); 1212 rcar_i2c_release_dma(priv); 1213 if (priv->flags & ID_P_PM_BLOCKED) 1214 pm_runtime_put(dev); 1215 pm_runtime_disable(dev); 1216 } 1217 1218 static int rcar_i2c_suspend(struct device *dev) 1219 { 1220 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1221 1222 i2c_mark_adapter_suspended(&priv->adap); 1223 return 0; 1224 } 1225 1226 static int rcar_i2c_resume(struct device *dev) 1227 { 1228 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1229 1230 i2c_mark_adapter_resumed(&priv->adap); 1231 return 0; 1232 } 1233 1234 static const struct dev_pm_ops rcar_i2c_pm_ops = { 1235 NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume) 1236 }; 1237 1238 static struct platform_driver rcar_i2c_driver = { 1239 .driver = { 1240 .name = "i2c-rcar", 1241 .of_match_table = rcar_i2c_dt_ids, 1242 .pm = pm_sleep_ptr(&rcar_i2c_pm_ops), 1243 }, 1244 .probe = rcar_i2c_probe, 1245 .remove_new = rcar_i2c_remove, 1246 }; 1247 1248 module_platform_driver(rcar_i2c_driver); 1249 1250 MODULE_LICENSE("GPL v2"); 1251 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); 1252 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); 1253