1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Renesas R-Car I2C unit 4 * 5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com> 6 * Copyright (C) 2011-2019 Renesas Electronics Corporation 7 * 8 * Copyright (C) 2012-14 Renesas Solutions Corp. 9 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 10 * 11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c 12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> 13 */ 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dmaengine.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/i2c.h> 24 #include <linux/i2c-smbus.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/of.h> 28 #include <linux/platform_device.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/reset.h> 31 #include <linux/slab.h> 32 33 /* register offsets */ 34 #define ICSCR 0x00 /* slave ctrl */ 35 #define ICMCR 0x04 /* master ctrl */ 36 #define ICSSR 0x08 /* slave status */ 37 #define ICMSR 0x0C /* master status */ 38 #define ICSIER 0x10 /* slave irq enable */ 39 #define ICMIER 0x14 /* master irq enable */ 40 #define ICCCR 0x18 /* clock dividers */ 41 #define ICSAR 0x1C /* slave address */ 42 #define ICMAR 0x20 /* master address */ 43 #define ICRXTX 0x24 /* data port */ 44 #define ICCCR2 0x28 /* Clock control 2 */ 45 #define ICMPR 0x2C /* SCL mask control */ 46 #define ICHPR 0x30 /* SCL HIGH control */ 47 #define ICLPR 0x34 /* SCL LOW control */ 48 #define ICFBSCR 0x38 /* first bit setup cycle (Gen3) */ 49 #define ICDMAER 0x3c /* DMA enable (Gen3) */ 50 51 /* ICSCR */ 52 #define SDBS BIT(3) /* slave data buffer select */ 53 #define SIE BIT(2) /* slave interface enable */ 54 #define GCAE BIT(1) /* general call address enable */ 55 #define FNA BIT(0) /* forced non acknowledgment */ 56 57 /* ICMCR */ 58 #define MDBS BIT(7) /* non-fifo mode switch */ 59 #define FSCL BIT(6) /* override SCL pin */ 60 #define FSDA BIT(5) /* override SDA pin */ 61 #define OBPC BIT(4) /* override pins */ 62 #define MIE BIT(3) /* master if enable */ 63 #define TSBE BIT(2) 64 #define FSB BIT(1) /* force stop bit */ 65 #define ESG BIT(0) /* enable start bit gen */ 66 67 /* ICSSR (also for ICSIER) */ 68 #define GCAR BIT(6) /* general call received */ 69 #define STM BIT(5) /* slave transmit mode */ 70 #define SSR BIT(4) /* stop received */ 71 #define SDE BIT(3) /* slave data empty */ 72 #define SDT BIT(2) /* slave data transmitted */ 73 #define SDR BIT(1) /* slave data received */ 74 #define SAR BIT(0) /* slave addr received */ 75 76 /* ICMSR (also for ICMIE) */ 77 #define MNR BIT(6) /* nack received */ 78 #define MAL BIT(5) /* arbitration lost */ 79 #define MST BIT(4) /* sent a stop */ 80 #define MDE BIT(3) 81 #define MDT BIT(2) 82 #define MDR BIT(1) 83 #define MAT BIT(0) /* slave addr xfer done */ 84 85 /* ICDMAER */ 86 #define RSDMAE BIT(3) /* DMA Slave Received Enable */ 87 #define TSDMAE BIT(2) /* DMA Slave Transmitted Enable */ 88 #define RMDMAE BIT(1) /* DMA Master Received Enable */ 89 #define TMDMAE BIT(0) /* DMA Master Transmitted Enable */ 90 91 /* ICCCR2 */ 92 #define FMPE BIT(7) /* Fast Mode Plus Enable */ 93 #define CDFD BIT(2) /* CDF Disable */ 94 #define HLSE BIT(1) /* HIGH/LOW Separate Control Enable */ 95 #define SME BIT(0) /* SCL Mask Enable */ 96 97 /* ICFBSCR */ 98 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ 99 100 #define RCAR_MIN_DMA_LEN 8 101 102 /* SCL low/high ratio 5:4 to meet all I2C timing specs (incl safety margin) */ 103 #define RCAR_SCLD_RATIO 5 104 #define RCAR_SCHD_RATIO 4 105 /* 106 * SMD should be smaller than SCLD/SCHD and is always around 20 in the docs. 107 * Thus, we simply use 20 which works for low and high speeds. 108 */ 109 #define RCAR_DEFAULT_SMD 20 110 111 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) 112 #define RCAR_BUS_PHASE_DATA (MDBS | MIE) 113 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) 114 115 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) 116 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) 117 #define RCAR_IRQ_STOP (MST) 118 119 #define ID_LAST_MSG BIT(0) 120 #define ID_REP_AFTER_RD BIT(1) 121 #define ID_DONE BIT(2) 122 #define ID_ARBLOST BIT(3) 123 #define ID_NACK BIT(4) 124 #define ID_EPROTO BIT(5) 125 /* persistent flags */ 126 #define ID_P_NO_RST_STAT BIT(26) 127 #define ID_P_FMPLUS BIT(27) 128 #define ID_P_NOT_ATOMIC BIT(28) 129 #define ID_P_HOST_NOTIFY BIT(29) 130 #define ID_P_NO_RXDMA BIT(30) /* HW forbids RXDMA sometimes */ 131 #define ID_P_PM_BLOCKED BIT(31) 132 #define ID_P_MASK GENMASK(31, 26) 133 134 #define ID_SLAVE_NACK BIT(0) 135 136 enum rcar_i2c_type { 137 I2C_RCAR_GEN1, 138 I2C_RCAR_GEN2, 139 I2C_RCAR_GEN3, 140 I2C_RCAR_GEN4, 141 I2C_RCAR_GEN5, 142 }; 143 144 struct rcar_i2c_priv { 145 u32 flags; 146 void __iomem *io; 147 struct i2c_adapter adap; 148 struct i2c_msg *msg; 149 int msgs_left; 150 struct clk *clk; 151 152 wait_queue_head_t wait; 153 154 int pos; 155 u32 icccr; 156 u16 schd; 157 u16 scld; 158 u8 smd; 159 u8 recovery_icmcr; /* protected by adapter lock */ 160 enum rcar_i2c_type devtype; 161 struct i2c_client *slave; 162 163 struct resource *res; 164 struct dma_chan *dma_tx; 165 struct dma_chan *dma_rx; 166 struct scatterlist sg; 167 enum dma_data_direction dma_direction; 168 169 struct reset_control *rstc; 170 int irq; 171 172 struct i2c_client *host_notify_client; 173 u8 slave_flags; 174 }; 175 176 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) 177 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) 178 179 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) 180 { 181 writel(val, priv->io + reg); 182 } 183 184 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) 185 { 186 return readl(priv->io + reg); 187 } 188 189 static void rcar_i2c_clear_irq(struct rcar_i2c_priv *priv, u32 val) 190 { 191 writel(~val & 0x7f, priv->io + ICMSR); 192 } 193 194 static int rcar_i2c_get_scl(struct i2c_adapter *adap) 195 { 196 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 197 198 return !!(rcar_i2c_read(priv, ICMCR) & FSCL); 199 } 200 201 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val) 202 { 203 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 204 205 if (val) 206 priv->recovery_icmcr |= FSCL; 207 else 208 priv->recovery_icmcr &= ~FSCL; 209 210 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 211 } 212 213 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val) 214 { 215 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 216 217 if (val) 218 priv->recovery_icmcr |= FSDA; 219 else 220 priv->recovery_icmcr &= ~FSDA; 221 222 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 223 } 224 225 static int rcar_i2c_get_bus_free(struct i2c_adapter *adap) 226 { 227 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 228 229 return !(rcar_i2c_read(priv, ICMCR) & FSDA); 230 } 231 232 static struct i2c_bus_recovery_info rcar_i2c_bri = { 233 .get_scl = rcar_i2c_get_scl, 234 .set_scl = rcar_i2c_set_scl, 235 .set_sda = rcar_i2c_set_sda, 236 .get_bus_free = rcar_i2c_get_bus_free, 237 .recover_bus = i2c_generic_scl_recovery, 238 }; 239 240 static void rcar_i2c_init(struct rcar_i2c_priv *priv) 241 { 242 /* reset master mode */ 243 rcar_i2c_write(priv, ICMIER, 0); 244 rcar_i2c_write(priv, ICMCR, MDBS); 245 rcar_i2c_write(priv, ICMSR, 0); 246 /* start clock */ 247 if (priv->devtype < I2C_RCAR_GEN3) { 248 rcar_i2c_write(priv, ICCCR, priv->icccr); 249 } else { 250 u32 icccr2 = CDFD | HLSE | SME; 251 252 if (priv->flags & ID_P_FMPLUS) 253 icccr2 |= FMPE; 254 255 rcar_i2c_write(priv, ICCCR2, icccr2); 256 rcar_i2c_write(priv, ICCCR, priv->icccr); 257 rcar_i2c_write(priv, ICMPR, priv->smd); 258 rcar_i2c_write(priv, ICHPR, priv->schd); 259 rcar_i2c_write(priv, ICLPR, priv->scld); 260 rcar_i2c_write(priv, ICFBSCR, TCYC17); 261 } 262 } 263 264 static void rcar_i2c_reset_slave(struct rcar_i2c_priv *priv) 265 { 266 rcar_i2c_write(priv, ICSIER, 0); 267 rcar_i2c_write(priv, ICSSR, 0); 268 rcar_i2c_write(priv, ICSCR, SDBS); 269 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */ 270 } 271 272 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) 273 { 274 int ret; 275 u32 val; 276 277 ret = readl_poll_timeout(priv->io + ICMCR, val, !(val & FSDA), 10, 278 priv->adap.timeout); 279 if (ret) { 280 /* Waiting did not help, try to recover */ 281 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL; 282 ret = i2c_recover_bus(&priv->adap); 283 } 284 285 return ret; 286 } 287 288 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv) 289 { 290 u32 cdf, round, ick, sum, scl, cdf_width; 291 unsigned long rate; 292 struct device *dev = rcar_i2c_priv_to_dev(priv); 293 struct i2c_timings t = { 294 .bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ, 295 .scl_fall_ns = 35, 296 .scl_rise_ns = 200, 297 .scl_int_delay_ns = 50, 298 }; 299 300 /* Fall back to previously used values if not supplied */ 301 i2c_parse_fw_timings(dev, &t, false); 302 priv->smd = RCAR_DEFAULT_SMD; 303 304 /* 305 * calculate SCL clock 306 * see 307 * ICCCR (and ICCCR2 for Gen3+) 308 * 309 * ick = clkp / (1 + CDF) 310 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 311 * 312 * for Gen3+: 313 * SCL = clkp / (8 + SMD * 2 + SCLD + SCHD +F[(ticf + tr + intd) * clkp]) 314 * 315 * ick : I2C internal clock < 20 MHz 316 * ticf : I2C SCL falling time 317 * tr : I2C SCL rising time 318 * intd : LSI internal delay 319 * clkp : peripheral_clk 320 * F[] : integer up-valuation 321 */ 322 rate = clk_get_rate(priv->clk); 323 cdf = rate / 20000000; 324 cdf_width = (priv->devtype == I2C_RCAR_GEN1) ? 2 : 3; 325 if (cdf >= 1U << cdf_width) 326 goto err_no_val; 327 328 if (t.bus_freq_hz > I2C_MAX_FAST_MODE_FREQ && priv->devtype >= I2C_RCAR_GEN4) 329 priv->flags |= ID_P_FMPLUS; 330 else 331 priv->flags &= ~ID_P_FMPLUS; 332 333 /* On Gen3+, we use cdf only for the filters, not as a SCL divider */ 334 ick = rate / (priv->devtype < I2C_RCAR_GEN3 ? (cdf + 1) : 1); 335 336 /* 337 * It is impossible to calculate a large scale number on u32. Separate it. 338 * 339 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd) 340 * = F[sum * ick / 1000000000] 341 * = F[(ick / 1000000) * sum / 1000] 342 */ 343 sum = t.scl_fall_ns + t.scl_rise_ns + t.scl_int_delay_ns; 344 round = DIV_ROUND_CLOSEST(ick, 1000000); 345 round = DIV_ROUND_CLOSEST(round * sum, 1000); 346 347 if (priv->devtype < I2C_RCAR_GEN3) { 348 u32 scgd; 349 /* 350 * SCL = ick / (20 + 8 * SCGD + F[(ticf + tr + intd) * ick]) 351 * 20 + 8 * SCGD + F[...] = ick / SCL 352 * SCGD = ((ick / SCL) - 20 - F[...]) / 8 353 * Result (= SCL) should be less than bus_speed for hardware safety 354 */ 355 scgd = DIV_ROUND_UP(ick, t.bus_freq_hz ?: 1); 356 scgd = DIV_ROUND_UP(scgd - 20 - round, 8); 357 scl = ick / (20 + 8 * scgd + round); 358 359 if (scgd > 0x3f) 360 goto err_no_val; 361 362 dev_dbg(dev, "clk %u/%u(%lu), round %u, CDF: %u, SCGD: %u\n", 363 scl, t.bus_freq_hz, rate, round, cdf, scgd); 364 365 priv->icccr = scgd << cdf_width | cdf; 366 } else { 367 u32 x, sum_ratio = RCAR_SCHD_RATIO + RCAR_SCLD_RATIO; 368 /* 369 * SCLD/SCHD ratio and SMD default value are explained above 370 * where they are defined. With these definitions, we can compute 371 * x as a base value for the SCLD/SCHD ratio: 372 * 373 * SCL = clkp / (8 + 2 * SMD + SCLD + SCHD + F[(ticf + tr + intd) * clkp]) 374 * SCL = clkp / (8 + 2 * SMD + RCAR_SCLD_RATIO * x 375 * + RCAR_SCHD_RATIO * x + F[...]) 376 * 377 * with: sum_ratio = RCAR_SCLD_RATIO + RCAR_SCHD_RATIO 378 * 379 * SCL = clkp / (8 + 2 * smd + sum_ratio * x + F[...]) 380 * 8 + 2 * smd + sum_ratio * x + F[...] = clkp / SCL 381 * x = ((clkp / SCL) - 8 - 2 * smd - F[...]) / sum_ratio 382 */ 383 x = DIV_ROUND_UP(rate, t.bus_freq_hz ?: 1); 384 x = DIV_ROUND_UP(x - 8 - 2 * priv->smd - round, sum_ratio); 385 scl = rate / (8 + 2 * priv->smd + sum_ratio * x + round); 386 387 if (x == 0 || x * RCAR_SCLD_RATIO > 0xffff) 388 goto err_no_val; 389 390 priv->icccr = cdf; 391 priv->schd = RCAR_SCHD_RATIO * x; 392 priv->scld = RCAR_SCLD_RATIO * x; 393 if (priv->smd >= priv->schd) 394 priv->smd = priv->schd - 1; 395 396 dev_dbg(dev, "clk %u/%u(%lu), round %u, CDF: %u SCHD %u SCLD %u SMD %u\n", 397 scl, t.bus_freq_hz, rate, round, cdf, priv->schd, priv->scld, priv->smd); 398 } 399 400 return 0; 401 402 err_no_val: 403 dev_err(dev, "it is impossible to calculate best SCL\n"); 404 return -EINVAL; 405 } 406 407 /* 408 * We don't have a test case but the HW engineers say that the write order of 409 * ICMSR and ICMCR depends on whether we issue START or REP_START. So, ICMSR 410 * handling is outside of this function. First messages clear ICMSR before this 411 * function, interrupt handlers clear the relevant bits after this function. 412 */ 413 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) 414 { 415 int read = !!rcar_i2c_is_recv(priv); 416 bool rep_start = !(priv->flags & ID_REP_AFTER_RD); 417 418 priv->pos = 0; 419 priv->flags &= ID_P_MASK; 420 421 if (priv->msgs_left == 1) 422 priv->flags |= ID_LAST_MSG; 423 424 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg)); 425 if (priv->flags & ID_P_NOT_ATOMIC) 426 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); 427 428 if (rep_start) 429 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 430 } 431 432 static void rcar_i2c_first_msg(struct rcar_i2c_priv *priv, 433 struct i2c_msg *msgs, int num) 434 { 435 priv->msg = msgs; 436 priv->msgs_left = num; 437 rcar_i2c_write(priv, ICMSR, 0); /* must be before preparing msg */ 438 rcar_i2c_prepare_msg(priv); 439 } 440 441 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) 442 { 443 priv->msg++; 444 priv->msgs_left--; 445 rcar_i2c_prepare_msg(priv); 446 /* ICMSR handling must come afterwards in the irq handler */ 447 } 448 449 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv, bool terminate) 450 { 451 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE 452 ? priv->dma_rx : priv->dma_tx; 453 454 /* only allowed from thread context! */ 455 if (terminate) 456 dmaengine_terminate_sync(chan); 457 458 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), 459 sg_dma_len(&priv->sg), priv->dma_direction); 460 461 /* Gen3+ can only do one RXDMA per transfer and we just completed it */ 462 if (priv->devtype >= I2C_RCAR_GEN3 && 463 priv->dma_direction == DMA_FROM_DEVICE) 464 priv->flags |= ID_P_NO_RXDMA; 465 466 priv->dma_direction = DMA_NONE; 467 468 /* Disable DMA Master Received/Transmitted, must be last! */ 469 rcar_i2c_write(priv, ICDMAER, 0); 470 } 471 472 static void rcar_i2c_dma_callback(void *data) 473 { 474 struct rcar_i2c_priv *priv = data; 475 476 priv->pos += sg_dma_len(&priv->sg); 477 478 rcar_i2c_cleanup_dma(priv, false); 479 } 480 481 static bool rcar_i2c_dma(struct rcar_i2c_priv *priv) 482 { 483 struct device *dev = rcar_i2c_priv_to_dev(priv); 484 struct i2c_msg *msg = priv->msg; 485 bool read = msg->flags & I2C_M_RD; 486 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 487 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx; 488 struct dma_async_tx_descriptor *txdesc; 489 dma_addr_t dma_addr; 490 dma_cookie_t cookie; 491 unsigned char *buf; 492 int len; 493 494 /* Do various checks to see if DMA is feasible at all */ 495 if (!(priv->flags & ID_P_NOT_ATOMIC) || IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN || 496 !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA)) 497 return false; 498 499 if (read) { 500 /* 501 * The last two bytes needs to be fetched using PIO in 502 * order for the STOP phase to work. 503 */ 504 buf = priv->msg->buf; 505 len = priv->msg->len - 2; 506 } else { 507 /* 508 * First byte in message was sent using PIO. 509 */ 510 buf = priv->msg->buf + 1; 511 len = priv->msg->len - 1; 512 } 513 514 dma_addr = dma_map_single(chan->device->dev, buf, len, dir); 515 if (dma_mapping_error(chan->device->dev, dma_addr)) { 516 dev_dbg(dev, "dma map failed, using PIO\n"); 517 return false; 518 } 519 520 sg_dma_len(&priv->sg) = len; 521 sg_dma_address(&priv->sg) = dma_addr; 522 523 priv->dma_direction = dir; 524 525 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1, 526 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 527 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 528 if (!txdesc) { 529 dev_dbg(dev, "dma prep slave sg failed, using PIO\n"); 530 rcar_i2c_cleanup_dma(priv, false); 531 return false; 532 } 533 534 txdesc->callback = rcar_i2c_dma_callback; 535 txdesc->callback_param = priv; 536 537 cookie = dmaengine_submit(txdesc); 538 if (dma_submit_error(cookie)) { 539 dev_dbg(dev, "submitting dma failed, using PIO\n"); 540 rcar_i2c_cleanup_dma(priv, false); 541 return false; 542 } 543 544 /* Enable DMA Master Received/Transmitted */ 545 if (read) 546 rcar_i2c_write(priv, ICDMAER, RMDMAE); 547 else 548 rcar_i2c_write(priv, ICDMAER, TMDMAE); 549 550 dma_async_issue_pending(chan); 551 return true; 552 } 553 554 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) 555 { 556 struct i2c_msg *msg = priv->msg; 557 u32 irqs_to_clear = MDE; 558 559 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 560 if (WARN(!(msr & MDE), "spurious irq")) 561 return; 562 563 if (msr & MAT) 564 irqs_to_clear |= MAT; 565 566 /* Check if DMA can be enabled and take over */ 567 if (priv->pos == 1 && rcar_i2c_dma(priv)) 568 return; 569 570 if (priv->pos < msg->len) { 571 /* 572 * Prepare next data to ICRXTX register. 573 * This data will go to _SHIFT_ register. 574 * 575 * * 576 * [ICRXTX] -> [SHIFT] -> [I2C bus] 577 */ 578 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); 579 priv->pos++; 580 } else { 581 /* 582 * The last data was pushed to ICRXTX on _PREV_ empty irq. 583 * It is on _SHIFT_ register, and will sent to I2C bus. 584 * 585 * * 586 * [ICRXTX] -> [SHIFT] -> [I2C bus] 587 */ 588 589 if (priv->flags & ID_LAST_MSG) 590 /* 591 * If current msg is the _LAST_ msg, 592 * prepare stop condition here. 593 * ID_DONE will be set on STOP irq. 594 */ 595 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 596 else 597 rcar_i2c_next_msg(priv); 598 } 599 600 rcar_i2c_clear_irq(priv, irqs_to_clear); 601 } 602 603 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) 604 { 605 struct i2c_msg *msg = priv->msg; 606 bool recv_len_init = priv->pos == 0 && msg->flags & I2C_M_RECV_LEN; 607 u32 irqs_to_clear = MDR; 608 609 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 610 if (!(msr & MDR)) 611 return; 612 613 if (msr & MAT) { 614 irqs_to_clear |= MAT; 615 /* 616 * Address transfer phase finished, but no data at this point. 617 * Try to use DMA to receive data. 618 */ 619 rcar_i2c_dma(priv); 620 } else if (priv->pos < msg->len) { 621 /* get received data */ 622 u8 data = rcar_i2c_read(priv, ICRXTX); 623 624 msg->buf[priv->pos] = data; 625 if (recv_len_init) { 626 if (data == 0 || data > I2C_SMBUS_BLOCK_MAX) { 627 priv->flags |= ID_DONE | ID_EPROTO; 628 return; 629 } 630 msg->len += msg->buf[0]; 631 /* Enough data for DMA? */ 632 if (rcar_i2c_dma(priv)) 633 return; 634 /* new length after RECV_LEN now properly initialized */ 635 recv_len_init = false; 636 } 637 priv->pos++; 638 } 639 640 /* 641 * If next received data is the _LAST_ and we are not waiting for a new 642 * length because of RECV_LEN, then go to a new phase. 643 */ 644 if (priv->pos + 1 == msg->len && !recv_len_init) { 645 if (priv->flags & ID_LAST_MSG) { 646 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 647 } else { 648 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 649 priv->flags |= ID_REP_AFTER_RD; 650 } 651 } 652 653 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG)) 654 rcar_i2c_next_msg(priv); 655 656 rcar_i2c_clear_irq(priv, irqs_to_clear); 657 } 658 659 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) 660 { 661 u32 ssr_raw, ssr_filtered; 662 u8 value; 663 int ret; 664 665 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; 666 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); 667 668 if (!ssr_filtered) 669 return false; 670 671 /* address detected */ 672 if (ssr_filtered & SAR) { 673 /* read or write request */ 674 if (ssr_raw & STM) { 675 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); 676 rcar_i2c_write(priv, ICRXTX, value); 677 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); 678 } else { 679 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); 680 if (ret) 681 priv->slave_flags |= ID_SLAVE_NACK; 682 683 rcar_i2c_read(priv, ICRXTX); /* dummy read */ 684 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); 685 } 686 687 /* Clear SSR, too, because of old STOPs to other clients than us */ 688 rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff); 689 } 690 691 /* master sent stop */ 692 if (ssr_filtered & SSR) { 693 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); 694 rcar_i2c_write(priv, ICSCR, SIE | SDBS); /* clear our NACK */ 695 priv->slave_flags &= ~ID_SLAVE_NACK; 696 rcar_i2c_write(priv, ICSIER, SAR); 697 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); 698 } 699 700 /* master wants to write to us */ 701 if (ssr_filtered & SDR) { 702 value = rcar_i2c_read(priv, ICRXTX); 703 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); 704 if (ret) 705 priv->slave_flags |= ID_SLAVE_NACK; 706 707 /* Send NACK in case of error, but it will come 1 byte late :( */ 708 rcar_i2c_write(priv, ICSCR, SIE | SDBS | 709 (priv->slave_flags & ID_SLAVE_NACK ? FNA : 0)); 710 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); 711 } 712 713 /* master wants to read from us */ 714 if (ssr_filtered & SDE) { 715 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); 716 rcar_i2c_write(priv, ICRXTX, value); 717 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); 718 } 719 720 return true; 721 } 722 723 /* 724 * This driver has a lock-free design because there are IP cores (at least 725 * R-Car Gen2) which have an inherent race condition in their hardware design. 726 * There, we need to switch to RCAR_BUS_PHASE_DATA as soon as possible after 727 * the interrupt was generated, otherwise an unwanted repeated message gets 728 * generated. It turned out that taking a spinlock at the beginning of the ISR 729 * was already causing repeated messages. Thus, this driver was converted to 730 * the now lockless behaviour. Please keep this in mind when hacking the driver. 731 * R-Car Gen3 seems to have this fixed but earlier versions than R-Car Gen2 are 732 * likely affected. Therefore, we have different interrupt handler entries. 733 */ 734 static irqreturn_t rcar_i2c_irq(int irq, struct rcar_i2c_priv *priv, u32 msr) 735 { 736 if (!msr) { 737 if (rcar_i2c_slave_irq(priv)) 738 return IRQ_HANDLED; 739 740 return IRQ_NONE; 741 } 742 743 /* Arbitration lost */ 744 if (msr & MAL) { 745 priv->flags |= ID_DONE | ID_ARBLOST; 746 goto out; 747 } 748 749 /* Nack */ 750 if (msr & MNR) { 751 /* HW automatically sends STOP after received NACK */ 752 if (priv->flags & ID_P_NOT_ATOMIC) 753 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); 754 priv->flags |= ID_NACK; 755 goto out; 756 } 757 758 /* Stop */ 759 if (msr & MST) { 760 priv->msgs_left--; /* The last message also made it */ 761 priv->flags |= ID_DONE; 762 goto out; 763 } 764 765 if (rcar_i2c_is_recv(priv)) 766 rcar_i2c_irq_recv(priv, msr); 767 else 768 rcar_i2c_irq_send(priv, msr); 769 770 out: 771 if (priv->flags & ID_DONE) { 772 rcar_i2c_write(priv, ICMIER, 0); 773 rcar_i2c_write(priv, ICMSR, 0); 774 if (priv->flags & ID_P_NOT_ATOMIC) 775 wake_up(&priv->wait); 776 } 777 778 return IRQ_HANDLED; 779 } 780 781 static irqreturn_t rcar_i2c_gen2_irq(int irq, void *ptr) 782 { 783 struct rcar_i2c_priv *priv = ptr; 784 u32 msr; 785 786 /* Clear START or STOP immediately, except for REPSTART after read */ 787 if (likely(!(priv->flags & ID_REP_AFTER_RD))) 788 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); 789 790 /* Only handle interrupts that are currently enabled */ 791 msr = rcar_i2c_read(priv, ICMSR); 792 if (priv->flags & ID_P_NOT_ATOMIC) 793 msr &= rcar_i2c_read(priv, ICMIER); 794 795 return rcar_i2c_irq(irq, priv, msr); 796 } 797 798 static irqreturn_t rcar_i2c_gen3_irq(int irq, void *ptr) 799 { 800 struct rcar_i2c_priv *priv = ptr; 801 u32 msr; 802 803 /* Only handle interrupts that are currently enabled */ 804 msr = rcar_i2c_read(priv, ICMSR); 805 if (priv->flags & ID_P_NOT_ATOMIC) 806 msr &= rcar_i2c_read(priv, ICMIER); 807 808 /* 809 * Clear START or STOP immediately, except for REPSTART after read or 810 * if a spurious interrupt was detected. 811 */ 812 if (likely(!(priv->flags & ID_REP_AFTER_RD) && msr)) 813 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); 814 815 return rcar_i2c_irq(irq, priv, msr); 816 } 817 818 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev, 819 enum dma_transfer_direction dir, 820 dma_addr_t port_addr) 821 { 822 struct dma_chan *chan; 823 struct dma_slave_config cfg; 824 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; 825 int ret; 826 827 chan = dma_request_chan(dev, chan_name); 828 if (IS_ERR(chan)) { 829 dev_dbg(dev, "request_channel failed for %s (%ld)\n", 830 chan_name, PTR_ERR(chan)); 831 return chan; 832 } 833 834 memset(&cfg, 0, sizeof(cfg)); 835 cfg.direction = dir; 836 if (dir == DMA_MEM_TO_DEV) { 837 cfg.dst_addr = port_addr; 838 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 839 } else { 840 cfg.src_addr = port_addr; 841 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 842 } 843 844 ret = dmaengine_slave_config(chan, &cfg); 845 if (ret) { 846 dev_dbg(dev, "slave_config failed for %s (%d)\n", 847 chan_name, ret); 848 dma_release_channel(chan); 849 return ERR_PTR(ret); 850 } 851 852 dev_dbg(dev, "got DMA channel for %s\n", chan_name); 853 return chan; 854 } 855 856 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv, 857 struct i2c_msg *msg) 858 { 859 struct device *dev = rcar_i2c_priv_to_dev(priv); 860 bool read; 861 struct dma_chan *chan; 862 enum dma_transfer_direction dir; 863 864 read = msg->flags & I2C_M_RD; 865 866 chan = read ? priv->dma_rx : priv->dma_tx; 867 if (PTR_ERR(chan) != -EPROBE_DEFER) 868 return; 869 870 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 871 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX); 872 873 if (read) 874 priv->dma_rx = chan; 875 else 876 priv->dma_tx = chan; 877 } 878 879 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv) 880 { 881 if (!IS_ERR(priv->dma_tx)) { 882 dma_release_channel(priv->dma_tx); 883 priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 884 } 885 886 if (!IS_ERR(priv->dma_rx)) { 887 dma_release_channel(priv->dma_rx); 888 priv->dma_rx = ERR_PTR(-EPROBE_DEFER); 889 } 890 } 891 892 /* I2C is a special case, we need to poll the status of a reset */ 893 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv) 894 { 895 int ret; 896 897 /* Don't reset if a slave instance is currently running */ 898 if (priv->slave) 899 return -EISCONN; 900 901 ret = reset_control_reset(priv->rstc); 902 if (ret) 903 return ret; 904 905 if (priv->flags & ID_P_NO_RST_STAT) 906 return 0; 907 908 return read_poll_timeout_atomic(reset_control_status, ret, ret == 0, 909 1, 100, false, priv->rstc); 910 } 911 912 static int rcar_i2c_master_xfer(struct i2c_adapter *adap, 913 struct i2c_msg *msgs, 914 int num) 915 { 916 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 917 struct device *dev = rcar_i2c_priv_to_dev(priv); 918 int i, ret; 919 long time_left; 920 921 priv->flags |= ID_P_NOT_ATOMIC; 922 923 pm_runtime_get_sync(dev); 924 925 /* Check bus state before init otherwise bus busy info will be lost */ 926 ret = rcar_i2c_bus_barrier(priv); 927 if (ret < 0) 928 goto out; 929 930 /* Gen3+ needs a reset. That also allows RXDMA once */ 931 if (priv->devtype >= I2C_RCAR_GEN3) { 932 ret = rcar_i2c_do_reset(priv); 933 if (ret) 934 goto out; 935 priv->flags &= ~ID_P_NO_RXDMA; 936 } 937 938 rcar_i2c_init(priv); 939 940 for (i = 0; i < num; i++) 941 rcar_i2c_request_dma(priv, msgs + i); 942 943 rcar_i2c_first_msg(priv, msgs, num); 944 945 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE, 946 num * adap->timeout); 947 948 /* cleanup DMA if it couldn't complete properly due to an error */ 949 if (priv->dma_direction != DMA_NONE) 950 rcar_i2c_cleanup_dma(priv, true); 951 952 if (!time_left) { 953 rcar_i2c_init(priv); 954 ret = -ETIMEDOUT; 955 } else if (priv->flags & ID_NACK) { 956 ret = -ENXIO; 957 } else if (priv->flags & ID_ARBLOST) { 958 ret = -EAGAIN; 959 } else if (priv->flags & ID_EPROTO) { 960 ret = -EPROTO; 961 } else { 962 ret = num - priv->msgs_left; /* The number of transfer */ 963 } 964 out: 965 pm_runtime_put(dev); 966 967 if (ret < 0 && ret != -ENXIO) 968 dev_err(dev, "error %d : %x\n", ret, priv->flags); 969 970 return ret; 971 } 972 973 static int rcar_i2c_master_xfer_atomic(struct i2c_adapter *adap, 974 struct i2c_msg *msgs, 975 int num) 976 { 977 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 978 struct device *dev = rcar_i2c_priv_to_dev(priv); 979 unsigned long j; 980 bool time_left; 981 int ret; 982 983 priv->flags &= ~ID_P_NOT_ATOMIC; 984 985 pm_runtime_get_sync(dev); 986 987 /* Check bus state before init otherwise bus busy info will be lost */ 988 ret = rcar_i2c_bus_barrier(priv); 989 if (ret < 0) 990 goto out; 991 992 rcar_i2c_init(priv); 993 rcar_i2c_first_msg(priv, msgs, num); 994 995 j = jiffies + num * adap->timeout; 996 do { 997 u32 msr = rcar_i2c_read(priv, ICMSR); 998 999 msr &= (rcar_i2c_is_recv(priv) ? RCAR_IRQ_RECV : RCAR_IRQ_SEND) | RCAR_IRQ_STOP; 1000 1001 if (msr) { 1002 if (priv->devtype < I2C_RCAR_GEN3) 1003 rcar_i2c_gen2_irq(0, priv); 1004 else 1005 rcar_i2c_gen3_irq(0, priv); 1006 } 1007 1008 time_left = time_before_eq(jiffies, j); 1009 } while (!(priv->flags & ID_DONE) && time_left); 1010 1011 if (!time_left) { 1012 rcar_i2c_init(priv); 1013 ret = -ETIMEDOUT; 1014 } else if (priv->flags & ID_NACK) { 1015 ret = -ENXIO; 1016 } else if (priv->flags & ID_ARBLOST) { 1017 ret = -EAGAIN; 1018 } else if (priv->flags & ID_EPROTO) { 1019 ret = -EPROTO; 1020 } else { 1021 ret = num - priv->msgs_left; /* The number of transfer */ 1022 } 1023 out: 1024 pm_runtime_put(dev); 1025 1026 if (ret < 0 && ret != -ENXIO) 1027 dev_err(dev, "error %d : %x\n", ret, priv->flags); 1028 1029 return ret; 1030 } 1031 1032 static int rcar_reg_slave(struct i2c_client *slave) 1033 { 1034 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 1035 1036 if (priv->slave) 1037 return -EBUSY; 1038 1039 if (slave->flags & I2C_CLIENT_TEN) 1040 return -EAFNOSUPPORT; 1041 1042 /* Keep device active for slave address detection logic */ 1043 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv)); 1044 1045 priv->slave = slave; 1046 rcar_i2c_write(priv, ICSAR, slave->addr); 1047 rcar_i2c_write(priv, ICSSR, 0); 1048 rcar_i2c_write(priv, ICSIER, SAR); 1049 rcar_i2c_write(priv, ICSCR, SIE | SDBS); 1050 1051 return 0; 1052 } 1053 1054 static int rcar_unreg_slave(struct i2c_client *slave) 1055 { 1056 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 1057 1058 WARN_ON(!priv->slave); 1059 1060 /* ensure no irq is running before clearing ptr */ 1061 disable_irq(priv->irq); 1062 rcar_i2c_reset_slave(priv); 1063 enable_irq(priv->irq); 1064 1065 priv->slave = NULL; 1066 1067 pm_runtime_put(rcar_i2c_priv_to_dev(priv)); 1068 1069 return 0; 1070 } 1071 1072 static u32 rcar_i2c_func(struct i2c_adapter *adap) 1073 { 1074 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 1075 1076 /* 1077 * This HW can't do: 1078 * I2C_SMBUS_QUICK (setting FSB during START didn't work) 1079 * I2C_M_NOSTART (automatically sends address after START) 1080 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK) 1081 */ 1082 u32 func = I2C_FUNC_I2C | I2C_FUNC_SLAVE | 1083 (I2C_FUNC_SMBUS_EMUL_ALL & ~I2C_FUNC_SMBUS_QUICK); 1084 1085 if (priv->flags & ID_P_HOST_NOTIFY) 1086 func |= I2C_FUNC_SMBUS_HOST_NOTIFY; 1087 1088 return func; 1089 } 1090 1091 static const struct i2c_algorithm rcar_i2c_algo = { 1092 .xfer = rcar_i2c_master_xfer, 1093 .xfer_atomic = rcar_i2c_master_xfer_atomic, 1094 .functionality = rcar_i2c_func, 1095 .reg_slave = rcar_reg_slave, 1096 .unreg_slave = rcar_unreg_slave, 1097 }; 1098 1099 static const struct i2c_adapter_quirks rcar_i2c_quirks = { 1100 .flags = I2C_AQ_NO_ZERO_LEN, 1101 }; 1102 1103 static const struct of_device_id rcar_i2c_dt_ids[] = { 1104 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, 1105 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, 1106 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, 1107 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, 1108 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, 1109 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, 1110 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, 1111 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, 1112 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 }, 1113 /* S4 has no FM+ bit */ 1114 { .compatible = "renesas,i2c-r8a779f0", .data = (void *)I2C_RCAR_GEN3 }, 1115 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 }, 1116 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 }, 1117 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 }, 1118 { .compatible = "renesas,rcar-gen4-i2c", .data = (void *)I2C_RCAR_GEN4 }, 1119 { .compatible = "renesas,rcar-gen5-i2c", .data = (void *)I2C_RCAR_GEN5 }, 1120 {}, 1121 }; 1122 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); 1123 1124 static int rcar_i2c_probe(struct platform_device *pdev) 1125 { 1126 struct rcar_i2c_priv *priv; 1127 struct i2c_adapter *adap; 1128 struct device *dev = &pdev->dev; 1129 unsigned long irqflags = 0; 1130 irqreturn_t (*irqhandler)(int irq, void *ptr) = rcar_i2c_gen3_irq; 1131 int ret; 1132 1133 /* Otherwise logic will break because some bytes must always use PIO */ 1134 BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length"); 1135 1136 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); 1137 if (!priv) 1138 return -ENOMEM; 1139 1140 priv->clk = devm_clk_get(dev, NULL); 1141 if (IS_ERR(priv->clk)) { 1142 dev_err(dev, "cannot get clock\n"); 1143 return PTR_ERR(priv->clk); 1144 } 1145 1146 priv->io = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->res); 1147 if (IS_ERR(priv->io)) 1148 return PTR_ERR(priv->io); 1149 1150 priv->devtype = (kernel_ulong_t)of_device_get_match_data(dev); 1151 init_waitqueue_head(&priv->wait); 1152 1153 adap = &priv->adap; 1154 adap->nr = pdev->id; 1155 adap->algo = &rcar_i2c_algo; 1156 adap->class = I2C_CLASS_DEPRECATED; 1157 adap->retries = 3; 1158 adap->dev.parent = dev; 1159 adap->dev.of_node = dev->of_node; 1160 adap->bus_recovery_info = &rcar_i2c_bri; 1161 adap->quirks = &rcar_i2c_quirks; 1162 i2c_set_adapdata(adap, priv); 1163 strscpy(adap->name, pdev->name, sizeof(adap->name)); 1164 1165 /* Init DMA */ 1166 sg_init_table(&priv->sg, 1); 1167 priv->dma_direction = DMA_NONE; 1168 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 1169 1170 /* Activate device for clock calculation */ 1171 pm_runtime_enable(dev); 1172 pm_runtime_get_sync(dev); 1173 ret = rcar_i2c_clock_calculate(priv); 1174 if (ret < 0) { 1175 pm_runtime_put(dev); 1176 goto out_pm_disable; 1177 } 1178 1179 /* Bring hardware to known state */ 1180 rcar_i2c_init(priv); 1181 rcar_i2c_reset_slave(priv); 1182 1183 /* Stay always active when multi-master to keep arbitration working */ 1184 if (of_property_read_bool(dev->of_node, "multi-master")) 1185 priv->flags |= ID_P_PM_BLOCKED; 1186 else 1187 pm_runtime_put(dev); 1188 1189 if (of_property_read_bool(dev->of_node, "smbus")) 1190 priv->flags |= ID_P_HOST_NOTIFY; 1191 1192 if (priv->devtype < I2C_RCAR_GEN3) { 1193 irqflags |= IRQF_NO_THREAD; 1194 irqhandler = rcar_i2c_gen2_irq; 1195 } else { 1196 /* R-Car Gen3+ needs a reset before every transfer */ 1197 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1198 if (IS_ERR(priv->rstc)) { 1199 ret = PTR_ERR(priv->rstc); 1200 goto out_pm_put; 1201 } 1202 1203 ret = reset_control_status(priv->rstc); 1204 /* Some SCMI firmware does not support reading reset status */ 1205 if (ret == -ENOTSUPP) 1206 priv->flags |= ID_P_NO_RST_STAT; 1207 else if (ret < 0) 1208 goto out_pm_put; 1209 1210 /* hard reset disturbs HostNotify local target, so disable it */ 1211 priv->flags &= ~ID_P_HOST_NOTIFY; 1212 } 1213 1214 ret = platform_get_irq(pdev, 0); 1215 if (ret < 0) 1216 goto out_pm_put; 1217 priv->irq = ret; 1218 ret = devm_request_irq(dev, priv->irq, irqhandler, irqflags, dev_name(dev), priv); 1219 if (ret < 0) { 1220 dev_err(dev, "cannot get irq %d\n", priv->irq); 1221 goto out_pm_put; 1222 } 1223 1224 platform_set_drvdata(pdev, priv); 1225 1226 ret = i2c_add_numbered_adapter(adap); 1227 if (ret < 0) 1228 goto out_pm_put; 1229 1230 if (priv->flags & ID_P_HOST_NOTIFY) { 1231 priv->host_notify_client = i2c_new_slave_host_notify_device(adap); 1232 if (IS_ERR(priv->host_notify_client)) { 1233 ret = PTR_ERR(priv->host_notify_client); 1234 goto out_del_device; 1235 } 1236 } 1237 1238 dev_info(dev, "probed\n"); 1239 1240 return 0; 1241 1242 out_del_device: 1243 i2c_del_adapter(&priv->adap); 1244 out_pm_put: 1245 if (priv->flags & ID_P_PM_BLOCKED) 1246 pm_runtime_put(dev); 1247 out_pm_disable: 1248 pm_runtime_disable(dev); 1249 return ret; 1250 } 1251 1252 static void rcar_i2c_remove(struct platform_device *pdev) 1253 { 1254 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); 1255 struct device *dev = &pdev->dev; 1256 1257 if (priv->host_notify_client) 1258 i2c_free_slave_host_notify_device(priv->host_notify_client); 1259 i2c_del_adapter(&priv->adap); 1260 rcar_i2c_release_dma(priv); 1261 if (priv->flags & ID_P_PM_BLOCKED) 1262 pm_runtime_put(dev); 1263 pm_runtime_disable(dev); 1264 } 1265 1266 static int rcar_i2c_suspend(struct device *dev) 1267 { 1268 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1269 1270 i2c_mark_adapter_suspended(&priv->adap); 1271 return 0; 1272 } 1273 1274 static int rcar_i2c_resume(struct device *dev) 1275 { 1276 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1277 1278 i2c_mark_adapter_resumed(&priv->adap); 1279 return 0; 1280 } 1281 1282 static const struct dev_pm_ops rcar_i2c_pm_ops = { 1283 NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume) 1284 }; 1285 1286 static struct platform_driver rcar_i2c_driver = { 1287 .driver = { 1288 .name = "i2c-rcar", 1289 .of_match_table = rcar_i2c_dt_ids, 1290 .pm = pm_sleep_ptr(&rcar_i2c_pm_ops), 1291 }, 1292 .probe = rcar_i2c_probe, 1293 .remove = rcar_i2c_remove, 1294 }; 1295 1296 module_platform_driver(rcar_i2c_driver); 1297 1298 MODULE_LICENSE("GPL v2"); 1299 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); 1300 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); 1301