1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Renesas R-Car I2C unit 4 * 5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com> 6 * Copyright (C) 2011-2019 Renesas Electronics Corporation 7 * 8 * Copyright (C) 2012-14 Renesas Solutions Corp. 9 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 10 * 11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c 12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> 13 */ 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dmaengine.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/err.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/i2c.h> 24 #include <linux/i2c-smbus.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/of_device.h> 28 #include <linux/platform_device.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/reset.h> 31 #include <linux/slab.h> 32 33 /* register offsets */ 34 #define ICSCR 0x00 /* slave ctrl */ 35 #define ICMCR 0x04 /* master ctrl */ 36 #define ICSSR 0x08 /* slave status */ 37 #define ICMSR 0x0C /* master status */ 38 #define ICSIER 0x10 /* slave irq enable */ 39 #define ICMIER 0x14 /* master irq enable */ 40 #define ICCCR 0x18 /* clock dividers */ 41 #define ICSAR 0x1C /* slave address */ 42 #define ICMAR 0x20 /* master address */ 43 #define ICRXTX 0x24 /* data port */ 44 #define ICFBSCR 0x38 /* first bit setup cycle (Gen3) */ 45 #define ICDMAER 0x3c /* DMA enable (Gen3) */ 46 47 /* ICSCR */ 48 #define SDBS (1 << 3) /* slave data buffer select */ 49 #define SIE (1 << 2) /* slave interface enable */ 50 #define GCAE (1 << 1) /* general call address enable */ 51 #define FNA (1 << 0) /* forced non acknowledgment */ 52 53 /* ICMCR */ 54 #define MDBS (1 << 7) /* non-fifo mode switch */ 55 #define FSCL (1 << 6) /* override SCL pin */ 56 #define FSDA (1 << 5) /* override SDA pin */ 57 #define OBPC (1 << 4) /* override pins */ 58 #define MIE (1 << 3) /* master if enable */ 59 #define TSBE (1 << 2) 60 #define FSB (1 << 1) /* force stop bit */ 61 #define ESG (1 << 0) /* enable start bit gen */ 62 63 /* ICSSR (also for ICSIER) */ 64 #define GCAR (1 << 6) /* general call received */ 65 #define STM (1 << 5) /* slave transmit mode */ 66 #define SSR (1 << 4) /* stop received */ 67 #define SDE (1 << 3) /* slave data empty */ 68 #define SDT (1 << 2) /* slave data transmitted */ 69 #define SDR (1 << 1) /* slave data received */ 70 #define SAR (1 << 0) /* slave addr received */ 71 72 /* ICMSR (also for ICMIE) */ 73 #define MNR (1 << 6) /* nack received */ 74 #define MAL (1 << 5) /* arbitration lost */ 75 #define MST (1 << 4) /* sent a stop */ 76 #define MDE (1 << 3) 77 #define MDT (1 << 2) 78 #define MDR (1 << 1) 79 #define MAT (1 << 0) /* slave addr xfer done */ 80 81 /* ICDMAER */ 82 #define RSDMAE (1 << 3) /* DMA Slave Received Enable */ 83 #define TSDMAE (1 << 2) /* DMA Slave Transmitted Enable */ 84 #define RMDMAE (1 << 1) /* DMA Master Received Enable */ 85 #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */ 86 87 /* ICFBSCR */ 88 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ 89 90 #define RCAR_MIN_DMA_LEN 8 91 92 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) 93 #define RCAR_BUS_PHASE_DATA (MDBS | MIE) 94 #define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF) 95 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) 96 97 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) 98 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR) 99 #define RCAR_IRQ_STOP (MST) 100 101 #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0x7F) 102 #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0x7F) 103 104 #define ID_LAST_MSG (1 << 0) 105 #define ID_FIRST_MSG (1 << 1) 106 #define ID_DONE (1 << 2) 107 #define ID_ARBLOST (1 << 3) 108 #define ID_NACK (1 << 4) 109 /* persistent flags */ 110 #define ID_P_HOST_NOTIFY BIT(28) 111 #define ID_P_REP_AFTER_RD BIT(29) 112 #define ID_P_NO_RXDMA BIT(30) /* HW forbids RXDMA sometimes */ 113 #define ID_P_PM_BLOCKED BIT(31) 114 #define ID_P_MASK GENMASK(31, 28) 115 116 enum rcar_i2c_type { 117 I2C_RCAR_GEN1, 118 I2C_RCAR_GEN2, 119 I2C_RCAR_GEN3, 120 }; 121 122 struct rcar_i2c_priv { 123 void __iomem *io; 124 struct i2c_adapter adap; 125 struct i2c_msg *msg; 126 int msgs_left; 127 struct clk *clk; 128 129 wait_queue_head_t wait; 130 131 int pos; 132 u32 icccr; 133 u32 flags; 134 u8 recovery_icmcr; /* protected by adapter lock */ 135 enum rcar_i2c_type devtype; 136 struct i2c_client *slave; 137 138 struct resource *res; 139 struct dma_chan *dma_tx; 140 struct dma_chan *dma_rx; 141 struct scatterlist sg; 142 enum dma_data_direction dma_direction; 143 144 struct reset_control *rstc; 145 int irq; 146 147 struct i2c_client *host_notify_client; 148 }; 149 150 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) 151 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) 152 153 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) 154 { 155 writel(val, priv->io + reg); 156 } 157 158 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) 159 { 160 return readl(priv->io + reg); 161 } 162 163 static int rcar_i2c_get_scl(struct i2c_adapter *adap) 164 { 165 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 166 167 return !!(rcar_i2c_read(priv, ICMCR) & FSCL); 168 169 }; 170 171 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val) 172 { 173 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 174 175 if (val) 176 priv->recovery_icmcr |= FSCL; 177 else 178 priv->recovery_icmcr &= ~FSCL; 179 180 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 181 }; 182 183 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val) 184 { 185 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 186 187 if (val) 188 priv->recovery_icmcr |= FSDA; 189 else 190 priv->recovery_icmcr &= ~FSDA; 191 192 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr); 193 }; 194 195 static int rcar_i2c_get_bus_free(struct i2c_adapter *adap) 196 { 197 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 198 199 return !(rcar_i2c_read(priv, ICMCR) & FSDA); 200 201 }; 202 203 static struct i2c_bus_recovery_info rcar_i2c_bri = { 204 .get_scl = rcar_i2c_get_scl, 205 .set_scl = rcar_i2c_set_scl, 206 .set_sda = rcar_i2c_set_sda, 207 .get_bus_free = rcar_i2c_get_bus_free, 208 .recover_bus = i2c_generic_scl_recovery, 209 }; 210 static void rcar_i2c_init(struct rcar_i2c_priv *priv) 211 { 212 /* reset master mode */ 213 rcar_i2c_write(priv, ICMIER, 0); 214 rcar_i2c_write(priv, ICMCR, MDBS); 215 rcar_i2c_write(priv, ICMSR, 0); 216 /* start clock */ 217 rcar_i2c_write(priv, ICCCR, priv->icccr); 218 219 if (priv->devtype == I2C_RCAR_GEN3) 220 rcar_i2c_write(priv, ICFBSCR, TCYC17); 221 222 } 223 224 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) 225 { 226 int ret; 227 u32 val; 228 229 ret = readl_poll_timeout(priv->io + ICMCR, val, !(val & FSDA), 10, 230 priv->adap.timeout); 231 if (ret) { 232 /* Waiting did not help, try to recover */ 233 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL; 234 ret = i2c_recover_bus(&priv->adap); 235 } 236 237 return ret; 238 } 239 240 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv) 241 { 242 u32 scgd, cdf, round, ick, sum, scl, cdf_width; 243 unsigned long rate; 244 struct device *dev = rcar_i2c_priv_to_dev(priv); 245 struct i2c_timings t = { 246 .bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ, 247 .scl_fall_ns = 35, 248 .scl_rise_ns = 200, 249 .scl_int_delay_ns = 50, 250 }; 251 252 /* Fall back to previously used values if not supplied */ 253 i2c_parse_fw_timings(dev, &t, false); 254 255 switch (priv->devtype) { 256 case I2C_RCAR_GEN1: 257 cdf_width = 2; 258 break; 259 case I2C_RCAR_GEN2: 260 case I2C_RCAR_GEN3: 261 cdf_width = 3; 262 break; 263 default: 264 dev_err(dev, "device type error\n"); 265 return -EIO; 266 } 267 268 /* 269 * calculate SCL clock 270 * see 271 * ICCCR 272 * 273 * ick = clkp / (1 + CDF) 274 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 275 * 276 * ick : I2C internal clock < 20 MHz 277 * ticf : I2C SCL falling time 278 * tr : I2C SCL rising time 279 * intd : LSI internal delay 280 * clkp : peripheral_clk 281 * F[] : integer up-valuation 282 */ 283 rate = clk_get_rate(priv->clk); 284 cdf = rate / 20000000; 285 if (cdf >= 1U << cdf_width) { 286 dev_err(dev, "Input clock %lu too high\n", rate); 287 return -EIO; 288 } 289 ick = rate / (cdf + 1); 290 291 /* 292 * it is impossible to calculate large scale 293 * number on u32. separate it 294 * 295 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd) 296 * = F[sum * ick / 1000000000] 297 * = F[(ick / 1000000) * sum / 1000] 298 */ 299 sum = t.scl_fall_ns + t.scl_rise_ns + t.scl_int_delay_ns; 300 round = (ick + 500000) / 1000000 * sum; 301 round = (round + 500) / 1000; 302 303 /* 304 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) 305 * 306 * Calculation result (= SCL) should be less than 307 * bus_speed for hardware safety 308 * 309 * We could use something along the lines of 310 * div = ick / (bus_speed + 1) + 1; 311 * scgd = (div - 20 - round + 7) / 8; 312 * scl = ick / (20 + (scgd * 8) + round); 313 * (not fully verified) but that would get pretty involved 314 */ 315 for (scgd = 0; scgd < 0x40; scgd++) { 316 scl = ick / (20 + (scgd * 8) + round); 317 if (scl <= t.bus_freq_hz) 318 goto scgd_find; 319 } 320 dev_err(dev, "it is impossible to calculate best SCL\n"); 321 return -EIO; 322 323 scgd_find: 324 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", 325 scl, t.bus_freq_hz, rate, round, cdf, scgd); 326 327 /* keep icccr value */ 328 priv->icccr = scgd << cdf_width | cdf; 329 330 return 0; 331 } 332 333 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) 334 { 335 int read = !!rcar_i2c_is_recv(priv); 336 337 priv->pos = 0; 338 if (priv->msgs_left == 1) 339 priv->flags |= ID_LAST_MSG; 340 341 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg)); 342 /* 343 * We don't have a test case but the HW engineers say that the write order 344 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since 345 * it didn't cause a drawback for me, let's rather be safe than sorry. 346 */ 347 if (priv->flags & ID_FIRST_MSG) { 348 rcar_i2c_write(priv, ICMSR, 0); 349 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 350 } else { 351 if (priv->flags & ID_P_REP_AFTER_RD) 352 priv->flags &= ~ID_P_REP_AFTER_RD; 353 else 354 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 355 rcar_i2c_write(priv, ICMSR, 0); 356 } 357 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); 358 } 359 360 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) 361 { 362 priv->msg++; 363 priv->msgs_left--; 364 priv->flags &= ID_P_MASK; 365 rcar_i2c_prepare_msg(priv); 366 } 367 368 static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv) 369 { 370 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE 371 ? priv->dma_rx : priv->dma_tx; 372 373 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), 374 sg_dma_len(&priv->sg), priv->dma_direction); 375 376 /* Gen3 can only do one RXDMA per transfer and we just completed it */ 377 if (priv->devtype == I2C_RCAR_GEN3 && 378 priv->dma_direction == DMA_FROM_DEVICE) 379 priv->flags |= ID_P_NO_RXDMA; 380 381 priv->dma_direction = DMA_NONE; 382 383 /* Disable DMA Master Received/Transmitted, must be last! */ 384 rcar_i2c_write(priv, ICDMAER, 0); 385 } 386 387 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv) 388 { 389 if (priv->dma_direction == DMA_NONE) 390 return; 391 else if (priv->dma_direction == DMA_FROM_DEVICE) 392 dmaengine_terminate_all(priv->dma_rx); 393 else if (priv->dma_direction == DMA_TO_DEVICE) 394 dmaengine_terminate_all(priv->dma_tx); 395 396 rcar_i2c_dma_unmap(priv); 397 } 398 399 static void rcar_i2c_dma_callback(void *data) 400 { 401 struct rcar_i2c_priv *priv = data; 402 403 priv->pos += sg_dma_len(&priv->sg); 404 405 rcar_i2c_dma_unmap(priv); 406 } 407 408 static bool rcar_i2c_dma(struct rcar_i2c_priv *priv) 409 { 410 struct device *dev = rcar_i2c_priv_to_dev(priv); 411 struct i2c_msg *msg = priv->msg; 412 bool read = msg->flags & I2C_M_RD; 413 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 414 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx; 415 struct dma_async_tx_descriptor *txdesc; 416 dma_addr_t dma_addr; 417 dma_cookie_t cookie; 418 unsigned char *buf; 419 int len; 420 421 /* Do various checks to see if DMA is feasible at all */ 422 if (IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN || 423 !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA)) 424 return false; 425 426 if (read) { 427 /* 428 * The last two bytes needs to be fetched using PIO in 429 * order for the STOP phase to work. 430 */ 431 buf = priv->msg->buf; 432 len = priv->msg->len - 2; 433 } else { 434 /* 435 * First byte in message was sent using PIO. 436 */ 437 buf = priv->msg->buf + 1; 438 len = priv->msg->len - 1; 439 } 440 441 dma_addr = dma_map_single(chan->device->dev, buf, len, dir); 442 if (dma_mapping_error(chan->device->dev, dma_addr)) { 443 dev_dbg(dev, "dma map failed, using PIO\n"); 444 return false; 445 } 446 447 sg_dma_len(&priv->sg) = len; 448 sg_dma_address(&priv->sg) = dma_addr; 449 450 priv->dma_direction = dir; 451 452 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1, 453 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 454 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 455 if (!txdesc) { 456 dev_dbg(dev, "dma prep slave sg failed, using PIO\n"); 457 rcar_i2c_cleanup_dma(priv); 458 return false; 459 } 460 461 txdesc->callback = rcar_i2c_dma_callback; 462 txdesc->callback_param = priv; 463 464 cookie = dmaengine_submit(txdesc); 465 if (dma_submit_error(cookie)) { 466 dev_dbg(dev, "submitting dma failed, using PIO\n"); 467 rcar_i2c_cleanup_dma(priv); 468 return false; 469 } 470 471 /* Enable DMA Master Received/Transmitted */ 472 if (read) 473 rcar_i2c_write(priv, ICDMAER, RMDMAE); 474 else 475 rcar_i2c_write(priv, ICDMAER, TMDMAE); 476 477 dma_async_issue_pending(chan); 478 return true; 479 } 480 481 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) 482 { 483 struct i2c_msg *msg = priv->msg; 484 485 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 486 if (!(msr & MDE)) 487 return; 488 489 /* Check if DMA can be enabled and take over */ 490 if (priv->pos == 1 && rcar_i2c_dma(priv)) 491 return; 492 493 if (priv->pos < msg->len) { 494 /* 495 * Prepare next data to ICRXTX register. 496 * This data will go to _SHIFT_ register. 497 * 498 * * 499 * [ICRXTX] -> [SHIFT] -> [I2C bus] 500 */ 501 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); 502 priv->pos++; 503 } else { 504 /* 505 * The last data was pushed to ICRXTX on _PREV_ empty irq. 506 * It is on _SHIFT_ register, and will sent to I2C bus. 507 * 508 * * 509 * [ICRXTX] -> [SHIFT] -> [I2C bus] 510 */ 511 512 if (priv->flags & ID_LAST_MSG) { 513 /* 514 * If current msg is the _LAST_ msg, 515 * prepare stop condition here. 516 * ID_DONE will be set on STOP irq. 517 */ 518 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 519 } else { 520 rcar_i2c_next_msg(priv); 521 return; 522 } 523 } 524 525 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND); 526 } 527 528 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) 529 { 530 struct i2c_msg *msg = priv->msg; 531 532 /* FIXME: sometimes, unknown interrupt happened. Do nothing */ 533 if (!(msr & MDR)) 534 return; 535 536 if (msr & MAT) { 537 /* 538 * Address transfer phase finished, but no data at this point. 539 * Try to use DMA to receive data. 540 */ 541 rcar_i2c_dma(priv); 542 } else if (priv->pos < msg->len) { 543 /* get received data */ 544 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); 545 priv->pos++; 546 } 547 548 /* If next received data is the _LAST_, go to new phase. */ 549 if (priv->pos + 1 == msg->len) { 550 if (priv->flags & ID_LAST_MSG) { 551 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 552 } else { 553 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 554 priv->flags |= ID_P_REP_AFTER_RD; 555 } 556 } 557 558 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG)) 559 rcar_i2c_next_msg(priv); 560 else 561 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV); 562 } 563 564 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) 565 { 566 u32 ssr_raw, ssr_filtered; 567 u8 value; 568 569 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff; 570 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER); 571 572 if (!ssr_filtered) 573 return false; 574 575 /* address detected */ 576 if (ssr_filtered & SAR) { 577 /* read or write request */ 578 if (ssr_raw & STM) { 579 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value); 580 rcar_i2c_write(priv, ICRXTX, value); 581 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); 582 } else { 583 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value); 584 rcar_i2c_read(priv, ICRXTX); /* dummy read */ 585 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); 586 } 587 588 /* Clear SSR, too, because of old STOPs to other clients than us */ 589 rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff); 590 } 591 592 /* master sent stop */ 593 if (ssr_filtered & SSR) { 594 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value); 595 rcar_i2c_write(priv, ICSCR, SIE | SDBS); /* clear our NACK */ 596 rcar_i2c_write(priv, ICSIER, SAR); 597 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff); 598 } 599 600 /* master wants to write to us */ 601 if (ssr_filtered & SDR) { 602 int ret; 603 604 value = rcar_i2c_read(priv, ICRXTX); 605 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value); 606 /* Send NACK in case of error */ 607 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0)); 608 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff); 609 } 610 611 /* master wants to read from us */ 612 if (ssr_filtered & SDE) { 613 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value); 614 rcar_i2c_write(priv, ICRXTX, value); 615 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff); 616 } 617 618 return true; 619 } 620 621 /* 622 * This driver has a lock-free design because there are IP cores (at least 623 * R-Car Gen2) which have an inherent race condition in their hardware design. 624 * There, we need to clear RCAR_BUS_MASK_DATA bits as soon as possible after 625 * the interrupt was generated, otherwise an unwanted repeated message gets 626 * generated. It turned out that taking a spinlock at the beginning of the ISR 627 * was already causing repeated messages. Thus, this driver was converted to 628 * the now lockless behaviour. Please keep this in mind when hacking the driver. 629 */ 630 static irqreturn_t rcar_i2c_irq(int irq, void *ptr) 631 { 632 struct rcar_i2c_priv *priv = ptr; 633 u32 msr, val; 634 635 /* Clear START or STOP immediately, except for REPSTART after read */ 636 if (likely(!(priv->flags & ID_P_REP_AFTER_RD))) { 637 val = rcar_i2c_read(priv, ICMCR); 638 rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA); 639 } 640 641 msr = rcar_i2c_read(priv, ICMSR); 642 643 /* Only handle interrupts that are currently enabled */ 644 msr &= rcar_i2c_read(priv, ICMIER); 645 if (!msr) { 646 if (rcar_i2c_slave_irq(priv)) 647 return IRQ_HANDLED; 648 649 return IRQ_NONE; 650 } 651 652 /* Arbitration lost */ 653 if (msr & MAL) { 654 priv->flags |= ID_DONE | ID_ARBLOST; 655 goto out; 656 } 657 658 /* Nack */ 659 if (msr & MNR) { 660 /* HW automatically sends STOP after received NACK */ 661 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP); 662 priv->flags |= ID_NACK; 663 goto out; 664 } 665 666 /* Stop */ 667 if (msr & MST) { 668 priv->msgs_left--; /* The last message also made it */ 669 priv->flags |= ID_DONE; 670 goto out; 671 } 672 673 if (rcar_i2c_is_recv(priv)) 674 rcar_i2c_irq_recv(priv, msr); 675 else 676 rcar_i2c_irq_send(priv, msr); 677 678 out: 679 if (priv->flags & ID_DONE) { 680 rcar_i2c_write(priv, ICMIER, 0); 681 rcar_i2c_write(priv, ICMSR, 0); 682 wake_up(&priv->wait); 683 } 684 685 return IRQ_HANDLED; 686 } 687 688 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev, 689 enum dma_transfer_direction dir, 690 dma_addr_t port_addr) 691 { 692 struct dma_chan *chan; 693 struct dma_slave_config cfg; 694 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; 695 int ret; 696 697 chan = dma_request_chan(dev, chan_name); 698 if (IS_ERR(chan)) { 699 dev_dbg(dev, "request_channel failed for %s (%ld)\n", 700 chan_name, PTR_ERR(chan)); 701 return chan; 702 } 703 704 memset(&cfg, 0, sizeof(cfg)); 705 cfg.direction = dir; 706 if (dir == DMA_MEM_TO_DEV) { 707 cfg.dst_addr = port_addr; 708 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 709 } else { 710 cfg.src_addr = port_addr; 711 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 712 } 713 714 ret = dmaengine_slave_config(chan, &cfg); 715 if (ret) { 716 dev_dbg(dev, "slave_config failed for %s (%d)\n", 717 chan_name, ret); 718 dma_release_channel(chan); 719 return ERR_PTR(ret); 720 } 721 722 dev_dbg(dev, "got DMA channel for %s\n", chan_name); 723 return chan; 724 } 725 726 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv, 727 struct i2c_msg *msg) 728 { 729 struct device *dev = rcar_i2c_priv_to_dev(priv); 730 bool read; 731 struct dma_chan *chan; 732 enum dma_transfer_direction dir; 733 734 read = msg->flags & I2C_M_RD; 735 736 chan = read ? priv->dma_rx : priv->dma_tx; 737 if (PTR_ERR(chan) != -EPROBE_DEFER) 738 return; 739 740 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 741 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX); 742 743 if (read) 744 priv->dma_rx = chan; 745 else 746 priv->dma_tx = chan; 747 } 748 749 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv) 750 { 751 if (!IS_ERR(priv->dma_tx)) { 752 dma_release_channel(priv->dma_tx); 753 priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 754 } 755 756 if (!IS_ERR(priv->dma_rx)) { 757 dma_release_channel(priv->dma_rx); 758 priv->dma_rx = ERR_PTR(-EPROBE_DEFER); 759 } 760 } 761 762 /* I2C is a special case, we need to poll the status of a reset */ 763 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv) 764 { 765 int ret; 766 767 ret = reset_control_reset(priv->rstc); 768 if (ret) 769 return ret; 770 771 return read_poll_timeout_atomic(reset_control_status, ret, ret == 0, 1, 772 100, false, priv->rstc); 773 } 774 775 static int rcar_i2c_master_xfer(struct i2c_adapter *adap, 776 struct i2c_msg *msgs, 777 int num) 778 { 779 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 780 struct device *dev = rcar_i2c_priv_to_dev(priv); 781 int i, ret; 782 long time_left; 783 784 pm_runtime_get_sync(dev); 785 786 /* Check bus state before init otherwise bus busy info will be lost */ 787 ret = rcar_i2c_bus_barrier(priv); 788 if (ret < 0) 789 goto out; 790 791 /* Gen3 needs a reset before allowing RXDMA once */ 792 if (priv->devtype == I2C_RCAR_GEN3) { 793 priv->flags |= ID_P_NO_RXDMA; 794 if (!IS_ERR(priv->rstc)) { 795 ret = rcar_i2c_do_reset(priv); 796 if (ret == 0) 797 priv->flags &= ~ID_P_NO_RXDMA; 798 } 799 } 800 801 rcar_i2c_init(priv); 802 803 for (i = 0; i < num; i++) 804 rcar_i2c_request_dma(priv, msgs + i); 805 806 /* init first message */ 807 priv->msg = msgs; 808 priv->msgs_left = num; 809 priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG; 810 rcar_i2c_prepare_msg(priv); 811 812 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE, 813 num * adap->timeout); 814 815 /* cleanup DMA if it couldn't complete properly due to an error */ 816 if (priv->dma_direction != DMA_NONE) 817 rcar_i2c_cleanup_dma(priv); 818 819 if (!time_left) { 820 rcar_i2c_init(priv); 821 ret = -ETIMEDOUT; 822 } else if (priv->flags & ID_NACK) { 823 ret = -ENXIO; 824 } else if (priv->flags & ID_ARBLOST) { 825 ret = -EAGAIN; 826 } else { 827 ret = num - priv->msgs_left; /* The number of transfer */ 828 } 829 out: 830 pm_runtime_put(dev); 831 832 if (ret < 0 && ret != -ENXIO) 833 dev_err(dev, "error %d : %x\n", ret, priv->flags); 834 835 return ret; 836 } 837 838 static int rcar_reg_slave(struct i2c_client *slave) 839 { 840 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 841 842 if (priv->slave) 843 return -EBUSY; 844 845 if (slave->flags & I2C_CLIENT_TEN) 846 return -EAFNOSUPPORT; 847 848 /* Keep device active for slave address detection logic */ 849 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv)); 850 851 priv->slave = slave; 852 rcar_i2c_write(priv, ICSAR, slave->addr); 853 rcar_i2c_write(priv, ICSSR, 0); 854 rcar_i2c_write(priv, ICSIER, SAR); 855 rcar_i2c_write(priv, ICSCR, SIE | SDBS); 856 857 return 0; 858 } 859 860 static int rcar_unreg_slave(struct i2c_client *slave) 861 { 862 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 863 864 WARN_ON(!priv->slave); 865 866 /* ensure no irq is running before clearing ptr */ 867 disable_irq(priv->irq); 868 rcar_i2c_write(priv, ICSIER, 0); 869 rcar_i2c_write(priv, ICSSR, 0); 870 enable_irq(priv->irq); 871 rcar_i2c_write(priv, ICSCR, SDBS); 872 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */ 873 874 priv->slave = NULL; 875 876 pm_runtime_put(rcar_i2c_priv_to_dev(priv)); 877 878 return 0; 879 } 880 881 static u32 rcar_i2c_func(struct i2c_adapter *adap) 882 { 883 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 884 885 /* 886 * This HW can't do: 887 * I2C_SMBUS_QUICK (setting FSB during START didn't work) 888 * I2C_M_NOSTART (automatically sends address after START) 889 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK) 890 */ 891 u32 func = I2C_FUNC_I2C | I2C_FUNC_SLAVE | 892 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 893 894 if (priv->flags & ID_P_HOST_NOTIFY) 895 func |= I2C_FUNC_SMBUS_HOST_NOTIFY; 896 897 return func; 898 } 899 900 static const struct i2c_algorithm rcar_i2c_algo = { 901 .master_xfer = rcar_i2c_master_xfer, 902 .functionality = rcar_i2c_func, 903 .reg_slave = rcar_reg_slave, 904 .unreg_slave = rcar_unreg_slave, 905 }; 906 907 static const struct i2c_adapter_quirks rcar_i2c_quirks = { 908 .flags = I2C_AQ_NO_ZERO_LEN, 909 }; 910 911 static const struct of_device_id rcar_i2c_dt_ids[] = { 912 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 }, 913 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 }, 914 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 }, 915 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 }, 916 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 }, 917 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 }, 918 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 }, 919 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 }, 920 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 }, 921 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, /* Deprecated */ 922 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 }, 923 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 }, 924 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 }, 925 {}, 926 }; 927 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids); 928 929 static int rcar_i2c_probe(struct platform_device *pdev) 930 { 931 struct rcar_i2c_priv *priv; 932 struct i2c_adapter *adap; 933 struct device *dev = &pdev->dev; 934 int ret; 935 936 /* Otherwise logic will break because some bytes must always use PIO */ 937 BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length"); 938 939 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); 940 if (!priv) 941 return -ENOMEM; 942 943 priv->clk = devm_clk_get(dev, NULL); 944 if (IS_ERR(priv->clk)) { 945 dev_err(dev, "cannot get clock\n"); 946 return PTR_ERR(priv->clk); 947 } 948 949 priv->io = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->res); 950 if (IS_ERR(priv->io)) 951 return PTR_ERR(priv->io); 952 953 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev); 954 init_waitqueue_head(&priv->wait); 955 956 adap = &priv->adap; 957 adap->nr = pdev->id; 958 adap->algo = &rcar_i2c_algo; 959 adap->class = I2C_CLASS_DEPRECATED; 960 adap->retries = 3; 961 adap->dev.parent = dev; 962 adap->dev.of_node = dev->of_node; 963 adap->bus_recovery_info = &rcar_i2c_bri; 964 adap->quirks = &rcar_i2c_quirks; 965 i2c_set_adapdata(adap, priv); 966 strlcpy(adap->name, pdev->name, sizeof(adap->name)); 967 968 /* Init DMA */ 969 sg_init_table(&priv->sg, 1); 970 priv->dma_direction = DMA_NONE; 971 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER); 972 973 /* Activate device for clock calculation */ 974 pm_runtime_enable(dev); 975 pm_runtime_get_sync(dev); 976 ret = rcar_i2c_clock_calculate(priv); 977 if (ret < 0) 978 goto out_pm_put; 979 980 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */ 981 982 if (priv->devtype == I2C_RCAR_GEN3) { 983 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 984 if (!IS_ERR(priv->rstc)) { 985 ret = reset_control_status(priv->rstc); 986 if (ret < 0) 987 priv->rstc = ERR_PTR(-ENOTSUPP); 988 } 989 } 990 991 /* Stay always active when multi-master to keep arbitration working */ 992 if (of_property_read_bool(dev->of_node, "multi-master")) 993 priv->flags |= ID_P_PM_BLOCKED; 994 else 995 pm_runtime_put(dev); 996 997 if (of_property_read_bool(dev->of_node, "smbus")) 998 priv->flags |= ID_P_HOST_NOTIFY; 999 1000 priv->irq = platform_get_irq(pdev, 0); 1001 ret = devm_request_irq(dev, priv->irq, rcar_i2c_irq, 0, dev_name(dev), priv); 1002 if (ret < 0) { 1003 dev_err(dev, "cannot get irq %d\n", priv->irq); 1004 goto out_pm_disable; 1005 } 1006 1007 platform_set_drvdata(pdev, priv); 1008 1009 ret = i2c_add_numbered_adapter(adap); 1010 if (ret < 0) 1011 goto out_pm_disable; 1012 1013 if (priv->flags & ID_P_HOST_NOTIFY) { 1014 priv->host_notify_client = i2c_new_slave_host_notify_device(adap); 1015 if (IS_ERR(priv->host_notify_client)) { 1016 ret = PTR_ERR(priv->host_notify_client); 1017 goto out_del_device; 1018 } 1019 } 1020 1021 dev_info(dev, "probed\n"); 1022 1023 return 0; 1024 1025 out_del_device: 1026 i2c_del_adapter(&priv->adap); 1027 out_pm_put: 1028 pm_runtime_put(dev); 1029 out_pm_disable: 1030 pm_runtime_disable(dev); 1031 return ret; 1032 } 1033 1034 static int rcar_i2c_remove(struct platform_device *pdev) 1035 { 1036 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); 1037 struct device *dev = &pdev->dev; 1038 1039 if (priv->host_notify_client) 1040 i2c_free_slave_host_notify_device(priv->host_notify_client); 1041 i2c_del_adapter(&priv->adap); 1042 rcar_i2c_release_dma(priv); 1043 if (priv->flags & ID_P_PM_BLOCKED) 1044 pm_runtime_put(dev); 1045 pm_runtime_disable(dev); 1046 1047 return 0; 1048 } 1049 1050 #ifdef CONFIG_PM_SLEEP 1051 static int rcar_i2c_suspend(struct device *dev) 1052 { 1053 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1054 1055 i2c_mark_adapter_suspended(&priv->adap); 1056 return 0; 1057 } 1058 1059 static int rcar_i2c_resume(struct device *dev) 1060 { 1061 struct rcar_i2c_priv *priv = dev_get_drvdata(dev); 1062 1063 i2c_mark_adapter_resumed(&priv->adap); 1064 return 0; 1065 } 1066 1067 static const struct dev_pm_ops rcar_i2c_pm_ops = { 1068 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume) 1069 }; 1070 1071 #define DEV_PM_OPS (&rcar_i2c_pm_ops) 1072 #else 1073 #define DEV_PM_OPS NULL 1074 #endif /* CONFIG_PM_SLEEP */ 1075 1076 static struct platform_driver rcar_i2c_driver = { 1077 .driver = { 1078 .name = "i2c-rcar", 1079 .of_match_table = rcar_i2c_dt_ids, 1080 .pm = DEV_PM_OPS, 1081 }, 1082 .probe = rcar_i2c_probe, 1083 .remove = rcar_i2c_remove, 1084 }; 1085 1086 module_platform_driver(rcar_i2c_driver); 1087 1088 MODULE_LICENSE("GPL v2"); 1089 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); 1090 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); 1091