1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2014, Sony Mobile Communications AB. 5 * 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/atomic.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/dmaengine.h> 13 #include <linux/dmapool.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/i2c.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/scatterlist.h> 24 25 /* QUP Registers */ 26 #define QUP_CONFIG 0x000 27 #define QUP_STATE 0x004 28 #define QUP_IO_MODE 0x008 29 #define QUP_SW_RESET 0x00c 30 #define QUP_OPERATIONAL 0x018 31 #define QUP_ERROR_FLAGS 0x01c 32 #define QUP_ERROR_FLAGS_EN 0x020 33 #define QUP_OPERATIONAL_MASK 0x028 34 #define QUP_HW_VERSION 0x030 35 #define QUP_MX_OUTPUT_CNT 0x100 36 #define QUP_OUT_FIFO_BASE 0x110 37 #define QUP_MX_WRITE_CNT 0x150 38 #define QUP_MX_INPUT_CNT 0x200 39 #define QUP_MX_READ_CNT 0x208 40 #define QUP_IN_FIFO_BASE 0x218 41 #define QUP_I2C_CLK_CTL 0x400 42 #define QUP_I2C_STATUS 0x404 43 #define QUP_I2C_MASTER_GEN 0x408 44 45 /* QUP States and reset values */ 46 #define QUP_RESET_STATE 0 47 #define QUP_RUN_STATE 1 48 #define QUP_PAUSE_STATE 3 49 #define QUP_STATE_MASK 3 50 51 #define QUP_STATE_VALID BIT(2) 52 #define QUP_I2C_MAST_GEN BIT(4) 53 #define QUP_I2C_FLUSH BIT(6) 54 55 #define QUP_OPERATIONAL_RESET 0x000ff0 56 #define QUP_I2C_STATUS_RESET 0xfffffc 57 58 /* QUP OPERATIONAL FLAGS */ 59 #define QUP_I2C_NACK_FLAG BIT(3) 60 #define QUP_OUT_NOT_EMPTY BIT(4) 61 #define QUP_IN_NOT_EMPTY BIT(5) 62 #define QUP_OUT_FULL BIT(6) 63 #define QUP_OUT_SVC_FLAG BIT(8) 64 #define QUP_IN_SVC_FLAG BIT(9) 65 #define QUP_MX_OUTPUT_DONE BIT(10) 66 #define QUP_MX_INPUT_DONE BIT(11) 67 #define OUT_BLOCK_WRITE_REQ BIT(12) 68 #define IN_BLOCK_READ_REQ BIT(13) 69 70 /* I2C mini core related values */ 71 #define QUP_NO_INPUT BIT(7) 72 #define QUP_CLOCK_AUTO_GATE BIT(13) 73 #define I2C_MINI_CORE (2 << 8) 74 #define I2C_N_VAL 15 75 #define I2C_N_VAL_V2 7 76 77 /* Most significant word offset in FIFO port */ 78 #define QUP_MSW_SHIFT (I2C_N_VAL + 1) 79 80 /* Packing/Unpacking words in FIFOs, and IO modes */ 81 #define QUP_OUTPUT_BLK_MODE (1 << 10) 82 #define QUP_OUTPUT_BAM_MODE (3 << 10) 83 #define QUP_INPUT_BLK_MODE (1 << 12) 84 #define QUP_INPUT_BAM_MODE (3 << 12) 85 #define QUP_BAM_MODE (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE) 86 #define QUP_UNPACK_EN BIT(14) 87 #define QUP_PACK_EN BIT(15) 88 89 #define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN) 90 #define QUP_V2_TAGS_EN 1 91 92 #define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03) 93 #define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07) 94 #define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03) 95 #define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07) 96 97 /* QUP tags */ 98 #define QUP_TAG_START (1 << 8) 99 #define QUP_TAG_DATA (2 << 8) 100 #define QUP_TAG_STOP (3 << 8) 101 #define QUP_TAG_REC (4 << 8) 102 #define QUP_BAM_INPUT_EOT 0x93 103 #define QUP_BAM_FLUSH_STOP 0x96 104 105 /* QUP v2 tags */ 106 #define QUP_TAG_V2_START 0x81 107 #define QUP_TAG_V2_DATAWR 0x82 108 #define QUP_TAG_V2_DATAWR_STOP 0x83 109 #define QUP_TAG_V2_DATARD 0x85 110 #define QUP_TAG_V2_DATARD_NACK 0x86 111 #define QUP_TAG_V2_DATARD_STOP 0x87 112 113 /* Status, Error flags */ 114 #define I2C_STATUS_WR_BUFFER_FULL BIT(0) 115 #define I2C_STATUS_BUS_ACTIVE BIT(8) 116 #define I2C_STATUS_ERROR_MASK 0x38000fc 117 #define QUP_STATUS_ERROR_FLAGS 0x7c 118 119 #define QUP_READ_LIMIT 256 120 #define SET_BIT 0x1 121 #define RESET_BIT 0x0 122 #define ONE_BYTE 0x1 123 #define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31) 124 125 /* Maximum transfer length for single DMA descriptor */ 126 #define MX_TX_RX_LEN SZ_64K 127 #define MX_BLOCKS (MX_TX_RX_LEN / QUP_READ_LIMIT) 128 /* Maximum transfer length for all DMA descriptors */ 129 #define MX_DMA_TX_RX_LEN (2 * MX_TX_RX_LEN) 130 #define MX_DMA_BLOCKS (MX_DMA_TX_RX_LEN / QUP_READ_LIMIT) 131 132 /* 133 * Minimum transfer timeout for i2c transfers in seconds. It will be added on 134 * the top of maximum transfer time calculated from i2c bus speed to compensate 135 * the overheads. 136 */ 137 #define TOUT_MIN 2 138 139 /* I2C Frequency Modes */ 140 #define I2C_STANDARD_FREQ 100000 141 #define I2C_FAST_MODE_FREQ 400000 142 #define I2C_FAST_MODE_PLUS_FREQ 1000000 143 144 /* Default values. Use these if FW query fails */ 145 #define DEFAULT_CLK_FREQ I2C_STANDARD_FREQ 146 #define DEFAULT_SRC_CLK 20000000 147 148 /* 149 * Max tags length (start, stop and maximum 2 bytes address) for each QUP 150 * data transfer 151 */ 152 #define QUP_MAX_TAGS_LEN 4 153 /* Max data length for each DATARD tags */ 154 #define RECV_MAX_DATA_LEN 254 155 /* TAG length for DATA READ in RX FIFO */ 156 #define READ_RX_TAGS_LEN 2 157 158 static unsigned int scl_freq; 159 module_param_named(scl_freq, scl_freq, uint, 0444); 160 MODULE_PARM_DESC(scl_freq, "SCL frequency override"); 161 162 /* 163 * count: no of blocks 164 * pos: current block number 165 * tx_tag_len: tx tag length for current block 166 * rx_tag_len: rx tag length for current block 167 * data_len: remaining data length for current message 168 * cur_blk_len: data length for current block 169 * total_tx_len: total tx length including tag bytes for current QUP transfer 170 * total_rx_len: total rx length including tag bytes for current QUP transfer 171 * tx_fifo_data_pos: current byte number in TX FIFO word 172 * tx_fifo_free: number of free bytes in current QUP block write. 173 * rx_fifo_data_pos: current byte number in RX FIFO word 174 * fifo_available: number of available bytes in RX FIFO for current 175 * QUP block read 176 * tx_fifo_data: QUP TX FIFO write works on word basis (4 bytes). New byte write 177 * to TX FIFO will be appended in this data and will be written to 178 * TX FIFO when all the 4 bytes are available. 179 * rx_fifo_data: QUP RX FIFO read works on word basis (4 bytes). This will 180 * contains the 4 bytes of RX data. 181 * cur_data: pointer to tell cur data position for current message 182 * cur_tx_tags: pointer to tell cur position in tags 183 * tx_tags_sent: all tx tag bytes have been written in FIFO word 184 * send_last_word: for tx FIFO, last word send is pending in current block 185 * rx_bytes_read: if all the bytes have been read from rx FIFO. 186 * rx_tags_fetched: all the rx tag bytes have been fetched from rx fifo word 187 * is_tx_blk_mode: whether tx uses block or FIFO mode in case of non BAM xfer. 188 * is_rx_blk_mode: whether rx uses block or FIFO mode in case of non BAM xfer. 189 * tags: contains tx tag bytes for current QUP transfer 190 */ 191 struct qup_i2c_block { 192 int count; 193 int pos; 194 int tx_tag_len; 195 int rx_tag_len; 196 int data_len; 197 int cur_blk_len; 198 int total_tx_len; 199 int total_rx_len; 200 int tx_fifo_data_pos; 201 int tx_fifo_free; 202 int rx_fifo_data_pos; 203 int fifo_available; 204 u32 tx_fifo_data; 205 u32 rx_fifo_data; 206 u8 *cur_data; 207 u8 *cur_tx_tags; 208 bool tx_tags_sent; 209 bool send_last_word; 210 bool rx_tags_fetched; 211 bool rx_bytes_read; 212 bool is_tx_blk_mode; 213 bool is_rx_blk_mode; 214 u8 tags[6]; 215 }; 216 217 struct qup_i2c_tag { 218 u8 *start; 219 dma_addr_t addr; 220 }; 221 222 struct qup_i2c_bam { 223 struct qup_i2c_tag tag; 224 struct dma_chan *dma; 225 struct scatterlist *sg; 226 unsigned int sg_cnt; 227 }; 228 229 struct qup_i2c_dev { 230 struct device *dev; 231 void __iomem *base; 232 int irq; 233 struct clk *clk; 234 struct clk *pclk; 235 struct i2c_adapter adap; 236 237 int clk_ctl; 238 int out_fifo_sz; 239 int in_fifo_sz; 240 int out_blk_sz; 241 int in_blk_sz; 242 243 int blk_xfer_limit; 244 unsigned long one_byte_t; 245 unsigned long xfer_timeout; 246 struct qup_i2c_block blk; 247 248 struct i2c_msg *msg; 249 /* Current posion in user message buffer */ 250 int pos; 251 /* I2C protocol errors */ 252 u32 bus_err; 253 /* QUP core errors */ 254 u32 qup_err; 255 256 /* To check if this is the last msg */ 257 bool is_last; 258 bool is_smbus_read; 259 260 /* To configure when bus is in run state */ 261 u32 config_run; 262 263 /* dma parameters */ 264 bool is_dma; 265 /* To check if the current transfer is using DMA */ 266 bool use_dma; 267 unsigned int max_xfer_sg_len; 268 unsigned int tag_buf_pos; 269 /* The threshold length above which block mode will be used */ 270 unsigned int blk_mode_threshold; 271 struct dma_pool *dpool; 272 struct qup_i2c_tag start_tag; 273 struct qup_i2c_bam brx; 274 struct qup_i2c_bam btx; 275 276 struct completion xfer; 277 /* function to write data in tx fifo */ 278 void (*write_tx_fifo)(struct qup_i2c_dev *qup); 279 /* function to read data from rx fifo */ 280 void (*read_rx_fifo)(struct qup_i2c_dev *qup); 281 /* function to write tags in tx fifo for i2c read transfer */ 282 void (*write_rx_tags)(struct qup_i2c_dev *qup); 283 }; 284 285 static irqreturn_t qup_i2c_interrupt(int irq, void *dev) 286 { 287 struct qup_i2c_dev *qup = dev; 288 struct qup_i2c_block *blk = &qup->blk; 289 u32 bus_err; 290 u32 qup_err; 291 u32 opflags; 292 293 bus_err = readl(qup->base + QUP_I2C_STATUS); 294 qup_err = readl(qup->base + QUP_ERROR_FLAGS); 295 opflags = readl(qup->base + QUP_OPERATIONAL); 296 297 if (!qup->msg) { 298 /* Clear Error interrupt */ 299 writel(QUP_RESET_STATE, qup->base + QUP_STATE); 300 return IRQ_HANDLED; 301 } 302 303 bus_err &= I2C_STATUS_ERROR_MASK; 304 qup_err &= QUP_STATUS_ERROR_FLAGS; 305 306 /* Clear the error bits in QUP_ERROR_FLAGS */ 307 if (qup_err) 308 writel(qup_err, qup->base + QUP_ERROR_FLAGS); 309 310 /* Clear the error bits in QUP_I2C_STATUS */ 311 if (bus_err) 312 writel(bus_err, qup->base + QUP_I2C_STATUS); 313 314 /* 315 * Check for BAM mode and returns if already error has come for current 316 * transfer. In Error case, sometimes, QUP generates more than one 317 * interrupt. 318 */ 319 if (qup->use_dma && (qup->qup_err || qup->bus_err)) 320 return IRQ_HANDLED; 321 322 /* Reset the QUP State in case of error */ 323 if (qup_err || bus_err) { 324 /* 325 * Don’t reset the QUP state in case of BAM mode. The BAM 326 * flush operation needs to be scheduled in transfer function 327 * which will clear the remaining schedule descriptors in BAM 328 * HW FIFO and generates the BAM interrupt. 329 */ 330 if (!qup->use_dma) 331 writel(QUP_RESET_STATE, qup->base + QUP_STATE); 332 goto done; 333 } 334 335 if (opflags & QUP_OUT_SVC_FLAG) { 336 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL); 337 338 if (opflags & OUT_BLOCK_WRITE_REQ) { 339 blk->tx_fifo_free += qup->out_blk_sz; 340 if (qup->msg->flags & I2C_M_RD) 341 qup->write_rx_tags(qup); 342 else 343 qup->write_tx_fifo(qup); 344 } 345 } 346 347 if (opflags & QUP_IN_SVC_FLAG) { 348 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL); 349 350 if (!blk->is_rx_blk_mode) { 351 blk->fifo_available += qup->in_fifo_sz; 352 qup->read_rx_fifo(qup); 353 } else if (opflags & IN_BLOCK_READ_REQ) { 354 blk->fifo_available += qup->in_blk_sz; 355 qup->read_rx_fifo(qup); 356 } 357 } 358 359 if (qup->msg->flags & I2C_M_RD) { 360 if (!blk->rx_bytes_read) 361 return IRQ_HANDLED; 362 } else { 363 /* 364 * Ideally, QUP_MAX_OUTPUT_DONE_FLAG should be checked 365 * for FIFO mode also. But, QUP_MAX_OUTPUT_DONE_FLAG lags 366 * behind QUP_OUTPUT_SERVICE_FLAG sometimes. The only reason 367 * of interrupt for write message in FIFO mode is 368 * QUP_MAX_OUTPUT_DONE_FLAG condition. 369 */ 370 if (blk->is_tx_blk_mode && !(opflags & QUP_MX_OUTPUT_DONE)) 371 return IRQ_HANDLED; 372 } 373 374 done: 375 qup->qup_err = qup_err; 376 qup->bus_err = bus_err; 377 complete(&qup->xfer); 378 return IRQ_HANDLED; 379 } 380 381 static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup, 382 u32 req_state, u32 req_mask) 383 { 384 int retries = 1; 385 u32 state; 386 387 /* 388 * State transition takes 3 AHB clocks cycles + 3 I2C master clock 389 * cycles. So retry once after a 1uS delay. 390 */ 391 do { 392 state = readl(qup->base + QUP_STATE); 393 394 if (state & QUP_STATE_VALID && 395 (state & req_mask) == req_state) 396 return 0; 397 398 udelay(1); 399 } while (retries--); 400 401 return -ETIMEDOUT; 402 } 403 404 static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state) 405 { 406 return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK); 407 } 408 409 static void qup_i2c_flush(struct qup_i2c_dev *qup) 410 { 411 u32 val = readl(qup->base + QUP_STATE); 412 413 val |= QUP_I2C_FLUSH; 414 writel(val, qup->base + QUP_STATE); 415 } 416 417 static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup) 418 { 419 return qup_i2c_poll_state_mask(qup, 0, 0); 420 } 421 422 static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup) 423 { 424 return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN); 425 } 426 427 static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state) 428 { 429 if (qup_i2c_poll_state_valid(qup) != 0) 430 return -EIO; 431 432 writel(state, qup->base + QUP_STATE); 433 434 if (qup_i2c_poll_state(qup, state) != 0) 435 return -EIO; 436 return 0; 437 } 438 439 /* Check if I2C bus returns to IDLE state */ 440 static int qup_i2c_bus_active(struct qup_i2c_dev *qup, int len) 441 { 442 unsigned long timeout; 443 u32 status; 444 int ret = 0; 445 446 timeout = jiffies + len * 4; 447 for (;;) { 448 status = readl(qup->base + QUP_I2C_STATUS); 449 if (!(status & I2C_STATUS_BUS_ACTIVE)) 450 break; 451 452 if (time_after(jiffies, timeout)) 453 ret = -ETIMEDOUT; 454 455 usleep_range(len, len * 2); 456 } 457 458 return ret; 459 } 460 461 static void qup_i2c_write_tx_fifo_v1(struct qup_i2c_dev *qup) 462 { 463 struct qup_i2c_block *blk = &qup->blk; 464 struct i2c_msg *msg = qup->msg; 465 u32 addr = i2c_8bit_addr_from_msg(msg); 466 u32 qup_tag; 467 int idx; 468 u32 val; 469 470 if (qup->pos == 0) { 471 val = QUP_TAG_START | addr; 472 idx = 1; 473 blk->tx_fifo_free--; 474 } else { 475 val = 0; 476 idx = 0; 477 } 478 479 while (blk->tx_fifo_free && qup->pos < msg->len) { 480 if (qup->pos == msg->len - 1) 481 qup_tag = QUP_TAG_STOP; 482 else 483 qup_tag = QUP_TAG_DATA; 484 485 if (idx & 1) 486 val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT; 487 else 488 val = qup_tag | msg->buf[qup->pos]; 489 490 /* Write out the pair and the last odd value */ 491 if (idx & 1 || qup->pos == msg->len - 1) 492 writel(val, qup->base + QUP_OUT_FIFO_BASE); 493 494 qup->pos++; 495 idx++; 496 blk->tx_fifo_free--; 497 } 498 } 499 500 static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup, 501 struct i2c_msg *msg) 502 { 503 qup->blk.pos = 0; 504 qup->blk.data_len = msg->len; 505 qup->blk.count = DIV_ROUND_UP(msg->len, qup->blk_xfer_limit); 506 } 507 508 static int qup_i2c_get_data_len(struct qup_i2c_dev *qup) 509 { 510 int data_len; 511 512 if (qup->blk.data_len > qup->blk_xfer_limit) 513 data_len = qup->blk_xfer_limit; 514 else 515 data_len = qup->blk.data_len; 516 517 return data_len; 518 } 519 520 static bool qup_i2c_check_msg_len(struct i2c_msg *msg) 521 { 522 return ((msg->flags & I2C_M_RD) && (msg->flags & I2C_M_RECV_LEN)); 523 } 524 525 static int qup_i2c_set_tags_smb(u16 addr, u8 *tags, struct qup_i2c_dev *qup, 526 struct i2c_msg *msg) 527 { 528 int len = 0; 529 530 if (qup->is_smbus_read) { 531 tags[len++] = QUP_TAG_V2_DATARD_STOP; 532 tags[len++] = qup_i2c_get_data_len(qup); 533 } else { 534 tags[len++] = QUP_TAG_V2_START; 535 tags[len++] = addr & 0xff; 536 537 if (msg->flags & I2C_M_TEN) 538 tags[len++] = addr >> 8; 539 540 tags[len++] = QUP_TAG_V2_DATARD; 541 /* Read 1 byte indicating the length of the SMBus message */ 542 tags[len++] = 1; 543 } 544 return len; 545 } 546 547 static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup, 548 struct i2c_msg *msg) 549 { 550 u16 addr = i2c_8bit_addr_from_msg(msg); 551 int len = 0; 552 int data_len; 553 554 int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last); 555 556 /* Handle tags for SMBus block read */ 557 if (qup_i2c_check_msg_len(msg)) 558 return qup_i2c_set_tags_smb(addr, tags, qup, msg); 559 560 if (qup->blk.pos == 0) { 561 tags[len++] = QUP_TAG_V2_START; 562 tags[len++] = addr & 0xff; 563 564 if (msg->flags & I2C_M_TEN) 565 tags[len++] = addr >> 8; 566 } 567 568 /* Send _STOP commands for the last block */ 569 if (last) { 570 if (msg->flags & I2C_M_RD) 571 tags[len++] = QUP_TAG_V2_DATARD_STOP; 572 else 573 tags[len++] = QUP_TAG_V2_DATAWR_STOP; 574 } else { 575 if (msg->flags & I2C_M_RD) 576 tags[len++] = qup->blk.pos == (qup->blk.count - 1) ? 577 QUP_TAG_V2_DATARD_NACK : 578 QUP_TAG_V2_DATARD; 579 else 580 tags[len++] = QUP_TAG_V2_DATAWR; 581 } 582 583 data_len = qup_i2c_get_data_len(qup); 584 585 /* 0 implies 256 bytes */ 586 if (data_len == QUP_READ_LIMIT) 587 tags[len++] = 0; 588 else 589 tags[len++] = data_len; 590 591 return len; 592 } 593 594 595 static void qup_i2c_bam_cb(void *data) 596 { 597 struct qup_i2c_dev *qup = data; 598 599 complete(&qup->xfer); 600 } 601 602 static int qup_sg_set_buf(struct scatterlist *sg, void *buf, 603 unsigned int buflen, struct qup_i2c_dev *qup, 604 int dir) 605 { 606 int ret; 607 608 sg_set_buf(sg, buf, buflen); 609 ret = dma_map_sg(qup->dev, sg, 1, dir); 610 if (!ret) 611 return -EINVAL; 612 613 return 0; 614 } 615 616 static void qup_i2c_rel_dma(struct qup_i2c_dev *qup) 617 { 618 if (qup->btx.dma) 619 dma_release_channel(qup->btx.dma); 620 if (qup->brx.dma) 621 dma_release_channel(qup->brx.dma); 622 qup->btx.dma = NULL; 623 qup->brx.dma = NULL; 624 } 625 626 static int qup_i2c_req_dma(struct qup_i2c_dev *qup) 627 { 628 int err; 629 630 if (!qup->btx.dma) { 631 qup->btx.dma = dma_request_slave_channel_reason(qup->dev, "tx"); 632 if (IS_ERR(qup->btx.dma)) { 633 err = PTR_ERR(qup->btx.dma); 634 qup->btx.dma = NULL; 635 dev_err(qup->dev, "\n tx channel not available"); 636 return err; 637 } 638 } 639 640 if (!qup->brx.dma) { 641 qup->brx.dma = dma_request_slave_channel_reason(qup->dev, "rx"); 642 if (IS_ERR(qup->brx.dma)) { 643 dev_err(qup->dev, "\n rx channel not available"); 644 err = PTR_ERR(qup->brx.dma); 645 qup->brx.dma = NULL; 646 qup_i2c_rel_dma(qup); 647 return err; 648 } 649 } 650 return 0; 651 } 652 653 static int qup_i2c_bam_make_desc(struct qup_i2c_dev *qup, struct i2c_msg *msg) 654 { 655 int ret = 0, limit = QUP_READ_LIMIT; 656 u32 len = 0, blocks, rem; 657 u32 i = 0, tlen, tx_len = 0; 658 u8 *tags; 659 660 qup->blk_xfer_limit = QUP_READ_LIMIT; 661 qup_i2c_set_blk_data(qup, msg); 662 663 blocks = qup->blk.count; 664 rem = msg->len - (blocks - 1) * limit; 665 666 if (msg->flags & I2C_M_RD) { 667 while (qup->blk.pos < blocks) { 668 tlen = (i == (blocks - 1)) ? rem : limit; 669 tags = &qup->start_tag.start[qup->tag_buf_pos + len]; 670 len += qup_i2c_set_tags(tags, qup, msg); 671 qup->blk.data_len -= tlen; 672 673 /* scratch buf to read the start and len tags */ 674 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++], 675 &qup->brx.tag.start[0], 676 2, qup, DMA_FROM_DEVICE); 677 678 if (ret) 679 return ret; 680 681 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++], 682 &msg->buf[limit * i], 683 tlen, qup, 684 DMA_FROM_DEVICE); 685 if (ret) 686 return ret; 687 688 i++; 689 qup->blk.pos = i; 690 } 691 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], 692 &qup->start_tag.start[qup->tag_buf_pos], 693 len, qup, DMA_TO_DEVICE); 694 if (ret) 695 return ret; 696 697 qup->tag_buf_pos += len; 698 } else { 699 while (qup->blk.pos < blocks) { 700 tlen = (i == (blocks - 1)) ? rem : limit; 701 tags = &qup->start_tag.start[qup->tag_buf_pos + tx_len]; 702 len = qup_i2c_set_tags(tags, qup, msg); 703 qup->blk.data_len -= tlen; 704 705 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], 706 tags, len, 707 qup, DMA_TO_DEVICE); 708 if (ret) 709 return ret; 710 711 tx_len += len; 712 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], 713 &msg->buf[limit * i], 714 tlen, qup, DMA_TO_DEVICE); 715 if (ret) 716 return ret; 717 i++; 718 qup->blk.pos = i; 719 } 720 721 qup->tag_buf_pos += tx_len; 722 } 723 724 return 0; 725 } 726 727 static int qup_i2c_bam_schedule_desc(struct qup_i2c_dev *qup) 728 { 729 struct dma_async_tx_descriptor *txd, *rxd = NULL; 730 int ret = 0; 731 dma_cookie_t cookie_rx, cookie_tx; 732 u32 len = 0; 733 u32 tx_cnt = qup->btx.sg_cnt, rx_cnt = qup->brx.sg_cnt; 734 735 /* schedule the EOT and FLUSH I2C tags */ 736 len = 1; 737 if (rx_cnt) { 738 qup->btx.tag.start[0] = QUP_BAM_INPUT_EOT; 739 len++; 740 741 /* scratch buf to read the BAM EOT FLUSH tags */ 742 ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++], 743 &qup->brx.tag.start[0], 744 1, qup, DMA_FROM_DEVICE); 745 if (ret) 746 return ret; 747 } 748 749 qup->btx.tag.start[len - 1] = QUP_BAM_FLUSH_STOP; 750 ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++], &qup->btx.tag.start[0], 751 len, qup, DMA_TO_DEVICE); 752 if (ret) 753 return ret; 754 755 txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_cnt, 756 DMA_MEM_TO_DEV, 757 DMA_PREP_INTERRUPT | DMA_PREP_FENCE); 758 if (!txd) { 759 dev_err(qup->dev, "failed to get tx desc\n"); 760 ret = -EINVAL; 761 goto desc_err; 762 } 763 764 if (!rx_cnt) { 765 txd->callback = qup_i2c_bam_cb; 766 txd->callback_param = qup; 767 } 768 769 cookie_tx = dmaengine_submit(txd); 770 if (dma_submit_error(cookie_tx)) { 771 ret = -EINVAL; 772 goto desc_err; 773 } 774 775 dma_async_issue_pending(qup->btx.dma); 776 777 if (rx_cnt) { 778 rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg, 779 rx_cnt, DMA_DEV_TO_MEM, 780 DMA_PREP_INTERRUPT); 781 if (!rxd) { 782 dev_err(qup->dev, "failed to get rx desc\n"); 783 ret = -EINVAL; 784 785 /* abort TX descriptors */ 786 dmaengine_terminate_all(qup->btx.dma); 787 goto desc_err; 788 } 789 790 rxd->callback = qup_i2c_bam_cb; 791 rxd->callback_param = qup; 792 cookie_rx = dmaengine_submit(rxd); 793 if (dma_submit_error(cookie_rx)) { 794 ret = -EINVAL; 795 goto desc_err; 796 } 797 798 dma_async_issue_pending(qup->brx.dma); 799 } 800 801 if (!wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout)) { 802 dev_err(qup->dev, "normal trans timed out\n"); 803 ret = -ETIMEDOUT; 804 } 805 806 if (ret || qup->bus_err || qup->qup_err) { 807 reinit_completion(&qup->xfer); 808 809 if (qup_i2c_change_state(qup, QUP_RUN_STATE)) { 810 dev_err(qup->dev, "change to run state timed out"); 811 goto desc_err; 812 } 813 814 qup_i2c_flush(qup); 815 816 /* wait for remaining interrupts to occur */ 817 if (!wait_for_completion_timeout(&qup->xfer, HZ)) 818 dev_err(qup->dev, "flush timed out\n"); 819 820 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO; 821 } 822 823 desc_err: 824 dma_unmap_sg(qup->dev, qup->btx.sg, tx_cnt, DMA_TO_DEVICE); 825 826 if (rx_cnt) 827 dma_unmap_sg(qup->dev, qup->brx.sg, rx_cnt, 828 DMA_FROM_DEVICE); 829 830 return ret; 831 } 832 833 static void qup_i2c_bam_clear_tag_buffers(struct qup_i2c_dev *qup) 834 { 835 qup->btx.sg_cnt = 0; 836 qup->brx.sg_cnt = 0; 837 qup->tag_buf_pos = 0; 838 } 839 840 static int qup_i2c_bam_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, 841 int num) 842 { 843 struct qup_i2c_dev *qup = i2c_get_adapdata(adap); 844 int ret = 0; 845 int idx = 0; 846 847 enable_irq(qup->irq); 848 ret = qup_i2c_req_dma(qup); 849 850 if (ret) 851 goto out; 852 853 writel(0, qup->base + QUP_MX_INPUT_CNT); 854 writel(0, qup->base + QUP_MX_OUTPUT_CNT); 855 856 /* set BAM mode */ 857 writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE); 858 859 /* mask fifo irqs */ 860 writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK); 861 862 /* set RUN STATE */ 863 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); 864 if (ret) 865 goto out; 866 867 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); 868 qup_i2c_bam_clear_tag_buffers(qup); 869 870 for (idx = 0; idx < num; idx++) { 871 qup->msg = msg + idx; 872 qup->is_last = idx == (num - 1); 873 874 ret = qup_i2c_bam_make_desc(qup, qup->msg); 875 if (ret) 876 break; 877 878 /* 879 * Make DMA descriptor and schedule the BAM transfer if its 880 * already crossed the maximum length. Since the memory for all 881 * tags buffers have been taken for 2 maximum possible 882 * transfers length so it will never cross the buffer actual 883 * length. 884 */ 885 if (qup->btx.sg_cnt > qup->max_xfer_sg_len || 886 qup->brx.sg_cnt > qup->max_xfer_sg_len || 887 qup->is_last) { 888 ret = qup_i2c_bam_schedule_desc(qup); 889 if (ret) 890 break; 891 892 qup_i2c_bam_clear_tag_buffers(qup); 893 } 894 } 895 896 out: 897 disable_irq(qup->irq); 898 899 qup->msg = NULL; 900 return ret; 901 } 902 903 static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup, 904 struct i2c_msg *msg) 905 { 906 unsigned long left; 907 int ret = 0; 908 909 left = wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout); 910 if (!left) { 911 writel(1, qup->base + QUP_SW_RESET); 912 ret = -ETIMEDOUT; 913 } 914 915 if (qup->bus_err || qup->qup_err) 916 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO; 917 918 return ret; 919 } 920 921 static void qup_i2c_read_rx_fifo_v1(struct qup_i2c_dev *qup) 922 { 923 struct qup_i2c_block *blk = &qup->blk; 924 struct i2c_msg *msg = qup->msg; 925 u32 val = 0; 926 int idx = 0; 927 928 while (blk->fifo_available && qup->pos < msg->len) { 929 if ((idx & 1) == 0) { 930 /* Reading 2 words at time */ 931 val = readl(qup->base + QUP_IN_FIFO_BASE); 932 msg->buf[qup->pos++] = val & 0xFF; 933 } else { 934 msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT; 935 } 936 idx++; 937 blk->fifo_available--; 938 } 939 940 if (qup->pos == msg->len) 941 blk->rx_bytes_read = true; 942 } 943 944 static void qup_i2c_write_rx_tags_v1(struct qup_i2c_dev *qup) 945 { 946 struct i2c_msg *msg = qup->msg; 947 u32 addr, len, val; 948 949 addr = i2c_8bit_addr_from_msg(msg); 950 951 /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */ 952 len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len; 953 954 val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr; 955 writel(val, qup->base + QUP_OUT_FIFO_BASE); 956 } 957 958 static void qup_i2c_conf_v1(struct qup_i2c_dev *qup) 959 { 960 struct qup_i2c_block *blk = &qup->blk; 961 u32 qup_config = I2C_MINI_CORE | I2C_N_VAL; 962 u32 io_mode = QUP_REPACK_EN; 963 964 blk->is_tx_blk_mode = 965 blk->total_tx_len > qup->out_fifo_sz ? true : false; 966 blk->is_rx_blk_mode = 967 blk->total_rx_len > qup->in_fifo_sz ? true : false; 968 969 if (blk->is_tx_blk_mode) { 970 io_mode |= QUP_OUTPUT_BLK_MODE; 971 writel(0, qup->base + QUP_MX_WRITE_CNT); 972 writel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT); 973 } else { 974 writel(0, qup->base + QUP_MX_OUTPUT_CNT); 975 writel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT); 976 } 977 978 if (blk->total_rx_len) { 979 if (blk->is_rx_blk_mode) { 980 io_mode |= QUP_INPUT_BLK_MODE; 981 writel(0, qup->base + QUP_MX_READ_CNT); 982 writel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT); 983 } else { 984 writel(0, qup->base + QUP_MX_INPUT_CNT); 985 writel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT); 986 } 987 } else { 988 qup_config |= QUP_NO_INPUT; 989 } 990 991 writel(qup_config, qup->base + QUP_CONFIG); 992 writel(io_mode, qup->base + QUP_IO_MODE); 993 } 994 995 static void qup_i2c_clear_blk_v1(struct qup_i2c_block *blk) 996 { 997 blk->tx_fifo_free = 0; 998 blk->fifo_available = 0; 999 blk->rx_bytes_read = false; 1000 } 1001 1002 static int qup_i2c_conf_xfer_v1(struct qup_i2c_dev *qup, bool is_rx) 1003 { 1004 struct qup_i2c_block *blk = &qup->blk; 1005 int ret; 1006 1007 qup_i2c_clear_blk_v1(blk); 1008 qup_i2c_conf_v1(qup); 1009 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); 1010 if (ret) 1011 return ret; 1012 1013 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); 1014 1015 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); 1016 if (ret) 1017 return ret; 1018 1019 reinit_completion(&qup->xfer); 1020 enable_irq(qup->irq); 1021 if (!blk->is_tx_blk_mode) { 1022 blk->tx_fifo_free = qup->out_fifo_sz; 1023 1024 if (is_rx) 1025 qup_i2c_write_rx_tags_v1(qup); 1026 else 1027 qup_i2c_write_tx_fifo_v1(qup); 1028 } 1029 1030 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); 1031 if (ret) 1032 goto err; 1033 1034 ret = qup_i2c_wait_for_complete(qup, qup->msg); 1035 if (ret) 1036 goto err; 1037 1038 ret = qup_i2c_bus_active(qup, ONE_BYTE); 1039 1040 err: 1041 disable_irq(qup->irq); 1042 return ret; 1043 } 1044 1045 static int qup_i2c_write_one(struct qup_i2c_dev *qup) 1046 { 1047 struct i2c_msg *msg = qup->msg; 1048 struct qup_i2c_block *blk = &qup->blk; 1049 1050 qup->pos = 0; 1051 blk->total_tx_len = msg->len + 1; 1052 blk->total_rx_len = 0; 1053 1054 return qup_i2c_conf_xfer_v1(qup, false); 1055 } 1056 1057 static int qup_i2c_read_one(struct qup_i2c_dev *qup) 1058 { 1059 struct qup_i2c_block *blk = &qup->blk; 1060 1061 qup->pos = 0; 1062 blk->total_tx_len = 2; 1063 blk->total_rx_len = qup->msg->len; 1064 1065 return qup_i2c_conf_xfer_v1(qup, true); 1066 } 1067 1068 static int qup_i2c_xfer(struct i2c_adapter *adap, 1069 struct i2c_msg msgs[], 1070 int num) 1071 { 1072 struct qup_i2c_dev *qup = i2c_get_adapdata(adap); 1073 int ret, idx; 1074 1075 ret = pm_runtime_get_sync(qup->dev); 1076 if (ret < 0) 1077 goto out; 1078 1079 qup->bus_err = 0; 1080 qup->qup_err = 0; 1081 1082 writel(1, qup->base + QUP_SW_RESET); 1083 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE); 1084 if (ret) 1085 goto out; 1086 1087 /* Configure QUP as I2C mini core */ 1088 writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG); 1089 1090 for (idx = 0; idx < num; idx++) { 1091 if (msgs[idx].len == 0) { 1092 ret = -EINVAL; 1093 goto out; 1094 } 1095 1096 if (qup_i2c_poll_state_i2c_master(qup)) { 1097 ret = -EIO; 1098 goto out; 1099 } 1100 1101 if (qup_i2c_check_msg_len(&msgs[idx])) { 1102 ret = -EINVAL; 1103 goto out; 1104 } 1105 1106 qup->msg = &msgs[idx]; 1107 if (msgs[idx].flags & I2C_M_RD) 1108 ret = qup_i2c_read_one(qup); 1109 else 1110 ret = qup_i2c_write_one(qup); 1111 1112 if (ret) 1113 break; 1114 1115 ret = qup_i2c_change_state(qup, QUP_RESET_STATE); 1116 if (ret) 1117 break; 1118 } 1119 1120 if (ret == 0) 1121 ret = num; 1122 out: 1123 1124 pm_runtime_mark_last_busy(qup->dev); 1125 pm_runtime_put_autosuspend(qup->dev); 1126 1127 return ret; 1128 } 1129 1130 /* 1131 * Configure registers related with reconfiguration during run and call it 1132 * before each i2c sub transfer. 1133 */ 1134 static void qup_i2c_conf_count_v2(struct qup_i2c_dev *qup) 1135 { 1136 struct qup_i2c_block *blk = &qup->blk; 1137 u32 qup_config = I2C_MINI_CORE | I2C_N_VAL_V2; 1138 1139 if (blk->is_tx_blk_mode) 1140 writel(qup->config_run | blk->total_tx_len, 1141 qup->base + QUP_MX_OUTPUT_CNT); 1142 else 1143 writel(qup->config_run | blk->total_tx_len, 1144 qup->base + QUP_MX_WRITE_CNT); 1145 1146 if (blk->total_rx_len) { 1147 if (blk->is_rx_blk_mode) 1148 writel(qup->config_run | blk->total_rx_len, 1149 qup->base + QUP_MX_INPUT_CNT); 1150 else 1151 writel(qup->config_run | blk->total_rx_len, 1152 qup->base + QUP_MX_READ_CNT); 1153 } else { 1154 qup_config |= QUP_NO_INPUT; 1155 } 1156 1157 writel(qup_config, qup->base + QUP_CONFIG); 1158 } 1159 1160 /* 1161 * Configure registers related with transfer mode (FIFO/Block) 1162 * before starting of i2c transfer. It will be called only once in 1163 * QUP RESET state. 1164 */ 1165 static void qup_i2c_conf_mode_v2(struct qup_i2c_dev *qup) 1166 { 1167 struct qup_i2c_block *blk = &qup->blk; 1168 u32 io_mode = QUP_REPACK_EN; 1169 1170 if (blk->is_tx_blk_mode) { 1171 io_mode |= QUP_OUTPUT_BLK_MODE; 1172 writel(0, qup->base + QUP_MX_WRITE_CNT); 1173 } else { 1174 writel(0, qup->base + QUP_MX_OUTPUT_CNT); 1175 } 1176 1177 if (blk->is_rx_blk_mode) { 1178 io_mode |= QUP_INPUT_BLK_MODE; 1179 writel(0, qup->base + QUP_MX_READ_CNT); 1180 } else { 1181 writel(0, qup->base + QUP_MX_INPUT_CNT); 1182 } 1183 1184 writel(io_mode, qup->base + QUP_IO_MODE); 1185 } 1186 1187 /* Clear required variables before starting of any QUP v2 sub transfer. */ 1188 static void qup_i2c_clear_blk_v2(struct qup_i2c_block *blk) 1189 { 1190 blk->send_last_word = false; 1191 blk->tx_tags_sent = false; 1192 blk->tx_fifo_data = 0; 1193 blk->tx_fifo_data_pos = 0; 1194 blk->tx_fifo_free = 0; 1195 1196 blk->rx_tags_fetched = false; 1197 blk->rx_bytes_read = false; 1198 blk->rx_fifo_data = 0; 1199 blk->rx_fifo_data_pos = 0; 1200 blk->fifo_available = 0; 1201 } 1202 1203 /* Receive data from RX FIFO for read message in QUP v2 i2c transfer. */ 1204 static void qup_i2c_recv_data(struct qup_i2c_dev *qup) 1205 { 1206 struct qup_i2c_block *blk = &qup->blk; 1207 int j; 1208 1209 for (j = blk->rx_fifo_data_pos; 1210 blk->cur_blk_len && blk->fifo_available; 1211 blk->cur_blk_len--, blk->fifo_available--) { 1212 if (j == 0) 1213 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE); 1214 1215 *(blk->cur_data++) = blk->rx_fifo_data; 1216 blk->rx_fifo_data >>= 8; 1217 1218 if (j == 3) 1219 j = 0; 1220 else 1221 j++; 1222 } 1223 1224 blk->rx_fifo_data_pos = j; 1225 } 1226 1227 /* Receive tags for read message in QUP v2 i2c transfer. */ 1228 static void qup_i2c_recv_tags(struct qup_i2c_dev *qup) 1229 { 1230 struct qup_i2c_block *blk = &qup->blk; 1231 1232 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE); 1233 blk->rx_fifo_data >>= blk->rx_tag_len * 8; 1234 blk->rx_fifo_data_pos = blk->rx_tag_len; 1235 blk->fifo_available -= blk->rx_tag_len; 1236 } 1237 1238 /* 1239 * Read the data and tags from RX FIFO. Since in read case, the tags will be 1240 * preceded by received data bytes so 1241 * 1. Check if rx_tags_fetched is false i.e. the start of QUP block so receive 1242 * all tag bytes and discard that. 1243 * 2. Read the data from RX FIFO. When all the data bytes have been read then 1244 * set rx_bytes_read to true. 1245 */ 1246 static void qup_i2c_read_rx_fifo_v2(struct qup_i2c_dev *qup) 1247 { 1248 struct qup_i2c_block *blk = &qup->blk; 1249 1250 if (!blk->rx_tags_fetched) { 1251 qup_i2c_recv_tags(qup); 1252 blk->rx_tags_fetched = true; 1253 } 1254 1255 qup_i2c_recv_data(qup); 1256 if (!blk->cur_blk_len) 1257 blk->rx_bytes_read = true; 1258 } 1259 1260 /* 1261 * Write bytes in TX FIFO for write message in QUP v2 i2c transfer. QUP TX FIFO 1262 * write works on word basis (4 bytes). Append new data byte write for TX FIFO 1263 * in tx_fifo_data and write to TX FIFO when all the 4 bytes are present. 1264 */ 1265 static void 1266 qup_i2c_write_blk_data(struct qup_i2c_dev *qup, u8 **data, unsigned int *len) 1267 { 1268 struct qup_i2c_block *blk = &qup->blk; 1269 unsigned int j; 1270 1271 for (j = blk->tx_fifo_data_pos; *len && blk->tx_fifo_free; 1272 (*len)--, blk->tx_fifo_free--) { 1273 blk->tx_fifo_data |= *(*data)++ << (j * 8); 1274 if (j == 3) { 1275 writel(blk->tx_fifo_data, 1276 qup->base + QUP_OUT_FIFO_BASE); 1277 blk->tx_fifo_data = 0x0; 1278 j = 0; 1279 } else { 1280 j++; 1281 } 1282 } 1283 1284 blk->tx_fifo_data_pos = j; 1285 } 1286 1287 /* Transfer tags for read message in QUP v2 i2c transfer. */ 1288 static void qup_i2c_write_rx_tags_v2(struct qup_i2c_dev *qup) 1289 { 1290 struct qup_i2c_block *blk = &qup->blk; 1291 1292 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, &blk->tx_tag_len); 1293 if (blk->tx_fifo_data_pos) 1294 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE); 1295 } 1296 1297 /* 1298 * Write the data and tags in TX FIFO. Since in write case, both tags and data 1299 * need to be written and QUP write tags can have maximum 256 data length, so 1300 * 1301 * 1. Check if tx_tags_sent is false i.e. the start of QUP block so write the 1302 * tags to TX FIFO and set tx_tags_sent to true. 1303 * 2. Check if send_last_word is true. It will be set when last few data bytes 1304 * (less than 4 bytes) are reamining to be written in FIFO because of no FIFO 1305 * space. All this data bytes are available in tx_fifo_data so write this 1306 * in FIFO. 1307 * 3. Write the data to TX FIFO and check for cur_blk_len. If it is non zero 1308 * then more data is pending otherwise following 3 cases can be possible 1309 * a. if tx_fifo_data_pos is zero i.e. all the data bytes in this block 1310 * have been written in TX FIFO so nothing else is required. 1311 * b. tx_fifo_free is non zero i.e tx FIFO is free so copy the remaining data 1312 * from tx_fifo_data to tx FIFO. Since, qup_i2c_write_blk_data do write 1313 * in 4 bytes and FIFO space is in multiple of 4 bytes so tx_fifo_free 1314 * will be always greater than or equal to 4 bytes. 1315 * c. tx_fifo_free is zero. In this case, last few bytes (less than 4 1316 * bytes) are copied to tx_fifo_data but couldn't be sent because of 1317 * FIFO full so make send_last_word true. 1318 */ 1319 static void qup_i2c_write_tx_fifo_v2(struct qup_i2c_dev *qup) 1320 { 1321 struct qup_i2c_block *blk = &qup->blk; 1322 1323 if (!blk->tx_tags_sent) { 1324 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, 1325 &blk->tx_tag_len); 1326 blk->tx_tags_sent = true; 1327 } 1328 1329 if (blk->send_last_word) 1330 goto send_last_word; 1331 1332 qup_i2c_write_blk_data(qup, &blk->cur_data, &blk->cur_blk_len); 1333 if (!blk->cur_blk_len) { 1334 if (!blk->tx_fifo_data_pos) 1335 return; 1336 1337 if (blk->tx_fifo_free) 1338 goto send_last_word; 1339 1340 blk->send_last_word = true; 1341 } 1342 1343 return; 1344 1345 send_last_word: 1346 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE); 1347 } 1348 1349 /* 1350 * Main transfer function which read or write i2c data. 1351 * The QUP v2 supports reconfiguration during run in which multiple i2c sub 1352 * transfers can be scheduled. 1353 */ 1354 static int 1355 qup_i2c_conf_xfer_v2(struct qup_i2c_dev *qup, bool is_rx, bool is_first, 1356 bool change_pause_state) 1357 { 1358 struct qup_i2c_block *blk = &qup->blk; 1359 struct i2c_msg *msg = qup->msg; 1360 int ret; 1361 1362 /* 1363 * Check if its SMBus Block read for which the top level read will be 1364 * done into 2 QUP reads. One with message length 1 while other one is 1365 * with actual length. 1366 */ 1367 if (qup_i2c_check_msg_len(msg)) { 1368 if (qup->is_smbus_read) { 1369 /* 1370 * If the message length is already read in 1371 * the first byte of the buffer, account for 1372 * that by setting the offset 1373 */ 1374 blk->cur_data += 1; 1375 is_first = false; 1376 } else { 1377 change_pause_state = false; 1378 } 1379 } 1380 1381 qup->config_run = is_first ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN; 1382 1383 qup_i2c_clear_blk_v2(blk); 1384 qup_i2c_conf_count_v2(qup); 1385 1386 /* If it is first sub transfer, then configure i2c bus clocks */ 1387 if (is_first) { 1388 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); 1389 if (ret) 1390 return ret; 1391 1392 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); 1393 1394 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); 1395 if (ret) 1396 return ret; 1397 } 1398 1399 reinit_completion(&qup->xfer); 1400 enable_irq(qup->irq); 1401 /* 1402 * In FIFO mode, tx FIFO can be written directly while in block mode the 1403 * it will be written after getting OUT_BLOCK_WRITE_REQ interrupt 1404 */ 1405 if (!blk->is_tx_blk_mode) { 1406 blk->tx_fifo_free = qup->out_fifo_sz; 1407 1408 if (is_rx) 1409 qup_i2c_write_rx_tags_v2(qup); 1410 else 1411 qup_i2c_write_tx_fifo_v2(qup); 1412 } 1413 1414 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); 1415 if (ret) 1416 goto err; 1417 1418 ret = qup_i2c_wait_for_complete(qup, msg); 1419 if (ret) 1420 goto err; 1421 1422 /* Move to pause state for all the transfers, except last one */ 1423 if (change_pause_state) { 1424 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); 1425 if (ret) 1426 goto err; 1427 } 1428 1429 err: 1430 disable_irq(qup->irq); 1431 return ret; 1432 } 1433 1434 /* 1435 * Transfer one read/write message in i2c transfer. It splits the message into 1436 * multiple of blk_xfer_limit data length blocks and schedule each 1437 * QUP block individually. 1438 */ 1439 static int qup_i2c_xfer_v2_msg(struct qup_i2c_dev *qup, int msg_id, bool is_rx) 1440 { 1441 int ret = 0; 1442 unsigned int data_len, i; 1443 struct i2c_msg *msg = qup->msg; 1444 struct qup_i2c_block *blk = &qup->blk; 1445 u8 *msg_buf = msg->buf; 1446 1447 qup->blk_xfer_limit = is_rx ? RECV_MAX_DATA_LEN : QUP_READ_LIMIT; 1448 qup_i2c_set_blk_data(qup, msg); 1449 1450 for (i = 0; i < blk->count; i++) { 1451 data_len = qup_i2c_get_data_len(qup); 1452 blk->pos = i; 1453 blk->cur_tx_tags = blk->tags; 1454 blk->cur_blk_len = data_len; 1455 blk->tx_tag_len = 1456 qup_i2c_set_tags(blk->cur_tx_tags, qup, qup->msg); 1457 1458 blk->cur_data = msg_buf; 1459 1460 if (is_rx) { 1461 blk->total_tx_len = blk->tx_tag_len; 1462 blk->rx_tag_len = 2; 1463 blk->total_rx_len = blk->rx_tag_len + data_len; 1464 } else { 1465 blk->total_tx_len = blk->tx_tag_len + data_len; 1466 blk->total_rx_len = 0; 1467 } 1468 1469 ret = qup_i2c_conf_xfer_v2(qup, is_rx, !msg_id && !i, 1470 !qup->is_last || i < blk->count - 1); 1471 if (ret) 1472 return ret; 1473 1474 /* Handle SMBus block read length */ 1475 if (qup_i2c_check_msg_len(msg) && msg->len == 1 && 1476 !qup->is_smbus_read) { 1477 if (msg->buf[0] > I2C_SMBUS_BLOCK_MAX) 1478 return -EPROTO; 1479 1480 msg->len = msg->buf[0]; 1481 qup->is_smbus_read = true; 1482 ret = qup_i2c_xfer_v2_msg(qup, msg_id, true); 1483 qup->is_smbus_read = false; 1484 if (ret) 1485 return ret; 1486 1487 msg->len += 1; 1488 } 1489 1490 msg_buf += data_len; 1491 blk->data_len -= qup->blk_xfer_limit; 1492 } 1493 1494 return ret; 1495 } 1496 1497 /* 1498 * QUP v2 supports 3 modes 1499 * Programmed IO using FIFO mode : Less than FIFO size 1500 * Programmed IO using Block mode : Greater than FIFO size 1501 * DMA using BAM : Appropriate for any transaction size but the address should 1502 * be DMA applicable 1503 * 1504 * This function determines the mode which will be used for this transfer. An 1505 * i2c transfer contains multiple message. Following are the rules to determine 1506 * the mode used. 1507 * 1. Determine complete length, maximum tx and rx length for complete transfer. 1508 * 2. If complete transfer length is greater than fifo size then use the DMA 1509 * mode. 1510 * 3. In FIFO or block mode, tx and rx can operate in different mode so check 1511 * for maximum tx and rx length to determine mode. 1512 */ 1513 static int 1514 qup_i2c_determine_mode_v2(struct qup_i2c_dev *qup, 1515 struct i2c_msg msgs[], int num) 1516 { 1517 int idx; 1518 bool no_dma = false; 1519 unsigned int max_tx_len = 0, max_rx_len = 0, total_len = 0; 1520 1521 /* All i2c_msgs should be transferred using either dma or cpu */ 1522 for (idx = 0; idx < num; idx++) { 1523 if (msgs[idx].len == 0) 1524 return -EINVAL; 1525 1526 if (msgs[idx].flags & I2C_M_RD) 1527 max_rx_len = max_t(unsigned int, max_rx_len, 1528 msgs[idx].len); 1529 else 1530 max_tx_len = max_t(unsigned int, max_tx_len, 1531 msgs[idx].len); 1532 1533 if (is_vmalloc_addr(msgs[idx].buf)) 1534 no_dma = true; 1535 1536 total_len += msgs[idx].len; 1537 } 1538 1539 if (!no_dma && qup->is_dma && 1540 (total_len > qup->out_fifo_sz || total_len > qup->in_fifo_sz)) { 1541 qup->use_dma = true; 1542 } else { 1543 qup->blk.is_tx_blk_mode = max_tx_len > qup->out_fifo_sz - 1544 QUP_MAX_TAGS_LEN ? true : false; 1545 qup->blk.is_rx_blk_mode = max_rx_len > qup->in_fifo_sz - 1546 READ_RX_TAGS_LEN ? true : false; 1547 } 1548 1549 return 0; 1550 } 1551 1552 static int qup_i2c_xfer_v2(struct i2c_adapter *adap, 1553 struct i2c_msg msgs[], 1554 int num) 1555 { 1556 struct qup_i2c_dev *qup = i2c_get_adapdata(adap); 1557 int ret, idx = 0; 1558 1559 qup->bus_err = 0; 1560 qup->qup_err = 0; 1561 1562 ret = pm_runtime_get_sync(qup->dev); 1563 if (ret < 0) 1564 goto out; 1565 1566 ret = qup_i2c_determine_mode_v2(qup, msgs, num); 1567 if (ret) 1568 goto out; 1569 1570 writel(1, qup->base + QUP_SW_RESET); 1571 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE); 1572 if (ret) 1573 goto out; 1574 1575 /* Configure QUP as I2C mini core */ 1576 writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG); 1577 writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN); 1578 1579 if (qup_i2c_poll_state_i2c_master(qup)) { 1580 ret = -EIO; 1581 goto out; 1582 } 1583 1584 if (qup->use_dma) { 1585 reinit_completion(&qup->xfer); 1586 ret = qup_i2c_bam_xfer(adap, &msgs[0], num); 1587 qup->use_dma = false; 1588 } else { 1589 qup_i2c_conf_mode_v2(qup); 1590 1591 for (idx = 0; idx < num; idx++) { 1592 qup->msg = &msgs[idx]; 1593 qup->is_last = idx == (num - 1); 1594 1595 ret = qup_i2c_xfer_v2_msg(qup, idx, 1596 !!(msgs[idx].flags & I2C_M_RD)); 1597 if (ret) 1598 break; 1599 } 1600 qup->msg = NULL; 1601 } 1602 1603 if (!ret) 1604 ret = qup_i2c_bus_active(qup, ONE_BYTE); 1605 1606 if (!ret) 1607 qup_i2c_change_state(qup, QUP_RESET_STATE); 1608 1609 if (ret == 0) 1610 ret = num; 1611 out: 1612 pm_runtime_mark_last_busy(qup->dev); 1613 pm_runtime_put_autosuspend(qup->dev); 1614 1615 return ret; 1616 } 1617 1618 static u32 qup_i2c_func(struct i2c_adapter *adap) 1619 { 1620 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 1621 } 1622 1623 static const struct i2c_algorithm qup_i2c_algo = { 1624 .master_xfer = qup_i2c_xfer, 1625 .functionality = qup_i2c_func, 1626 }; 1627 1628 static const struct i2c_algorithm qup_i2c_algo_v2 = { 1629 .master_xfer = qup_i2c_xfer_v2, 1630 .functionality = qup_i2c_func, 1631 }; 1632 1633 /* 1634 * The QUP block will issue a NACK and STOP on the bus when reaching 1635 * the end of the read, the length of the read is specified as one byte 1636 * which limits the possible read to 256 (QUP_READ_LIMIT) bytes. 1637 */ 1638 static const struct i2c_adapter_quirks qup_i2c_quirks = { 1639 .max_read_len = QUP_READ_LIMIT, 1640 }; 1641 1642 static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup) 1643 { 1644 clk_prepare_enable(qup->clk); 1645 clk_prepare_enable(qup->pclk); 1646 } 1647 1648 static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup) 1649 { 1650 u32 config; 1651 1652 qup_i2c_change_state(qup, QUP_RESET_STATE); 1653 clk_disable_unprepare(qup->clk); 1654 config = readl(qup->base + QUP_CONFIG); 1655 config |= QUP_CLOCK_AUTO_GATE; 1656 writel(config, qup->base + QUP_CONFIG); 1657 clk_disable_unprepare(qup->pclk); 1658 } 1659 1660 static const struct acpi_device_id qup_i2c_acpi_match[] = { 1661 { "QCOM8010"}, 1662 { }, 1663 }; 1664 MODULE_DEVICE_TABLE(acpi, qup_i2c_acpi_match); 1665 1666 static int qup_i2c_probe(struct platform_device *pdev) 1667 { 1668 static const int blk_sizes[] = {4, 16, 32}; 1669 struct qup_i2c_dev *qup; 1670 unsigned long one_bit_t; 1671 struct resource *res; 1672 u32 io_mode, hw_ver, size; 1673 int ret, fs_div, hs_div; 1674 u32 src_clk_freq = DEFAULT_SRC_CLK; 1675 u32 clk_freq = DEFAULT_CLK_FREQ; 1676 int blocks; 1677 bool is_qup_v1; 1678 1679 qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL); 1680 if (!qup) 1681 return -ENOMEM; 1682 1683 qup->dev = &pdev->dev; 1684 init_completion(&qup->xfer); 1685 platform_set_drvdata(pdev, qup); 1686 1687 if (scl_freq) { 1688 dev_notice(qup->dev, "Using override frequency of %u\n", scl_freq); 1689 clk_freq = scl_freq; 1690 } else { 1691 ret = device_property_read_u32(qup->dev, "clock-frequency", &clk_freq); 1692 if (ret) { 1693 dev_notice(qup->dev, "using default clock-frequency %d", 1694 DEFAULT_CLK_FREQ); 1695 } 1696 } 1697 1698 if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) { 1699 qup->adap.algo = &qup_i2c_algo; 1700 qup->adap.quirks = &qup_i2c_quirks; 1701 is_qup_v1 = true; 1702 } else { 1703 qup->adap.algo = &qup_i2c_algo_v2; 1704 is_qup_v1 = false; 1705 if (acpi_match_device(qup_i2c_acpi_match, qup->dev)) 1706 goto nodma; 1707 else 1708 ret = qup_i2c_req_dma(qup); 1709 1710 if (ret == -EPROBE_DEFER) 1711 goto fail_dma; 1712 else if (ret != 0) 1713 goto nodma; 1714 1715 qup->max_xfer_sg_len = (MX_BLOCKS << 1); 1716 blocks = (MX_DMA_BLOCKS << 1) + 1; 1717 qup->btx.sg = devm_kcalloc(&pdev->dev, 1718 blocks, sizeof(*qup->btx.sg), 1719 GFP_KERNEL); 1720 if (!qup->btx.sg) { 1721 ret = -ENOMEM; 1722 goto fail_dma; 1723 } 1724 sg_init_table(qup->btx.sg, blocks); 1725 1726 qup->brx.sg = devm_kcalloc(&pdev->dev, 1727 blocks, sizeof(*qup->brx.sg), 1728 GFP_KERNEL); 1729 if (!qup->brx.sg) { 1730 ret = -ENOMEM; 1731 goto fail_dma; 1732 } 1733 sg_init_table(qup->brx.sg, blocks); 1734 1735 /* 2 tag bytes for each block + 5 for start, stop tags */ 1736 size = blocks * 2 + 5; 1737 1738 qup->start_tag.start = devm_kzalloc(&pdev->dev, 1739 size, GFP_KERNEL); 1740 if (!qup->start_tag.start) { 1741 ret = -ENOMEM; 1742 goto fail_dma; 1743 } 1744 1745 qup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL); 1746 if (!qup->brx.tag.start) { 1747 ret = -ENOMEM; 1748 goto fail_dma; 1749 } 1750 1751 qup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL); 1752 if (!qup->btx.tag.start) { 1753 ret = -ENOMEM; 1754 goto fail_dma; 1755 } 1756 qup->is_dma = true; 1757 } 1758 1759 nodma: 1760 /* We support frequencies up to FAST Mode Plus (1MHz) */ 1761 if (!clk_freq || clk_freq > I2C_FAST_MODE_PLUS_FREQ) { 1762 dev_err(qup->dev, "clock frequency not supported %d\n", 1763 clk_freq); 1764 return -EINVAL; 1765 } 1766 1767 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1768 qup->base = devm_ioremap_resource(qup->dev, res); 1769 if (IS_ERR(qup->base)) 1770 return PTR_ERR(qup->base); 1771 1772 qup->irq = platform_get_irq(pdev, 0); 1773 if (qup->irq < 0) { 1774 dev_err(qup->dev, "No IRQ defined\n"); 1775 return qup->irq; 1776 } 1777 1778 if (has_acpi_companion(qup->dev)) { 1779 ret = device_property_read_u32(qup->dev, 1780 "src-clock-hz", &src_clk_freq); 1781 if (ret) { 1782 dev_notice(qup->dev, "using default src-clock-hz %d", 1783 DEFAULT_SRC_CLK); 1784 } 1785 ACPI_COMPANION_SET(&qup->adap.dev, ACPI_COMPANION(qup->dev)); 1786 } else { 1787 qup->clk = devm_clk_get(qup->dev, "core"); 1788 if (IS_ERR(qup->clk)) { 1789 dev_err(qup->dev, "Could not get core clock\n"); 1790 return PTR_ERR(qup->clk); 1791 } 1792 1793 qup->pclk = devm_clk_get(qup->dev, "iface"); 1794 if (IS_ERR(qup->pclk)) { 1795 dev_err(qup->dev, "Could not get iface clock\n"); 1796 return PTR_ERR(qup->pclk); 1797 } 1798 qup_i2c_enable_clocks(qup); 1799 src_clk_freq = clk_get_rate(qup->clk); 1800 } 1801 1802 /* 1803 * Bootloaders might leave a pending interrupt on certain QUP's, 1804 * so we reset the core before registering for interrupts. 1805 */ 1806 writel(1, qup->base + QUP_SW_RESET); 1807 ret = qup_i2c_poll_state_valid(qup); 1808 if (ret) 1809 goto fail; 1810 1811 ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt, 1812 IRQF_TRIGGER_HIGH, "i2c_qup", qup); 1813 if (ret) { 1814 dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq); 1815 goto fail; 1816 } 1817 disable_irq(qup->irq); 1818 1819 hw_ver = readl(qup->base + QUP_HW_VERSION); 1820 dev_dbg(qup->dev, "Revision %x\n", hw_ver); 1821 1822 io_mode = readl(qup->base + QUP_IO_MODE); 1823 1824 /* 1825 * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag' 1826 * associated with each byte written/received 1827 */ 1828 size = QUP_OUTPUT_BLOCK_SIZE(io_mode); 1829 if (size >= ARRAY_SIZE(blk_sizes)) { 1830 ret = -EIO; 1831 goto fail; 1832 } 1833 qup->out_blk_sz = blk_sizes[size]; 1834 1835 size = QUP_INPUT_BLOCK_SIZE(io_mode); 1836 if (size >= ARRAY_SIZE(blk_sizes)) { 1837 ret = -EIO; 1838 goto fail; 1839 } 1840 qup->in_blk_sz = blk_sizes[size]; 1841 1842 if (is_qup_v1) { 1843 /* 1844 * in QUP v1, QUP_CONFIG uses N as 15 i.e 16 bits constitutes a 1845 * single transfer but the block size is in bytes so divide the 1846 * in_blk_sz and out_blk_sz by 2 1847 */ 1848 qup->in_blk_sz /= 2; 1849 qup->out_blk_sz /= 2; 1850 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v1; 1851 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v1; 1852 qup->write_rx_tags = qup_i2c_write_rx_tags_v1; 1853 } else { 1854 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v2; 1855 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v2; 1856 qup->write_rx_tags = qup_i2c_write_rx_tags_v2; 1857 } 1858 1859 size = QUP_OUTPUT_FIFO_SIZE(io_mode); 1860 qup->out_fifo_sz = qup->out_blk_sz * (2 << size); 1861 1862 size = QUP_INPUT_FIFO_SIZE(io_mode); 1863 qup->in_fifo_sz = qup->in_blk_sz * (2 << size); 1864 1865 hs_div = 3; 1866 if (clk_freq <= I2C_STANDARD_FREQ) { 1867 fs_div = ((src_clk_freq / clk_freq) / 2) - 3; 1868 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff); 1869 } else { 1870 /* 33%/66% duty cycle */ 1871 fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3; 1872 qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff); 1873 } 1874 1875 /* 1876 * Time it takes for a byte to be clocked out on the bus. 1877 * Each byte takes 9 clock cycles (8 bits + 1 ack). 1878 */ 1879 one_bit_t = (USEC_PER_SEC / clk_freq) + 1; 1880 qup->one_byte_t = one_bit_t * 9; 1881 qup->xfer_timeout = TOUT_MIN * HZ + 1882 usecs_to_jiffies(MX_DMA_TX_RX_LEN * qup->one_byte_t); 1883 1884 dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n", 1885 qup->in_blk_sz, qup->in_fifo_sz, 1886 qup->out_blk_sz, qup->out_fifo_sz); 1887 1888 i2c_set_adapdata(&qup->adap, qup); 1889 qup->adap.dev.parent = qup->dev; 1890 qup->adap.dev.of_node = pdev->dev.of_node; 1891 qup->is_last = true; 1892 1893 strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name)); 1894 1895 pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC); 1896 pm_runtime_use_autosuspend(qup->dev); 1897 pm_runtime_set_active(qup->dev); 1898 pm_runtime_enable(qup->dev); 1899 1900 ret = i2c_add_adapter(&qup->adap); 1901 if (ret) 1902 goto fail_runtime; 1903 1904 return 0; 1905 1906 fail_runtime: 1907 pm_runtime_disable(qup->dev); 1908 pm_runtime_set_suspended(qup->dev); 1909 fail: 1910 qup_i2c_disable_clocks(qup); 1911 fail_dma: 1912 if (qup->btx.dma) 1913 dma_release_channel(qup->btx.dma); 1914 if (qup->brx.dma) 1915 dma_release_channel(qup->brx.dma); 1916 return ret; 1917 } 1918 1919 static int qup_i2c_remove(struct platform_device *pdev) 1920 { 1921 struct qup_i2c_dev *qup = platform_get_drvdata(pdev); 1922 1923 if (qup->is_dma) { 1924 dma_release_channel(qup->btx.dma); 1925 dma_release_channel(qup->brx.dma); 1926 } 1927 1928 disable_irq(qup->irq); 1929 qup_i2c_disable_clocks(qup); 1930 i2c_del_adapter(&qup->adap); 1931 pm_runtime_disable(qup->dev); 1932 pm_runtime_set_suspended(qup->dev); 1933 return 0; 1934 } 1935 1936 #ifdef CONFIG_PM 1937 static int qup_i2c_pm_suspend_runtime(struct device *device) 1938 { 1939 struct qup_i2c_dev *qup = dev_get_drvdata(device); 1940 1941 dev_dbg(device, "pm_runtime: suspending...\n"); 1942 qup_i2c_disable_clocks(qup); 1943 return 0; 1944 } 1945 1946 static int qup_i2c_pm_resume_runtime(struct device *device) 1947 { 1948 struct qup_i2c_dev *qup = dev_get_drvdata(device); 1949 1950 dev_dbg(device, "pm_runtime: resuming...\n"); 1951 qup_i2c_enable_clocks(qup); 1952 return 0; 1953 } 1954 #endif 1955 1956 #ifdef CONFIG_PM_SLEEP 1957 static int qup_i2c_suspend(struct device *device) 1958 { 1959 if (!pm_runtime_suspended(device)) 1960 return qup_i2c_pm_suspend_runtime(device); 1961 return 0; 1962 } 1963 1964 static int qup_i2c_resume(struct device *device) 1965 { 1966 qup_i2c_pm_resume_runtime(device); 1967 pm_runtime_mark_last_busy(device); 1968 pm_request_autosuspend(device); 1969 return 0; 1970 } 1971 #endif 1972 1973 static const struct dev_pm_ops qup_i2c_qup_pm_ops = { 1974 SET_SYSTEM_SLEEP_PM_OPS( 1975 qup_i2c_suspend, 1976 qup_i2c_resume) 1977 SET_RUNTIME_PM_OPS( 1978 qup_i2c_pm_suspend_runtime, 1979 qup_i2c_pm_resume_runtime, 1980 NULL) 1981 }; 1982 1983 static const struct of_device_id qup_i2c_dt_match[] = { 1984 { .compatible = "qcom,i2c-qup-v1.1.1" }, 1985 { .compatible = "qcom,i2c-qup-v2.1.1" }, 1986 { .compatible = "qcom,i2c-qup-v2.2.1" }, 1987 {} 1988 }; 1989 MODULE_DEVICE_TABLE(of, qup_i2c_dt_match); 1990 1991 static struct platform_driver qup_i2c_driver = { 1992 .probe = qup_i2c_probe, 1993 .remove = qup_i2c_remove, 1994 .driver = { 1995 .name = "i2c_qup", 1996 .pm = &qup_i2c_qup_pm_ops, 1997 .of_match_table = qup_i2c_dt_match, 1998 .acpi_match_table = ACPI_PTR(qup_i2c_acpi_match), 1999 }, 2000 }; 2001 2002 module_platform_driver(qup_i2c_driver); 2003 2004 MODULE_LICENSE("GPL v2"); 2005 MODULE_ALIAS("platform:i2c_qup"); 2006