1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 3 4 #include <linux/acpi.h> 5 #include <linux/clk.h> 6 #include <linux/dmaengine.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/dma/qcom-gpi-dma.h> 9 #include <linux/err.h> 10 #include <linux/i2c.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/soc/qcom/geni-se.h> 18 #include <linux/spinlock.h> 19 #include <linux/units.h> 20 21 #define SE_I2C_TX_TRANS_LEN 0x26c 22 #define SE_I2C_RX_TRANS_LEN 0x270 23 #define SE_I2C_SCL_COUNTERS 0x278 24 25 #define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\ 26 M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN) 27 #define SE_I2C_ABORT BIT(1) 28 29 /* M_CMD OP codes for I2C */ 30 #define I2C_WRITE 0x1 31 #define I2C_READ 0x2 32 #define I2C_WRITE_READ 0x3 33 #define I2C_ADDR_ONLY 0x4 34 #define I2C_BUS_CLEAR 0x6 35 #define I2C_STOP_ON_BUS 0x7 36 /* M_CMD params for I2C */ 37 #define PRE_CMD_DELAY BIT(0) 38 #define TIMESTAMP_BEFORE BIT(1) 39 #define STOP_STRETCH BIT(2) 40 #define TIMESTAMP_AFTER BIT(3) 41 #define POST_COMMAND_DELAY BIT(4) 42 #define IGNORE_ADD_NACK BIT(6) 43 #define READ_FINISHED_WITH_ACK BIT(7) 44 #define BYPASS_ADDR_PHASE BIT(8) 45 #define SLV_ADDR_MSK GENMASK(15, 9) 46 #define SLV_ADDR_SHFT 9 47 /* I2C SCL COUNTER fields */ 48 #define HIGH_COUNTER_MSK GENMASK(29, 20) 49 #define HIGH_COUNTER_SHFT 20 50 #define LOW_COUNTER_MSK GENMASK(19, 10) 51 #define LOW_COUNTER_SHFT 10 52 #define CYCLE_COUNTER_MSK GENMASK(9, 0) 53 54 #define I2C_PACK_TX BIT(0) 55 #define I2C_PACK_RX BIT(1) 56 57 enum geni_i2c_err_code { 58 GP_IRQ0, 59 NACK, 60 GP_IRQ2, 61 BUS_PROTO, 62 ARB_LOST, 63 GP_IRQ5, 64 GENI_OVERRUN, 65 GENI_ILLEGAL_CMD, 66 GENI_ABORT_DONE, 67 GENI_TIMEOUT, 68 }; 69 70 #define DM_I2C_CB_ERR ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \ 71 << 5) 72 73 #define I2C_AUTO_SUSPEND_DELAY 250 74 #define PACKING_BYTES_PW 4 75 76 #define ABORT_TIMEOUT HZ 77 #define XFER_TIMEOUT HZ 78 #define RST_TIMEOUT HZ 79 80 #define QCOM_I2C_MIN_NUM_OF_MSGS_MULTI_DESC 2 81 82 /** 83 * struct geni_i2c_gpi_multi_desc_xfer - Structure for multi transfer support 84 * 85 * @msg_idx_cnt: Current message index being processed in the transfer 86 * @unmap_msg_cnt: Number of messages that have been unmapped 87 * @irq_cnt: Number of transfer completion interrupts received 88 * @dma_buf: Array of virtual addresses for DMA-safe buffers 89 * @dma_addr: Array of DMA addresses corresponding to the buffers 90 */ 91 struct geni_i2c_gpi_multi_desc_xfer { 92 u32 msg_idx_cnt; 93 u32 unmap_msg_cnt; 94 u32 irq_cnt; 95 void **dma_buf; 96 dma_addr_t *dma_addr; 97 }; 98 99 struct geni_i2c_dev { 100 struct geni_se se; 101 u32 tx_wm; 102 int irq; 103 int err; 104 struct i2c_adapter adap; 105 struct completion done; 106 struct i2c_msg *cur; 107 int cur_wr; 108 int cur_rd; 109 spinlock_t lock; 110 struct clk *core_clk; 111 u32 clk_freq_out; 112 const struct geni_i2c_clk_fld *clk_fld; 113 void *dma_buf; 114 size_t xfer_len; 115 dma_addr_t dma_addr; 116 struct dma_chan *tx_c; 117 struct dma_chan *rx_c; 118 bool no_dma; 119 bool gpi_mode; 120 bool abort_done; 121 bool is_tx_multi_desc_xfer; 122 u32 num_msgs; 123 struct geni_i2c_gpi_multi_desc_xfer i2c_multi_desc_config; 124 }; 125 126 struct geni_i2c_desc { 127 bool has_core_clk; 128 char *icc_ddr; 129 bool no_dma_support; 130 unsigned int tx_fifo_depth; 131 }; 132 133 struct geni_i2c_err_log { 134 int err; 135 const char *msg; 136 }; 137 138 static const struct geni_i2c_err_log gi2c_log[] = { 139 [GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"}, 140 [NACK] = {-ENXIO, "NACK: slv unresponsive, check its power/reset-ln"}, 141 [GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"}, 142 [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unexpected start/stop"}, 143 [ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"}, 144 [GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"}, 145 [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"}, 146 [GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"}, 147 [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"}, 148 [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"}, 149 }; 150 151 struct geni_i2c_clk_fld { 152 u32 clk_freq_out; 153 u8 clk_div; 154 u8 t_high_cnt; 155 u8 t_low_cnt; 156 u8 t_cycle_cnt; 157 }; 158 159 /* 160 * Hardware uses the underlying formula to calculate time periods of 161 * SCL clock cycle. Firmware uses some additional cycles excluded from the 162 * below formula and it is confirmed that the time periods are within 163 * specification limits. 164 * 165 * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock 166 * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock 167 * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock 168 * clk_freq_out = t / t_cycle 169 * source_clock = 19.2 MHz 170 */ 171 static const struct geni_i2c_clk_fld geni_i2c_clk_map_19p2mhz[] = { 172 { I2C_MAX_STANDARD_MODE_FREQ, 7, 10, 12, 26 }, 173 { I2C_MAX_FAST_MODE_FREQ, 2, 5, 11, 22 }, 174 { I2C_MAX_FAST_MODE_PLUS_FREQ, 1, 2, 8, 18 }, 175 {} 176 }; 177 178 /* source_clock = 32 MHz */ 179 static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = { 180 { I2C_MAX_STANDARD_MODE_FREQ, 8, 14, 18, 38 }, 181 { I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 19 }, 182 { I2C_MAX_FAST_MODE_PLUS_FREQ, 2, 3, 5, 15 }, 183 {} 184 }; 185 186 static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c) 187 { 188 const struct geni_i2c_clk_fld *itr; 189 190 if (clk_get_rate(gi2c->se.clk) == 32 * HZ_PER_MHZ) 191 itr = geni_i2c_clk_map_32mhz; 192 else 193 itr = geni_i2c_clk_map_19p2mhz; 194 195 while (itr->clk_freq_out != 0) { 196 if (itr->clk_freq_out == gi2c->clk_freq_out) { 197 gi2c->clk_fld = itr; 198 return 0; 199 } 200 itr++; 201 } 202 return -EINVAL; 203 } 204 205 static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c) 206 { 207 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; 208 u32 val; 209 210 writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL); 211 212 val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN; 213 writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG); 214 215 val = itr->t_high_cnt << HIGH_COUNTER_SHFT; 216 val |= itr->t_low_cnt << LOW_COUNTER_SHFT; 217 val |= itr->t_cycle_cnt; 218 writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS); 219 } 220 221 static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c) 222 { 223 u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0); 224 u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS); 225 u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS); 226 u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS); 227 u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN); 228 u32 rx_st, tx_st; 229 230 if (dma) { 231 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); 232 tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT); 233 } else { 234 rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS); 235 tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS); 236 } 237 dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n", 238 dma, tx_st, rx_st, m_stat); 239 dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n", 240 m_cmd, geni_s, geni_ios); 241 } 242 243 static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err) 244 { 245 if (!gi2c->err) 246 gi2c->err = gi2c_log[err].err; 247 if (gi2c->cur) 248 dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n", 249 gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags); 250 251 switch (err) { 252 case GENI_ABORT_DONE: 253 gi2c->abort_done = true; 254 break; 255 case NACK: 256 case GENI_TIMEOUT: 257 dev_dbg(gi2c->se.dev, "%s\n", gi2c_log[err].msg); 258 break; 259 default: 260 dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg); 261 geni_i2c_err_misc(gi2c); 262 break; 263 } 264 } 265 266 static irqreturn_t geni_i2c_irq(int irq, void *dev) 267 { 268 struct geni_i2c_dev *gi2c = dev; 269 void __iomem *base = gi2c->se.base; 270 int j, p; 271 u32 m_stat; 272 u32 rx_st; 273 u32 dm_tx_st; 274 u32 dm_rx_st; 275 u32 dma; 276 u32 val; 277 struct i2c_msg *cur; 278 279 spin_lock(&gi2c->lock); 280 m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS); 281 rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS); 282 dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT); 283 dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT); 284 dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN); 285 cur = gi2c->cur; 286 287 if (!cur || 288 m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) || 289 dm_rx_st & (DM_I2C_CB_ERR)) { 290 if (m_stat & M_GP_IRQ_1_EN) 291 geni_i2c_err(gi2c, NACK); 292 if (m_stat & M_GP_IRQ_3_EN) 293 geni_i2c_err(gi2c, BUS_PROTO); 294 if (m_stat & M_GP_IRQ_4_EN) 295 geni_i2c_err(gi2c, ARB_LOST); 296 if (m_stat & M_CMD_OVERRUN_EN) 297 geni_i2c_err(gi2c, GENI_OVERRUN); 298 if (m_stat & M_ILLEGAL_CMD_EN) 299 geni_i2c_err(gi2c, GENI_ILLEGAL_CMD); 300 if (m_stat & M_CMD_ABORT_EN) 301 geni_i2c_err(gi2c, GENI_ABORT_DONE); 302 if (m_stat & M_GP_IRQ_0_EN) 303 geni_i2c_err(gi2c, GP_IRQ0); 304 305 /* Disable the TX Watermark interrupt to stop TX */ 306 if (!dma) 307 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG); 308 } else if (dma) { 309 dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n", 310 dm_tx_st, dm_rx_st); 311 } else if (cur->flags & I2C_M_RD && 312 m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) { 313 u32 rxcnt = rx_st & RX_FIFO_WC_MSK; 314 315 for (j = 0; j < rxcnt; j++) { 316 p = 0; 317 val = readl_relaxed(base + SE_GENI_RX_FIFOn); 318 while (gi2c->cur_rd < cur->len && p < sizeof(val)) { 319 cur->buf[gi2c->cur_rd++] = val & 0xff; 320 val >>= 8; 321 p++; 322 } 323 if (gi2c->cur_rd == cur->len) 324 break; 325 } 326 } else if (!(cur->flags & I2C_M_RD) && 327 m_stat & M_TX_FIFO_WATERMARK_EN) { 328 for (j = 0; j < gi2c->tx_wm; j++) { 329 u32 temp; 330 331 val = 0; 332 p = 0; 333 while (gi2c->cur_wr < cur->len && p < sizeof(val)) { 334 temp = cur->buf[gi2c->cur_wr++]; 335 val |= temp << (p * 8); 336 p++; 337 } 338 writel_relaxed(val, base + SE_GENI_TX_FIFOn); 339 /* TX Complete, Disable the TX Watermark interrupt */ 340 if (gi2c->cur_wr == cur->len) { 341 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG); 342 break; 343 } 344 } 345 } 346 347 if (m_stat) 348 writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR); 349 350 if (dma && dm_tx_st) 351 writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR); 352 if (dma && dm_rx_st) 353 writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR); 354 355 /* if this is err with done-bit not set, handle that through timeout. */ 356 if (m_stat & M_CMD_DONE_EN || m_stat & M_CMD_ABORT_EN || 357 dm_tx_st & TX_DMA_DONE || dm_tx_st & TX_RESET_DONE || 358 dm_rx_st & RX_DMA_DONE || dm_rx_st & RX_RESET_DONE) 359 complete(&gi2c->done); 360 361 spin_unlock(&gi2c->lock); 362 363 return IRQ_HANDLED; 364 } 365 366 static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c) 367 { 368 unsigned long time_left = ABORT_TIMEOUT; 369 unsigned long flags; 370 371 spin_lock_irqsave(&gi2c->lock, flags); 372 geni_i2c_err(gi2c, GENI_TIMEOUT); 373 gi2c->cur = NULL; 374 gi2c->abort_done = false; 375 geni_se_abort_m_cmd(&gi2c->se); 376 spin_unlock_irqrestore(&gi2c->lock, flags); 377 378 do { 379 time_left = wait_for_completion_timeout(&gi2c->done, time_left); 380 } while (!gi2c->abort_done && time_left); 381 382 if (!time_left) 383 dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n"); 384 } 385 386 static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c) 387 { 388 u32 val; 389 unsigned long time_left = RST_TIMEOUT; 390 391 writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST); 392 do { 393 time_left = wait_for_completion_timeout(&gi2c->done, time_left); 394 val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); 395 } while (!(val & RX_RESET_DONE) && time_left); 396 397 if (!(val & RX_RESET_DONE)) 398 dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n"); 399 } 400 401 static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c) 402 { 403 u32 val; 404 unsigned long time_left = RST_TIMEOUT; 405 406 writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST); 407 do { 408 time_left = wait_for_completion_timeout(&gi2c->done, time_left); 409 val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT); 410 } while (!(val & TX_RESET_DONE) && time_left); 411 412 if (!(val & TX_RESET_DONE)) 413 dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n"); 414 } 415 416 static void geni_i2c_rx_msg_cleanup(struct geni_i2c_dev *gi2c, 417 struct i2c_msg *cur) 418 { 419 gi2c->cur_rd = 0; 420 if (gi2c->dma_buf) { 421 if (gi2c->err) 422 geni_i2c_rx_fsm_rst(gi2c); 423 geni_se_rx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len); 424 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err); 425 } 426 } 427 428 static void geni_i2c_tx_msg_cleanup(struct geni_i2c_dev *gi2c, 429 struct i2c_msg *cur) 430 { 431 gi2c->cur_wr = 0; 432 if (gi2c->dma_buf) { 433 if (gi2c->err) 434 geni_i2c_tx_fsm_rst(gi2c); 435 geni_se_tx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len); 436 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err); 437 } 438 } 439 440 static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 441 u32 m_param) 442 { 443 dma_addr_t rx_dma = 0; 444 unsigned long time_left; 445 void *dma_buf; 446 struct geni_se *se = &gi2c->se; 447 size_t len = msg->len; 448 struct i2c_msg *cur; 449 450 dma_buf = gi2c->no_dma ? NULL : i2c_get_dma_safe_msg_buf(msg, 32); 451 if (dma_buf) 452 geni_se_select_mode(se, GENI_SE_DMA); 453 else 454 geni_se_select_mode(se, GENI_SE_FIFO); 455 456 writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN); 457 geni_se_setup_m_cmd(se, I2C_READ, m_param); 458 459 if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) { 460 geni_se_select_mode(se, GENI_SE_FIFO); 461 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 462 dma_buf = NULL; 463 } else { 464 gi2c->xfer_len = len; 465 gi2c->dma_addr = rx_dma; 466 gi2c->dma_buf = dma_buf; 467 } 468 469 cur = gi2c->cur; 470 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); 471 if (!time_left) 472 geni_i2c_abort_xfer(gi2c); 473 474 geni_i2c_rx_msg_cleanup(gi2c, cur); 475 476 return gi2c->err; 477 } 478 479 static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 480 u32 m_param) 481 { 482 dma_addr_t tx_dma = 0; 483 unsigned long time_left; 484 void *dma_buf; 485 struct geni_se *se = &gi2c->se; 486 size_t len = msg->len; 487 struct i2c_msg *cur; 488 489 dma_buf = gi2c->no_dma ? NULL : i2c_get_dma_safe_msg_buf(msg, 32); 490 if (dma_buf) 491 geni_se_select_mode(se, GENI_SE_DMA); 492 else 493 geni_se_select_mode(se, GENI_SE_FIFO); 494 495 writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN); 496 geni_se_setup_m_cmd(se, I2C_WRITE, m_param); 497 498 if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) { 499 geni_se_select_mode(se, GENI_SE_FIFO); 500 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 501 dma_buf = NULL; 502 } else { 503 gi2c->xfer_len = len; 504 gi2c->dma_addr = tx_dma; 505 gi2c->dma_buf = dma_buf; 506 } 507 508 if (!dma_buf) /* Get FIFO IRQ */ 509 writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG); 510 511 cur = gi2c->cur; 512 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); 513 if (!time_left) 514 geni_i2c_abort_xfer(gi2c); 515 516 geni_i2c_tx_msg_cleanup(gi2c, cur); 517 518 return gi2c->err; 519 } 520 521 static void i2c_gpi_cb_result(void *cb, const struct dmaengine_result *result) 522 { 523 struct geni_i2c_dev *gi2c = cb; 524 struct geni_i2c_gpi_multi_desc_xfer *tx_multi_xfer; 525 526 if (result->result != DMA_TRANS_NOERROR) { 527 dev_err(gi2c->se.dev, "DMA txn failed:%d\n", result->result); 528 gi2c->err = -EIO; 529 } else if (result->residue) { 530 dev_dbg(gi2c->se.dev, "DMA xfer has pending: %d\n", result->residue); 531 } 532 533 if (gi2c->is_tx_multi_desc_xfer) { 534 tx_multi_xfer = &gi2c->i2c_multi_desc_config; 535 tx_multi_xfer->irq_cnt++; 536 } 537 538 complete(&gi2c->done); 539 } 540 541 static void geni_i2c_gpi_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 542 void *tx_buf, dma_addr_t tx_addr, 543 void *rx_buf, dma_addr_t rx_addr) 544 { 545 if (tx_buf) { 546 dma_unmap_single(gi2c->se.dev->parent, tx_addr, msg->len, DMA_TO_DEVICE); 547 i2c_put_dma_safe_msg_buf(tx_buf, msg, !gi2c->err); 548 } 549 550 if (rx_buf) { 551 dma_unmap_single(gi2c->se.dev->parent, rx_addr, msg->len, DMA_FROM_DEVICE); 552 i2c_put_dma_safe_msg_buf(rx_buf, msg, !gi2c->err); 553 } 554 } 555 556 /** 557 * geni_i2c_gpi_multi_desc_unmap() - Unmaps DMA buffers post multi message TX transfers 558 * @gi2c: I2C dev handle 559 * @msgs: Array of I2C messages 560 * @peripheral: Pointer to gpi_i2c_config 561 */ 562 static void geni_i2c_gpi_multi_desc_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], 563 struct gpi_i2c_config *peripheral) 564 { 565 u32 msg_xfer_cnt, wr_idx = 0; 566 struct geni_i2c_gpi_multi_desc_xfer *tx_multi_xfer = &gi2c->i2c_multi_desc_config; 567 568 msg_xfer_cnt = gi2c->err ? tx_multi_xfer->msg_idx_cnt : tx_multi_xfer->irq_cnt; 569 570 /* Unmap the processed DMA buffers based on the received interrupt count */ 571 for (; tx_multi_xfer->unmap_msg_cnt < msg_xfer_cnt; tx_multi_xfer->unmap_msg_cnt++) { 572 wr_idx = tx_multi_xfer->unmap_msg_cnt; 573 geni_i2c_gpi_unmap(gi2c, &msgs[wr_idx], 574 tx_multi_xfer->dma_buf[wr_idx], 575 tx_multi_xfer->dma_addr[wr_idx], 576 NULL, 0); 577 578 if (tx_multi_xfer->unmap_msg_cnt == gi2c->num_msgs - 1) { 579 kfree(tx_multi_xfer->dma_buf); 580 kfree(tx_multi_xfer->dma_addr); 581 break; 582 } 583 } 584 } 585 586 /** 587 * geni_i2c_gpi_multi_xfer_timeout_handler() - Handles multi message transfer timeout 588 * @dev: Pointer to the corresponding dev node 589 * @multi_xfer: Pointer to the geni_i2c_gpi_multi_desc_xfer 590 * @transfer_timeout_msecs: Timeout value in milliseconds 591 * @transfer_comp: Completion object of the transfer 592 * 593 * This function waits for the completion of each processed transfer messages 594 * based on the interrupts generated upon transfer completion. 595 * 596 * Return: On success returns 0, -ETIMEDOUT on timeout. 597 */ 598 static int geni_i2c_gpi_multi_xfer_timeout_handler(struct device *dev, 599 struct geni_i2c_gpi_multi_desc_xfer *multi_xfer, 600 u32 transfer_timeout_msecs, 601 struct completion *transfer_comp) 602 { 603 int i; 604 u32 time_left; 605 606 for (i = 0; i < multi_xfer->msg_idx_cnt - 1; i++) { 607 reinit_completion(transfer_comp); 608 609 if (multi_xfer->msg_idx_cnt != multi_xfer->irq_cnt) { 610 time_left = wait_for_completion_timeout(transfer_comp, 611 transfer_timeout_msecs); 612 if (!time_left) { 613 dev_err(dev, "%s: Transfer timeout\n", __func__); 614 return -ETIMEDOUT; 615 } 616 } 617 } 618 return 0; 619 } 620 621 static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], 622 struct dma_slave_config *config, dma_addr_t *dma_addr_p, 623 void **buf, unsigned int op, struct dma_chan *dma_chan) 624 { 625 struct gpi_i2c_config *peripheral; 626 unsigned int flags; 627 void *dma_buf = NULL; 628 dma_addr_t addr = 0; 629 enum dma_data_direction map_dirn; 630 enum dma_transfer_direction dma_dirn; 631 struct dma_async_tx_descriptor *desc; 632 int ret; 633 struct geni_i2c_gpi_multi_desc_xfer *gi2c_gpi_xfer; 634 dma_cookie_t cookie; 635 u32 msg_idx; 636 637 peripheral = config->peripheral_config; 638 gi2c_gpi_xfer = &gi2c->i2c_multi_desc_config; 639 msg_idx = gi2c_gpi_xfer->msg_idx_cnt; 640 641 /* 642 * Skip TX DMA mapping for a read message (I2C_M_RD) to avoid 643 * programming an extra TX DMA TRE that would cause an unintended 644 * write cycle on the I2C bus before the actual read operation. 645 */ 646 if (op == I2C_WRITE && msgs[msg_idx].flags & I2C_M_RD) { 647 peripheral->multi_msg = true; 648 goto skip_tx_dma_map; 649 } 650 651 dma_buf = i2c_get_dma_safe_msg_buf(&msgs[msg_idx], 1); 652 if (!dma_buf) { 653 ret = -ENOMEM; 654 goto out; 655 } 656 657 if (op == I2C_WRITE) 658 map_dirn = DMA_TO_DEVICE; 659 else 660 map_dirn = DMA_FROM_DEVICE; 661 662 addr = dma_map_single(gi2c->se.dev->parent, dma_buf, 663 msgs[msg_idx].len, map_dirn); 664 if (dma_mapping_error(gi2c->se.dev->parent, addr)) { 665 i2c_put_dma_safe_msg_buf(dma_buf, &msgs[msg_idx], false); 666 ret = -ENOMEM; 667 goto out; 668 } 669 670 skip_tx_dma_map: 671 if (gi2c->is_tx_multi_desc_xfer) { 672 flags = DMA_CTRL_ACK; 673 674 /* BEI bit to be cleared for last TRE */ 675 if (msg_idx == gi2c->num_msgs - 1) 676 flags |= DMA_PREP_INTERRUPT; 677 } else { 678 flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK; 679 } 680 681 /* set the length as message for rx txn */ 682 peripheral->rx_len = msgs[msg_idx].len; 683 peripheral->op = op; 684 685 ret = dmaengine_slave_config(dma_chan, config); 686 if (ret) { 687 dev_err(gi2c->se.dev, "dma config error: %d for op:%d\n", ret, op); 688 goto err_config; 689 } 690 691 peripheral->set_config = 0; 692 peripheral->multi_msg = true; 693 694 if (op == I2C_WRITE) 695 dma_dirn = DMA_MEM_TO_DEV; 696 else 697 dma_dirn = DMA_DEV_TO_MEM; 698 699 desc = dmaengine_prep_slave_single(dma_chan, addr, msgs[msg_idx].len, 700 dma_dirn, flags); 701 if (!desc && !(flags & DMA_PREP_INTERRUPT)) { 702 /* Retry with interrupt if not enough TREs */ 703 flags |= DMA_PREP_INTERRUPT; 704 desc = dmaengine_prep_slave_single(dma_chan, addr, msgs[msg_idx].len, 705 dma_dirn, flags); 706 } 707 708 if (!desc) { 709 dev_err(gi2c->se.dev, "prep_slave_sg failed\n"); 710 ret = -EIO; 711 goto err_config; 712 } 713 714 desc->callback_result = i2c_gpi_cb_result; 715 desc->callback_param = gi2c; 716 717 if (!((msgs[msg_idx].flags & I2C_M_RD) && op == I2C_WRITE)) 718 gi2c_gpi_xfer->msg_idx_cnt++; 719 720 cookie = dmaengine_submit(desc); 721 if (dma_submit_error(cookie)) { 722 dev_err(gi2c->se.dev, 723 "%s: dmaengine_submit failed (%d)\n", __func__, cookie); 724 ret = -EINVAL; 725 goto err_config; 726 } 727 728 if (gi2c->is_tx_multi_desc_xfer) { 729 gi2c_gpi_xfer->dma_buf[msg_idx] = dma_buf; 730 gi2c_gpi_xfer->dma_addr[msg_idx] = addr; 731 732 dma_async_issue_pending(gi2c->tx_c); 733 734 if ((msg_idx == (gi2c->num_msgs - 1)) || flags & DMA_PREP_INTERRUPT) { 735 ret = geni_i2c_gpi_multi_xfer_timeout_handler(gi2c->se.dev, gi2c_gpi_xfer, 736 XFER_TIMEOUT, &gi2c->done); 737 if (ret) { 738 dev_err(gi2c->se.dev, 739 "I2C multi write msg transfer timeout: %d\n", 740 ret); 741 gi2c->err = ret; 742 return ret; 743 } 744 } 745 } else { 746 /* Non multi descriptor message transfer */ 747 *buf = dma_buf; 748 *dma_addr_p = addr; 749 } 750 return 0; 751 752 err_config: 753 /* Avoid DMA unmap as the write operation skipped DMA mapping */ 754 if (dma_buf) { 755 dma_unmap_single(gi2c->se.dev->parent, addr, 756 msgs[msg_idx].len, map_dirn); 757 i2c_put_dma_safe_msg_buf(dma_buf, &msgs[msg_idx], false); 758 } 759 760 out: 761 gi2c->err = ret; 762 return ret; 763 } 764 765 static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], int num) 766 { 767 struct dma_slave_config config = {}; 768 struct gpi_i2c_config peripheral = {}; 769 int i, ret = 0; 770 unsigned long time_left; 771 dma_addr_t tx_addr, rx_addr; 772 void *tx_buf = NULL, *rx_buf = NULL; 773 struct geni_i2c_gpi_multi_desc_xfer *tx_multi_xfer; 774 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; 775 776 config.peripheral_config = &peripheral; 777 config.peripheral_size = sizeof(peripheral); 778 779 peripheral.pack_enable = I2C_PACK_TX | I2C_PACK_RX; 780 peripheral.cycle_count = itr->t_cycle_cnt; 781 peripheral.high_count = itr->t_high_cnt; 782 peripheral.low_count = itr->t_low_cnt; 783 peripheral.clk_div = itr->clk_div; 784 peripheral.set_config = 1; 785 peripheral.multi_msg = false; 786 787 gi2c->num_msgs = num; 788 gi2c->is_tx_multi_desc_xfer = false; 789 790 tx_multi_xfer = &gi2c->i2c_multi_desc_config; 791 memset(tx_multi_xfer, 0, sizeof(struct geni_i2c_gpi_multi_desc_xfer)); 792 793 /* 794 * If number of write messages are two and higher then 795 * configure hardware for multi descriptor transfers with BEI. 796 */ 797 if (num >= QCOM_I2C_MIN_NUM_OF_MSGS_MULTI_DESC) { 798 gi2c->is_tx_multi_desc_xfer = true; 799 for (i = 0; i < num; i++) { 800 if (msgs[i].flags & I2C_M_RD) { 801 /* 802 * Multi descriptor transfer with BEI 803 * support is enabled for write transfers. 804 * TODO: Add BEI optimization support for 805 * read transfers later. 806 */ 807 gi2c->is_tx_multi_desc_xfer = false; 808 break; 809 } 810 } 811 } 812 813 if (gi2c->is_tx_multi_desc_xfer) { 814 tx_multi_xfer->dma_buf = kcalloc(num, sizeof(void *), GFP_KERNEL); 815 tx_multi_xfer->dma_addr = kzalloc_objs(dma_addr_t, num); 816 if (!tx_multi_xfer->dma_buf || !tx_multi_xfer->dma_addr) { 817 ret = -ENOMEM; 818 goto err; 819 } 820 } 821 822 for (i = 0; i < num; i++) { 823 gi2c->cur = &msgs[i]; 824 gi2c->err = 0; 825 dev_dbg(gi2c->se.dev, "msg[%d].len:%d\n", i, gi2c->cur->len); 826 827 peripheral.stretch = 0; 828 if (i < num - 1) 829 peripheral.stretch = 1; 830 831 peripheral.addr = msgs[i].addr; 832 if (i > 0 && (!(msgs[i].flags & I2C_M_RD))) 833 peripheral.multi_msg = false; 834 835 ret = geni_i2c_gpi(gi2c, msgs, &config, 836 &tx_addr, &tx_buf, I2C_WRITE, gi2c->tx_c); 837 if (ret) 838 goto err; 839 840 if (msgs[i].flags & I2C_M_RD) { 841 ret = geni_i2c_gpi(gi2c, msgs, &config, 842 &rx_addr, &rx_buf, I2C_READ, gi2c->rx_c); 843 if (ret) 844 goto err; 845 846 dma_async_issue_pending(gi2c->rx_c); 847 } 848 849 if (!gi2c->is_tx_multi_desc_xfer) { 850 dma_async_issue_pending(gi2c->tx_c); 851 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); 852 if (!time_left) { 853 dev_err(gi2c->se.dev, "%s:I2C timeout\n", __func__); 854 gi2c->err = -ETIMEDOUT; 855 } 856 } 857 858 if (gi2c->err) { 859 ret = gi2c->err; 860 goto err; 861 } 862 863 if (!gi2c->is_tx_multi_desc_xfer) 864 geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); 865 else if (tx_multi_xfer->unmap_msg_cnt != tx_multi_xfer->irq_cnt) 866 geni_i2c_gpi_multi_desc_unmap(gi2c, msgs, &peripheral); 867 } 868 869 return num; 870 871 err: 872 dev_err(gi2c->se.dev, "GPI transfer failed: %d\n", ret); 873 dmaengine_terminate_sync(gi2c->rx_c); 874 dmaengine_terminate_sync(gi2c->tx_c); 875 if (gi2c->is_tx_multi_desc_xfer) 876 geni_i2c_gpi_multi_desc_unmap(gi2c, msgs, &peripheral); 877 else 878 geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); 879 880 return ret; 881 } 882 883 static int geni_i2c_fifo_xfer(struct geni_i2c_dev *gi2c, 884 struct i2c_msg msgs[], int num) 885 { 886 int i, ret = 0; 887 888 for (i = 0; i < num; i++) { 889 u32 m_param = i < (num - 1) ? STOP_STRETCH : 0; 890 891 m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK); 892 893 gi2c->cur = &msgs[i]; 894 if (msgs[i].flags & I2C_M_RD) 895 ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param); 896 else 897 ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param); 898 899 if (ret) 900 return ret; 901 } 902 903 return num; 904 } 905 906 static int geni_i2c_xfer(struct i2c_adapter *adap, 907 struct i2c_msg msgs[], 908 int num) 909 { 910 struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap); 911 int ret; 912 913 gi2c->err = 0; 914 reinit_completion(&gi2c->done); 915 ret = pm_runtime_get_sync(gi2c->se.dev); 916 if (ret < 0) { 917 dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret); 918 pm_runtime_put_noidle(gi2c->se.dev); 919 /* Set device in suspended since resume failed */ 920 pm_runtime_set_suspended(gi2c->se.dev); 921 return ret; 922 } 923 924 qcom_geni_i2c_conf(gi2c); 925 926 if (gi2c->gpi_mode) 927 ret = geni_i2c_gpi_xfer(gi2c, msgs, num); 928 else 929 ret = geni_i2c_fifo_xfer(gi2c, msgs, num); 930 931 pm_runtime_put_autosuspend(gi2c->se.dev); 932 gi2c->cur = NULL; 933 gi2c->err = 0; 934 return ret; 935 } 936 937 static u32 geni_i2c_func(struct i2c_adapter *adap) 938 { 939 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 940 } 941 942 static const struct i2c_algorithm geni_i2c_algo = { 943 .xfer = geni_i2c_xfer, 944 .functionality = geni_i2c_func, 945 }; 946 947 #ifdef CONFIG_ACPI 948 static const struct acpi_device_id geni_i2c_acpi_match[] = { 949 { "QCOM0220"}, 950 { "QCOM0411" }, 951 { } 952 }; 953 MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match); 954 #endif 955 956 static void release_gpi_dma(struct geni_i2c_dev *gi2c) 957 { 958 if (gi2c->rx_c) 959 dma_release_channel(gi2c->rx_c); 960 961 if (gi2c->tx_c) 962 dma_release_channel(gi2c->tx_c); 963 } 964 965 static int setup_gpi_dma(struct geni_i2c_dev *gi2c) 966 { 967 int ret; 968 969 geni_se_select_mode(&gi2c->se, GENI_GPI_DMA); 970 gi2c->tx_c = dma_request_chan(gi2c->se.dev, "tx"); 971 if (IS_ERR(gi2c->tx_c)) { 972 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->tx_c), 973 "Failed to get tx DMA ch\n"); 974 goto err_tx; 975 } 976 977 gi2c->rx_c = dma_request_chan(gi2c->se.dev, "rx"); 978 if (IS_ERR(gi2c->rx_c)) { 979 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->rx_c), 980 "Failed to get rx DMA ch\n"); 981 goto err_rx; 982 } 983 984 dev_dbg(gi2c->se.dev, "Grabbed GPI dma channels\n"); 985 return 0; 986 987 err_rx: 988 dma_release_channel(gi2c->tx_c); 989 err_tx: 990 return ret; 991 } 992 993 static int geni_i2c_probe(struct platform_device *pdev) 994 { 995 struct geni_i2c_dev *gi2c; 996 u32 proto, tx_depth, fifo_disable; 997 int ret; 998 struct device *dev = &pdev->dev; 999 const struct geni_i2c_desc *desc = NULL; 1000 1001 gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL); 1002 if (!gi2c) 1003 return -ENOMEM; 1004 1005 gi2c->se.dev = dev; 1006 gi2c->se.wrapper = dev_get_drvdata(dev->parent); 1007 gi2c->se.base = devm_platform_ioremap_resource(pdev, 0); 1008 if (IS_ERR(gi2c->se.base)) 1009 return PTR_ERR(gi2c->se.base); 1010 1011 desc = device_get_match_data(&pdev->dev); 1012 1013 if (desc && desc->has_core_clk) { 1014 gi2c->core_clk = devm_clk_get(dev, "core"); 1015 if (IS_ERR(gi2c->core_clk)) 1016 return PTR_ERR(gi2c->core_clk); 1017 } 1018 1019 gi2c->se.clk = devm_clk_get(dev, "se"); 1020 if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev)) 1021 return PTR_ERR(gi2c->se.clk); 1022 1023 ret = device_property_read_u32(dev, "clock-frequency", 1024 &gi2c->clk_freq_out); 1025 if (ret) { 1026 dev_info(dev, "Bus frequency not specified, default to 100kHz.\n"); 1027 gi2c->clk_freq_out = I2C_MAX_STANDARD_MODE_FREQ; 1028 } 1029 1030 if (has_acpi_companion(dev)) 1031 ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev)); 1032 1033 gi2c->irq = platform_get_irq(pdev, 0); 1034 if (gi2c->irq < 0) 1035 return gi2c->irq; 1036 1037 ret = geni_i2c_clk_map_idx(gi2c); 1038 if (ret) 1039 return dev_err_probe(dev, ret, "Invalid clk frequency %d Hz\n", 1040 gi2c->clk_freq_out); 1041 1042 gi2c->adap.algo = &geni_i2c_algo; 1043 init_completion(&gi2c->done); 1044 spin_lock_init(&gi2c->lock); 1045 platform_set_drvdata(pdev, gi2c); 1046 1047 /* Keep interrupts disabled initially to allow for low-power modes */ 1048 ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, IRQF_NO_AUTOEN, 1049 dev_name(dev), gi2c); 1050 if (ret) 1051 return dev_err_probe(dev, ret, 1052 "Request_irq failed: %d\n", gi2c->irq); 1053 1054 i2c_set_adapdata(&gi2c->adap, gi2c); 1055 gi2c->adap.dev.parent = dev; 1056 gi2c->adap.dev.of_node = dev->of_node; 1057 strscpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); 1058 1059 ret = geni_icc_get(&gi2c->se, desc ? desc->icc_ddr : "qup-memory"); 1060 if (ret) 1061 return ret; 1062 /* 1063 * Set the bus quota for core and cpu to a reasonable value for 1064 * register access. 1065 * Set quota for DDR based on bus speed. 1066 */ 1067 gi2c->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; 1068 gi2c->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 1069 if (!desc || desc->icc_ddr) 1070 gi2c->se.icc_paths[GENI_TO_DDR].avg_bw = Bps_to_icc(gi2c->clk_freq_out); 1071 1072 ret = geni_icc_set_bw(&gi2c->se); 1073 if (ret) 1074 return ret; 1075 1076 ret = clk_prepare_enable(gi2c->core_clk); 1077 if (ret) 1078 return ret; 1079 1080 ret = geni_se_resources_on(&gi2c->se); 1081 if (ret) { 1082 dev_err_probe(dev, ret, "Error turning on resources\n"); 1083 goto err_clk; 1084 } 1085 proto = geni_se_read_proto(&gi2c->se); 1086 if (proto == GENI_SE_INVALID_PROTO) { 1087 ret = geni_load_se_firmware(&gi2c->se, GENI_SE_I2C); 1088 if (ret) { 1089 dev_err_probe(dev, ret, "i2c firmware load failed ret: %d\n", ret); 1090 goto err_resources; 1091 } 1092 } else if (proto != GENI_SE_I2C) { 1093 ret = dev_err_probe(dev, -ENXIO, "Invalid proto %d\n", proto); 1094 goto err_resources; 1095 } 1096 1097 if (desc && desc->no_dma_support) { 1098 fifo_disable = false; 1099 gi2c->no_dma = true; 1100 } else { 1101 fifo_disable = readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; 1102 } 1103 1104 if (fifo_disable) { 1105 /* FIFO is disabled, so we can only use GPI DMA */ 1106 gi2c->gpi_mode = true; 1107 ret = setup_gpi_dma(gi2c); 1108 if (ret) 1109 goto err_resources; 1110 1111 dev_dbg(dev, "Using GPI DMA mode for I2C\n"); 1112 } else { 1113 gi2c->gpi_mode = false; 1114 tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se); 1115 1116 /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */ 1117 if (!tx_depth && desc) 1118 tx_depth = desc->tx_fifo_depth; 1119 1120 if (!tx_depth) { 1121 ret = dev_err_probe(dev, -EINVAL, 1122 "Invalid TX FIFO depth\n"); 1123 goto err_resources; 1124 } 1125 1126 gi2c->tx_wm = tx_depth - 1; 1127 geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth); 1128 geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, 1129 PACKING_BYTES_PW, true, true, true); 1130 1131 dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth); 1132 } 1133 1134 clk_disable_unprepare(gi2c->core_clk); 1135 ret = geni_se_resources_off(&gi2c->se); 1136 if (ret) { 1137 dev_err_probe(dev, ret, "Error turning off resources\n"); 1138 goto err_dma; 1139 } 1140 1141 ret = geni_icc_disable(&gi2c->se); 1142 if (ret) 1143 goto err_dma; 1144 1145 pm_runtime_set_suspended(gi2c->se.dev); 1146 pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY); 1147 pm_runtime_use_autosuspend(gi2c->se.dev); 1148 pm_runtime_enable(gi2c->se.dev); 1149 1150 ret = i2c_add_adapter(&gi2c->adap); 1151 if (ret) { 1152 dev_err_probe(dev, ret, "Error adding i2c adapter\n"); 1153 pm_runtime_disable(gi2c->se.dev); 1154 goto err_dma; 1155 } 1156 1157 dev_dbg(dev, "Geni-I2C adaptor successfully added\n"); 1158 1159 return ret; 1160 1161 err_resources: 1162 geni_se_resources_off(&gi2c->se); 1163 err_clk: 1164 clk_disable_unprepare(gi2c->core_clk); 1165 1166 return ret; 1167 1168 err_dma: 1169 release_gpi_dma(gi2c); 1170 1171 return ret; 1172 } 1173 1174 static void geni_i2c_remove(struct platform_device *pdev) 1175 { 1176 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev); 1177 1178 i2c_del_adapter(&gi2c->adap); 1179 release_gpi_dma(gi2c); 1180 pm_runtime_disable(gi2c->se.dev); 1181 } 1182 1183 static void geni_i2c_shutdown(struct platform_device *pdev) 1184 { 1185 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev); 1186 1187 /* Make client i2c transfers start failing */ 1188 i2c_mark_adapter_suspended(&gi2c->adap); 1189 } 1190 1191 static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev) 1192 { 1193 int ret; 1194 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 1195 1196 disable_irq(gi2c->irq); 1197 ret = geni_se_resources_off(&gi2c->se); 1198 if (ret) { 1199 enable_irq(gi2c->irq); 1200 return ret; 1201 } 1202 1203 clk_disable_unprepare(gi2c->core_clk); 1204 1205 return geni_icc_disable(&gi2c->se); 1206 } 1207 1208 static int __maybe_unused geni_i2c_runtime_resume(struct device *dev) 1209 { 1210 int ret; 1211 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 1212 1213 ret = geni_icc_enable(&gi2c->se); 1214 if (ret) 1215 return ret; 1216 1217 ret = clk_prepare_enable(gi2c->core_clk); 1218 if (ret) 1219 goto out_icc_disable; 1220 1221 ret = geni_se_resources_on(&gi2c->se); 1222 if (ret) 1223 goto out_clk_disable; 1224 1225 enable_irq(gi2c->irq); 1226 1227 return 0; 1228 1229 out_clk_disable: 1230 clk_disable_unprepare(gi2c->core_clk); 1231 out_icc_disable: 1232 geni_icc_disable(&gi2c->se); 1233 1234 return ret; 1235 } 1236 1237 static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev) 1238 { 1239 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 1240 int ret; 1241 1242 i2c_mark_adapter_suspended(&gi2c->adap); 1243 1244 ret = pm_runtime_force_suspend(dev); 1245 if (ret) 1246 i2c_mark_adapter_resumed(&gi2c->adap); 1247 1248 return ret; 1249 } 1250 1251 static int __maybe_unused geni_i2c_resume_noirq(struct device *dev) 1252 { 1253 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 1254 int ret; 1255 1256 ret = pm_runtime_force_resume(dev); 1257 if (ret) 1258 return ret; 1259 1260 i2c_mark_adapter_resumed(&gi2c->adap); 1261 return 0; 1262 } 1263 1264 static const struct dev_pm_ops geni_i2c_pm_ops = { 1265 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, geni_i2c_resume_noirq) 1266 SET_RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume, 1267 NULL) 1268 }; 1269 1270 static const struct geni_i2c_desc i2c_master_hub = { 1271 .has_core_clk = true, 1272 .icc_ddr = NULL, 1273 .no_dma_support = true, 1274 .tx_fifo_depth = 16, 1275 }; 1276 1277 static const struct of_device_id geni_i2c_dt_match[] = { 1278 { .compatible = "qcom,geni-i2c" }, 1279 { .compatible = "qcom,geni-i2c-master-hub", .data = &i2c_master_hub }, 1280 {} 1281 }; 1282 MODULE_DEVICE_TABLE(of, geni_i2c_dt_match); 1283 1284 static struct platform_driver geni_i2c_driver = { 1285 .probe = geni_i2c_probe, 1286 .remove = geni_i2c_remove, 1287 .shutdown = geni_i2c_shutdown, 1288 .driver = { 1289 .name = "geni_i2c", 1290 .pm = &geni_i2c_pm_ops, 1291 .of_match_table = geni_i2c_dt_match, 1292 .acpi_match_table = ACPI_PTR(geni_i2c_acpi_match), 1293 }, 1294 }; 1295 1296 module_platform_driver(geni_i2c_driver); 1297 1298 MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores"); 1299 MODULE_LICENSE("GPL v2"); 1300