1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 3 4 #include <linux/acpi.h> 5 #include <linux/clk.h> 6 #include <linux/dma-mapping.h> 7 #include <linux/err.h> 8 #include <linux/i2c.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/qcom-geni-se.h> 16 #include <linux/spinlock.h> 17 18 #define SE_I2C_TX_TRANS_LEN 0x26c 19 #define SE_I2C_RX_TRANS_LEN 0x270 20 #define SE_I2C_SCL_COUNTERS 0x278 21 22 #define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\ 23 M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN) 24 #define SE_I2C_ABORT BIT(1) 25 26 /* M_CMD OP codes for I2C */ 27 #define I2C_WRITE 0x1 28 #define I2C_READ 0x2 29 #define I2C_WRITE_READ 0x3 30 #define I2C_ADDR_ONLY 0x4 31 #define I2C_BUS_CLEAR 0x6 32 #define I2C_STOP_ON_BUS 0x7 33 /* M_CMD params for I2C */ 34 #define PRE_CMD_DELAY BIT(0) 35 #define TIMESTAMP_BEFORE BIT(1) 36 #define STOP_STRETCH BIT(2) 37 #define TIMESTAMP_AFTER BIT(3) 38 #define POST_COMMAND_DELAY BIT(4) 39 #define IGNORE_ADD_NACK BIT(6) 40 #define READ_FINISHED_WITH_ACK BIT(7) 41 #define BYPASS_ADDR_PHASE BIT(8) 42 #define SLV_ADDR_MSK GENMASK(15, 9) 43 #define SLV_ADDR_SHFT 9 44 /* I2C SCL COUNTER fields */ 45 #define HIGH_COUNTER_MSK GENMASK(29, 20) 46 #define HIGH_COUNTER_SHFT 20 47 #define LOW_COUNTER_MSK GENMASK(19, 10) 48 #define LOW_COUNTER_SHFT 10 49 #define CYCLE_COUNTER_MSK GENMASK(9, 0) 50 51 enum geni_i2c_err_code { 52 GP_IRQ0, 53 NACK, 54 GP_IRQ2, 55 BUS_PROTO, 56 ARB_LOST, 57 GP_IRQ5, 58 GENI_OVERRUN, 59 GENI_ILLEGAL_CMD, 60 GENI_ABORT_DONE, 61 GENI_TIMEOUT, 62 }; 63 64 #define DM_I2C_CB_ERR ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \ 65 << 5) 66 67 #define I2C_AUTO_SUSPEND_DELAY 250 68 #define KHZ(freq) (1000 * freq) 69 #define PACKING_BYTES_PW 4 70 71 #define ABORT_TIMEOUT HZ 72 #define XFER_TIMEOUT HZ 73 #define RST_TIMEOUT HZ 74 75 struct geni_i2c_dev { 76 struct geni_se se; 77 u32 tx_wm; 78 int irq; 79 int err; 80 struct i2c_adapter adap; 81 struct completion done; 82 struct i2c_msg *cur; 83 int cur_wr; 84 int cur_rd; 85 spinlock_t lock; 86 u32 clk_freq_out; 87 const struct geni_i2c_clk_fld *clk_fld; 88 int suspended; 89 }; 90 91 struct geni_i2c_err_log { 92 int err; 93 const char *msg; 94 }; 95 96 static const struct geni_i2c_err_log gi2c_log[] = { 97 [GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"}, 98 [NACK] = {-ENXIO, "NACK: slv unresponsive, check its power/reset-ln"}, 99 [GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"}, 100 [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unepxected start/stop"}, 101 [ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"}, 102 [GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"}, 103 [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"}, 104 [GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"}, 105 [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"}, 106 [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"}, 107 }; 108 109 struct geni_i2c_clk_fld { 110 u32 clk_freq_out; 111 u8 clk_div; 112 u8 t_high_cnt; 113 u8 t_low_cnt; 114 u8 t_cycle_cnt; 115 }; 116 117 /* 118 * Hardware uses the underlying formula to calculate time periods of 119 * SCL clock cycle. Firmware uses some additional cycles excluded from the 120 * below formula and it is confirmed that the time periods are within 121 * specification limits. 122 * 123 * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock 124 * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock 125 * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock 126 * clk_freq_out = t / t_cycle 127 * source_clock = 19.2 MHz 128 */ 129 static const struct geni_i2c_clk_fld geni_i2c_clk_map[] = { 130 {KHZ(100), 7, 10, 11, 26}, 131 {KHZ(400), 2, 5, 12, 24}, 132 {KHZ(1000), 1, 3, 9, 18}, 133 }; 134 135 static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c) 136 { 137 int i; 138 const struct geni_i2c_clk_fld *itr = geni_i2c_clk_map; 139 140 for (i = 0; i < ARRAY_SIZE(geni_i2c_clk_map); i++, itr++) { 141 if (itr->clk_freq_out == gi2c->clk_freq_out) { 142 gi2c->clk_fld = itr; 143 return 0; 144 } 145 } 146 return -EINVAL; 147 } 148 149 static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c) 150 { 151 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; 152 u32 val; 153 154 writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL); 155 156 val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN; 157 writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG); 158 159 val = itr->t_high_cnt << HIGH_COUNTER_SHFT; 160 val |= itr->t_low_cnt << LOW_COUNTER_SHFT; 161 val |= itr->t_cycle_cnt; 162 writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS); 163 } 164 165 static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c) 166 { 167 u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0); 168 u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS); 169 u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS); 170 u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS); 171 u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN); 172 u32 rx_st, tx_st; 173 174 if (dma) { 175 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); 176 tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT); 177 } else { 178 rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS); 179 tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS); 180 } 181 dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n", 182 dma, tx_st, rx_st, m_stat); 183 dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n", 184 m_cmd, geni_s, geni_ios); 185 } 186 187 static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err) 188 { 189 if (!gi2c->err) 190 gi2c->err = gi2c_log[err].err; 191 if (gi2c->cur) 192 dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n", 193 gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags); 194 195 if (err != NACK && err != GENI_ABORT_DONE) { 196 dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg); 197 geni_i2c_err_misc(gi2c); 198 } 199 } 200 201 static irqreturn_t geni_i2c_irq(int irq, void *dev) 202 { 203 struct geni_i2c_dev *gi2c = dev; 204 void __iomem *base = gi2c->se.base; 205 int j, p; 206 u32 m_stat; 207 u32 rx_st; 208 u32 dm_tx_st; 209 u32 dm_rx_st; 210 u32 dma; 211 u32 val; 212 struct i2c_msg *cur; 213 214 spin_lock(&gi2c->lock); 215 m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS); 216 rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS); 217 dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT); 218 dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT); 219 dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN); 220 cur = gi2c->cur; 221 222 if (!cur || 223 m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) || 224 dm_rx_st & (DM_I2C_CB_ERR)) { 225 if (m_stat & M_GP_IRQ_1_EN) 226 geni_i2c_err(gi2c, NACK); 227 if (m_stat & M_GP_IRQ_3_EN) 228 geni_i2c_err(gi2c, BUS_PROTO); 229 if (m_stat & M_GP_IRQ_4_EN) 230 geni_i2c_err(gi2c, ARB_LOST); 231 if (m_stat & M_CMD_OVERRUN_EN) 232 geni_i2c_err(gi2c, GENI_OVERRUN); 233 if (m_stat & M_ILLEGAL_CMD_EN) 234 geni_i2c_err(gi2c, GENI_ILLEGAL_CMD); 235 if (m_stat & M_CMD_ABORT_EN) 236 geni_i2c_err(gi2c, GENI_ABORT_DONE); 237 if (m_stat & M_GP_IRQ_0_EN) 238 geni_i2c_err(gi2c, GP_IRQ0); 239 240 /* Disable the TX Watermark interrupt to stop TX */ 241 if (!dma) 242 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG); 243 } else if (dma) { 244 dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n", 245 dm_tx_st, dm_rx_st); 246 } else if (cur->flags & I2C_M_RD && 247 m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) { 248 u32 rxcnt = rx_st & RX_FIFO_WC_MSK; 249 250 for (j = 0; j < rxcnt; j++) { 251 p = 0; 252 val = readl_relaxed(base + SE_GENI_RX_FIFOn); 253 while (gi2c->cur_rd < cur->len && p < sizeof(val)) { 254 cur->buf[gi2c->cur_rd++] = val & 0xff; 255 val >>= 8; 256 p++; 257 } 258 if (gi2c->cur_rd == cur->len) 259 break; 260 } 261 } else if (!(cur->flags & I2C_M_RD) && 262 m_stat & M_TX_FIFO_WATERMARK_EN) { 263 for (j = 0; j < gi2c->tx_wm; j++) { 264 u32 temp; 265 266 val = 0; 267 p = 0; 268 while (gi2c->cur_wr < cur->len && p < sizeof(val)) { 269 temp = cur->buf[gi2c->cur_wr++]; 270 val |= temp << (p * 8); 271 p++; 272 } 273 writel_relaxed(val, base + SE_GENI_TX_FIFOn); 274 /* TX Complete, Disable the TX Watermark interrupt */ 275 if (gi2c->cur_wr == cur->len) { 276 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG); 277 break; 278 } 279 } 280 } 281 282 if (m_stat) 283 writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR); 284 285 if (dma && dm_tx_st) 286 writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR); 287 if (dma && dm_rx_st) 288 writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR); 289 290 /* if this is err with done-bit not set, handle that through timeout. */ 291 if (m_stat & M_CMD_DONE_EN || m_stat & M_CMD_ABORT_EN || 292 dm_tx_st & TX_DMA_DONE || dm_tx_st & TX_RESET_DONE || 293 dm_rx_st & RX_DMA_DONE || dm_rx_st & RX_RESET_DONE) 294 complete(&gi2c->done); 295 296 spin_unlock(&gi2c->lock); 297 298 return IRQ_HANDLED; 299 } 300 301 static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c) 302 { 303 u32 val; 304 unsigned long time_left = ABORT_TIMEOUT; 305 unsigned long flags; 306 307 spin_lock_irqsave(&gi2c->lock, flags); 308 geni_i2c_err(gi2c, GENI_TIMEOUT); 309 gi2c->cur = NULL; 310 geni_se_abort_m_cmd(&gi2c->se); 311 spin_unlock_irqrestore(&gi2c->lock, flags); 312 do { 313 time_left = wait_for_completion_timeout(&gi2c->done, time_left); 314 val = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS); 315 } while (!(val & M_CMD_ABORT_EN) && time_left); 316 317 if (!(val & M_CMD_ABORT_EN)) 318 dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n"); 319 } 320 321 static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c) 322 { 323 u32 val; 324 unsigned long time_left = RST_TIMEOUT; 325 326 writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST); 327 do { 328 time_left = wait_for_completion_timeout(&gi2c->done, time_left); 329 val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); 330 } while (!(val & RX_RESET_DONE) && time_left); 331 332 if (!(val & RX_RESET_DONE)) 333 dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n"); 334 } 335 336 static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c) 337 { 338 u32 val; 339 unsigned long time_left = RST_TIMEOUT; 340 341 writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST); 342 do { 343 time_left = wait_for_completion_timeout(&gi2c->done, time_left); 344 val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT); 345 } while (!(val & TX_RESET_DONE) && time_left); 346 347 if (!(val & TX_RESET_DONE)) 348 dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n"); 349 } 350 351 static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 352 u32 m_param) 353 { 354 dma_addr_t rx_dma; 355 unsigned long time_left; 356 void *dma_buf; 357 struct geni_se *se = &gi2c->se; 358 size_t len = msg->len; 359 360 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32); 361 if (dma_buf) 362 geni_se_select_mode(se, GENI_SE_DMA); 363 else 364 geni_se_select_mode(se, GENI_SE_FIFO); 365 366 writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN); 367 geni_se_setup_m_cmd(se, I2C_READ, m_param); 368 369 if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) { 370 geni_se_select_mode(se, GENI_SE_FIFO); 371 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 372 dma_buf = NULL; 373 } 374 375 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); 376 if (!time_left) 377 geni_i2c_abort_xfer(gi2c); 378 379 gi2c->cur_rd = 0; 380 if (dma_buf) { 381 if (gi2c->err) 382 geni_i2c_rx_fsm_rst(gi2c); 383 geni_se_rx_dma_unprep(se, rx_dma, len); 384 i2c_put_dma_safe_msg_buf(dma_buf, msg, !gi2c->err); 385 } 386 387 return gi2c->err; 388 } 389 390 static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 391 u32 m_param) 392 { 393 dma_addr_t tx_dma; 394 unsigned long time_left; 395 void *dma_buf; 396 struct geni_se *se = &gi2c->se; 397 size_t len = msg->len; 398 399 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32); 400 if (dma_buf) 401 geni_se_select_mode(se, GENI_SE_DMA); 402 else 403 geni_se_select_mode(se, GENI_SE_FIFO); 404 405 writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN); 406 geni_se_setup_m_cmd(se, I2C_WRITE, m_param); 407 408 if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) { 409 geni_se_select_mode(se, GENI_SE_FIFO); 410 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 411 dma_buf = NULL; 412 } 413 414 if (!dma_buf) /* Get FIFO IRQ */ 415 writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG); 416 417 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); 418 if (!time_left) 419 geni_i2c_abort_xfer(gi2c); 420 421 gi2c->cur_wr = 0; 422 if (dma_buf) { 423 if (gi2c->err) 424 geni_i2c_tx_fsm_rst(gi2c); 425 geni_se_tx_dma_unprep(se, tx_dma, len); 426 i2c_put_dma_safe_msg_buf(dma_buf, msg, !gi2c->err); 427 } 428 429 return gi2c->err; 430 } 431 432 static int geni_i2c_xfer(struct i2c_adapter *adap, 433 struct i2c_msg msgs[], 434 int num) 435 { 436 struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap); 437 int i, ret; 438 439 gi2c->err = 0; 440 reinit_completion(&gi2c->done); 441 ret = pm_runtime_get_sync(gi2c->se.dev); 442 if (ret < 0) { 443 dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret); 444 pm_runtime_put_noidle(gi2c->se.dev); 445 /* Set device in suspended since resume failed */ 446 pm_runtime_set_suspended(gi2c->se.dev); 447 return ret; 448 } 449 450 qcom_geni_i2c_conf(gi2c); 451 for (i = 0; i < num; i++) { 452 u32 m_param = i < (num - 1) ? STOP_STRETCH : 0; 453 454 m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK); 455 456 gi2c->cur = &msgs[i]; 457 if (msgs[i].flags & I2C_M_RD) 458 ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param); 459 else 460 ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param); 461 462 if (ret) 463 break; 464 } 465 if (ret == 0) 466 ret = num; 467 468 pm_runtime_mark_last_busy(gi2c->se.dev); 469 pm_runtime_put_autosuspend(gi2c->se.dev); 470 gi2c->cur = NULL; 471 gi2c->err = 0; 472 return ret; 473 } 474 475 static u32 geni_i2c_func(struct i2c_adapter *adap) 476 { 477 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 478 } 479 480 static const struct i2c_algorithm geni_i2c_algo = { 481 .master_xfer = geni_i2c_xfer, 482 .functionality = geni_i2c_func, 483 }; 484 485 #ifdef CONFIG_ACPI 486 static const struct acpi_device_id geni_i2c_acpi_match[] = { 487 { "QCOM0220"}, 488 { }, 489 }; 490 MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match); 491 #endif 492 493 static int geni_i2c_probe(struct platform_device *pdev) 494 { 495 struct geni_i2c_dev *gi2c; 496 struct resource *res; 497 u32 proto, tx_depth; 498 int ret; 499 struct device *dev = &pdev->dev; 500 501 gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL); 502 if (!gi2c) 503 return -ENOMEM; 504 505 gi2c->se.dev = dev; 506 gi2c->se.wrapper = dev_get_drvdata(dev->parent); 507 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 508 gi2c->se.base = devm_ioremap_resource(dev, res); 509 if (IS_ERR(gi2c->se.base)) 510 return PTR_ERR(gi2c->se.base); 511 512 gi2c->se.clk = devm_clk_get(dev, "se"); 513 if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev)) 514 return PTR_ERR(gi2c->se.clk); 515 516 ret = device_property_read_u32(dev, "clock-frequency", 517 &gi2c->clk_freq_out); 518 if (ret) { 519 dev_info(dev, "Bus frequency not specified, default to 100kHz.\n"); 520 gi2c->clk_freq_out = KHZ(100); 521 } 522 523 if (has_acpi_companion(dev)) 524 ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev)); 525 526 gi2c->irq = platform_get_irq(pdev, 0); 527 if (gi2c->irq < 0) 528 return gi2c->irq; 529 530 ret = geni_i2c_clk_map_idx(gi2c); 531 if (ret) { 532 dev_err(dev, "Invalid clk frequency %d Hz: %d\n", 533 gi2c->clk_freq_out, ret); 534 return ret; 535 } 536 537 gi2c->adap.algo = &geni_i2c_algo; 538 init_completion(&gi2c->done); 539 spin_lock_init(&gi2c->lock); 540 platform_set_drvdata(pdev, gi2c); 541 ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, 0, 542 dev_name(dev), gi2c); 543 if (ret) { 544 dev_err(dev, "Request_irq failed:%d: err:%d\n", 545 gi2c->irq, ret); 546 return ret; 547 } 548 /* Disable the interrupt so that the system can enter low-power mode */ 549 disable_irq(gi2c->irq); 550 i2c_set_adapdata(&gi2c->adap, gi2c); 551 gi2c->adap.dev.parent = dev; 552 gi2c->adap.dev.of_node = dev->of_node; 553 strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); 554 555 ret = geni_icc_get(&gi2c->se, "qup-memory"); 556 if (ret) 557 return ret; 558 /* 559 * Set the bus quota for core and cpu to a reasonable value for 560 * register access. 561 * Set quota for DDR based on bus speed. 562 */ 563 gi2c->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; 564 gi2c->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 565 gi2c->se.icc_paths[GENI_TO_DDR].avg_bw = Bps_to_icc(gi2c->clk_freq_out); 566 567 ret = geni_icc_set_bw(&gi2c->se); 568 if (ret) 569 return ret; 570 571 ret = geni_se_resources_on(&gi2c->se); 572 if (ret) { 573 dev_err(dev, "Error turning on resources %d\n", ret); 574 return ret; 575 } 576 proto = geni_se_read_proto(&gi2c->se); 577 tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se); 578 if (proto != GENI_SE_I2C) { 579 dev_err(dev, "Invalid proto %d\n", proto); 580 geni_se_resources_off(&gi2c->se); 581 return -ENXIO; 582 } 583 gi2c->tx_wm = tx_depth - 1; 584 geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth); 585 geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, PACKING_BYTES_PW, 586 true, true, true); 587 ret = geni_se_resources_off(&gi2c->se); 588 if (ret) { 589 dev_err(dev, "Error turning off resources %d\n", ret); 590 return ret; 591 } 592 593 ret = geni_icc_disable(&gi2c->se); 594 if (ret) 595 return ret; 596 597 dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth); 598 599 gi2c->suspended = 1; 600 pm_runtime_set_suspended(gi2c->se.dev); 601 pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY); 602 pm_runtime_use_autosuspend(gi2c->se.dev); 603 pm_runtime_enable(gi2c->se.dev); 604 605 ret = i2c_add_adapter(&gi2c->adap); 606 if (ret) { 607 dev_err(dev, "Error adding i2c adapter %d\n", ret); 608 pm_runtime_disable(gi2c->se.dev); 609 return ret; 610 } 611 612 dev_dbg(dev, "Geni-I2C adaptor successfully added\n"); 613 614 return 0; 615 } 616 617 static int geni_i2c_remove(struct platform_device *pdev) 618 { 619 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev); 620 621 i2c_del_adapter(&gi2c->adap); 622 pm_runtime_disable(gi2c->se.dev); 623 return 0; 624 } 625 626 static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev) 627 { 628 int ret; 629 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 630 631 disable_irq(gi2c->irq); 632 ret = geni_se_resources_off(&gi2c->se); 633 if (ret) { 634 enable_irq(gi2c->irq); 635 return ret; 636 637 } else { 638 gi2c->suspended = 1; 639 } 640 641 return geni_icc_disable(&gi2c->se); 642 } 643 644 static int __maybe_unused geni_i2c_runtime_resume(struct device *dev) 645 { 646 int ret; 647 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 648 649 ret = geni_icc_enable(&gi2c->se); 650 if (ret) 651 return ret; 652 653 ret = geni_se_resources_on(&gi2c->se); 654 if (ret) 655 return ret; 656 657 enable_irq(gi2c->irq); 658 gi2c->suspended = 0; 659 return 0; 660 } 661 662 static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev) 663 { 664 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 665 666 if (!gi2c->suspended) { 667 geni_i2c_runtime_suspend(dev); 668 pm_runtime_disable(dev); 669 pm_runtime_set_suspended(dev); 670 pm_runtime_enable(dev); 671 } 672 return 0; 673 } 674 675 static const struct dev_pm_ops geni_i2c_pm_ops = { 676 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, NULL) 677 SET_RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume, 678 NULL) 679 }; 680 681 static const struct of_device_id geni_i2c_dt_match[] = { 682 { .compatible = "qcom,geni-i2c" }, 683 {} 684 }; 685 MODULE_DEVICE_TABLE(of, geni_i2c_dt_match); 686 687 static struct platform_driver geni_i2c_driver = { 688 .probe = geni_i2c_probe, 689 .remove = geni_i2c_remove, 690 .driver = { 691 .name = "geni_i2c", 692 .pm = &geni_i2c_pm_ops, 693 .of_match_table = geni_i2c_dt_match, 694 .acpi_match_table = ACPI_PTR(geni_i2c_acpi_match), 695 }, 696 }; 697 698 module_platform_driver(geni_i2c_driver); 699 700 MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores"); 701 MODULE_LICENSE("GPL v2"); 702