1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 3 4 #include <linux/acpi.h> 5 #include <linux/clk.h> 6 #include <linux/dmaengine.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/dma/qcom-gpi-dma.h> 9 #include <linux/err.h> 10 #include <linux/i2c.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/soc/qcom/geni-se.h> 18 #include <linux/spinlock.h> 19 #include <linux/units.h> 20 21 #define SE_I2C_TX_TRANS_LEN 0x26c 22 #define SE_I2C_RX_TRANS_LEN 0x270 23 #define SE_I2C_SCL_COUNTERS 0x278 24 25 #define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\ 26 M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN) 27 #define SE_I2C_ABORT BIT(1) 28 29 /* M_CMD OP codes for I2C */ 30 #define I2C_WRITE 0x1 31 #define I2C_READ 0x2 32 #define I2C_WRITE_READ 0x3 33 #define I2C_ADDR_ONLY 0x4 34 #define I2C_BUS_CLEAR 0x6 35 #define I2C_STOP_ON_BUS 0x7 36 /* M_CMD params for I2C */ 37 #define PRE_CMD_DELAY BIT(0) 38 #define TIMESTAMP_BEFORE BIT(1) 39 #define STOP_STRETCH BIT(2) 40 #define TIMESTAMP_AFTER BIT(3) 41 #define POST_COMMAND_DELAY BIT(4) 42 #define IGNORE_ADD_NACK BIT(6) 43 #define READ_FINISHED_WITH_ACK BIT(7) 44 #define BYPASS_ADDR_PHASE BIT(8) 45 #define SLV_ADDR_MSK GENMASK(15, 9) 46 #define SLV_ADDR_SHFT 9 47 /* I2C SCL COUNTER fields */ 48 #define HIGH_COUNTER_MSK GENMASK(29, 20) 49 #define HIGH_COUNTER_SHFT 20 50 #define LOW_COUNTER_MSK GENMASK(19, 10) 51 #define LOW_COUNTER_SHFT 10 52 #define CYCLE_COUNTER_MSK GENMASK(9, 0) 53 54 #define I2C_PACK_TX BIT(0) 55 #define I2C_PACK_RX BIT(1) 56 57 enum geni_i2c_err_code { 58 GP_IRQ0, 59 NACK, 60 GP_IRQ2, 61 BUS_PROTO, 62 ARB_LOST, 63 GP_IRQ5, 64 GENI_OVERRUN, 65 GENI_ILLEGAL_CMD, 66 GENI_ABORT_DONE, 67 GENI_TIMEOUT, 68 }; 69 70 #define DM_I2C_CB_ERR ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \ 71 << 5) 72 73 #define I2C_AUTO_SUSPEND_DELAY 250 74 #define PACKING_BYTES_PW 4 75 76 #define ABORT_TIMEOUT HZ 77 #define XFER_TIMEOUT HZ 78 #define RST_TIMEOUT HZ 79 80 struct geni_i2c_dev { 81 struct geni_se se; 82 u32 tx_wm; 83 int irq; 84 int err; 85 struct i2c_adapter adap; 86 struct completion done; 87 struct i2c_msg *cur; 88 int cur_wr; 89 int cur_rd; 90 spinlock_t lock; 91 struct clk *core_clk; 92 u32 clk_freq_out; 93 const struct geni_i2c_clk_fld *clk_fld; 94 int suspended; 95 void *dma_buf; 96 size_t xfer_len; 97 dma_addr_t dma_addr; 98 struct dma_chan *tx_c; 99 struct dma_chan *rx_c; 100 bool gpi_mode; 101 bool abort_done; 102 }; 103 104 struct geni_i2c_desc { 105 bool has_core_clk; 106 char *icc_ddr; 107 bool no_dma_support; 108 unsigned int tx_fifo_depth; 109 }; 110 111 struct geni_i2c_err_log { 112 int err; 113 const char *msg; 114 }; 115 116 static const struct geni_i2c_err_log gi2c_log[] = { 117 [GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"}, 118 [NACK] = {-ENXIO, "NACK: slv unresponsive, check its power/reset-ln"}, 119 [GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"}, 120 [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unexpected start/stop"}, 121 [ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"}, 122 [GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"}, 123 [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"}, 124 [GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"}, 125 [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"}, 126 [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"}, 127 }; 128 129 struct geni_i2c_clk_fld { 130 u32 clk_freq_out; 131 u8 clk_div; 132 u8 t_high_cnt; 133 u8 t_low_cnt; 134 u8 t_cycle_cnt; 135 }; 136 137 /* 138 * Hardware uses the underlying formula to calculate time periods of 139 * SCL clock cycle. Firmware uses some additional cycles excluded from the 140 * below formula and it is confirmed that the time periods are within 141 * specification limits. 142 * 143 * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock 144 * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock 145 * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock 146 * clk_freq_out = t / t_cycle 147 * source_clock = 19.2 MHz 148 */ 149 static const struct geni_i2c_clk_fld geni_i2c_clk_map_19p2mhz[] = { 150 { I2C_MAX_STANDARD_MODE_FREQ, 7, 10, 12, 26 }, 151 { I2C_MAX_FAST_MODE_FREQ, 2, 5, 11, 22 }, 152 { I2C_MAX_FAST_MODE_PLUS_FREQ, 1, 2, 8, 18 }, 153 {} 154 }; 155 156 /* source_clock = 32 MHz */ 157 static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = { 158 { I2C_MAX_STANDARD_MODE_FREQ, 8, 14, 18, 38 }, 159 { I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 19 }, 160 { I2C_MAX_FAST_MODE_PLUS_FREQ, 2, 3, 5, 15 }, 161 {} 162 }; 163 164 static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c) 165 { 166 const struct geni_i2c_clk_fld *itr; 167 168 if (clk_get_rate(gi2c->se.clk) == 32 * HZ_PER_MHZ) 169 itr = geni_i2c_clk_map_32mhz; 170 else 171 itr = geni_i2c_clk_map_19p2mhz; 172 173 while (itr->clk_freq_out != 0) { 174 if (itr->clk_freq_out == gi2c->clk_freq_out) { 175 gi2c->clk_fld = itr; 176 return 0; 177 } 178 itr++; 179 } 180 return -EINVAL; 181 } 182 183 static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c) 184 { 185 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; 186 u32 val; 187 188 writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL); 189 190 val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN; 191 writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG); 192 193 val = itr->t_high_cnt << HIGH_COUNTER_SHFT; 194 val |= itr->t_low_cnt << LOW_COUNTER_SHFT; 195 val |= itr->t_cycle_cnt; 196 writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS); 197 } 198 199 static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c) 200 { 201 u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0); 202 u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS); 203 u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS); 204 u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS); 205 u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN); 206 u32 rx_st, tx_st; 207 208 if (dma) { 209 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); 210 tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT); 211 } else { 212 rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS); 213 tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS); 214 } 215 dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n", 216 dma, tx_st, rx_st, m_stat); 217 dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n", 218 m_cmd, geni_s, geni_ios); 219 } 220 221 static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err) 222 { 223 if (!gi2c->err) 224 gi2c->err = gi2c_log[err].err; 225 if (gi2c->cur) 226 dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n", 227 gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags); 228 229 switch (err) { 230 case GENI_ABORT_DONE: 231 gi2c->abort_done = true; 232 break; 233 case NACK: 234 case GENI_TIMEOUT: 235 dev_dbg(gi2c->se.dev, "%s\n", gi2c_log[err].msg); 236 break; 237 default: 238 dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg); 239 geni_i2c_err_misc(gi2c); 240 break; 241 } 242 } 243 244 static irqreturn_t geni_i2c_irq(int irq, void *dev) 245 { 246 struct geni_i2c_dev *gi2c = dev; 247 void __iomem *base = gi2c->se.base; 248 int j, p; 249 u32 m_stat; 250 u32 rx_st; 251 u32 dm_tx_st; 252 u32 dm_rx_st; 253 u32 dma; 254 u32 val; 255 struct i2c_msg *cur; 256 257 spin_lock(&gi2c->lock); 258 m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS); 259 rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS); 260 dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT); 261 dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT); 262 dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN); 263 cur = gi2c->cur; 264 265 if (!cur || 266 m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) || 267 dm_rx_st & (DM_I2C_CB_ERR)) { 268 if (m_stat & M_GP_IRQ_1_EN) 269 geni_i2c_err(gi2c, NACK); 270 if (m_stat & M_GP_IRQ_3_EN) 271 geni_i2c_err(gi2c, BUS_PROTO); 272 if (m_stat & M_GP_IRQ_4_EN) 273 geni_i2c_err(gi2c, ARB_LOST); 274 if (m_stat & M_CMD_OVERRUN_EN) 275 geni_i2c_err(gi2c, GENI_OVERRUN); 276 if (m_stat & M_ILLEGAL_CMD_EN) 277 geni_i2c_err(gi2c, GENI_ILLEGAL_CMD); 278 if (m_stat & M_CMD_ABORT_EN) 279 geni_i2c_err(gi2c, GENI_ABORT_DONE); 280 if (m_stat & M_GP_IRQ_0_EN) 281 geni_i2c_err(gi2c, GP_IRQ0); 282 283 /* Disable the TX Watermark interrupt to stop TX */ 284 if (!dma) 285 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG); 286 } else if (dma) { 287 dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n", 288 dm_tx_st, dm_rx_st); 289 } else if (cur->flags & I2C_M_RD && 290 m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) { 291 u32 rxcnt = rx_st & RX_FIFO_WC_MSK; 292 293 for (j = 0; j < rxcnt; j++) { 294 p = 0; 295 val = readl_relaxed(base + SE_GENI_RX_FIFOn); 296 while (gi2c->cur_rd < cur->len && p < sizeof(val)) { 297 cur->buf[gi2c->cur_rd++] = val & 0xff; 298 val >>= 8; 299 p++; 300 } 301 if (gi2c->cur_rd == cur->len) 302 break; 303 } 304 } else if (!(cur->flags & I2C_M_RD) && 305 m_stat & M_TX_FIFO_WATERMARK_EN) { 306 for (j = 0; j < gi2c->tx_wm; j++) { 307 u32 temp; 308 309 val = 0; 310 p = 0; 311 while (gi2c->cur_wr < cur->len && p < sizeof(val)) { 312 temp = cur->buf[gi2c->cur_wr++]; 313 val |= temp << (p * 8); 314 p++; 315 } 316 writel_relaxed(val, base + SE_GENI_TX_FIFOn); 317 /* TX Complete, Disable the TX Watermark interrupt */ 318 if (gi2c->cur_wr == cur->len) { 319 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG); 320 break; 321 } 322 } 323 } 324 325 if (m_stat) 326 writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR); 327 328 if (dma && dm_tx_st) 329 writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR); 330 if (dma && dm_rx_st) 331 writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR); 332 333 /* if this is err with done-bit not set, handle that through timeout. */ 334 if (m_stat & M_CMD_DONE_EN || m_stat & M_CMD_ABORT_EN || 335 dm_tx_st & TX_DMA_DONE || dm_tx_st & TX_RESET_DONE || 336 dm_rx_st & RX_DMA_DONE || dm_rx_st & RX_RESET_DONE) 337 complete(&gi2c->done); 338 339 spin_unlock(&gi2c->lock); 340 341 return IRQ_HANDLED; 342 } 343 344 static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c) 345 { 346 unsigned long time_left = ABORT_TIMEOUT; 347 unsigned long flags; 348 349 spin_lock_irqsave(&gi2c->lock, flags); 350 geni_i2c_err(gi2c, GENI_TIMEOUT); 351 gi2c->cur = NULL; 352 gi2c->abort_done = false; 353 geni_se_abort_m_cmd(&gi2c->se); 354 spin_unlock_irqrestore(&gi2c->lock, flags); 355 356 do { 357 time_left = wait_for_completion_timeout(&gi2c->done, time_left); 358 } while (!gi2c->abort_done && time_left); 359 360 if (!time_left) 361 dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n"); 362 } 363 364 static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c) 365 { 366 u32 val; 367 unsigned long time_left = RST_TIMEOUT; 368 369 writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST); 370 do { 371 time_left = wait_for_completion_timeout(&gi2c->done, time_left); 372 val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); 373 } while (!(val & RX_RESET_DONE) && time_left); 374 375 if (!(val & RX_RESET_DONE)) 376 dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n"); 377 } 378 379 static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c) 380 { 381 u32 val; 382 unsigned long time_left = RST_TIMEOUT; 383 384 writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST); 385 do { 386 time_left = wait_for_completion_timeout(&gi2c->done, time_left); 387 val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT); 388 } while (!(val & TX_RESET_DONE) && time_left); 389 390 if (!(val & TX_RESET_DONE)) 391 dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n"); 392 } 393 394 static void geni_i2c_rx_msg_cleanup(struct geni_i2c_dev *gi2c, 395 struct i2c_msg *cur) 396 { 397 gi2c->cur_rd = 0; 398 if (gi2c->dma_buf) { 399 if (gi2c->err) 400 geni_i2c_rx_fsm_rst(gi2c); 401 geni_se_rx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len); 402 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err); 403 } 404 } 405 406 static void geni_i2c_tx_msg_cleanup(struct geni_i2c_dev *gi2c, 407 struct i2c_msg *cur) 408 { 409 gi2c->cur_wr = 0; 410 if (gi2c->dma_buf) { 411 if (gi2c->err) 412 geni_i2c_tx_fsm_rst(gi2c); 413 geni_se_tx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len); 414 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err); 415 } 416 } 417 418 static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 419 u32 m_param) 420 { 421 dma_addr_t rx_dma = 0; 422 unsigned long time_left; 423 void *dma_buf; 424 struct geni_se *se = &gi2c->se; 425 size_t len = msg->len; 426 struct i2c_msg *cur; 427 428 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32); 429 if (dma_buf) 430 geni_se_select_mode(se, GENI_SE_DMA); 431 else 432 geni_se_select_mode(se, GENI_SE_FIFO); 433 434 writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN); 435 geni_se_setup_m_cmd(se, I2C_READ, m_param); 436 437 if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) { 438 geni_se_select_mode(se, GENI_SE_FIFO); 439 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 440 dma_buf = NULL; 441 } else { 442 gi2c->xfer_len = len; 443 gi2c->dma_addr = rx_dma; 444 gi2c->dma_buf = dma_buf; 445 } 446 447 cur = gi2c->cur; 448 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); 449 if (!time_left) 450 geni_i2c_abort_xfer(gi2c); 451 452 geni_i2c_rx_msg_cleanup(gi2c, cur); 453 454 return gi2c->err; 455 } 456 457 static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 458 u32 m_param) 459 { 460 dma_addr_t tx_dma = 0; 461 unsigned long time_left; 462 void *dma_buf; 463 struct geni_se *se = &gi2c->se; 464 size_t len = msg->len; 465 struct i2c_msg *cur; 466 467 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32); 468 if (dma_buf) 469 geni_se_select_mode(se, GENI_SE_DMA); 470 else 471 geni_se_select_mode(se, GENI_SE_FIFO); 472 473 writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN); 474 geni_se_setup_m_cmd(se, I2C_WRITE, m_param); 475 476 if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) { 477 geni_se_select_mode(se, GENI_SE_FIFO); 478 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 479 dma_buf = NULL; 480 } else { 481 gi2c->xfer_len = len; 482 gi2c->dma_addr = tx_dma; 483 gi2c->dma_buf = dma_buf; 484 } 485 486 if (!dma_buf) /* Get FIFO IRQ */ 487 writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG); 488 489 cur = gi2c->cur; 490 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); 491 if (!time_left) 492 geni_i2c_abort_xfer(gi2c); 493 494 geni_i2c_tx_msg_cleanup(gi2c, cur); 495 496 return gi2c->err; 497 } 498 499 static void i2c_gpi_cb_result(void *cb, const struct dmaengine_result *result) 500 { 501 struct geni_i2c_dev *gi2c = cb; 502 503 if (result->result != DMA_TRANS_NOERROR) { 504 dev_err(gi2c->se.dev, "DMA txn failed:%d\n", result->result); 505 gi2c->err = -EIO; 506 } else if (result->residue) { 507 dev_dbg(gi2c->se.dev, "DMA xfer has pending: %d\n", result->residue); 508 } 509 510 complete(&gi2c->done); 511 } 512 513 static void geni_i2c_gpi_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 514 void *tx_buf, dma_addr_t tx_addr, 515 void *rx_buf, dma_addr_t rx_addr) 516 { 517 if (tx_buf) { 518 dma_unmap_single(gi2c->se.dev->parent, tx_addr, msg->len, DMA_TO_DEVICE); 519 i2c_put_dma_safe_msg_buf(tx_buf, msg, !gi2c->err); 520 } 521 522 if (rx_buf) { 523 dma_unmap_single(gi2c->se.dev->parent, rx_addr, msg->len, DMA_FROM_DEVICE); 524 i2c_put_dma_safe_msg_buf(rx_buf, msg, !gi2c->err); 525 } 526 } 527 528 static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 529 struct dma_slave_config *config, dma_addr_t *dma_addr_p, 530 void **buf, unsigned int op, struct dma_chan *dma_chan) 531 { 532 struct gpi_i2c_config *peripheral; 533 unsigned int flags; 534 void *dma_buf; 535 dma_addr_t addr; 536 enum dma_data_direction map_dirn; 537 enum dma_transfer_direction dma_dirn; 538 struct dma_async_tx_descriptor *desc; 539 int ret; 540 541 peripheral = config->peripheral_config; 542 543 dma_buf = i2c_get_dma_safe_msg_buf(msg, 1); 544 if (!dma_buf) 545 return -ENOMEM; 546 547 if (op == I2C_WRITE) 548 map_dirn = DMA_TO_DEVICE; 549 else 550 map_dirn = DMA_FROM_DEVICE; 551 552 addr = dma_map_single(gi2c->se.dev->parent, dma_buf, msg->len, map_dirn); 553 if (dma_mapping_error(gi2c->se.dev->parent, addr)) { 554 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 555 return -ENOMEM; 556 } 557 558 /* set the length as message for rx txn */ 559 peripheral->rx_len = msg->len; 560 peripheral->op = op; 561 562 ret = dmaengine_slave_config(dma_chan, config); 563 if (ret) { 564 dev_err(gi2c->se.dev, "dma config error: %d for op:%d\n", ret, op); 565 goto err_config; 566 } 567 568 peripheral->set_config = 0; 569 peripheral->multi_msg = true; 570 flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK; 571 572 if (op == I2C_WRITE) 573 dma_dirn = DMA_MEM_TO_DEV; 574 else 575 dma_dirn = DMA_DEV_TO_MEM; 576 577 desc = dmaengine_prep_slave_single(dma_chan, addr, msg->len, dma_dirn, flags); 578 if (!desc) { 579 dev_err(gi2c->se.dev, "prep_slave_sg failed\n"); 580 ret = -EIO; 581 goto err_config; 582 } 583 584 desc->callback_result = i2c_gpi_cb_result; 585 desc->callback_param = gi2c; 586 587 dmaengine_submit(desc); 588 *buf = dma_buf; 589 *dma_addr_p = addr; 590 591 return 0; 592 593 err_config: 594 dma_unmap_single(gi2c->se.dev->parent, addr, msg->len, map_dirn); 595 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 596 return ret; 597 } 598 599 static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], int num) 600 { 601 struct dma_slave_config config = {}; 602 struct gpi_i2c_config peripheral = {}; 603 int i, ret = 0; 604 unsigned long time_left; 605 dma_addr_t tx_addr, rx_addr; 606 void *tx_buf = NULL, *rx_buf = NULL; 607 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; 608 609 config.peripheral_config = &peripheral; 610 config.peripheral_size = sizeof(peripheral); 611 612 peripheral.pack_enable = I2C_PACK_TX | I2C_PACK_RX; 613 peripheral.cycle_count = itr->t_cycle_cnt; 614 peripheral.high_count = itr->t_high_cnt; 615 peripheral.low_count = itr->t_low_cnt; 616 peripheral.clk_div = itr->clk_div; 617 peripheral.set_config = 1; 618 peripheral.multi_msg = false; 619 620 for (i = 0; i < num; i++) { 621 gi2c->cur = &msgs[i]; 622 gi2c->err = 0; 623 dev_dbg(gi2c->se.dev, "msg[%d].len:%d\n", i, gi2c->cur->len); 624 625 peripheral.stretch = 0; 626 if (i < num - 1) 627 peripheral.stretch = 1; 628 629 peripheral.addr = msgs[i].addr; 630 631 ret = geni_i2c_gpi(gi2c, &msgs[i], &config, 632 &tx_addr, &tx_buf, I2C_WRITE, gi2c->tx_c); 633 if (ret) 634 goto err; 635 636 if (msgs[i].flags & I2C_M_RD) { 637 ret = geni_i2c_gpi(gi2c, &msgs[i], &config, 638 &rx_addr, &rx_buf, I2C_READ, gi2c->rx_c); 639 if (ret) 640 goto err; 641 642 dma_async_issue_pending(gi2c->rx_c); 643 } 644 645 dma_async_issue_pending(gi2c->tx_c); 646 647 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); 648 if (!time_left) 649 gi2c->err = -ETIMEDOUT; 650 651 if (gi2c->err) { 652 ret = gi2c->err; 653 goto err; 654 } 655 656 geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); 657 } 658 659 return num; 660 661 err: 662 dev_err(gi2c->se.dev, "GPI transfer failed: %d\n", ret); 663 dmaengine_terminate_sync(gi2c->rx_c); 664 dmaengine_terminate_sync(gi2c->tx_c); 665 geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); 666 return ret; 667 } 668 669 static int geni_i2c_fifo_xfer(struct geni_i2c_dev *gi2c, 670 struct i2c_msg msgs[], int num) 671 { 672 int i, ret = 0; 673 674 for (i = 0; i < num; i++) { 675 u32 m_param = i < (num - 1) ? STOP_STRETCH : 0; 676 677 m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK); 678 679 gi2c->cur = &msgs[i]; 680 if (msgs[i].flags & I2C_M_RD) 681 ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param); 682 else 683 ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param); 684 685 if (ret) 686 return ret; 687 } 688 689 return num; 690 } 691 692 static int geni_i2c_xfer(struct i2c_adapter *adap, 693 struct i2c_msg msgs[], 694 int num) 695 { 696 struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap); 697 int ret; 698 699 gi2c->err = 0; 700 reinit_completion(&gi2c->done); 701 ret = pm_runtime_get_sync(gi2c->se.dev); 702 if (ret < 0) { 703 dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret); 704 pm_runtime_put_noidle(gi2c->se.dev); 705 /* Set device in suspended since resume failed */ 706 pm_runtime_set_suspended(gi2c->se.dev); 707 return ret; 708 } 709 710 qcom_geni_i2c_conf(gi2c); 711 712 if (gi2c->gpi_mode) 713 ret = geni_i2c_gpi_xfer(gi2c, msgs, num); 714 else 715 ret = geni_i2c_fifo_xfer(gi2c, msgs, num); 716 717 pm_runtime_mark_last_busy(gi2c->se.dev); 718 pm_runtime_put_autosuspend(gi2c->se.dev); 719 gi2c->cur = NULL; 720 gi2c->err = 0; 721 return ret; 722 } 723 724 static u32 geni_i2c_func(struct i2c_adapter *adap) 725 { 726 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 727 } 728 729 static const struct i2c_algorithm geni_i2c_algo = { 730 .xfer = geni_i2c_xfer, 731 .functionality = geni_i2c_func, 732 }; 733 734 #ifdef CONFIG_ACPI 735 static const struct acpi_device_id geni_i2c_acpi_match[] = { 736 { "QCOM0220"}, 737 { "QCOM0411" }, 738 { } 739 }; 740 MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match); 741 #endif 742 743 static void release_gpi_dma(struct geni_i2c_dev *gi2c) 744 { 745 if (gi2c->rx_c) 746 dma_release_channel(gi2c->rx_c); 747 748 if (gi2c->tx_c) 749 dma_release_channel(gi2c->tx_c); 750 } 751 752 static int setup_gpi_dma(struct geni_i2c_dev *gi2c) 753 { 754 int ret; 755 756 geni_se_select_mode(&gi2c->se, GENI_GPI_DMA); 757 gi2c->tx_c = dma_request_chan(gi2c->se.dev, "tx"); 758 if (IS_ERR(gi2c->tx_c)) { 759 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->tx_c), 760 "Failed to get tx DMA ch\n"); 761 goto err_tx; 762 } 763 764 gi2c->rx_c = dma_request_chan(gi2c->se.dev, "rx"); 765 if (IS_ERR(gi2c->rx_c)) { 766 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->rx_c), 767 "Failed to get rx DMA ch\n"); 768 goto err_rx; 769 } 770 771 dev_dbg(gi2c->se.dev, "Grabbed GPI dma channels\n"); 772 return 0; 773 774 err_rx: 775 dma_release_channel(gi2c->tx_c); 776 err_tx: 777 return ret; 778 } 779 780 static int geni_i2c_probe(struct platform_device *pdev) 781 { 782 struct geni_i2c_dev *gi2c; 783 u32 proto, tx_depth, fifo_disable; 784 int ret; 785 struct device *dev = &pdev->dev; 786 const struct geni_i2c_desc *desc = NULL; 787 788 gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL); 789 if (!gi2c) 790 return -ENOMEM; 791 792 gi2c->se.dev = dev; 793 gi2c->se.wrapper = dev_get_drvdata(dev->parent); 794 gi2c->se.base = devm_platform_ioremap_resource(pdev, 0); 795 if (IS_ERR(gi2c->se.base)) 796 return PTR_ERR(gi2c->se.base); 797 798 desc = device_get_match_data(&pdev->dev); 799 800 if (desc && desc->has_core_clk) { 801 gi2c->core_clk = devm_clk_get(dev, "core"); 802 if (IS_ERR(gi2c->core_clk)) 803 return PTR_ERR(gi2c->core_clk); 804 } 805 806 gi2c->se.clk = devm_clk_get(dev, "se"); 807 if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev)) 808 return PTR_ERR(gi2c->se.clk); 809 810 ret = device_property_read_u32(dev, "clock-frequency", 811 &gi2c->clk_freq_out); 812 if (ret) { 813 dev_info(dev, "Bus frequency not specified, default to 100kHz.\n"); 814 gi2c->clk_freq_out = I2C_MAX_STANDARD_MODE_FREQ; 815 } 816 817 if (has_acpi_companion(dev)) 818 ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev)); 819 820 gi2c->irq = platform_get_irq(pdev, 0); 821 if (gi2c->irq < 0) 822 return gi2c->irq; 823 824 ret = geni_i2c_clk_map_idx(gi2c); 825 if (ret) 826 return dev_err_probe(dev, ret, "Invalid clk frequency %d Hz\n", 827 gi2c->clk_freq_out); 828 829 gi2c->adap.algo = &geni_i2c_algo; 830 init_completion(&gi2c->done); 831 spin_lock_init(&gi2c->lock); 832 platform_set_drvdata(pdev, gi2c); 833 834 /* Keep interrupts disabled initially to allow for low-power modes */ 835 ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, IRQF_NO_AUTOEN, 836 dev_name(dev), gi2c); 837 if (ret) 838 return dev_err_probe(dev, ret, 839 "Request_irq failed: %d\n", gi2c->irq); 840 841 i2c_set_adapdata(&gi2c->adap, gi2c); 842 gi2c->adap.dev.parent = dev; 843 gi2c->adap.dev.of_node = dev->of_node; 844 strscpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); 845 846 ret = geni_icc_get(&gi2c->se, desc ? desc->icc_ddr : "qup-memory"); 847 if (ret) 848 return ret; 849 /* 850 * Set the bus quota for core and cpu to a reasonable value for 851 * register access. 852 * Set quota for DDR based on bus speed. 853 */ 854 gi2c->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; 855 gi2c->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 856 if (!desc || desc->icc_ddr) 857 gi2c->se.icc_paths[GENI_TO_DDR].avg_bw = Bps_to_icc(gi2c->clk_freq_out); 858 859 ret = geni_icc_set_bw(&gi2c->se); 860 if (ret) 861 return ret; 862 863 ret = clk_prepare_enable(gi2c->core_clk); 864 if (ret) 865 return ret; 866 867 ret = geni_se_resources_on(&gi2c->se); 868 if (ret) { 869 dev_err_probe(dev, ret, "Error turning on resources\n"); 870 goto err_clk; 871 } 872 proto = geni_se_read_proto(&gi2c->se); 873 if (proto != GENI_SE_I2C) { 874 ret = dev_err_probe(dev, -ENXIO, "Invalid proto %d\n", proto); 875 goto err_resources; 876 } 877 878 if (desc && desc->no_dma_support) 879 fifo_disable = false; 880 else 881 fifo_disable = readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; 882 883 if (fifo_disable) { 884 /* FIFO is disabled, so we can only use GPI DMA */ 885 gi2c->gpi_mode = true; 886 ret = setup_gpi_dma(gi2c); 887 if (ret) 888 goto err_resources; 889 890 dev_dbg(dev, "Using GPI DMA mode for I2C\n"); 891 } else { 892 gi2c->gpi_mode = false; 893 tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se); 894 895 /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */ 896 if (!tx_depth && desc) 897 tx_depth = desc->tx_fifo_depth; 898 899 if (!tx_depth) { 900 ret = dev_err_probe(dev, -EINVAL, 901 "Invalid TX FIFO depth\n"); 902 goto err_resources; 903 } 904 905 gi2c->tx_wm = tx_depth - 1; 906 geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth); 907 geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, 908 PACKING_BYTES_PW, true, true, true); 909 910 dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth); 911 } 912 913 clk_disable_unprepare(gi2c->core_clk); 914 ret = geni_se_resources_off(&gi2c->se); 915 if (ret) { 916 dev_err_probe(dev, ret, "Error turning off resources\n"); 917 goto err_dma; 918 } 919 920 ret = geni_icc_disable(&gi2c->se); 921 if (ret) 922 goto err_dma; 923 924 gi2c->suspended = 1; 925 pm_runtime_set_suspended(gi2c->se.dev); 926 pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY); 927 pm_runtime_use_autosuspend(gi2c->se.dev); 928 pm_runtime_enable(gi2c->se.dev); 929 930 ret = i2c_add_adapter(&gi2c->adap); 931 if (ret) { 932 dev_err_probe(dev, ret, "Error adding i2c adapter\n"); 933 pm_runtime_disable(gi2c->se.dev); 934 goto err_dma; 935 } 936 937 dev_dbg(dev, "Geni-I2C adaptor successfully added\n"); 938 939 return ret; 940 941 err_resources: 942 geni_se_resources_off(&gi2c->se); 943 err_clk: 944 clk_disable_unprepare(gi2c->core_clk); 945 946 return ret; 947 948 err_dma: 949 release_gpi_dma(gi2c); 950 951 return ret; 952 } 953 954 static void geni_i2c_remove(struct platform_device *pdev) 955 { 956 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev); 957 958 i2c_del_adapter(&gi2c->adap); 959 release_gpi_dma(gi2c); 960 pm_runtime_disable(gi2c->se.dev); 961 } 962 963 static void geni_i2c_shutdown(struct platform_device *pdev) 964 { 965 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev); 966 967 /* Make client i2c transfers start failing */ 968 i2c_mark_adapter_suspended(&gi2c->adap); 969 } 970 971 static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev) 972 { 973 int ret; 974 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 975 976 disable_irq(gi2c->irq); 977 ret = geni_se_resources_off(&gi2c->se); 978 if (ret) { 979 enable_irq(gi2c->irq); 980 return ret; 981 982 } else { 983 gi2c->suspended = 1; 984 } 985 986 clk_disable_unprepare(gi2c->core_clk); 987 988 return geni_icc_disable(&gi2c->se); 989 } 990 991 static int __maybe_unused geni_i2c_runtime_resume(struct device *dev) 992 { 993 int ret; 994 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 995 996 ret = geni_icc_enable(&gi2c->se); 997 if (ret) 998 return ret; 999 1000 ret = clk_prepare_enable(gi2c->core_clk); 1001 if (ret) 1002 goto out_icc_disable; 1003 1004 ret = geni_se_resources_on(&gi2c->se); 1005 if (ret) 1006 goto out_clk_disable; 1007 1008 enable_irq(gi2c->irq); 1009 gi2c->suspended = 0; 1010 1011 return 0; 1012 1013 out_clk_disable: 1014 clk_disable_unprepare(gi2c->core_clk); 1015 out_icc_disable: 1016 geni_icc_disable(&gi2c->se); 1017 1018 return ret; 1019 } 1020 1021 static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev) 1022 { 1023 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 1024 1025 i2c_mark_adapter_suspended(&gi2c->adap); 1026 1027 if (!gi2c->suspended) { 1028 geni_i2c_runtime_suspend(dev); 1029 pm_runtime_disable(dev); 1030 pm_runtime_set_suspended(dev); 1031 pm_runtime_enable(dev); 1032 } 1033 return 0; 1034 } 1035 1036 static int __maybe_unused geni_i2c_resume_noirq(struct device *dev) 1037 { 1038 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 1039 1040 i2c_mark_adapter_resumed(&gi2c->adap); 1041 return 0; 1042 } 1043 1044 static const struct dev_pm_ops geni_i2c_pm_ops = { 1045 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, geni_i2c_resume_noirq) 1046 SET_RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume, 1047 NULL) 1048 }; 1049 1050 static const struct geni_i2c_desc i2c_master_hub = { 1051 .has_core_clk = true, 1052 .icc_ddr = NULL, 1053 .no_dma_support = true, 1054 .tx_fifo_depth = 16, 1055 }; 1056 1057 static const struct of_device_id geni_i2c_dt_match[] = { 1058 { .compatible = "qcom,geni-i2c" }, 1059 { .compatible = "qcom,geni-i2c-master-hub", .data = &i2c_master_hub }, 1060 {} 1061 }; 1062 MODULE_DEVICE_TABLE(of, geni_i2c_dt_match); 1063 1064 static struct platform_driver geni_i2c_driver = { 1065 .probe = geni_i2c_probe, 1066 .remove = geni_i2c_remove, 1067 .shutdown = geni_i2c_shutdown, 1068 .driver = { 1069 .name = "geni_i2c", 1070 .pm = &geni_i2c_pm_ops, 1071 .of_match_table = geni_i2c_dt_match, 1072 .acpi_match_table = ACPI_PTR(geni_i2c_acpi_match), 1073 }, 1074 }; 1075 1076 module_platform_driver(geni_i2c_driver); 1077 1078 MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores"); 1079 MODULE_LICENSE("GPL v2"); 1080