1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. 3 // Copyright (c) 2017-2022 Linaro Limited. 4 5 #include <linux/clk.h> 6 #include <linux/completion.h> 7 #include <linux/i2c.h> 8 #include <linux/io.h> 9 #include <linux/interrupt.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 15 #define CCI_HW_VERSION 0x0 16 #define CCI_RESET_CMD 0x004 17 #define CCI_RESET_CMD_MASK 0x0f73f3f7 18 #define CCI_RESET_CMD_M0_MASK 0x000003f1 19 #define CCI_RESET_CMD_M1_MASK 0x0003f001 20 #define CCI_QUEUE_START 0x008 21 #define CCI_HALT_REQ 0x034 22 #define CCI_HALT_REQ_I2C_M0_Q0Q1 BIT(0) 23 #define CCI_HALT_REQ_I2C_M1_Q0Q1 BIT(1) 24 25 #define CCI_I2C_Mm_SCL_CTL(m) (0x100 + 0x100 * (m)) 26 #define CCI_I2C_Mm_SDA_CTL_0(m) (0x104 + 0x100 * (m)) 27 #define CCI_I2C_Mm_SDA_CTL_1(m) (0x108 + 0x100 * (m)) 28 #define CCI_I2C_Mm_SDA_CTL_2(m) (0x10c + 0x100 * (m)) 29 #define CCI_I2C_Mm_MISC_CTL(m) (0x110 + 0x100 * (m)) 30 31 #define CCI_I2C_Mm_READ_DATA(m) (0x118 + 0x100 * (m)) 32 #define CCI_I2C_Mm_READ_BUF_LEVEL(m) (0x11c + 0x100 * (m)) 33 #define CCI_I2C_Mm_Qn_EXEC_WORD_CNT(m, n) (0x300 + 0x200 * (m) + 0x100 * (n)) 34 #define CCI_I2C_Mm_Qn_CUR_WORD_CNT(m, n) (0x304 + 0x200 * (m) + 0x100 * (n)) 35 #define CCI_I2C_Mm_Qn_CUR_CMD(m, n) (0x308 + 0x200 * (m) + 0x100 * (n)) 36 #define CCI_I2C_Mm_Qn_REPORT_STATUS(m, n) (0x30c + 0x200 * (m) + 0x100 * (n)) 37 #define CCI_I2C_Mm_Qn_LOAD_DATA(m, n) (0x310 + 0x200 * (m) + 0x100 * (n)) 38 39 #define CCI_IRQ_GLOBAL_CLEAR_CMD 0xc00 40 #define CCI_IRQ_MASK_0 0xc04 41 #define CCI_IRQ_MASK_0_I2C_M0_RD_DONE BIT(0) 42 #define CCI_IRQ_MASK_0_I2C_M0_Q0_REPORT BIT(4) 43 #define CCI_IRQ_MASK_0_I2C_M0_Q1_REPORT BIT(8) 44 #define CCI_IRQ_MASK_0_I2C_M1_RD_DONE BIT(12) 45 #define CCI_IRQ_MASK_0_I2C_M1_Q0_REPORT BIT(16) 46 #define CCI_IRQ_MASK_0_I2C_M1_Q1_REPORT BIT(20) 47 #define CCI_IRQ_MASK_0_RST_DONE_ACK BIT(24) 48 #define CCI_IRQ_MASK_0_I2C_M0_Q0Q1_HALT_ACK BIT(25) 49 #define CCI_IRQ_MASK_0_I2C_M1_Q0Q1_HALT_ACK BIT(26) 50 #define CCI_IRQ_MASK_0_I2C_M0_ERROR 0x18000ee6 51 #define CCI_IRQ_MASK_0_I2C_M1_ERROR 0x60ee6000 52 #define CCI_IRQ_CLEAR_0 0xc08 53 #define CCI_IRQ_STATUS_0 0xc0c 54 #define CCI_IRQ_STATUS_0_I2C_M0_RD_DONE BIT(0) 55 #define CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT BIT(4) 56 #define CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT BIT(8) 57 #define CCI_IRQ_STATUS_0_I2C_M1_RD_DONE BIT(12) 58 #define CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT BIT(16) 59 #define CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT BIT(20) 60 #define CCI_IRQ_STATUS_0_RST_DONE_ACK BIT(24) 61 #define CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK BIT(25) 62 #define CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK BIT(26) 63 #define CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERR BIT(27) 64 #define CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERR BIT(28) 65 #define CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERR BIT(29) 66 #define CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERR BIT(30) 67 #define CCI_IRQ_STATUS_0_I2C_M0_ERROR 0x18000ee6 68 #define CCI_IRQ_STATUS_0_I2C_M1_ERROR 0x60ee6000 69 70 #define CCI_TIMEOUT (msecs_to_jiffies(100)) 71 #define NUM_MASTERS 2 72 #define NUM_QUEUES 2 73 74 #define CCI_I2C_SET_PARAM 1 75 #define CCI_I2C_REPORT 8 76 #define CCI_I2C_WRITE 9 77 #define CCI_I2C_READ 10 78 79 #define CCI_I2C_REPORT_IRQ_EN BIT(8) 80 81 enum { 82 I2C_MODE_STANDARD, 83 I2C_MODE_FAST, 84 I2C_MODE_FAST_PLUS, 85 }; 86 87 enum cci_i2c_queue_t { 88 QUEUE_0, 89 QUEUE_1 90 }; 91 92 struct hw_params { 93 u16 thigh; /* HIGH period of the SCL clock in clock ticks */ 94 u16 tlow; /* LOW period of the SCL clock */ 95 u16 tsu_sto; /* set-up time for STOP condition */ 96 u16 tsu_sta; /* set-up time for a repeated START condition */ 97 u16 thd_dat; /* data hold time */ 98 u16 thd_sta; /* hold time (repeated) START condition */ 99 u16 tbuf; /* bus free time between a STOP and START condition */ 100 u8 scl_stretch_en; 101 u16 trdhld; 102 u16 tsp; /* pulse width of spikes suppressed by the input filter */ 103 }; 104 105 struct cci; 106 107 struct cci_master { 108 struct i2c_adapter adap; 109 u16 master; 110 u8 mode; 111 int status; 112 struct completion irq_complete; 113 struct cci *cci; 114 }; 115 116 struct cci_data { 117 unsigned int num_masters; 118 struct i2c_adapter_quirks quirks; 119 u16 queue_size[NUM_QUEUES]; 120 struct hw_params params[3]; 121 }; 122 123 struct cci { 124 struct device *dev; 125 void __iomem *base; 126 unsigned int irq; 127 const struct cci_data *data; 128 struct clk_bulk_data *clocks; 129 int nclocks; 130 struct cci_master master[NUM_MASTERS]; 131 }; 132 133 static irqreturn_t cci_isr(int irq, void *dev) 134 { 135 struct cci *cci = dev; 136 u32 val, reset = 0; 137 int ret = IRQ_NONE; 138 139 val = readl(cci->base + CCI_IRQ_STATUS_0); 140 writel(val, cci->base + CCI_IRQ_CLEAR_0); 141 writel(0x1, cci->base + CCI_IRQ_GLOBAL_CLEAR_CMD); 142 143 if (val & CCI_IRQ_STATUS_0_RST_DONE_ACK) { 144 complete(&cci->master[0].irq_complete); 145 if (cci->master[1].master) 146 complete(&cci->master[1].irq_complete); 147 ret = IRQ_HANDLED; 148 } 149 150 if (val & CCI_IRQ_STATUS_0_I2C_M0_RD_DONE || 151 val & CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT || 152 val & CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT) { 153 cci->master[0].status = 0; 154 complete(&cci->master[0].irq_complete); 155 ret = IRQ_HANDLED; 156 } 157 158 if (val & CCI_IRQ_STATUS_0_I2C_M1_RD_DONE || 159 val & CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT || 160 val & CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT) { 161 cci->master[1].status = 0; 162 complete(&cci->master[1].irq_complete); 163 ret = IRQ_HANDLED; 164 } 165 166 if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK)) { 167 reset = CCI_RESET_CMD_M0_MASK; 168 ret = IRQ_HANDLED; 169 } 170 171 if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK)) { 172 reset = CCI_RESET_CMD_M1_MASK; 173 ret = IRQ_HANDLED; 174 } 175 176 if (unlikely(reset)) 177 writel(reset, cci->base + CCI_RESET_CMD); 178 179 if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M0_ERROR)) { 180 if (val & CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERR || 181 val & CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERR) 182 cci->master[0].status = -ENXIO; 183 else 184 cci->master[0].status = -EIO; 185 186 writel(CCI_HALT_REQ_I2C_M0_Q0Q1, cci->base + CCI_HALT_REQ); 187 ret = IRQ_HANDLED; 188 } 189 190 if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M1_ERROR)) { 191 if (val & CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERR || 192 val & CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERR) 193 cci->master[1].status = -ENXIO; 194 else 195 cci->master[1].status = -EIO; 196 197 writel(CCI_HALT_REQ_I2C_M1_Q0Q1, cci->base + CCI_HALT_REQ); 198 ret = IRQ_HANDLED; 199 } 200 201 return ret; 202 } 203 204 static int cci_halt(struct cci *cci, u8 master_num) 205 { 206 struct cci_master *master; 207 u32 val; 208 209 if (master_num >= cci->data->num_masters) { 210 dev_err(cci->dev, "Unsupported master idx (%u)\n", master_num); 211 return -EINVAL; 212 } 213 214 val = BIT(master_num); 215 master = &cci->master[master_num]; 216 217 reinit_completion(&master->irq_complete); 218 writel(val, cci->base + CCI_HALT_REQ); 219 220 if (!wait_for_completion_timeout(&master->irq_complete, CCI_TIMEOUT)) { 221 dev_err(cci->dev, "CCI halt timeout\n"); 222 return -ETIMEDOUT; 223 } 224 225 return 0; 226 } 227 228 static void cci_init(struct cci *cci) 229 { 230 u32 val = CCI_IRQ_MASK_0_I2C_M0_RD_DONE | 231 CCI_IRQ_MASK_0_I2C_M0_Q0_REPORT | 232 CCI_IRQ_MASK_0_I2C_M0_Q1_REPORT | 233 CCI_IRQ_MASK_0_I2C_M1_RD_DONE | 234 CCI_IRQ_MASK_0_I2C_M1_Q0_REPORT | 235 CCI_IRQ_MASK_0_I2C_M1_Q1_REPORT | 236 CCI_IRQ_MASK_0_RST_DONE_ACK | 237 CCI_IRQ_MASK_0_I2C_M0_Q0Q1_HALT_ACK | 238 CCI_IRQ_MASK_0_I2C_M1_Q0Q1_HALT_ACK | 239 CCI_IRQ_MASK_0_I2C_M0_ERROR | 240 CCI_IRQ_MASK_0_I2C_M1_ERROR; 241 int i; 242 243 writel(val, cci->base + CCI_IRQ_MASK_0); 244 245 for (i = 0; i < cci->data->num_masters; i++) { 246 int mode = cci->master[i].mode; 247 const struct hw_params *hw; 248 249 if (!cci->master[i].cci) 250 continue; 251 252 hw = &cci->data->params[mode]; 253 254 val = hw->thigh << 16 | hw->tlow; 255 writel(val, cci->base + CCI_I2C_Mm_SCL_CTL(i)); 256 257 val = hw->tsu_sto << 16 | hw->tsu_sta; 258 writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_0(i)); 259 260 val = hw->thd_dat << 16 | hw->thd_sta; 261 writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_1(i)); 262 263 val = hw->tbuf; 264 writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_2(i)); 265 266 val = hw->scl_stretch_en << 8 | hw->trdhld << 4 | hw->tsp; 267 writel(val, cci->base + CCI_I2C_Mm_MISC_CTL(i)); 268 } 269 } 270 271 static int cci_reset(struct cci *cci) 272 { 273 /* 274 * we reset the whole controller, here and for implicity use 275 * master[0].xxx for waiting on it. 276 */ 277 reinit_completion(&cci->master[0].irq_complete); 278 writel(CCI_RESET_CMD_MASK, cci->base + CCI_RESET_CMD); 279 280 if (!wait_for_completion_timeout(&cci->master[0].irq_complete, 281 CCI_TIMEOUT)) { 282 dev_err(cci->dev, "CCI reset timeout\n"); 283 return -ETIMEDOUT; 284 } 285 286 cci_init(cci); 287 288 return 0; 289 } 290 291 static int cci_run_queue(struct cci *cci, u8 master, u8 queue) 292 { 293 u32 val; 294 295 val = readl(cci->base + CCI_I2C_Mm_Qn_CUR_WORD_CNT(master, queue)); 296 writel(val, cci->base + CCI_I2C_Mm_Qn_EXEC_WORD_CNT(master, queue)); 297 298 reinit_completion(&cci->master[master].irq_complete); 299 val = BIT(master * 2 + queue); 300 writel(val, cci->base + CCI_QUEUE_START); 301 302 if (!wait_for_completion_timeout(&cci->master[master].irq_complete, 303 CCI_TIMEOUT)) { 304 dev_err(cci->dev, "master %d queue %d timeout\n", 305 master, queue); 306 cci_reset(cci); 307 return -ETIMEDOUT; 308 } 309 310 return cci->master[master].status; 311 } 312 313 static int cci_validate_queue(struct cci *cci, u8 master, u8 queue) 314 { 315 u32 val; 316 317 val = readl(cci->base + CCI_I2C_Mm_Qn_CUR_WORD_CNT(master, queue)); 318 if (val == cci->data->queue_size[queue]) 319 return -EINVAL; 320 321 if (!val) 322 return 0; 323 324 val = CCI_I2C_REPORT | CCI_I2C_REPORT_IRQ_EN; 325 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue)); 326 327 return cci_run_queue(cci, master, queue); 328 } 329 330 static int cci_i2c_read(struct cci *cci, u16 master, 331 u16 addr, u8 *buf, u16 len) 332 { 333 u32 val, words_read, words_exp; 334 u8 queue = QUEUE_1; 335 int i, index = 0, ret; 336 bool first = true; 337 338 /* 339 * Call validate queue to make sure queue is empty before starting. 340 * This is to avoid overflow / underflow of queue. 341 */ 342 ret = cci_validate_queue(cci, master, queue); 343 if (ret < 0) 344 return ret; 345 346 val = CCI_I2C_SET_PARAM | (addr & 0x7f) << 4; 347 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue)); 348 349 val = CCI_I2C_READ | len << 4; 350 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue)); 351 352 ret = cci_run_queue(cci, master, queue); 353 if (ret < 0) 354 return ret; 355 356 words_read = readl(cci->base + CCI_I2C_Mm_READ_BUF_LEVEL(master)); 357 words_exp = len / 4 + 1; 358 if (words_read != words_exp) { 359 dev_err(cci->dev, "words read = %d, words expected = %d\n", 360 words_read, words_exp); 361 return -EIO; 362 } 363 364 do { 365 val = readl(cci->base + CCI_I2C_Mm_READ_DATA(master)); 366 367 for (i = 0; i < 4 && index < len; i++) { 368 if (first) { 369 /* The LS byte of this register represents the 370 * first byte read from the slave during a read 371 * access. 372 */ 373 first = false; 374 continue; 375 } 376 buf[index++] = (val >> (i * 8)) & 0xff; 377 } 378 } while (--words_read); 379 380 return 0; 381 } 382 383 static int cci_i2c_write(struct cci *cci, u16 master, 384 u16 addr, u8 *buf, u16 len) 385 { 386 u8 queue = QUEUE_0; 387 u8 load[12] = { 0 }; 388 int i = 0, j, ret; 389 u32 val; 390 391 /* 392 * Call validate queue to make sure queue is empty before starting. 393 * This is to avoid overflow / underflow of queue. 394 */ 395 ret = cci_validate_queue(cci, master, queue); 396 if (ret < 0) 397 return ret; 398 399 val = CCI_I2C_SET_PARAM | (addr & 0x7f) << 4; 400 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue)); 401 402 load[i++] = CCI_I2C_WRITE | len << 4; 403 404 for (j = 0; j < len; j++) 405 load[i++] = buf[j]; 406 407 for (j = 0; j < i; j += 4) { 408 val = load[j]; 409 val |= load[j + 1] << 8; 410 val |= load[j + 2] << 16; 411 val |= load[j + 3] << 24; 412 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue)); 413 } 414 415 val = CCI_I2C_REPORT | CCI_I2C_REPORT_IRQ_EN; 416 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue)); 417 418 return cci_run_queue(cci, master, queue); 419 } 420 421 static int cci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 422 { 423 struct cci_master *cci_master = i2c_get_adapdata(adap); 424 struct cci *cci = cci_master->cci; 425 int i, ret; 426 427 ret = pm_runtime_get_sync(cci->dev); 428 if (ret < 0) 429 goto err; 430 431 for (i = 0; i < num; i++) { 432 if (msgs[i].flags & I2C_M_RD) 433 ret = cci_i2c_read(cci, cci_master->master, 434 msgs[i].addr, msgs[i].buf, 435 msgs[i].len); 436 else 437 ret = cci_i2c_write(cci, cci_master->master, 438 msgs[i].addr, msgs[i].buf, 439 msgs[i].len); 440 441 if (ret < 0) 442 break; 443 } 444 445 if (!ret) 446 ret = num; 447 448 err: 449 pm_runtime_put_autosuspend(cci->dev); 450 451 return ret; 452 } 453 454 static u32 cci_func(struct i2c_adapter *adap) 455 { 456 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 457 } 458 459 static const struct i2c_algorithm cci_algo = { 460 .xfer = cci_xfer, 461 .functionality = cci_func, 462 }; 463 464 static int cci_enable_clocks(struct cci *cci) 465 { 466 return clk_bulk_prepare_enable(cci->nclocks, cci->clocks); 467 } 468 469 static void cci_disable_clocks(struct cci *cci) 470 { 471 clk_bulk_disable_unprepare(cci->nclocks, cci->clocks); 472 } 473 474 static int __maybe_unused cci_suspend_runtime(struct device *dev) 475 { 476 struct cci *cci = dev_get_drvdata(dev); 477 478 cci_disable_clocks(cci); 479 return 0; 480 } 481 482 static int __maybe_unused cci_resume_runtime(struct device *dev) 483 { 484 struct cci *cci = dev_get_drvdata(dev); 485 int ret; 486 487 ret = cci_enable_clocks(cci); 488 if (ret) 489 return ret; 490 491 cci_init(cci); 492 return 0; 493 } 494 495 static int __maybe_unused cci_suspend(struct device *dev) 496 { 497 if (!pm_runtime_suspended(dev)) 498 return cci_suspend_runtime(dev); 499 500 return 0; 501 } 502 503 static int __maybe_unused cci_resume(struct device *dev) 504 { 505 cci_resume_runtime(dev); 506 pm_request_autosuspend(dev); 507 508 return 0; 509 } 510 511 static const struct dev_pm_ops qcom_cci_pm = { 512 SET_SYSTEM_SLEEP_PM_OPS(cci_suspend, cci_resume) 513 SET_RUNTIME_PM_OPS(cci_suspend_runtime, cci_resume_runtime, NULL) 514 }; 515 516 static int cci_probe(struct platform_device *pdev) 517 { 518 struct device *dev = &pdev->dev; 519 struct device_node *child; 520 struct resource *r; 521 struct cci *cci; 522 int ret, i; 523 u32 val; 524 525 cci = devm_kzalloc(dev, sizeof(*cci), GFP_KERNEL); 526 if (!cci) 527 return -ENOMEM; 528 529 cci->dev = dev; 530 platform_set_drvdata(pdev, cci); 531 cci->data = device_get_match_data(dev); 532 if (!cci->data) 533 return -ENOENT; 534 535 for_each_available_child_of_node(dev->of_node, child) { 536 struct cci_master *master; 537 u32 idx; 538 539 ret = of_property_read_u32(child, "reg", &idx); 540 if (ret) { 541 dev_err(dev, "%pOF invalid 'reg' property", child); 542 continue; 543 } 544 545 if (idx >= cci->data->num_masters) { 546 dev_err(dev, "%pOF invalid 'reg' value: %u (max is %u)", 547 child, idx, cci->data->num_masters - 1); 548 continue; 549 } 550 551 master = &cci->master[idx]; 552 master->adap.quirks = &cci->data->quirks; 553 master->adap.algo = &cci_algo; 554 master->adap.dev.parent = dev; 555 master->adap.dev.of_node = of_node_get(child); 556 master->master = idx; 557 master->cci = cci; 558 559 i2c_set_adapdata(&master->adap, master); 560 snprintf(master->adap.name, sizeof(master->adap.name), "Qualcomm-CCI"); 561 562 master->mode = I2C_MODE_STANDARD; 563 ret = of_property_read_u32(child, "clock-frequency", &val); 564 if (!ret) { 565 if (val == I2C_MAX_FAST_MODE_FREQ) 566 master->mode = I2C_MODE_FAST; 567 else if (val == I2C_MAX_FAST_MODE_PLUS_FREQ) 568 master->mode = I2C_MODE_FAST_PLUS; 569 } 570 571 init_completion(&master->irq_complete); 572 } 573 574 /* Memory */ 575 576 cci->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r); 577 if (IS_ERR(cci->base)) 578 return PTR_ERR(cci->base); 579 580 /* Clocks */ 581 582 ret = devm_clk_bulk_get_all(dev, &cci->clocks); 583 if (ret < 0) 584 return dev_err_probe(dev, ret, "failed to get clocks\n"); 585 else if (!ret) 586 return dev_err_probe(dev, -EINVAL, "not enough clocks in DT\n"); 587 cci->nclocks = ret; 588 589 ret = cci_enable_clocks(cci); 590 if (ret < 0) 591 return ret; 592 593 /* Interrupt */ 594 595 ret = platform_get_irq(pdev, 0); 596 if (ret < 0) 597 goto disable_clocks; 598 cci->irq = ret; 599 600 ret = devm_request_irq(dev, cci->irq, cci_isr, 0, dev_name(dev), cci); 601 if (ret < 0) { 602 dev_err(dev, "request_irq failed, ret: %d\n", ret); 603 goto disable_clocks; 604 } 605 606 val = readl(cci->base + CCI_HW_VERSION); 607 dev_dbg(dev, "CCI HW version = 0x%08x", val); 608 609 ret = cci_reset(cci); 610 if (ret < 0) 611 goto disable_clocks; 612 613 pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC); 614 pm_runtime_use_autosuspend(dev); 615 pm_runtime_set_active(dev); 616 pm_runtime_enable(dev); 617 618 for (i = 0; i < cci->data->num_masters; i++) { 619 if (!cci->master[i].cci) 620 continue; 621 622 ret = i2c_add_adapter(&cci->master[i].adap); 623 if (ret < 0) { 624 of_node_put(cci->master[i].adap.dev.of_node); 625 goto error_i2c; 626 } 627 } 628 629 return 0; 630 631 error_i2c: 632 pm_runtime_disable(dev); 633 pm_runtime_dont_use_autosuspend(dev); 634 635 for (--i ; i >= 0; i--) { 636 if (cci->master[i].cci) { 637 i2c_del_adapter(&cci->master[i].adap); 638 of_node_put(cci->master[i].adap.dev.of_node); 639 } 640 } 641 disable_clocks: 642 cci_disable_clocks(cci); 643 644 return ret; 645 } 646 647 static void cci_remove(struct platform_device *pdev) 648 { 649 struct cci *cci = platform_get_drvdata(pdev); 650 int i; 651 652 for (i = 0; i < cci->data->num_masters; i++) { 653 if (cci->master[i].cci) { 654 i2c_del_adapter(&cci->master[i].adap); 655 of_node_put(cci->master[i].adap.dev.of_node); 656 cci_halt(cci, i); 657 } 658 } 659 660 pm_runtime_disable(&pdev->dev); 661 pm_runtime_set_suspended(&pdev->dev); 662 } 663 664 static const struct cci_data cci_v1_data = { 665 .num_masters = 1, 666 .queue_size = { 64, 16 }, 667 .quirks = { 668 .max_write_len = 10, 669 .max_read_len = 12, 670 }, 671 .params[I2C_MODE_STANDARD] = { 672 .thigh = 78, 673 .tlow = 114, 674 .tsu_sto = 28, 675 .tsu_sta = 28, 676 .thd_dat = 10, 677 .thd_sta = 77, 678 .tbuf = 118, 679 .scl_stretch_en = 0, 680 .trdhld = 6, 681 .tsp = 1 682 }, 683 .params[I2C_MODE_FAST] = { 684 .thigh = 20, 685 .tlow = 28, 686 .tsu_sto = 21, 687 .tsu_sta = 21, 688 .thd_dat = 13, 689 .thd_sta = 18, 690 .tbuf = 32, 691 .scl_stretch_en = 0, 692 .trdhld = 6, 693 .tsp = 3 694 }, 695 }; 696 697 static const struct cci_data cci_v1_5_data = { 698 .num_masters = 2, 699 .queue_size = { 64, 16 }, 700 .quirks = { 701 .max_write_len = 10, 702 .max_read_len = 12, 703 }, 704 .params[I2C_MODE_STANDARD] = { 705 .thigh = 78, 706 .tlow = 114, 707 .tsu_sto = 28, 708 .tsu_sta = 28, 709 .thd_dat = 10, 710 .thd_sta = 77, 711 .tbuf = 118, 712 .scl_stretch_en = 0, 713 .trdhld = 6, 714 .tsp = 1 715 }, 716 .params[I2C_MODE_FAST] = { 717 .thigh = 20, 718 .tlow = 28, 719 .tsu_sto = 21, 720 .tsu_sta = 21, 721 .thd_dat = 13, 722 .thd_sta = 18, 723 .tbuf = 32, 724 .scl_stretch_en = 0, 725 .trdhld = 6, 726 .tsp = 3 727 }, 728 }; 729 730 static const struct cci_data cci_v2_data = { 731 .num_masters = 2, 732 .queue_size = { 64, 16 }, 733 .quirks = { 734 .max_write_len = 11, 735 .max_read_len = 12, 736 }, 737 .params[I2C_MODE_STANDARD] = { 738 .thigh = 201, 739 .tlow = 174, 740 .tsu_sto = 204, 741 .tsu_sta = 231, 742 .thd_dat = 22, 743 .thd_sta = 162, 744 .tbuf = 227, 745 .scl_stretch_en = 0, 746 .trdhld = 6, 747 .tsp = 3 748 }, 749 .params[I2C_MODE_FAST] = { 750 .thigh = 38, 751 .tlow = 56, 752 .tsu_sto = 40, 753 .tsu_sta = 40, 754 .thd_dat = 22, 755 .thd_sta = 35, 756 .tbuf = 62, 757 .scl_stretch_en = 0, 758 .trdhld = 6, 759 .tsp = 3 760 }, 761 .params[I2C_MODE_FAST_PLUS] = { 762 .thigh = 16, 763 .tlow = 22, 764 .tsu_sto = 17, 765 .tsu_sta = 18, 766 .thd_dat = 16, 767 .thd_sta = 15, 768 .tbuf = 24, 769 .scl_stretch_en = 0, 770 .trdhld = 3, 771 .tsp = 3 772 }, 773 }; 774 775 static const struct cci_data cci_msm8953_data = { 776 .num_masters = 2, 777 .queue_size = { 64, 16 }, 778 .quirks = { 779 .max_write_len = 11, 780 .max_read_len = 12, 781 }, 782 .params[I2C_MODE_STANDARD] = { 783 .thigh = 78, 784 .tlow = 114, 785 .tsu_sto = 28, 786 .tsu_sta = 28, 787 .thd_dat = 10, 788 .thd_sta = 77, 789 .tbuf = 118, 790 .scl_stretch_en = 0, 791 .trdhld = 6, 792 .tsp = 1 793 }, 794 .params[I2C_MODE_FAST] = { 795 .thigh = 20, 796 .tlow = 28, 797 .tsu_sto = 21, 798 .tsu_sta = 21, 799 .thd_dat = 13, 800 .thd_sta = 18, 801 .tbuf = 32, 802 .scl_stretch_en = 0, 803 .trdhld = 6, 804 .tsp = 3 805 }, 806 .params[I2C_MODE_FAST_PLUS] = { 807 .thigh = 16, 808 .tlow = 22, 809 .tsu_sto = 17, 810 .tsu_sta = 18, 811 .thd_dat = 16, 812 .thd_sta = 15, 813 .tbuf = 19, 814 .scl_stretch_en = 1, 815 .trdhld = 3, 816 .tsp = 3 817 }, 818 }; 819 820 static const struct of_device_id cci_dt_match[] = { 821 { .compatible = "qcom,msm8226-cci", .data = &cci_v1_data}, 822 { .compatible = "qcom,msm8953-cci", .data = &cci_msm8953_data}, 823 { .compatible = "qcom,msm8974-cci", .data = &cci_v1_5_data}, 824 { .compatible = "qcom,msm8996-cci", .data = &cci_v2_data}, 825 826 827 /* 828 * Legacy compatibles kept for backwards compatibility. 829 * Do not add any new ones unless they introduce a new config 830 */ 831 { .compatible = "qcom,msm8916-cci", .data = &cci_v1_data}, 832 { .compatible = "qcom,sdm845-cci", .data = &cci_v2_data}, 833 { .compatible = "qcom,sm8250-cci", .data = &cci_v2_data}, 834 { .compatible = "qcom,sm8450-cci", .data = &cci_v2_data}, 835 {} 836 }; 837 MODULE_DEVICE_TABLE(of, cci_dt_match); 838 839 static struct platform_driver qcom_cci_driver = { 840 .probe = cci_probe, 841 .remove = cci_remove, 842 .driver = { 843 .name = "i2c-qcom-cci", 844 .of_match_table = cci_dt_match, 845 .pm = &qcom_cci_pm, 846 }, 847 }; 848 849 module_platform_driver(qcom_cci_driver); 850 851 MODULE_DESCRIPTION("Qualcomm Camera Control Interface driver"); 852 MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>"); 853 MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>"); 854 MODULE_LICENSE("GPL v2"); 855