1 /* 2 * Provides I2C support for Philips PNX010x/PNX4008 boards. 3 * 4 * Authors: Dennis Kovalev <dkovalev@ru.mvista.com> 5 * Vitaly Wool <vwool@ru.mvista.com> 6 * 7 * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under 8 * the terms of the GNU General Public License version 2. This program 9 * is licensed "as is" without any warranty of any kind, whether express 10 * or implied. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/interrupt.h> 15 #include <linux/ioport.h> 16 #include <linux/delay.h> 17 #include <linux/i2c.h> 18 #include <linux/completion.h> 19 #include <linux/platform_device.h> 20 #include <linux/io.h> 21 #include <linux/err.h> 22 #include <linux/clk.h> 23 #include <linux/slab.h> 24 #include <linux/of.h> 25 26 #define I2C_PNX_TIMEOUT_DEFAULT 10 /* msec */ 27 #define I2C_PNX_REGION_SIZE 0x100 28 29 struct i2c_pnx_mif { 30 int ret; /* Return value */ 31 int mode; /* Interface mode */ 32 struct completion complete; /* I/O completion */ 33 u8 * buf; /* Data buffer */ 34 int len; /* Length of data buffer */ 35 int order; /* RX Bytes to order via TX */ 36 }; 37 38 struct i2c_pnx_algo_data { 39 void __iomem *ioaddr; 40 struct i2c_pnx_mif mif; 41 int last; 42 struct clk *clk; 43 struct i2c_adapter adapter; 44 int irq; 45 u32 timeout; 46 }; 47 48 enum { 49 mstatus_tdi = 0x00000001, 50 mstatus_afi = 0x00000002, 51 mstatus_nai = 0x00000004, 52 mstatus_drmi = 0x00000008, 53 mstatus_active = 0x00000020, 54 mstatus_scl = 0x00000040, 55 mstatus_sda = 0x00000080, 56 mstatus_rff = 0x00000100, 57 mstatus_rfe = 0x00000200, 58 mstatus_tff = 0x00000400, 59 mstatus_tfe = 0x00000800, 60 }; 61 62 enum { 63 mcntrl_tdie = 0x00000001, 64 mcntrl_afie = 0x00000002, 65 mcntrl_naie = 0x00000004, 66 mcntrl_drmie = 0x00000008, 67 mcntrl_drsie = 0x00000010, 68 mcntrl_rffie = 0x00000020, 69 mcntrl_daie = 0x00000040, 70 mcntrl_tffie = 0x00000080, 71 mcntrl_reset = 0x00000100, 72 mcntrl_cdbmode = 0x00000400, 73 }; 74 75 enum { 76 rw_bit = 1 << 0, 77 start_bit = 1 << 8, 78 stop_bit = 1 << 9, 79 }; 80 81 #define I2C_REG_RX(a) ((a)->ioaddr) /* Rx FIFO reg (RO) */ 82 #define I2C_REG_TX(a) ((a)->ioaddr) /* Tx FIFO reg (WO) */ 83 #define I2C_REG_STS(a) ((a)->ioaddr + 0x04) /* Status reg (RO) */ 84 #define I2C_REG_CTL(a) ((a)->ioaddr + 0x08) /* Ctl reg */ 85 #define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c) /* Clock divider low */ 86 #define I2C_REG_CKH(a) ((a)->ioaddr + 0x10) /* Clock divider high */ 87 #define I2C_REG_ADR(a) ((a)->ioaddr + 0x14) /* I2C address */ 88 #define I2C_REG_RFL(a) ((a)->ioaddr + 0x18) /* Rx FIFO level (RO) */ 89 #define I2C_REG_TFL(a) ((a)->ioaddr + 0x1c) /* Tx FIFO level (RO) */ 90 #define I2C_REG_RXB(a) ((a)->ioaddr + 0x20) /* Num of bytes Rx-ed (RO) */ 91 #define I2C_REG_TXB(a) ((a)->ioaddr + 0x24) /* Num of bytes Tx-ed (RO) */ 92 #define I2C_REG_TXS(a) ((a)->ioaddr + 0x28) /* Tx slave FIFO (RO) */ 93 #define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c) /* Tx slave FIFO level (RO) */ 94 95 static inline int wait_timeout(struct i2c_pnx_algo_data *data) 96 { 97 long timeout = jiffies_to_msecs(data->timeout); 98 while (timeout > 0 && 99 (ioread32(I2C_REG_STS(data)) & mstatus_active)) { 100 mdelay(1); 101 timeout--; 102 } 103 return (timeout <= 0); 104 } 105 106 static inline int wait_reset(struct i2c_pnx_algo_data *data) 107 { 108 long timeout = jiffies_to_msecs(data->timeout); 109 while (timeout > 0 && 110 (ioread32(I2C_REG_CTL(data)) & mcntrl_reset)) { 111 mdelay(1); 112 timeout--; 113 } 114 return (timeout <= 0); 115 } 116 117 /** 118 * i2c_pnx_start - start a device 119 * @slave_addr: slave address 120 * @alg_data: pointer to local driver data structure 121 * 122 * Generate a START signal in the desired mode. 123 */ 124 static int i2c_pnx_start(unsigned char slave_addr, 125 struct i2c_pnx_algo_data *alg_data) 126 { 127 dev_dbg(&alg_data->adapter.dev, "%s(): addr 0x%x mode %d\n", __func__, 128 slave_addr, alg_data->mif.mode); 129 130 /* Check for 7 bit slave addresses only */ 131 if (slave_addr & ~0x7f) { 132 dev_err(&alg_data->adapter.dev, 133 "%s: Invalid slave address %x. Only 7-bit addresses are supported\n", 134 alg_data->adapter.name, slave_addr); 135 return -EINVAL; 136 } 137 138 /* First, make sure bus is idle */ 139 if (wait_timeout(alg_data)) { 140 /* Somebody else is monopolizing the bus */ 141 dev_err(&alg_data->adapter.dev, 142 "%s: Bus busy. Slave addr = %02x, cntrl = %x, stat = %x\n", 143 alg_data->adapter.name, slave_addr, 144 ioread32(I2C_REG_CTL(alg_data)), 145 ioread32(I2C_REG_STS(alg_data))); 146 return -EBUSY; 147 } else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) { 148 /* Sorry, we lost the bus */ 149 dev_err(&alg_data->adapter.dev, 150 "%s: Arbitration failure. Slave addr = %02x\n", 151 alg_data->adapter.name, slave_addr); 152 return -EIO; 153 } 154 155 /* 156 * OK, I2C is enabled and we have the bus. 157 * Clear the current TDI and AFI status flags. 158 */ 159 iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi, 160 I2C_REG_STS(alg_data)); 161 162 dev_dbg(&alg_data->adapter.dev, "%s(): sending %#x\n", __func__, 163 (slave_addr << 1) | start_bit | alg_data->mif.mode); 164 165 /* Write the slave address, START bit and R/W bit */ 166 iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode, 167 I2C_REG_TX(alg_data)); 168 169 dev_dbg(&alg_data->adapter.dev, "%s(): exit\n", __func__); 170 171 return 0; 172 } 173 174 /** 175 * i2c_pnx_stop - stop a device 176 * @alg_data: pointer to local driver data structure 177 * 178 * Generate a STOP signal to terminate the master transaction. 179 */ 180 static void i2c_pnx_stop(struct i2c_pnx_algo_data *alg_data) 181 { 182 /* Only 1 msec max timeout due to interrupt context */ 183 long timeout = 1000; 184 185 dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n", 186 __func__, ioread32(I2C_REG_STS(alg_data))); 187 188 /* Write a STOP bit to TX FIFO */ 189 iowrite32(0xff | stop_bit, I2C_REG_TX(alg_data)); 190 191 /* Wait until the STOP is seen. */ 192 while (timeout > 0 && 193 (ioread32(I2C_REG_STS(alg_data)) & mstatus_active)) { 194 /* may be called from interrupt context */ 195 udelay(1); 196 timeout--; 197 } 198 199 dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n", 200 __func__, ioread32(I2C_REG_STS(alg_data))); 201 } 202 203 /** 204 * i2c_pnx_master_xmit - transmit data to slave 205 * @alg_data: pointer to local driver data structure 206 * 207 * Sends one byte of data to the slave 208 */ 209 static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data *alg_data) 210 { 211 u32 val; 212 213 dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n", 214 __func__, ioread32(I2C_REG_STS(alg_data))); 215 216 if (alg_data->mif.len > 0) { 217 /* We still have something to talk about... */ 218 val = *alg_data->mif.buf++; 219 220 if (alg_data->mif.len == 1) 221 val |= stop_bit; 222 223 alg_data->mif.len--; 224 iowrite32(val, I2C_REG_TX(alg_data)); 225 226 dev_dbg(&alg_data->adapter.dev, "%s(): xmit %#x [%d]\n", 227 __func__, val, alg_data->mif.len + 1); 228 229 if (alg_data->mif.len == 0) { 230 if (alg_data->last) { 231 /* Wait until the STOP is seen. */ 232 if (wait_timeout(alg_data)) 233 dev_err(&alg_data->adapter.dev, 234 "The bus is still active after timeout\n"); 235 } 236 /* Disable master interrupts */ 237 iowrite32(ioread32(I2C_REG_CTL(alg_data)) & 238 ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie), 239 I2C_REG_CTL(alg_data)); 240 241 dev_dbg(&alg_data->adapter.dev, 242 "%s(): Waking up xfer routine.\n", 243 __func__); 244 245 complete(&alg_data->mif.complete); 246 } 247 } else if (alg_data->mif.len == 0) { 248 /* zero-sized transfer */ 249 i2c_pnx_stop(alg_data); 250 251 /* Disable master interrupts. */ 252 iowrite32(ioread32(I2C_REG_CTL(alg_data)) & 253 ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie), 254 I2C_REG_CTL(alg_data)); 255 256 dev_dbg(&alg_data->adapter.dev, 257 "%s(): Waking up xfer routine after zero-xfer.\n", 258 __func__); 259 260 complete(&alg_data->mif.complete); 261 } 262 263 dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n", 264 __func__, ioread32(I2C_REG_STS(alg_data))); 265 266 return 0; 267 } 268 269 /** 270 * i2c_pnx_master_rcv - receive data from slave 271 * @alg_data: pointer to local driver data structure 272 * 273 * Reads one byte data from the slave 274 */ 275 static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data *alg_data) 276 { 277 unsigned int val = 0; 278 u32 ctl = 0; 279 280 dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n", 281 __func__, ioread32(I2C_REG_STS(alg_data))); 282 283 /* Check, whether there is already data, 284 * or we didn't 'ask' for it yet. 285 */ 286 if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) { 287 /* 'Asking' is done asynchronously, e.g. dummy TX of several 288 * bytes is done before the first actual RX arrives in FIFO. 289 * Therefore, ordered bytes (via TX) are counted separately. 290 */ 291 if (alg_data->mif.order) { 292 dev_dbg(&alg_data->adapter.dev, 293 "%s(): Write dummy data to fill Rx-fifo...\n", 294 __func__); 295 296 if (alg_data->mif.order == 1) { 297 /* Last byte, do not acknowledge next rcv. */ 298 val |= stop_bit; 299 300 /* 301 * Enable interrupt RFDAIE (data in Rx fifo), 302 * and disable DRMIE (need data for Tx) 303 */ 304 ctl = ioread32(I2C_REG_CTL(alg_data)); 305 ctl |= mcntrl_rffie | mcntrl_daie; 306 ctl &= ~mcntrl_drmie; 307 iowrite32(ctl, I2C_REG_CTL(alg_data)); 308 } 309 310 /* 311 * Now we'll 'ask' for data: 312 * For each byte we want to receive, we must 313 * write a (dummy) byte to the Tx-FIFO. 314 */ 315 iowrite32(val, I2C_REG_TX(alg_data)); 316 alg_data->mif.order--; 317 } 318 return 0; 319 } 320 321 /* Handle data. */ 322 if (alg_data->mif.len > 0) { 323 val = ioread32(I2C_REG_RX(alg_data)); 324 *alg_data->mif.buf++ = (u8) (val & 0xff); 325 dev_dbg(&alg_data->adapter.dev, "%s(): rcv 0x%x [%d]\n", 326 __func__, val, alg_data->mif.len); 327 328 alg_data->mif.len--; 329 if (alg_data->mif.len == 0) { 330 if (alg_data->last) 331 /* Wait until the STOP is seen. */ 332 if (wait_timeout(alg_data)) 333 dev_err(&alg_data->adapter.dev, 334 "The bus is still active after timeout\n"); 335 336 /* Disable master interrupts */ 337 ctl = ioread32(I2C_REG_CTL(alg_data)); 338 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | 339 mcntrl_drmie | mcntrl_daie); 340 iowrite32(ctl, I2C_REG_CTL(alg_data)); 341 342 complete(&alg_data->mif.complete); 343 } 344 } 345 346 dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n", 347 __func__, ioread32(I2C_REG_STS(alg_data))); 348 349 return 0; 350 } 351 352 static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id) 353 { 354 struct i2c_pnx_algo_data *alg_data = dev_id; 355 u32 stat, ctl; 356 357 dev_dbg(&alg_data->adapter.dev, 358 "%s(): mstat = %x mctrl = %x, mode = %d\n", 359 __func__, 360 ioread32(I2C_REG_STS(alg_data)), 361 ioread32(I2C_REG_CTL(alg_data)), 362 alg_data->mif.mode); 363 stat = ioread32(I2C_REG_STS(alg_data)); 364 365 /* let's see what kind of event this is */ 366 if (stat & mstatus_afi) { 367 /* We lost arbitration in the midst of a transfer */ 368 alg_data->mif.ret = -EIO; 369 370 /* Disable master interrupts. */ 371 ctl = ioread32(I2C_REG_CTL(alg_data)); 372 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | 373 mcntrl_drmie); 374 iowrite32(ctl, I2C_REG_CTL(alg_data)); 375 376 complete(&alg_data->mif.complete); 377 } else if (stat & mstatus_nai) { 378 /* Slave did not acknowledge, generate a STOP */ 379 dev_dbg(&alg_data->adapter.dev, 380 "%s(): Slave did not acknowledge, generating a STOP.\n", 381 __func__); 382 i2c_pnx_stop(alg_data); 383 384 /* Disable master interrupts. */ 385 ctl = ioread32(I2C_REG_CTL(alg_data)); 386 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | 387 mcntrl_drmie); 388 iowrite32(ctl, I2C_REG_CTL(alg_data)); 389 390 /* Our return value. */ 391 alg_data->mif.ret = -EIO; 392 393 complete(&alg_data->mif.complete); 394 } else { 395 /* 396 * Two options: 397 * - Master Tx needs data. 398 * - There is data in the Rx-fifo 399 * The latter is only the case if we have requested for data, 400 * via a dummy write. (See 'i2c_pnx_master_rcv'.) 401 * We therefore check, as a sanity check, whether that interrupt 402 * has been enabled. 403 */ 404 if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) { 405 if (alg_data->mif.mode == I2C_SMBUS_WRITE) { 406 i2c_pnx_master_xmit(alg_data); 407 } else if (alg_data->mif.mode == I2C_SMBUS_READ) { 408 i2c_pnx_master_rcv(alg_data); 409 } 410 } 411 } 412 413 /* Clear TDI and AFI bits */ 414 stat = ioread32(I2C_REG_STS(alg_data)); 415 iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data)); 416 417 dev_dbg(&alg_data->adapter.dev, 418 "%s(): exiting, stat = %x ctrl = %x.\n", 419 __func__, ioread32(I2C_REG_STS(alg_data)), 420 ioread32(I2C_REG_CTL(alg_data))); 421 422 return IRQ_HANDLED; 423 } 424 425 static void i2c_pnx_timeout(struct i2c_pnx_algo_data *alg_data) 426 { 427 u32 ctl; 428 429 dev_err(&alg_data->adapter.dev, 430 "Master timed out. stat = %04x, cntrl = %04x. Resetting master...\n", 431 ioread32(I2C_REG_STS(alg_data)), 432 ioread32(I2C_REG_CTL(alg_data))); 433 434 /* Reset master and disable interrupts */ 435 ctl = ioread32(I2C_REG_CTL(alg_data)); 436 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | mcntrl_drmie); 437 iowrite32(ctl, I2C_REG_CTL(alg_data)); 438 439 ctl |= mcntrl_reset; 440 iowrite32(ctl, I2C_REG_CTL(alg_data)); 441 wait_reset(alg_data); 442 alg_data->mif.ret = -EIO; 443 } 444 445 static inline void bus_reset_if_active(struct i2c_pnx_algo_data *alg_data) 446 { 447 u32 stat; 448 449 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) { 450 dev_err(&alg_data->adapter.dev, 451 "%s: Bus is still active after xfer. Reset it...\n", 452 alg_data->adapter.name); 453 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset, 454 I2C_REG_CTL(alg_data)); 455 wait_reset(alg_data); 456 } else if (!(stat & mstatus_rfe) || !(stat & mstatus_tfe)) { 457 /* If there is data in the fifo's after transfer, 458 * flush fifo's by reset. 459 */ 460 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset, 461 I2C_REG_CTL(alg_data)); 462 wait_reset(alg_data); 463 } else if (stat & mstatus_nai) { 464 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset, 465 I2C_REG_CTL(alg_data)); 466 wait_reset(alg_data); 467 } 468 } 469 470 /** 471 * i2c_pnx_xfer - generic transfer entry point 472 * @adap: pointer to I2C adapter structure 473 * @msgs: array of messages 474 * @num: number of messages 475 * 476 * Initiates the transfer 477 */ 478 static int 479 i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 480 { 481 struct i2c_msg *pmsg; 482 int rc = 0, completed = 0, i; 483 struct i2c_pnx_algo_data *alg_data = adap->algo_data; 484 unsigned long time_left; 485 u32 stat; 486 487 dev_dbg(&alg_data->adapter.dev, 488 "%s(): entering: %d messages, stat = %04x.\n", 489 __func__, num, ioread32(I2C_REG_STS(alg_data))); 490 491 bus_reset_if_active(alg_data); 492 493 /* Process transactions in a loop. */ 494 for (i = 0; rc >= 0 && i < num; i++) { 495 u8 addr; 496 497 pmsg = &msgs[i]; 498 addr = pmsg->addr; 499 500 if (pmsg->flags & I2C_M_TEN) { 501 dev_err(&alg_data->adapter.dev, 502 "%s: 10 bits addr not supported!\n", 503 alg_data->adapter.name); 504 rc = -EINVAL; 505 break; 506 } 507 508 alg_data->mif.buf = pmsg->buf; 509 alg_data->mif.len = pmsg->len; 510 alg_data->mif.order = pmsg->len; 511 alg_data->mif.mode = (pmsg->flags & I2C_M_RD) ? 512 I2C_SMBUS_READ : I2C_SMBUS_WRITE; 513 alg_data->mif.ret = 0; 514 alg_data->last = (i == num - 1); 515 516 dev_dbg(&alg_data->adapter.dev, "%s(): mode %d, %d bytes\n", 517 __func__, alg_data->mif.mode, alg_data->mif.len); 518 519 520 /* initialize the completion var */ 521 init_completion(&alg_data->mif.complete); 522 523 /* Enable master interrupt */ 524 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_afie | 525 mcntrl_naie | mcntrl_drmie, 526 I2C_REG_CTL(alg_data)); 527 528 /* Put start-code and slave-address on the bus. */ 529 rc = i2c_pnx_start(addr, alg_data); 530 if (rc < 0) 531 break; 532 533 /* Wait for completion */ 534 time_left = wait_for_completion_timeout(&alg_data->mif.complete, 535 alg_data->timeout); 536 if (time_left == 0) 537 i2c_pnx_timeout(alg_data); 538 539 if (!(rc = alg_data->mif.ret)) 540 completed++; 541 dev_dbg(&alg_data->adapter.dev, 542 "%s(): Complete, return code = %d.\n", 543 __func__, rc); 544 545 /* Clear TDI and AFI bits in case they are set. */ 546 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) { 547 dev_dbg(&alg_data->adapter.dev, 548 "%s: TDI still set... clearing now.\n", 549 alg_data->adapter.name); 550 iowrite32(stat, I2C_REG_STS(alg_data)); 551 } 552 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) { 553 dev_dbg(&alg_data->adapter.dev, 554 "%s: AFI still set... clearing now.\n", 555 alg_data->adapter.name); 556 iowrite32(stat, I2C_REG_STS(alg_data)); 557 } 558 } 559 560 bus_reset_if_active(alg_data); 561 562 /* Cleanup to be sure... */ 563 alg_data->mif.buf = NULL; 564 alg_data->mif.len = 0; 565 alg_data->mif.order = 0; 566 567 dev_dbg(&alg_data->adapter.dev, "%s(): exiting, stat = %x\n", 568 __func__, ioread32(I2C_REG_STS(alg_data))); 569 570 if (completed != num) 571 return ((rc < 0) ? rc : -EREMOTEIO); 572 573 return num; 574 } 575 576 static u32 i2c_pnx_func(struct i2c_adapter *adapter) 577 { 578 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 579 } 580 581 static const struct i2c_algorithm pnx_algorithm = { 582 .xfer = i2c_pnx_xfer, 583 .functionality = i2c_pnx_func, 584 }; 585 586 static int i2c_pnx_controller_suspend(struct device *dev) 587 { 588 struct i2c_pnx_algo_data *alg_data = dev_get_drvdata(dev); 589 590 clk_disable_unprepare(alg_data->clk); 591 592 return 0; 593 } 594 595 static int i2c_pnx_controller_resume(struct device *dev) 596 { 597 struct i2c_pnx_algo_data *alg_data = dev_get_drvdata(dev); 598 599 return clk_prepare_enable(alg_data->clk); 600 } 601 602 static DEFINE_SIMPLE_DEV_PM_OPS(i2c_pnx_pm, 603 i2c_pnx_controller_suspend, 604 i2c_pnx_controller_resume); 605 606 static int i2c_pnx_probe(struct platform_device *pdev) 607 { 608 u32 speed = I2C_MAX_STANDARD_MODE_FREQ; 609 unsigned long tmp; 610 int ret = 0; 611 struct i2c_pnx_algo_data *alg_data; 612 unsigned long freq; 613 struct resource *res; 614 615 alg_data = devm_kzalloc(&pdev->dev, sizeof(*alg_data), GFP_KERNEL); 616 if (!alg_data) 617 return -ENOMEM; 618 619 platform_set_drvdata(pdev, alg_data); 620 621 alg_data->adapter.dev.parent = &pdev->dev; 622 alg_data->adapter.algo = &pnx_algorithm; 623 alg_data->adapter.algo_data = alg_data; 624 alg_data->adapter.nr = pdev->id; 625 626 alg_data->timeout = msecs_to_jiffies(I2C_PNX_TIMEOUT_DEFAULT); 627 if (alg_data->timeout <= 1) 628 alg_data->timeout = 2; 629 630 #ifdef CONFIG_OF 631 alg_data->adapter.dev.of_node = of_node_get(pdev->dev.of_node); 632 if (pdev->dev.of_node) { 633 of_property_read_u32(pdev->dev.of_node, "clock-frequency", 634 &speed); 635 /* 636 * At this point, it is planned to add an OF timeout property. 637 * As soon as there is a consensus about how to call and handle 638 * this, sth. like the following can be put here: 639 * 640 * of_property_read_u32(pdev->dev.of_node, "timeout", 641 * &alg_data->timeout); 642 */ 643 } 644 #endif 645 alg_data->clk = devm_clk_get(&pdev->dev, NULL); 646 if (IS_ERR(alg_data->clk)) 647 return PTR_ERR(alg_data->clk); 648 649 snprintf(alg_data->adapter.name, sizeof(alg_data->adapter.name), 650 "%s", pdev->name); 651 652 /* Register I/O resource */ 653 alg_data->ioaddr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 654 if (IS_ERR(alg_data->ioaddr)) 655 return PTR_ERR(alg_data->ioaddr); 656 657 ret = clk_prepare_enable(alg_data->clk); 658 if (ret) 659 return ret; 660 661 freq = clk_get_rate(alg_data->clk); 662 663 /* 664 * Clock Divisor High This value is the number of system clocks 665 * the serial clock (SCL) will be high. 666 * For example, if the system clock period is 50 ns and the maximum 667 * desired serial period is 10000 ns (100 kHz), then CLKHI would be 668 * set to 0.5*(f_sys/f_i2c)-2=0.5*(20e6/100e3)-2=98. The actual value 669 * programmed into CLKHI will vary from this slightly due to 670 * variations in the output pad's rise and fall times as well as 671 * the deglitching filter length. 672 */ 673 674 tmp = (freq / speed) / 2 - 2; 675 if (tmp > 0x3FF) 676 tmp = 0x3FF; 677 iowrite32(tmp, I2C_REG_CKH(alg_data)); 678 iowrite32(tmp, I2C_REG_CKL(alg_data)); 679 680 iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data)); 681 if (wait_reset(alg_data)) { 682 ret = -ENODEV; 683 goto out_clock; 684 } 685 init_completion(&alg_data->mif.complete); 686 687 alg_data->irq = platform_get_irq(pdev, 0); 688 if (alg_data->irq < 0) { 689 ret = alg_data->irq; 690 goto out_clock; 691 } 692 ret = devm_request_irq(&pdev->dev, alg_data->irq, i2c_pnx_interrupt, 693 0, pdev->name, alg_data); 694 if (ret) 695 goto out_clock; 696 697 /* Register this adapter with the I2C subsystem */ 698 ret = i2c_add_numbered_adapter(&alg_data->adapter); 699 if (ret < 0) 700 goto out_clock; 701 702 dev_dbg(&pdev->dev, "%s: Master at %pap, irq %d.\n", 703 alg_data->adapter.name, &res->start, alg_data->irq); 704 705 return 0; 706 707 out_clock: 708 clk_disable_unprepare(alg_data->clk); 709 return ret; 710 } 711 712 static void i2c_pnx_remove(struct platform_device *pdev) 713 { 714 struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev); 715 716 i2c_del_adapter(&alg_data->adapter); 717 clk_disable_unprepare(alg_data->clk); 718 } 719 720 #ifdef CONFIG_OF 721 static const struct of_device_id i2c_pnx_of_match[] = { 722 { .compatible = "nxp,pnx-i2c" }, 723 { } 724 }; 725 MODULE_DEVICE_TABLE(of, i2c_pnx_of_match); 726 #endif 727 728 static struct platform_driver i2c_pnx_driver = { 729 .driver = { 730 .name = "pnx-i2c", 731 .of_match_table = of_match_ptr(i2c_pnx_of_match), 732 .pm = pm_sleep_ptr(&i2c_pnx_pm), 733 }, 734 .probe = i2c_pnx_probe, 735 .remove = i2c_pnx_remove, 736 }; 737 738 static int __init i2c_adap_pnx_init(void) 739 { 740 return platform_driver_register(&i2c_pnx_driver); 741 } 742 743 static void __exit i2c_adap_pnx_exit(void) 744 { 745 platform_driver_unregister(&i2c_pnx_driver); 746 } 747 748 MODULE_AUTHOR("Vitaly Wool"); 749 MODULE_AUTHOR("Dennis Kovalev <source@mvista.com>"); 750 MODULE_DESCRIPTION("I2C driver for Philips IP3204-based I2C busses"); 751 MODULE_LICENSE("GPL"); 752 MODULE_ALIAS("platform:pnx-i2c"); 753 754 /* We need to make sure I2C is initialized before USB */ 755 subsys_initcall(i2c_adap_pnx_init); 756 module_exit(i2c_adap_pnx_exit); 757