1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Actions Semiconductor Owl SoC's I2C driver 4 * 5 * Copyright (c) 2014 Actions Semi Inc. 6 * Author: David Liu <liuwei@actions-semi.com> 7 * 8 * Copyright (c) 2018 Linaro Ltd. 9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/i2c.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/of_device.h> 19 20 /* I2C registers */ 21 #define OWL_I2C_REG_CTL 0x0000 22 #define OWL_I2C_REG_CLKDIV 0x0004 23 #define OWL_I2C_REG_STAT 0x0008 24 #define OWL_I2C_REG_ADDR 0x000C 25 #define OWL_I2C_REG_TXDAT 0x0010 26 #define OWL_I2C_REG_RXDAT 0x0014 27 #define OWL_I2C_REG_CMD 0x0018 28 #define OWL_I2C_REG_FIFOCTL 0x001C 29 #define OWL_I2C_REG_FIFOSTAT 0x0020 30 #define OWL_I2C_REG_DATCNT 0x0024 31 #define OWL_I2C_REG_RCNT 0x0028 32 33 /* I2Cx_CTL Bit Mask */ 34 #define OWL_I2C_CTL_RB BIT(1) 35 #define OWL_I2C_CTL_GBCC(x) (((x) & 0x3) << 2) 36 #define OWL_I2C_CTL_GBCC_NONE OWL_I2C_CTL_GBCC(0) 37 #define OWL_I2C_CTL_GBCC_START OWL_I2C_CTL_GBCC(1) 38 #define OWL_I2C_CTL_GBCC_STOP OWL_I2C_CTL_GBCC(2) 39 #define OWL_I2C_CTL_GBCC_RSTART OWL_I2C_CTL_GBCC(3) 40 #define OWL_I2C_CTL_IRQE BIT(5) 41 #define OWL_I2C_CTL_EN BIT(7) 42 #define OWL_I2C_CTL_AE BIT(8) 43 #define OWL_I2C_CTL_SHSM BIT(10) 44 45 #define OWL_I2C_DIV_FACTOR(x) ((x) & 0xff) 46 47 /* I2Cx_STAT Bit Mask */ 48 #define OWL_I2C_STAT_RACK BIT(0) 49 #define OWL_I2C_STAT_BEB BIT(1) 50 #define OWL_I2C_STAT_IRQP BIT(2) 51 #define OWL_I2C_STAT_LAB BIT(3) 52 #define OWL_I2C_STAT_STPD BIT(4) 53 #define OWL_I2C_STAT_STAD BIT(5) 54 #define OWL_I2C_STAT_BBB BIT(6) 55 #define OWL_I2C_STAT_TCB BIT(7) 56 #define OWL_I2C_STAT_LBST BIT(8) 57 #define OWL_I2C_STAT_SAMB BIT(9) 58 #define OWL_I2C_STAT_SRGC BIT(10) 59 60 /* I2Cx_CMD Bit Mask */ 61 #define OWL_I2C_CMD_SBE BIT(0) 62 #define OWL_I2C_CMD_RBE BIT(4) 63 #define OWL_I2C_CMD_DE BIT(8) 64 #define OWL_I2C_CMD_NS BIT(9) 65 #define OWL_I2C_CMD_SE BIT(10) 66 #define OWL_I2C_CMD_MSS BIT(11) 67 #define OWL_I2C_CMD_WRS BIT(12) 68 #define OWL_I2C_CMD_SECL BIT(15) 69 70 #define OWL_I2C_CMD_AS(x) (((x) & 0x7) << 1) 71 #define OWL_I2C_CMD_SAS(x) (((x) & 0x7) << 5) 72 73 /* I2Cx_FIFOCTL Bit Mask */ 74 #define OWL_I2C_FIFOCTL_NIB BIT(0) 75 #define OWL_I2C_FIFOCTL_RFR BIT(1) 76 #define OWL_I2C_FIFOCTL_TFR BIT(2) 77 78 /* I2Cc_FIFOSTAT Bit Mask */ 79 #define OWL_I2C_FIFOSTAT_RNB BIT(1) 80 #define OWL_I2C_FIFOSTAT_RFE BIT(2) 81 #define OWL_I2C_FIFOSTAT_TFF BIT(5) 82 #define OWL_I2C_FIFOSTAT_TFD GENMASK(23, 16) 83 #define OWL_I2C_FIFOSTAT_RFD GENMASK(15, 8) 84 85 /* I2C bus timeout */ 86 #define OWL_I2C_TIMEOUT msecs_to_jiffies(4 * 1000) 87 88 #define OWL_I2C_MAX_RETRIES 50 89 90 struct owl_i2c_dev { 91 struct i2c_adapter adap; 92 struct i2c_msg *msg; 93 struct completion msg_complete; 94 struct clk *clk; 95 spinlock_t lock; 96 void __iomem *base; 97 unsigned long clk_rate; 98 u32 bus_freq; 99 u32 msg_ptr; 100 int err; 101 }; 102 103 static void owl_i2c_update_reg(void __iomem *reg, unsigned int val, bool state) 104 { 105 unsigned int regval; 106 107 regval = readl(reg); 108 109 if (state) 110 regval |= val; 111 else 112 regval &= ~val; 113 114 writel(regval, reg); 115 } 116 117 static void owl_i2c_reset(struct owl_i2c_dev *i2c_dev) 118 { 119 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 120 OWL_I2C_CTL_EN, false); 121 mdelay(1); 122 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 123 OWL_I2C_CTL_EN, true); 124 125 /* Clear status registers */ 126 writel(0, i2c_dev->base + OWL_I2C_REG_STAT); 127 } 128 129 static int owl_i2c_reset_fifo(struct owl_i2c_dev *i2c_dev) 130 { 131 unsigned int val, timeout = 0; 132 133 /* Reset FIFO */ 134 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, 135 OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR, 136 true); 137 138 /* Wait 50ms for FIFO reset complete */ 139 do { 140 val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL); 141 if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR))) 142 break; 143 usleep_range(500, 1000); 144 } while (timeout++ < OWL_I2C_MAX_RETRIES); 145 146 if (timeout > OWL_I2C_MAX_RETRIES) { 147 dev_err(&i2c_dev->adap.dev, "FIFO reset timeout\n"); 148 return -ETIMEDOUT; 149 } 150 151 return 0; 152 } 153 154 static void owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev) 155 { 156 unsigned int val; 157 158 val = DIV_ROUND_UP(i2c_dev->clk_rate, i2c_dev->bus_freq * 16); 159 160 /* Set clock divider factor */ 161 writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV); 162 } 163 164 static irqreturn_t owl_i2c_interrupt(int irq, void *_dev) 165 { 166 struct owl_i2c_dev *i2c_dev = _dev; 167 struct i2c_msg *msg = i2c_dev->msg; 168 unsigned long flags; 169 unsigned int stat, fifostat; 170 171 spin_lock_irqsave(&i2c_dev->lock, flags); 172 173 i2c_dev->err = 0; 174 175 /* Handle NACK from slave */ 176 fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT); 177 if (fifostat & OWL_I2C_FIFOSTAT_RNB) { 178 i2c_dev->err = -ENXIO; 179 /* Clear NACK error bit by writing "1" */ 180 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOSTAT, 181 OWL_I2C_FIFOSTAT_RNB, true); 182 goto stop; 183 } 184 185 /* Handle bus error */ 186 stat = readl(i2c_dev->base + OWL_I2C_REG_STAT); 187 if (stat & OWL_I2C_STAT_BEB) { 188 i2c_dev->err = -EIO; 189 /* Clear BUS error bit by writing "1" */ 190 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT, 191 OWL_I2C_STAT_BEB, true); 192 goto stop; 193 } 194 195 /* Handle FIFO read */ 196 if (msg->flags & I2C_M_RD) { 197 while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & 198 OWL_I2C_FIFOSTAT_RFE) && i2c_dev->msg_ptr < msg->len) { 199 msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base + 200 OWL_I2C_REG_RXDAT); 201 } 202 } else { 203 /* Handle the remaining bytes which were not sent */ 204 while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & 205 OWL_I2C_FIFOSTAT_TFF) && i2c_dev->msg_ptr < msg->len) { 206 writel(msg->buf[i2c_dev->msg_ptr++], 207 i2c_dev->base + OWL_I2C_REG_TXDAT); 208 } 209 } 210 211 stop: 212 /* Clear pending interrupts */ 213 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT, 214 OWL_I2C_STAT_IRQP, true); 215 216 complete_all(&i2c_dev->msg_complete); 217 spin_unlock_irqrestore(&i2c_dev->lock, flags); 218 219 return IRQ_HANDLED; 220 } 221 222 static u32 owl_i2c_func(struct i2c_adapter *adap) 223 { 224 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 225 } 226 227 static int owl_i2c_check_bus_busy(struct i2c_adapter *adap) 228 { 229 struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 230 unsigned long timeout; 231 232 /* Check for Bus busy */ 233 timeout = jiffies + OWL_I2C_TIMEOUT; 234 while (readl(i2c_dev->base + OWL_I2C_REG_STAT) & OWL_I2C_STAT_BBB) { 235 if (time_after(jiffies, timeout)) { 236 dev_err(&adap->dev, "Bus busy timeout\n"); 237 return -ETIMEDOUT; 238 } 239 } 240 241 return 0; 242 } 243 244 static int owl_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 245 int num) 246 { 247 struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 248 struct i2c_msg *msg; 249 unsigned long time_left, flags; 250 unsigned int i2c_cmd, val; 251 unsigned int addr; 252 int ret, idx; 253 254 spin_lock_irqsave(&i2c_dev->lock, flags); 255 256 /* Reset I2C controller */ 257 owl_i2c_reset(i2c_dev); 258 259 /* Set bus frequency */ 260 owl_i2c_set_freq(i2c_dev); 261 262 /* 263 * Spinlock should be released before calling reset FIFO and 264 * bus busy check since those functions may sleep 265 */ 266 spin_unlock_irqrestore(&i2c_dev->lock, flags); 267 268 /* Reset FIFO */ 269 ret = owl_i2c_reset_fifo(i2c_dev); 270 if (ret) 271 goto unlocked_err_exit; 272 273 /* Check for bus busy */ 274 ret = owl_i2c_check_bus_busy(adap); 275 if (ret) 276 goto unlocked_err_exit; 277 278 spin_lock_irqsave(&i2c_dev->lock, flags); 279 280 /* Check for Arbitration lost */ 281 val = readl(i2c_dev->base + OWL_I2C_REG_STAT); 282 if (val & OWL_I2C_STAT_LAB) { 283 val &= ~OWL_I2C_STAT_LAB; 284 writel(val, i2c_dev->base + OWL_I2C_REG_STAT); 285 ret = -EAGAIN; 286 goto err_exit; 287 } 288 289 reinit_completion(&i2c_dev->msg_complete); 290 291 /* Enable I2C controller interrupt */ 292 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 293 OWL_I2C_CTL_IRQE, true); 294 295 /* 296 * Select: FIFO enable, Master mode, Stop enable, Data count enable, 297 * Send start bit 298 */ 299 i2c_cmd = OWL_I2C_CMD_SECL | OWL_I2C_CMD_MSS | OWL_I2C_CMD_SE | 300 OWL_I2C_CMD_NS | OWL_I2C_CMD_DE | OWL_I2C_CMD_SBE; 301 302 /* Handle repeated start condition */ 303 if (num > 1) { 304 /* Set internal address length and enable repeated start */ 305 i2c_cmd |= OWL_I2C_CMD_AS(msgs[0].len + 1) | 306 OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE; 307 308 /* Write slave address */ 309 addr = i2c_8bit_addr_from_msg(&msgs[0]); 310 writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT); 311 312 /* Write internal register address */ 313 for (idx = 0; idx < msgs[0].len; idx++) 314 writel(msgs[0].buf[idx], 315 i2c_dev->base + OWL_I2C_REG_TXDAT); 316 317 msg = &msgs[1]; 318 } else { 319 /* Set address length */ 320 i2c_cmd |= OWL_I2C_CMD_AS(1); 321 msg = &msgs[0]; 322 } 323 324 i2c_dev->msg = msg; 325 i2c_dev->msg_ptr = 0; 326 327 /* Set data count for the message */ 328 writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT); 329 330 addr = i2c_8bit_addr_from_msg(msg); 331 writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT); 332 333 if (!(msg->flags & I2C_M_RD)) { 334 /* Write data to FIFO */ 335 for (idx = 0; idx < msg->len; idx++) { 336 /* Check for FIFO full */ 337 if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & 338 OWL_I2C_FIFOSTAT_TFF) 339 break; 340 341 writel(msg->buf[idx], 342 i2c_dev->base + OWL_I2C_REG_TXDAT); 343 } 344 345 i2c_dev->msg_ptr = idx; 346 } 347 348 /* Ignore the NACK if needed */ 349 if (msg->flags & I2C_M_IGNORE_NAK) 350 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, 351 OWL_I2C_FIFOCTL_NIB, true); 352 else 353 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, 354 OWL_I2C_FIFOCTL_NIB, false); 355 356 /* Start the transfer */ 357 writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD); 358 359 spin_unlock_irqrestore(&i2c_dev->lock, flags); 360 361 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete, 362 adap->timeout); 363 364 spin_lock_irqsave(&i2c_dev->lock, flags); 365 if (time_left == 0) { 366 dev_err(&adap->dev, "Transaction timed out\n"); 367 /* Send stop condition and release the bus */ 368 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 369 OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB, 370 true); 371 ret = -ETIMEDOUT; 372 goto err_exit; 373 } 374 375 ret = i2c_dev->err < 0 ? i2c_dev->err : num; 376 377 err_exit: 378 spin_unlock_irqrestore(&i2c_dev->lock, flags); 379 380 unlocked_err_exit: 381 /* Disable I2C controller */ 382 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 383 OWL_I2C_CTL_EN, false); 384 385 return ret; 386 } 387 388 static const struct i2c_algorithm owl_i2c_algorithm = { 389 .master_xfer = owl_i2c_master_xfer, 390 .functionality = owl_i2c_func, 391 }; 392 393 static const struct i2c_adapter_quirks owl_i2c_quirks = { 394 .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST, 395 .max_read_len = 240, 396 .max_write_len = 240, 397 .max_comb_1st_msg_len = 6, 398 .max_comb_2nd_msg_len = 240, 399 }; 400 401 static int owl_i2c_probe(struct platform_device *pdev) 402 { 403 struct device *dev = &pdev->dev; 404 struct owl_i2c_dev *i2c_dev; 405 int ret, irq; 406 407 i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL); 408 if (!i2c_dev) 409 return -ENOMEM; 410 411 i2c_dev->base = devm_platform_ioremap_resource(pdev, 0); 412 if (IS_ERR(i2c_dev->base)) 413 return PTR_ERR(i2c_dev->base); 414 415 irq = platform_get_irq(pdev, 0); 416 if (irq < 0) 417 return irq; 418 419 if (of_property_read_u32(dev->of_node, "clock-frequency", 420 &i2c_dev->bus_freq)) 421 i2c_dev->bus_freq = I2C_MAX_STANDARD_MODE_FREQ; 422 423 /* We support only frequencies of 100k and 400k for now */ 424 if (i2c_dev->bus_freq != I2C_MAX_STANDARD_MODE_FREQ && 425 i2c_dev->bus_freq != I2C_MAX_FAST_MODE_FREQ) { 426 dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq); 427 return -EINVAL; 428 } 429 430 i2c_dev->clk = devm_clk_get(dev, NULL); 431 if (IS_ERR(i2c_dev->clk)) { 432 dev_err(dev, "failed to get clock\n"); 433 return PTR_ERR(i2c_dev->clk); 434 } 435 436 ret = clk_prepare_enable(i2c_dev->clk); 437 if (ret) 438 return ret; 439 440 i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk); 441 if (!i2c_dev->clk_rate) { 442 dev_err(dev, "input clock rate should not be zero\n"); 443 ret = -EINVAL; 444 goto disable_clk; 445 } 446 447 init_completion(&i2c_dev->msg_complete); 448 spin_lock_init(&i2c_dev->lock); 449 i2c_dev->adap.owner = THIS_MODULE; 450 i2c_dev->adap.algo = &owl_i2c_algorithm; 451 i2c_dev->adap.timeout = OWL_I2C_TIMEOUT; 452 i2c_dev->adap.quirks = &owl_i2c_quirks; 453 i2c_dev->adap.dev.parent = dev; 454 i2c_dev->adap.dev.of_node = dev->of_node; 455 snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name), 456 "%s", "OWL I2C adapter"); 457 i2c_set_adapdata(&i2c_dev->adap, i2c_dev); 458 459 platform_set_drvdata(pdev, i2c_dev); 460 461 ret = devm_request_irq(dev, irq, owl_i2c_interrupt, 0, pdev->name, 462 i2c_dev); 463 if (ret) { 464 dev_err(dev, "failed to request irq %d\n", irq); 465 goto disable_clk; 466 } 467 468 return i2c_add_adapter(&i2c_dev->adap); 469 470 disable_clk: 471 clk_disable_unprepare(i2c_dev->clk); 472 473 return ret; 474 } 475 476 static const struct of_device_id owl_i2c_of_match[] = { 477 { .compatible = "actions,s700-i2c" }, 478 { .compatible = "actions,s900-i2c" }, 479 { /* sentinel */ } 480 }; 481 MODULE_DEVICE_TABLE(of, owl_i2c_of_match); 482 483 static struct platform_driver owl_i2c_driver = { 484 .probe = owl_i2c_probe, 485 .driver = { 486 .name = "owl-i2c", 487 .of_match_table = of_match_ptr(owl_i2c_of_match), 488 }, 489 }; 490 module_platform_driver(owl_i2c_driver); 491 492 MODULE_AUTHOR("David Liu <liuwei@actions-semi.com>"); 493 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 494 MODULE_DESCRIPTION("Actions Semiconductor Owl SoC's I2C driver"); 495 MODULE_LICENSE("GPL"); 496