1 /* 2 * TI OMAP I2C master mode driver 3 * 4 * Copyright (C) 2003 MontaVista Software, Inc. 5 * Copyright (C) 2005 Nokia Corporation 6 * Copyright (C) 2004 - 2007 Texas Instruments. 7 * 8 * Originally written by MontaVista Software, Inc. 9 * Additional contributions by: 10 * Tony Lindgren <tony@atomide.com> 11 * Imre Deak <imre.deak@nokia.com> 12 * Juha Yrjölä <juha.yrjola@solidboot.com> 13 * Syed Khasim <x0khasim@ti.com> 14 * Nishant Menon <nm@ti.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2 of the License, or 19 * (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 29 */ 30 31 #include <linux/module.h> 32 #include <linux/delay.h> 33 #include <linux/i2c.h> 34 #include <linux/err.h> 35 #include <linux/interrupt.h> 36 #include <linux/completion.h> 37 #include <linux/platform_device.h> 38 #include <linux/clk.h> 39 #include <linux/io.h> 40 #include <linux/of.h> 41 #include <linux/of_i2c.h> 42 #include <linux/of_device.h> 43 #include <linux/slab.h> 44 #include <linux/i2c-omap.h> 45 #include <linux/pm_runtime.h> 46 47 /* I2C controller revisions */ 48 #define OMAP_I2C_OMAP1_REV_2 0x20 49 50 /* I2C controller revisions present on specific hardware */ 51 #define OMAP_I2C_REV_ON_2430 0x36 52 #define OMAP_I2C_REV_ON_3430_3530 0x3C 53 #define OMAP_I2C_REV_ON_3630_4430 0x40 54 55 /* timeout waiting for the controller to respond */ 56 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) 57 58 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ 59 enum { 60 OMAP_I2C_REV_REG = 0, 61 OMAP_I2C_IE_REG, 62 OMAP_I2C_STAT_REG, 63 OMAP_I2C_IV_REG, 64 OMAP_I2C_WE_REG, 65 OMAP_I2C_SYSS_REG, 66 OMAP_I2C_BUF_REG, 67 OMAP_I2C_CNT_REG, 68 OMAP_I2C_DATA_REG, 69 OMAP_I2C_SYSC_REG, 70 OMAP_I2C_CON_REG, 71 OMAP_I2C_OA_REG, 72 OMAP_I2C_SA_REG, 73 OMAP_I2C_PSC_REG, 74 OMAP_I2C_SCLL_REG, 75 OMAP_I2C_SCLH_REG, 76 OMAP_I2C_SYSTEST_REG, 77 OMAP_I2C_BUFSTAT_REG, 78 /* only on OMAP4430 */ 79 OMAP_I2C_IP_V2_REVNB_LO, 80 OMAP_I2C_IP_V2_REVNB_HI, 81 OMAP_I2C_IP_V2_IRQSTATUS_RAW, 82 OMAP_I2C_IP_V2_IRQENABLE_SET, 83 OMAP_I2C_IP_V2_IRQENABLE_CLR, 84 }; 85 86 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */ 87 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ 88 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */ 89 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */ 90 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */ 91 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */ 92 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */ 93 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */ 94 95 /* I2C Status Register (OMAP_I2C_STAT): */ 96 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */ 97 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */ 98 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */ 99 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ 100 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ 101 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */ 102 #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */ 103 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ 104 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ 105 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */ 106 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */ 107 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */ 108 109 /* I2C WE wakeup enable register */ 110 #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */ 111 #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */ 112 #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/ 113 #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */ 114 #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */ 115 #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */ 116 #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */ 117 #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */ 118 #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */ 119 #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */ 120 121 #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \ 122 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \ 123 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \ 124 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \ 125 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE) 126 127 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */ 128 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */ 129 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */ 130 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */ 131 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */ 132 133 /* I2C Configuration Register (OMAP_I2C_CON): */ 134 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */ 135 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */ 136 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */ 137 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */ 138 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */ 139 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */ 140 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */ 141 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */ 142 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */ 143 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */ 144 145 /* I2C SCL time value when Master */ 146 #define OMAP_I2C_SCLL_HSSCLL 8 147 #define OMAP_I2C_SCLH_HSSCLH 8 148 149 /* I2C System Test Register (OMAP_I2C_SYSTEST): */ 150 #ifdef DEBUG 151 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ 152 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */ 153 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ 154 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ 155 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */ 156 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */ 157 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */ 158 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */ 159 #endif 160 161 /* OCP_SYSSTATUS bit definitions */ 162 #define SYSS_RESETDONE_MASK (1 << 0) 163 164 /* OCP_SYSCONFIG bit definitions */ 165 #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8) 166 #define SYSC_SIDLEMODE_MASK (0x3 << 3) 167 #define SYSC_ENAWAKEUP_MASK (1 << 2) 168 #define SYSC_SOFTRESET_MASK (1 << 1) 169 #define SYSC_AUTOIDLE_MASK (1 << 0) 170 171 #define SYSC_IDLEMODE_SMART 0x2 172 #define SYSC_CLOCKACTIVITY_FCLK 0x2 173 174 /* Errata definitions */ 175 #define I2C_OMAP_ERRATA_I207 (1 << 0) 176 #define I2C_OMAP_ERRATA_I462 (1 << 1) 177 178 struct omap_i2c_dev { 179 struct device *dev; 180 void __iomem *base; /* virtual */ 181 int irq; 182 int reg_shift; /* bit shift for I2C register addresses */ 183 struct completion cmd_complete; 184 struct resource *ioarea; 185 u32 latency; /* maximum mpu wkup latency */ 186 void (*set_mpu_wkup_lat)(struct device *dev, 187 long latency); 188 u32 speed; /* Speed of bus in kHz */ 189 u32 dtrev; /* extra revision from DT */ 190 u32 flags; 191 u16 cmd_err; 192 u8 *buf; 193 u8 *regs; 194 size_t buf_len; 195 struct i2c_adapter adapter; 196 u8 fifo_size; /* use as flag and value 197 * fifo_size==0 implies no fifo 198 * if set, should be trsh+1 199 */ 200 u8 rev; 201 unsigned b_hw:1; /* bad h/w fixes */ 202 u16 iestate; /* Saved interrupt register */ 203 u16 pscstate; 204 u16 scllstate; 205 u16 sclhstate; 206 u16 bufstate; 207 u16 syscstate; 208 u16 westate; 209 u16 errata; 210 }; 211 212 static const u8 reg_map_ip_v1[] = { 213 [OMAP_I2C_REV_REG] = 0x00, 214 [OMAP_I2C_IE_REG] = 0x01, 215 [OMAP_I2C_STAT_REG] = 0x02, 216 [OMAP_I2C_IV_REG] = 0x03, 217 [OMAP_I2C_WE_REG] = 0x03, 218 [OMAP_I2C_SYSS_REG] = 0x04, 219 [OMAP_I2C_BUF_REG] = 0x05, 220 [OMAP_I2C_CNT_REG] = 0x06, 221 [OMAP_I2C_DATA_REG] = 0x07, 222 [OMAP_I2C_SYSC_REG] = 0x08, 223 [OMAP_I2C_CON_REG] = 0x09, 224 [OMAP_I2C_OA_REG] = 0x0a, 225 [OMAP_I2C_SA_REG] = 0x0b, 226 [OMAP_I2C_PSC_REG] = 0x0c, 227 [OMAP_I2C_SCLL_REG] = 0x0d, 228 [OMAP_I2C_SCLH_REG] = 0x0e, 229 [OMAP_I2C_SYSTEST_REG] = 0x0f, 230 [OMAP_I2C_BUFSTAT_REG] = 0x10, 231 }; 232 233 static const u8 reg_map_ip_v2[] = { 234 [OMAP_I2C_REV_REG] = 0x04, 235 [OMAP_I2C_IE_REG] = 0x2c, 236 [OMAP_I2C_STAT_REG] = 0x28, 237 [OMAP_I2C_IV_REG] = 0x34, 238 [OMAP_I2C_WE_REG] = 0x34, 239 [OMAP_I2C_SYSS_REG] = 0x90, 240 [OMAP_I2C_BUF_REG] = 0x94, 241 [OMAP_I2C_CNT_REG] = 0x98, 242 [OMAP_I2C_DATA_REG] = 0x9c, 243 [OMAP_I2C_SYSC_REG] = 0x10, 244 [OMAP_I2C_CON_REG] = 0xa4, 245 [OMAP_I2C_OA_REG] = 0xa8, 246 [OMAP_I2C_SA_REG] = 0xac, 247 [OMAP_I2C_PSC_REG] = 0xb0, 248 [OMAP_I2C_SCLL_REG] = 0xb4, 249 [OMAP_I2C_SCLH_REG] = 0xb8, 250 [OMAP_I2C_SYSTEST_REG] = 0xbC, 251 [OMAP_I2C_BUFSTAT_REG] = 0xc0, 252 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00, 253 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04, 254 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24, 255 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c, 256 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30, 257 }; 258 259 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, 260 int reg, u16 val) 261 { 262 __raw_writew(val, i2c_dev->base + 263 (i2c_dev->regs[reg] << i2c_dev->reg_shift)); 264 } 265 266 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) 267 { 268 return __raw_readw(i2c_dev->base + 269 (i2c_dev->regs[reg] << i2c_dev->reg_shift)); 270 } 271 272 static int omap_i2c_init(struct omap_i2c_dev *dev) 273 { 274 u16 psc = 0, scll = 0, sclh = 0, buf = 0; 275 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0; 276 unsigned long fclk_rate = 12000000; 277 unsigned long timeout; 278 unsigned long internal_clk = 0; 279 struct clk *fclk; 280 281 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) { 282 /* Disable I2C controller before soft reset */ 283 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 284 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & 285 ~(OMAP_I2C_CON_EN)); 286 287 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK); 288 /* For some reason we need to set the EN bit before the 289 * reset done bit gets set. */ 290 timeout = jiffies + OMAP_I2C_TIMEOUT; 291 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); 292 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) & 293 SYSS_RESETDONE_MASK)) { 294 if (time_after(jiffies, timeout)) { 295 dev_warn(dev->dev, "timeout waiting " 296 "for controller reset\n"); 297 return -ETIMEDOUT; 298 } 299 msleep(1); 300 } 301 302 /* SYSC register is cleared by the reset; rewrite it */ 303 if (dev->rev == OMAP_I2C_REV_ON_2430) { 304 305 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, 306 SYSC_AUTOIDLE_MASK); 307 308 } else if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) { 309 dev->syscstate = SYSC_AUTOIDLE_MASK; 310 dev->syscstate |= SYSC_ENAWAKEUP_MASK; 311 dev->syscstate |= (SYSC_IDLEMODE_SMART << 312 __ffs(SYSC_SIDLEMODE_MASK)); 313 dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK << 314 __ffs(SYSC_CLOCKACTIVITY_MASK)); 315 316 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, 317 dev->syscstate); 318 /* 319 * Enabling all wakup sources to stop I2C freezing on 320 * WFI instruction. 321 * REVISIT: Some wkup sources might not be needed. 322 */ 323 dev->westate = OMAP_I2C_WE_ALL; 324 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, 325 dev->westate); 326 } 327 } 328 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 329 330 if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) { 331 /* 332 * The I2C functional clock is the armxor_ck, so there's 333 * no need to get "armxor_ck" separately. Now, if OMAP2420 334 * always returns 12MHz for the functional clock, we can 335 * do this bit unconditionally. 336 */ 337 fclk = clk_get(dev->dev, "fck"); 338 fclk_rate = clk_get_rate(fclk); 339 clk_put(fclk); 340 341 /* TRM for 5912 says the I2C clock must be prescaled to be 342 * between 7 - 12 MHz. The XOR input clock is typically 343 * 12, 13 or 19.2 MHz. So we should have code that produces: 344 * 345 * XOR MHz Divider Prescaler 346 * 12 1 0 347 * 13 2 1 348 * 19.2 2 1 349 */ 350 if (fclk_rate > 12000000) 351 psc = fclk_rate / 12000000; 352 } 353 354 if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) { 355 356 /* 357 * HSI2C controller internal clk rate should be 19.2 Mhz for 358 * HS and for all modes on 2430. On 34xx we can use lower rate 359 * to get longer filter period for better noise suppression. 360 * The filter is iclk (fclk for HS) period. 361 */ 362 if (dev->speed > 400 || 363 dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK) 364 internal_clk = 19200; 365 else if (dev->speed > 100) 366 internal_clk = 9600; 367 else 368 internal_clk = 4000; 369 fclk = clk_get(dev->dev, "fck"); 370 fclk_rate = clk_get_rate(fclk) / 1000; 371 clk_put(fclk); 372 373 /* Compute prescaler divisor */ 374 psc = fclk_rate / internal_clk; 375 psc = psc - 1; 376 377 /* If configured for High Speed */ 378 if (dev->speed > 400) { 379 unsigned long scl; 380 381 /* For first phase of HS mode */ 382 scl = internal_clk / 400; 383 fsscll = scl - (scl / 3) - 7; 384 fssclh = (scl / 3) - 5; 385 386 /* For second phase of HS mode */ 387 scl = fclk_rate / dev->speed; 388 hsscll = scl - (scl / 3) - 7; 389 hssclh = (scl / 3) - 5; 390 } else if (dev->speed > 100) { 391 unsigned long scl; 392 393 /* Fast mode */ 394 scl = internal_clk / dev->speed; 395 fsscll = scl - (scl / 3) - 7; 396 fssclh = (scl / 3) - 5; 397 } else { 398 /* Standard mode */ 399 fsscll = internal_clk / (dev->speed * 2) - 7; 400 fssclh = internal_clk / (dev->speed * 2) - 5; 401 } 402 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; 403 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; 404 } else { 405 /* Program desired operating rate */ 406 fclk_rate /= (psc + 1) * 1000; 407 if (psc > 2) 408 psc = 2; 409 scll = fclk_rate / (dev->speed * 2) - 7 + psc; 410 sclh = fclk_rate / (dev->speed * 2) - 7 + psc; 411 } 412 413 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ 414 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc); 415 416 /* SCL low and high time values */ 417 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll); 418 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh); 419 420 if (dev->fifo_size) { 421 /* Note: setup required fifo size - 1. RTRSH and XTRSH */ 422 buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR | 423 (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR; 424 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf); 425 } 426 427 /* Take the I2C module out of reset: */ 428 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); 429 430 /* Enable interrupts */ 431 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | 432 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | 433 OMAP_I2C_IE_AL) | ((dev->fifo_size) ? 434 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); 435 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); 436 if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) { 437 dev->pscstate = psc; 438 dev->scllstate = scll; 439 dev->sclhstate = sclh; 440 dev->bufstate = buf; 441 } 442 return 0; 443 } 444 445 /* 446 * Waiting on Bus Busy 447 */ 448 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev) 449 { 450 unsigned long timeout; 451 452 timeout = jiffies + OMAP_I2C_TIMEOUT; 453 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) { 454 if (time_after(jiffies, timeout)) { 455 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 456 return -ETIMEDOUT; 457 } 458 msleep(1); 459 } 460 461 return 0; 462 } 463 464 /* 465 * Low level master read/write transaction. 466 */ 467 static int omap_i2c_xfer_msg(struct i2c_adapter *adap, 468 struct i2c_msg *msg, int stop) 469 { 470 struct omap_i2c_dev *dev = i2c_get_adapdata(adap); 471 unsigned long timeout; 472 u16 w; 473 474 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", 475 msg->addr, msg->len, msg->flags, stop); 476 477 if (msg->len == 0) 478 return -EINVAL; 479 480 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr); 481 482 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */ 483 dev->buf = msg->buf; 484 dev->buf_len = msg->len; 485 486 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len); 487 488 /* Clear the FIFO Buffers */ 489 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG); 490 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR; 491 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w); 492 493 INIT_COMPLETION(dev->cmd_complete); 494 dev->cmd_err = 0; 495 496 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT; 497 498 /* High speed configuration */ 499 if (dev->speed > 400) 500 w |= OMAP_I2C_CON_OPMODE_HS; 501 502 if (msg->flags & I2C_M_STOP) 503 stop = 1; 504 if (msg->flags & I2C_M_TEN) 505 w |= OMAP_I2C_CON_XA; 506 if (!(msg->flags & I2C_M_RD)) 507 w |= OMAP_I2C_CON_TRX; 508 509 if (!dev->b_hw && stop) 510 w |= OMAP_I2C_CON_STP; 511 512 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); 513 514 /* 515 * Don't write stt and stp together on some hardware. 516 */ 517 if (dev->b_hw && stop) { 518 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT; 519 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); 520 while (con & OMAP_I2C_CON_STT) { 521 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); 522 523 /* Let the user know if i2c is in a bad state */ 524 if (time_after(jiffies, delay)) { 525 dev_err(dev->dev, "controller timed out " 526 "waiting for start condition to finish\n"); 527 return -ETIMEDOUT; 528 } 529 cpu_relax(); 530 } 531 532 w |= OMAP_I2C_CON_STP; 533 w &= ~OMAP_I2C_CON_STT; 534 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); 535 } 536 537 /* 538 * REVISIT: We should abort the transfer on signals, but the bus goes 539 * into arbitration and we're currently unable to recover from it. 540 */ 541 timeout = wait_for_completion_timeout(&dev->cmd_complete, 542 OMAP_I2C_TIMEOUT); 543 dev->buf_len = 0; 544 if (timeout == 0) { 545 dev_err(dev->dev, "controller timed out\n"); 546 omap_i2c_init(dev); 547 return -ETIMEDOUT; 548 } 549 550 if (likely(!dev->cmd_err)) 551 return 0; 552 553 /* We have an error */ 554 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR | 555 OMAP_I2C_STAT_XUDF)) { 556 omap_i2c_init(dev); 557 return -EIO; 558 } 559 560 if (dev->cmd_err & OMAP_I2C_STAT_NACK) { 561 if (msg->flags & I2C_M_IGNORE_NAK) 562 return 0; 563 if (stop) { 564 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); 565 w |= OMAP_I2C_CON_STP; 566 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); 567 } 568 return -EREMOTEIO; 569 } 570 return -EIO; 571 } 572 573 574 /* 575 * Prepare controller for a transaction and call omap_i2c_xfer_msg 576 * to do the work during IRQ processing. 577 */ 578 static int 579 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 580 { 581 struct omap_i2c_dev *dev = i2c_get_adapdata(adap); 582 int i; 583 int r; 584 585 r = pm_runtime_get_sync(dev->dev); 586 if (IS_ERR_VALUE(r)) 587 goto out; 588 589 r = omap_i2c_wait_for_bb(dev); 590 if (r < 0) 591 goto out; 592 593 if (dev->set_mpu_wkup_lat != NULL) 594 dev->set_mpu_wkup_lat(dev->dev, dev->latency); 595 596 for (i = 0; i < num; i++) { 597 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1))); 598 if (r != 0) 599 break; 600 } 601 602 if (dev->set_mpu_wkup_lat != NULL) 603 dev->set_mpu_wkup_lat(dev->dev, -1); 604 605 if (r == 0) 606 r = num; 607 608 omap_i2c_wait_for_bb(dev); 609 out: 610 pm_runtime_put(dev->dev); 611 return r; 612 } 613 614 static u32 615 omap_i2c_func(struct i2c_adapter *adap) 616 { 617 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 618 I2C_FUNC_PROTOCOL_MANGLING; 619 } 620 621 static inline void 622 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err) 623 { 624 dev->cmd_err |= err; 625 complete(&dev->cmd_complete); 626 } 627 628 static inline void 629 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat) 630 { 631 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat); 632 } 633 634 static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat) 635 { 636 /* 637 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8) 638 * Not applicable for OMAP4. 639 * Under certain rare conditions, RDR could be set again 640 * when the bus is busy, then ignore the interrupt and 641 * clear the interrupt. 642 */ 643 if (stat & OMAP_I2C_STAT_RDR) { 644 /* Step 1: If RDR is set, clear it */ 645 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); 646 647 /* Step 2: */ 648 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) 649 & OMAP_I2C_STAT_BB)) { 650 651 /* Step 3: */ 652 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) 653 & OMAP_I2C_STAT_RDR) { 654 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); 655 dev_dbg(dev->dev, "RDR when bus is busy.\n"); 656 } 657 658 } 659 } 660 } 661 662 /* rev1 devices are apparently only on some 15xx */ 663 #ifdef CONFIG_ARCH_OMAP15XX 664 665 static irqreturn_t 666 omap_i2c_omap1_isr(int this_irq, void *dev_id) 667 { 668 struct omap_i2c_dev *dev = dev_id; 669 u16 iv, w; 670 671 if (pm_runtime_suspended(dev->dev)) 672 return IRQ_NONE; 673 674 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); 675 switch (iv) { 676 case 0x00: /* None */ 677 break; 678 case 0x01: /* Arbitration lost */ 679 dev_err(dev->dev, "Arbitration lost\n"); 680 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL); 681 break; 682 case 0x02: /* No acknowledgement */ 683 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK); 684 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP); 685 break; 686 case 0x03: /* Register access ready */ 687 omap_i2c_complete_cmd(dev, 0); 688 break; 689 case 0x04: /* Receive data ready */ 690 if (dev->buf_len) { 691 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); 692 *dev->buf++ = w; 693 dev->buf_len--; 694 if (dev->buf_len) { 695 *dev->buf++ = w >> 8; 696 dev->buf_len--; 697 } 698 } else 699 dev_err(dev->dev, "RRDY IRQ while no data requested\n"); 700 break; 701 case 0x05: /* Transmit data ready */ 702 if (dev->buf_len) { 703 w = *dev->buf++; 704 dev->buf_len--; 705 if (dev->buf_len) { 706 w |= *dev->buf++ << 8; 707 dev->buf_len--; 708 } 709 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); 710 } else 711 dev_err(dev->dev, "XRDY IRQ while no data to send\n"); 712 break; 713 default: 714 return IRQ_NONE; 715 } 716 717 return IRQ_HANDLED; 718 } 719 #else 720 #define omap_i2c_omap1_isr NULL 721 #endif 722 723 /* 724 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing 725 * data to DATA_REG. Otherwise some data bytes can be lost while transferring 726 * them from the memory to the I2C interface. 727 */ 728 static int errata_omap3_i462(struct omap_i2c_dev *dev, u16 *stat, int *err) 729 { 730 unsigned long timeout = 10000; 731 732 while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) { 733 if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) { 734 omap_i2c_ack_stat(dev, *stat & (OMAP_I2C_STAT_XRDY | 735 OMAP_I2C_STAT_XDR)); 736 return -ETIMEDOUT; 737 } 738 739 cpu_relax(); 740 *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); 741 } 742 743 if (!timeout) { 744 dev_err(dev->dev, "timeout waiting on XUDF bit\n"); 745 return 0; 746 } 747 748 *err |= OMAP_I2C_STAT_XUDF; 749 return 0; 750 } 751 752 static irqreturn_t 753 omap_i2c_isr(int this_irq, void *dev_id) 754 { 755 struct omap_i2c_dev *dev = dev_id; 756 u16 bits; 757 u16 stat, w; 758 int err, count = 0; 759 760 if (pm_runtime_suspended(dev->dev)) 761 return IRQ_NONE; 762 763 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); 764 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) { 765 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat); 766 if (count++ == 100) { 767 dev_warn(dev->dev, "Too much work in one IRQ\n"); 768 break; 769 } 770 771 err = 0; 772 complete: 773 /* 774 * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be 775 * acked after the data operation is complete. 776 * Ref: TRM SWPU114Q Figure 18-31 777 */ 778 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat & 779 ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR | 780 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)); 781 782 if (stat & OMAP_I2C_STAT_NACK) 783 err |= OMAP_I2C_STAT_NACK; 784 785 if (stat & OMAP_I2C_STAT_AL) { 786 dev_err(dev->dev, "Arbitration lost\n"); 787 err |= OMAP_I2C_STAT_AL; 788 } 789 /* 790 * ProDB0017052: Clear ARDY bit twice 791 */ 792 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK | 793 OMAP_I2C_STAT_AL)) { 794 omap_i2c_ack_stat(dev, stat & 795 (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR | 796 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR | 797 OMAP_I2C_STAT_ARDY)); 798 omap_i2c_complete_cmd(dev, err); 799 return IRQ_HANDLED; 800 } 801 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) { 802 u8 num_bytes = 1; 803 804 if (dev->errata & I2C_OMAP_ERRATA_I207) 805 i2c_omap_errata_i207(dev, stat); 806 807 if (dev->fifo_size) { 808 if (stat & OMAP_I2C_STAT_RRDY) 809 num_bytes = dev->fifo_size; 810 else /* read RXSTAT on RDR interrupt */ 811 num_bytes = (omap_i2c_read_reg(dev, 812 OMAP_I2C_BUFSTAT_REG) 813 >> 8) & 0x3F; 814 } 815 while (num_bytes) { 816 num_bytes--; 817 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); 818 if (dev->buf_len) { 819 *dev->buf++ = w; 820 dev->buf_len--; 821 /* 822 * Data reg in 2430, omap3 and 823 * omap4 is 8 bit wide 824 */ 825 if (dev->flags & 826 OMAP_I2C_FLAG_16BIT_DATA_REG) { 827 if (dev->buf_len) { 828 *dev->buf++ = w >> 8; 829 dev->buf_len--; 830 } 831 } 832 } else { 833 if (stat & OMAP_I2C_STAT_RRDY) 834 dev_err(dev->dev, 835 "RRDY IRQ while no data" 836 " requested\n"); 837 if (stat & OMAP_I2C_STAT_RDR) 838 dev_err(dev->dev, 839 "RDR IRQ while no data" 840 " requested\n"); 841 break; 842 } 843 } 844 omap_i2c_ack_stat(dev, 845 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)); 846 continue; 847 } 848 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) { 849 u8 num_bytes = 1; 850 if (dev->fifo_size) { 851 if (stat & OMAP_I2C_STAT_XRDY) 852 num_bytes = dev->fifo_size; 853 else /* read TXSTAT on XDR interrupt */ 854 num_bytes = omap_i2c_read_reg(dev, 855 OMAP_I2C_BUFSTAT_REG) 856 & 0x3F; 857 } 858 while (num_bytes) { 859 num_bytes--; 860 w = 0; 861 if (dev->buf_len) { 862 w = *dev->buf++; 863 dev->buf_len--; 864 /* 865 * Data reg in 2430, omap3 and 866 * omap4 is 8 bit wide 867 */ 868 if (dev->flags & 869 OMAP_I2C_FLAG_16BIT_DATA_REG) { 870 if (dev->buf_len) { 871 w |= *dev->buf++ << 8; 872 dev->buf_len--; 873 } 874 } 875 } else { 876 if (stat & OMAP_I2C_STAT_XRDY) 877 dev_err(dev->dev, 878 "XRDY IRQ while no " 879 "data to send\n"); 880 if (stat & OMAP_I2C_STAT_XDR) 881 dev_err(dev->dev, 882 "XDR IRQ while no " 883 "data to send\n"); 884 break; 885 } 886 887 if ((dev->errata & I2C_OMAP_ERRATA_I462) && 888 errata_omap3_i462(dev, &stat, &err)) 889 goto complete; 890 891 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); 892 } 893 omap_i2c_ack_stat(dev, 894 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)); 895 continue; 896 } 897 if (stat & OMAP_I2C_STAT_ROVR) { 898 dev_err(dev->dev, "Receive overrun\n"); 899 dev->cmd_err |= OMAP_I2C_STAT_ROVR; 900 } 901 if (stat & OMAP_I2C_STAT_XUDF) { 902 dev_err(dev->dev, "Transmit underflow\n"); 903 dev->cmd_err |= OMAP_I2C_STAT_XUDF; 904 } 905 } 906 907 return count ? IRQ_HANDLED : IRQ_NONE; 908 } 909 910 static const struct i2c_algorithm omap_i2c_algo = { 911 .master_xfer = omap_i2c_xfer, 912 .functionality = omap_i2c_func, 913 }; 914 915 #ifdef CONFIG_OF 916 static struct omap_i2c_bus_platform_data omap3_pdata = { 917 .rev = OMAP_I2C_IP_VERSION_1, 918 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 919 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | 920 OMAP_I2C_FLAG_BUS_SHIFT_2, 921 }; 922 923 static struct omap_i2c_bus_platform_data omap4_pdata = { 924 .rev = OMAP_I2C_IP_VERSION_2, 925 }; 926 927 static const struct of_device_id omap_i2c_of_match[] = { 928 { 929 .compatible = "ti,omap4-i2c", 930 .data = &omap4_pdata, 931 }, 932 { 933 .compatible = "ti,omap3-i2c", 934 .data = &omap3_pdata, 935 }, 936 { }, 937 }; 938 MODULE_DEVICE_TABLE(of, omap_i2c_of_match); 939 #endif 940 941 static int __devinit 942 omap_i2c_probe(struct platform_device *pdev) 943 { 944 struct omap_i2c_dev *dev; 945 struct i2c_adapter *adap; 946 struct resource *mem, *irq, *ioarea; 947 struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data; 948 struct device_node *node = pdev->dev.of_node; 949 const struct of_device_id *match; 950 irq_handler_t isr; 951 int r; 952 953 /* NOTE: driver uses the static register mapping */ 954 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 955 if (!mem) { 956 dev_err(&pdev->dev, "no mem resource?\n"); 957 return -ENODEV; 958 } 959 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 960 if (!irq) { 961 dev_err(&pdev->dev, "no irq resource?\n"); 962 return -ENODEV; 963 } 964 965 ioarea = request_mem_region(mem->start, resource_size(mem), 966 pdev->name); 967 if (!ioarea) { 968 dev_err(&pdev->dev, "I2C region already claimed\n"); 969 return -EBUSY; 970 } 971 972 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL); 973 if (!dev) { 974 r = -ENOMEM; 975 goto err_release_region; 976 } 977 978 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev); 979 if (match) { 980 u32 freq = 100000; /* default to 100000 Hz */ 981 982 pdata = match->data; 983 dev->dtrev = pdata->rev; 984 dev->flags = pdata->flags; 985 986 of_property_read_u32(node, "clock-frequency", &freq); 987 /* convert DT freq value in Hz into kHz for speed */ 988 dev->speed = freq / 1000; 989 } else if (pdata != NULL) { 990 dev->speed = pdata->clkrate; 991 dev->flags = pdata->flags; 992 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat; 993 dev->dtrev = pdata->rev; 994 } 995 996 dev->dev = &pdev->dev; 997 dev->irq = irq->start; 998 dev->base = ioremap(mem->start, resource_size(mem)); 999 if (!dev->base) { 1000 r = -ENOMEM; 1001 goto err_free_mem; 1002 } 1003 1004 platform_set_drvdata(pdev, dev); 1005 init_completion(&dev->cmd_complete); 1006 1007 dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3; 1008 1009 if (dev->dtrev == OMAP_I2C_IP_VERSION_2) 1010 dev->regs = (u8 *)reg_map_ip_v2; 1011 else 1012 dev->regs = (u8 *)reg_map_ip_v1; 1013 1014 pm_runtime_enable(dev->dev); 1015 r = pm_runtime_get_sync(dev->dev); 1016 if (IS_ERR_VALUE(r)) 1017 goto err_free_mem; 1018 1019 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff; 1020 1021 dev->errata = 0; 1022 1023 if (dev->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207) 1024 dev->errata |= I2C_OMAP_ERRATA_I207; 1025 1026 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530) 1027 dev->errata |= I2C_OMAP_ERRATA_I462; 1028 1029 if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) { 1030 u16 s; 1031 1032 /* Set up the fifo size - Get total size */ 1033 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3; 1034 dev->fifo_size = 0x8 << s; 1035 1036 /* 1037 * Set up notification threshold as half the total available 1038 * size. This is to ensure that we can handle the status on int 1039 * call back latencies. 1040 */ 1041 1042 dev->fifo_size = (dev->fifo_size / 2); 1043 1044 if (dev->rev >= OMAP_I2C_REV_ON_3630_4430) 1045 dev->b_hw = 0; /* Disable hardware fixes */ 1046 else 1047 dev->b_hw = 1; /* Enable hardware fixes */ 1048 1049 /* calculate wakeup latency constraint for MPU */ 1050 if (dev->set_mpu_wkup_lat != NULL) 1051 dev->latency = (1000000 * dev->fifo_size) / 1052 (1000 * dev->speed / 8); 1053 } 1054 1055 /* reset ASAP, clearing any IRQs */ 1056 omap_i2c_init(dev); 1057 1058 isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr : 1059 omap_i2c_isr; 1060 r = request_irq(dev->irq, isr, IRQF_NO_SUSPEND, pdev->name, dev); 1061 1062 if (r) { 1063 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq); 1064 goto err_unuse_clocks; 1065 } 1066 1067 dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", pdev->id, 1068 dev->dtrev, dev->rev >> 4, dev->rev & 0xf, dev->speed); 1069 1070 adap = &dev->adapter; 1071 i2c_set_adapdata(adap, dev); 1072 adap->owner = THIS_MODULE; 1073 adap->class = I2C_CLASS_HWMON; 1074 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); 1075 adap->algo = &omap_i2c_algo; 1076 adap->dev.parent = &pdev->dev; 1077 adap->dev.of_node = pdev->dev.of_node; 1078 1079 /* i2c device drivers may be active on return from add_adapter() */ 1080 adap->nr = pdev->id; 1081 r = i2c_add_numbered_adapter(adap); 1082 if (r) { 1083 dev_err(dev->dev, "failure adding adapter\n"); 1084 goto err_free_irq; 1085 } 1086 1087 of_i2c_register_devices(adap); 1088 1089 pm_runtime_put(dev->dev); 1090 1091 return 0; 1092 1093 err_free_irq: 1094 free_irq(dev->irq, dev); 1095 err_unuse_clocks: 1096 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 1097 pm_runtime_put(dev->dev); 1098 iounmap(dev->base); 1099 pm_runtime_disable(&pdev->dev); 1100 err_free_mem: 1101 platform_set_drvdata(pdev, NULL); 1102 kfree(dev); 1103 err_release_region: 1104 release_mem_region(mem->start, resource_size(mem)); 1105 1106 return r; 1107 } 1108 1109 static int __devexit omap_i2c_remove(struct platform_device *pdev) 1110 { 1111 struct omap_i2c_dev *dev = platform_get_drvdata(pdev); 1112 struct resource *mem; 1113 int ret; 1114 1115 platform_set_drvdata(pdev, NULL); 1116 1117 free_irq(dev->irq, dev); 1118 i2c_del_adapter(&dev->adapter); 1119 ret = pm_runtime_get_sync(&pdev->dev); 1120 if (IS_ERR_VALUE(ret)) 1121 return ret; 1122 1123 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 1124 pm_runtime_put(&pdev->dev); 1125 pm_runtime_disable(&pdev->dev); 1126 iounmap(dev->base); 1127 kfree(dev); 1128 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1129 release_mem_region(mem->start, resource_size(mem)); 1130 return 0; 1131 } 1132 1133 #ifdef CONFIG_PM 1134 #ifdef CONFIG_PM_RUNTIME 1135 static int omap_i2c_runtime_suspend(struct device *dev) 1136 { 1137 struct platform_device *pdev = to_platform_device(dev); 1138 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev); 1139 u16 iv; 1140 1141 _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG); 1142 1143 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0); 1144 1145 if (_dev->rev < OMAP_I2C_OMAP1_REV_2) { 1146 iv = omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */ 1147 } else { 1148 omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate); 1149 1150 /* Flush posted write */ 1151 omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG); 1152 } 1153 1154 return 0; 1155 } 1156 1157 static int omap_i2c_runtime_resume(struct device *dev) 1158 { 1159 struct platform_device *pdev = to_platform_device(dev); 1160 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev); 1161 1162 if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) { 1163 omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, 0); 1164 omap_i2c_write_reg(_dev, OMAP_I2C_PSC_REG, _dev->pscstate); 1165 omap_i2c_write_reg(_dev, OMAP_I2C_SCLL_REG, _dev->scllstate); 1166 omap_i2c_write_reg(_dev, OMAP_I2C_SCLH_REG, _dev->sclhstate); 1167 omap_i2c_write_reg(_dev, OMAP_I2C_BUF_REG, _dev->bufstate); 1168 omap_i2c_write_reg(_dev, OMAP_I2C_SYSC_REG, _dev->syscstate); 1169 omap_i2c_write_reg(_dev, OMAP_I2C_WE_REG, _dev->westate); 1170 omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); 1171 } 1172 1173 /* 1174 * Don't write to this register if the IE state is 0 as it can 1175 * cause deadlock. 1176 */ 1177 if (_dev->iestate) 1178 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, _dev->iestate); 1179 1180 return 0; 1181 } 1182 #endif /* CONFIG_PM_RUNTIME */ 1183 1184 static struct dev_pm_ops omap_i2c_pm_ops = { 1185 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend, 1186 omap_i2c_runtime_resume, NULL) 1187 }; 1188 #define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops) 1189 #else 1190 #define OMAP_I2C_PM_OPS NULL 1191 #endif /* CONFIG_PM */ 1192 1193 static struct platform_driver omap_i2c_driver = { 1194 .probe = omap_i2c_probe, 1195 .remove = __devexit_p(omap_i2c_remove), 1196 .driver = { 1197 .name = "omap_i2c", 1198 .owner = THIS_MODULE, 1199 .pm = OMAP_I2C_PM_OPS, 1200 .of_match_table = of_match_ptr(omap_i2c_of_match), 1201 }, 1202 }; 1203 1204 /* I2C may be needed to bring up other drivers */ 1205 static int __init 1206 omap_i2c_init_driver(void) 1207 { 1208 return platform_driver_register(&omap_i2c_driver); 1209 } 1210 subsys_initcall(omap_i2c_init_driver); 1211 1212 static void __exit omap_i2c_exit_driver(void) 1213 { 1214 platform_driver_unregister(&omap_i2c_driver); 1215 } 1216 module_exit(omap_i2c_exit_driver); 1217 1218 MODULE_AUTHOR("MontaVista Software, Inc. (and others)"); 1219 MODULE_DESCRIPTION("TI OMAP I2C bus adapter"); 1220 MODULE_LICENSE("GPL"); 1221 MODULE_ALIAS("platform:omap_i2c"); 1222