1 /* 2 * TI OMAP I2C master mode driver 3 * 4 * Copyright (C) 2003 MontaVista Software, Inc. 5 * Copyright (C) 2005 Nokia Corporation 6 * Copyright (C) 2004 - 2007 Texas Instruments. 7 * 8 * Originally written by MontaVista Software, Inc. 9 * Additional contributions by: 10 * Tony Lindgren <tony@atomide.com> 11 * Imre Deak <imre.deak@nokia.com> 12 * Juha Yrjölä <juha.yrjola@solidboot.com> 13 * Syed Khasim <x0khasim@ti.com> 14 * Nishant Menon <nm@ti.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2 of the License, or 19 * (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 29 */ 30 31 #include <linux/module.h> 32 #include <linux/delay.h> 33 #include <linux/i2c.h> 34 #include <linux/err.h> 35 #include <linux/interrupt.h> 36 #include <linux/completion.h> 37 #include <linux/platform_device.h> 38 #include <linux/clk.h> 39 #include <linux/io.h> 40 #include <linux/of.h> 41 #include <linux/of_i2c.h> 42 #include <linux/of_device.h> 43 #include <linux/slab.h> 44 #include <linux/i2c-omap.h> 45 #include <linux/pm_runtime.h> 46 #include <linux/pm_qos.h> 47 48 /* I2C controller revisions */ 49 #define OMAP_I2C_OMAP1_REV_2 0x20 50 51 /* I2C controller revisions present on specific hardware */ 52 #define OMAP_I2C_REV_ON_2430 0x36 53 #define OMAP_I2C_REV_ON_3430_3530 0x3C 54 #define OMAP_I2C_REV_ON_3630_4430 0x40 55 56 /* timeout waiting for the controller to respond */ 57 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) 58 59 /* timeout for pm runtime autosuspend */ 60 #define OMAP_I2C_PM_TIMEOUT 1000 /* ms */ 61 62 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ 63 enum { 64 OMAP_I2C_REV_REG = 0, 65 OMAP_I2C_IE_REG, 66 OMAP_I2C_STAT_REG, 67 OMAP_I2C_IV_REG, 68 OMAP_I2C_WE_REG, 69 OMAP_I2C_SYSS_REG, 70 OMAP_I2C_BUF_REG, 71 OMAP_I2C_CNT_REG, 72 OMAP_I2C_DATA_REG, 73 OMAP_I2C_SYSC_REG, 74 OMAP_I2C_CON_REG, 75 OMAP_I2C_OA_REG, 76 OMAP_I2C_SA_REG, 77 OMAP_I2C_PSC_REG, 78 OMAP_I2C_SCLL_REG, 79 OMAP_I2C_SCLH_REG, 80 OMAP_I2C_SYSTEST_REG, 81 OMAP_I2C_BUFSTAT_REG, 82 /* only on OMAP4430 */ 83 OMAP_I2C_IP_V2_REVNB_LO, 84 OMAP_I2C_IP_V2_REVNB_HI, 85 OMAP_I2C_IP_V2_IRQSTATUS_RAW, 86 OMAP_I2C_IP_V2_IRQENABLE_SET, 87 OMAP_I2C_IP_V2_IRQENABLE_CLR, 88 }; 89 90 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */ 91 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ 92 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */ 93 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */ 94 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */ 95 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */ 96 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */ 97 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */ 98 99 /* I2C Status Register (OMAP_I2C_STAT): */ 100 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */ 101 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */ 102 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */ 103 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ 104 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ 105 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */ 106 #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */ 107 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ 108 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ 109 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */ 110 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */ 111 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */ 112 113 /* I2C WE wakeup enable register */ 114 #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */ 115 #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */ 116 #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/ 117 #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */ 118 #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */ 119 #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */ 120 #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */ 121 #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */ 122 #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */ 123 #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */ 124 125 #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \ 126 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \ 127 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \ 128 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \ 129 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE) 130 131 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */ 132 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */ 133 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */ 134 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */ 135 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */ 136 137 /* I2C Configuration Register (OMAP_I2C_CON): */ 138 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */ 139 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */ 140 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */ 141 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */ 142 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */ 143 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */ 144 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */ 145 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */ 146 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */ 147 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */ 148 149 /* I2C SCL time value when Master */ 150 #define OMAP_I2C_SCLL_HSSCLL 8 151 #define OMAP_I2C_SCLH_HSSCLH 8 152 153 /* I2C System Test Register (OMAP_I2C_SYSTEST): */ 154 #ifdef DEBUG 155 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ 156 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */ 157 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ 158 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ 159 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */ 160 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */ 161 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */ 162 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */ 163 #endif 164 165 /* OCP_SYSSTATUS bit definitions */ 166 #define SYSS_RESETDONE_MASK (1 << 0) 167 168 /* OCP_SYSCONFIG bit definitions */ 169 #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8) 170 #define SYSC_SIDLEMODE_MASK (0x3 << 3) 171 #define SYSC_ENAWAKEUP_MASK (1 << 2) 172 #define SYSC_SOFTRESET_MASK (1 << 1) 173 #define SYSC_AUTOIDLE_MASK (1 << 0) 174 175 #define SYSC_IDLEMODE_SMART 0x2 176 #define SYSC_CLOCKACTIVITY_FCLK 0x2 177 178 /* Errata definitions */ 179 #define I2C_OMAP_ERRATA_I207 (1 << 0) 180 #define I2C_OMAP_ERRATA_I462 (1 << 1) 181 182 struct omap_i2c_dev { 183 spinlock_t lock; /* IRQ synchronization */ 184 struct device *dev; 185 void __iomem *base; /* virtual */ 186 int irq; 187 int reg_shift; /* bit shift for I2C register addresses */ 188 struct completion cmd_complete; 189 struct resource *ioarea; 190 u32 latency; /* maximum MPU wkup latency */ 191 struct pm_qos_request pm_qos_request; 192 u32 speed; /* Speed of bus in kHz */ 193 u32 dtrev; /* extra revision from DT */ 194 u32 flags; 195 u16 cmd_err; 196 u8 *buf; 197 u8 *regs; 198 size_t buf_len; 199 struct i2c_adapter adapter; 200 u8 threshold; 201 u8 fifo_size; /* use as flag and value 202 * fifo_size==0 implies no fifo 203 * if set, should be trsh+1 204 */ 205 u8 rev; 206 unsigned b_hw:1; /* bad h/w fixes */ 207 unsigned receiver:1; /* true when we're in receiver mode */ 208 u16 iestate; /* Saved interrupt register */ 209 u16 pscstate; 210 u16 scllstate; 211 u16 sclhstate; 212 u16 bufstate; 213 u16 syscstate; 214 u16 westate; 215 u16 errata; 216 }; 217 218 static const u8 reg_map_ip_v1[] = { 219 [OMAP_I2C_REV_REG] = 0x00, 220 [OMAP_I2C_IE_REG] = 0x01, 221 [OMAP_I2C_STAT_REG] = 0x02, 222 [OMAP_I2C_IV_REG] = 0x03, 223 [OMAP_I2C_WE_REG] = 0x03, 224 [OMAP_I2C_SYSS_REG] = 0x04, 225 [OMAP_I2C_BUF_REG] = 0x05, 226 [OMAP_I2C_CNT_REG] = 0x06, 227 [OMAP_I2C_DATA_REG] = 0x07, 228 [OMAP_I2C_SYSC_REG] = 0x08, 229 [OMAP_I2C_CON_REG] = 0x09, 230 [OMAP_I2C_OA_REG] = 0x0a, 231 [OMAP_I2C_SA_REG] = 0x0b, 232 [OMAP_I2C_PSC_REG] = 0x0c, 233 [OMAP_I2C_SCLL_REG] = 0x0d, 234 [OMAP_I2C_SCLH_REG] = 0x0e, 235 [OMAP_I2C_SYSTEST_REG] = 0x0f, 236 [OMAP_I2C_BUFSTAT_REG] = 0x10, 237 }; 238 239 static const u8 reg_map_ip_v2[] = { 240 [OMAP_I2C_REV_REG] = 0x04, 241 [OMAP_I2C_IE_REG] = 0x2c, 242 [OMAP_I2C_STAT_REG] = 0x28, 243 [OMAP_I2C_IV_REG] = 0x34, 244 [OMAP_I2C_WE_REG] = 0x34, 245 [OMAP_I2C_SYSS_REG] = 0x90, 246 [OMAP_I2C_BUF_REG] = 0x94, 247 [OMAP_I2C_CNT_REG] = 0x98, 248 [OMAP_I2C_DATA_REG] = 0x9c, 249 [OMAP_I2C_SYSC_REG] = 0x10, 250 [OMAP_I2C_CON_REG] = 0xa4, 251 [OMAP_I2C_OA_REG] = 0xa8, 252 [OMAP_I2C_SA_REG] = 0xac, 253 [OMAP_I2C_PSC_REG] = 0xb0, 254 [OMAP_I2C_SCLL_REG] = 0xb4, 255 [OMAP_I2C_SCLH_REG] = 0xb8, 256 [OMAP_I2C_SYSTEST_REG] = 0xbC, 257 [OMAP_I2C_BUFSTAT_REG] = 0xc0, 258 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00, 259 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04, 260 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24, 261 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c, 262 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30, 263 }; 264 265 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, 266 int reg, u16 val) 267 { 268 __raw_writew(val, i2c_dev->base + 269 (i2c_dev->regs[reg] << i2c_dev->reg_shift)); 270 } 271 272 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) 273 { 274 return __raw_readw(i2c_dev->base + 275 (i2c_dev->regs[reg] << i2c_dev->reg_shift)); 276 } 277 278 static int omap_i2c_init(struct omap_i2c_dev *dev) 279 { 280 u16 psc = 0, scll = 0, sclh = 0, buf = 0; 281 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0; 282 unsigned long fclk_rate = 12000000; 283 unsigned long timeout; 284 unsigned long internal_clk = 0; 285 struct clk *fclk; 286 287 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) { 288 /* Disable I2C controller before soft reset */ 289 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 290 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & 291 ~(OMAP_I2C_CON_EN)); 292 293 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK); 294 /* For some reason we need to set the EN bit before the 295 * reset done bit gets set. */ 296 timeout = jiffies + OMAP_I2C_TIMEOUT; 297 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); 298 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) & 299 SYSS_RESETDONE_MASK)) { 300 if (time_after(jiffies, timeout)) { 301 dev_warn(dev->dev, "timeout waiting " 302 "for controller reset\n"); 303 return -ETIMEDOUT; 304 } 305 msleep(1); 306 } 307 308 /* SYSC register is cleared by the reset; rewrite it */ 309 if (dev->rev == OMAP_I2C_REV_ON_2430) { 310 311 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, 312 SYSC_AUTOIDLE_MASK); 313 314 } else if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) { 315 dev->syscstate = SYSC_AUTOIDLE_MASK; 316 dev->syscstate |= SYSC_ENAWAKEUP_MASK; 317 dev->syscstate |= (SYSC_IDLEMODE_SMART << 318 __ffs(SYSC_SIDLEMODE_MASK)); 319 dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK << 320 __ffs(SYSC_CLOCKACTIVITY_MASK)); 321 322 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, 323 dev->syscstate); 324 /* 325 * Enabling all wakup sources to stop I2C freezing on 326 * WFI instruction. 327 * REVISIT: Some wkup sources might not be needed. 328 */ 329 dev->westate = OMAP_I2C_WE_ALL; 330 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, 331 dev->westate); 332 } 333 } 334 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 335 336 if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) { 337 /* 338 * The I2C functional clock is the armxor_ck, so there's 339 * no need to get "armxor_ck" separately. Now, if OMAP2420 340 * always returns 12MHz for the functional clock, we can 341 * do this bit unconditionally. 342 */ 343 fclk = clk_get(dev->dev, "fck"); 344 fclk_rate = clk_get_rate(fclk); 345 clk_put(fclk); 346 347 /* TRM for 5912 says the I2C clock must be prescaled to be 348 * between 7 - 12 MHz. The XOR input clock is typically 349 * 12, 13 or 19.2 MHz. So we should have code that produces: 350 * 351 * XOR MHz Divider Prescaler 352 * 12 1 0 353 * 13 2 1 354 * 19.2 2 1 355 */ 356 if (fclk_rate > 12000000) 357 psc = fclk_rate / 12000000; 358 } 359 360 if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) { 361 362 /* 363 * HSI2C controller internal clk rate should be 19.2 Mhz for 364 * HS and for all modes on 2430. On 34xx we can use lower rate 365 * to get longer filter period for better noise suppression. 366 * The filter is iclk (fclk for HS) period. 367 */ 368 if (dev->speed > 400 || 369 dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK) 370 internal_clk = 19200; 371 else if (dev->speed > 100) 372 internal_clk = 9600; 373 else 374 internal_clk = 4000; 375 fclk = clk_get(dev->dev, "fck"); 376 fclk_rate = clk_get_rate(fclk) / 1000; 377 clk_put(fclk); 378 379 /* Compute prescaler divisor */ 380 psc = fclk_rate / internal_clk; 381 psc = psc - 1; 382 383 /* If configured for High Speed */ 384 if (dev->speed > 400) { 385 unsigned long scl; 386 387 /* For first phase of HS mode */ 388 scl = internal_clk / 400; 389 fsscll = scl - (scl / 3) - 7; 390 fssclh = (scl / 3) - 5; 391 392 /* For second phase of HS mode */ 393 scl = fclk_rate / dev->speed; 394 hsscll = scl - (scl / 3) - 7; 395 hssclh = (scl / 3) - 5; 396 } else if (dev->speed > 100) { 397 unsigned long scl; 398 399 /* Fast mode */ 400 scl = internal_clk / dev->speed; 401 fsscll = scl - (scl / 3) - 7; 402 fssclh = (scl / 3) - 5; 403 } else { 404 /* Standard mode */ 405 fsscll = internal_clk / (dev->speed * 2) - 7; 406 fssclh = internal_clk / (dev->speed * 2) - 5; 407 } 408 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; 409 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; 410 } else { 411 /* Program desired operating rate */ 412 fclk_rate /= (psc + 1) * 1000; 413 if (psc > 2) 414 psc = 2; 415 scll = fclk_rate / (dev->speed * 2) - 7 + psc; 416 sclh = fclk_rate / (dev->speed * 2) - 7 + psc; 417 } 418 419 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ 420 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc); 421 422 /* SCL low and high time values */ 423 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll); 424 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh); 425 426 /* Take the I2C module out of reset: */ 427 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); 428 429 /* Enable interrupts */ 430 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | 431 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | 432 OMAP_I2C_IE_AL) | ((dev->fifo_size) ? 433 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); 434 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); 435 if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) { 436 dev->pscstate = psc; 437 dev->scllstate = scll; 438 dev->sclhstate = sclh; 439 dev->bufstate = buf; 440 } 441 return 0; 442 } 443 444 /* 445 * Waiting on Bus Busy 446 */ 447 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev) 448 { 449 unsigned long timeout; 450 451 timeout = jiffies + OMAP_I2C_TIMEOUT; 452 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) { 453 if (time_after(jiffies, timeout)) { 454 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 455 return -ETIMEDOUT; 456 } 457 msleep(1); 458 } 459 460 return 0; 461 } 462 463 static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx) 464 { 465 u16 buf; 466 467 if (dev->flags & OMAP_I2C_FLAG_NO_FIFO) 468 return; 469 470 /* 471 * Set up notification threshold based on message size. We're doing 472 * this to try and avoid draining feature as much as possible. Whenever 473 * we have big messages to transfer (bigger than our total fifo size) 474 * then we might use draining feature to transfer the remaining bytes. 475 */ 476 477 dev->threshold = clamp(size, (u8) 1, dev->fifo_size); 478 479 buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG); 480 481 if (is_rx) { 482 /* Clear RX Threshold */ 483 buf &= ~(0x3f << 8); 484 buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR; 485 } else { 486 /* Clear TX Threshold */ 487 buf &= ~0x3f; 488 buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR; 489 } 490 491 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf); 492 493 if (dev->rev < OMAP_I2C_REV_ON_3630_4430) 494 dev->b_hw = 1; /* Enable hardware fixes */ 495 496 /* calculate wakeup latency constraint for MPU */ 497 dev->latency = (1000000 * dev->threshold) / (1000 * dev->speed / 8); 498 } 499 500 /* 501 * Low level master read/write transaction. 502 */ 503 static int omap_i2c_xfer_msg(struct i2c_adapter *adap, 504 struct i2c_msg *msg, int stop) 505 { 506 struct omap_i2c_dev *dev = i2c_get_adapdata(adap); 507 unsigned long timeout; 508 u16 w; 509 510 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", 511 msg->addr, msg->len, msg->flags, stop); 512 513 if (msg->len == 0) 514 return -EINVAL; 515 516 dev->receiver = !!(msg->flags & I2C_M_RD); 517 omap_i2c_resize_fifo(dev, msg->len, dev->receiver); 518 519 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr); 520 521 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */ 522 dev->buf = msg->buf; 523 dev->buf_len = msg->len; 524 525 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len); 526 527 /* Clear the FIFO Buffers */ 528 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG); 529 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR; 530 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w); 531 532 INIT_COMPLETION(dev->cmd_complete); 533 dev->cmd_err = 0; 534 535 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT; 536 537 /* High speed configuration */ 538 if (dev->speed > 400) 539 w |= OMAP_I2C_CON_OPMODE_HS; 540 541 if (msg->flags & I2C_M_STOP) 542 stop = 1; 543 if (msg->flags & I2C_M_TEN) 544 w |= OMAP_I2C_CON_XA; 545 if (!(msg->flags & I2C_M_RD)) 546 w |= OMAP_I2C_CON_TRX; 547 548 if (!dev->b_hw && stop) 549 w |= OMAP_I2C_CON_STP; 550 551 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); 552 553 /* 554 * Don't write stt and stp together on some hardware. 555 */ 556 if (dev->b_hw && stop) { 557 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT; 558 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); 559 while (con & OMAP_I2C_CON_STT) { 560 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); 561 562 /* Let the user know if i2c is in a bad state */ 563 if (time_after(jiffies, delay)) { 564 dev_err(dev->dev, "controller timed out " 565 "waiting for start condition to finish\n"); 566 return -ETIMEDOUT; 567 } 568 cpu_relax(); 569 } 570 571 w |= OMAP_I2C_CON_STP; 572 w &= ~OMAP_I2C_CON_STT; 573 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); 574 } 575 576 /* 577 * REVISIT: We should abort the transfer on signals, but the bus goes 578 * into arbitration and we're currently unable to recover from it. 579 */ 580 timeout = wait_for_completion_timeout(&dev->cmd_complete, 581 OMAP_I2C_TIMEOUT); 582 dev->buf_len = 0; 583 if (timeout == 0) { 584 dev_err(dev->dev, "controller timed out\n"); 585 omap_i2c_init(dev); 586 return -ETIMEDOUT; 587 } 588 589 if (likely(!dev->cmd_err)) 590 return 0; 591 592 /* We have an error */ 593 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR | 594 OMAP_I2C_STAT_XUDF)) { 595 omap_i2c_init(dev); 596 return -EIO; 597 } 598 599 if (dev->cmd_err & OMAP_I2C_STAT_NACK) { 600 if (msg->flags & I2C_M_IGNORE_NAK) 601 return 0; 602 if (stop) { 603 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); 604 w |= OMAP_I2C_CON_STP; 605 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); 606 } 607 return -EREMOTEIO; 608 } 609 return -EIO; 610 } 611 612 613 /* 614 * Prepare controller for a transaction and call omap_i2c_xfer_msg 615 * to do the work during IRQ processing. 616 */ 617 static int 618 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 619 { 620 struct omap_i2c_dev *dev = i2c_get_adapdata(adap); 621 int i; 622 int r; 623 624 r = pm_runtime_get_sync(dev->dev); 625 if (IS_ERR_VALUE(r)) 626 goto out; 627 628 r = omap_i2c_wait_for_bb(dev); 629 if (r < 0) 630 goto out; 631 632 /* 633 * When waiting for completion of a i2c transfer, we need to 634 * set a wake up latency constraint for the MPU. This is to 635 * ensure quick enough wakeup from idle, when transfer 636 * completes. 637 */ 638 if (dev->latency) 639 pm_qos_add_request(&dev->pm_qos_request, 640 PM_QOS_CPU_DMA_LATENCY, 641 dev->latency); 642 643 for (i = 0; i < num; i++) { 644 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1))); 645 if (r != 0) 646 break; 647 } 648 649 if (dev->latency) 650 pm_qos_remove_request(&dev->pm_qos_request); 651 652 if (r == 0) 653 r = num; 654 655 omap_i2c_wait_for_bb(dev); 656 out: 657 pm_runtime_mark_last_busy(dev->dev); 658 pm_runtime_put_autosuspend(dev->dev); 659 return r; 660 } 661 662 static u32 663 omap_i2c_func(struct i2c_adapter *adap) 664 { 665 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 666 I2C_FUNC_PROTOCOL_MANGLING; 667 } 668 669 static inline void 670 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err) 671 { 672 dev->cmd_err |= err; 673 complete(&dev->cmd_complete); 674 } 675 676 static inline void 677 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat) 678 { 679 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat); 680 } 681 682 static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat) 683 { 684 /* 685 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8) 686 * Not applicable for OMAP4. 687 * Under certain rare conditions, RDR could be set again 688 * when the bus is busy, then ignore the interrupt and 689 * clear the interrupt. 690 */ 691 if (stat & OMAP_I2C_STAT_RDR) { 692 /* Step 1: If RDR is set, clear it */ 693 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); 694 695 /* Step 2: */ 696 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) 697 & OMAP_I2C_STAT_BB)) { 698 699 /* Step 3: */ 700 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) 701 & OMAP_I2C_STAT_RDR) { 702 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); 703 dev_dbg(dev->dev, "RDR when bus is busy.\n"); 704 } 705 706 } 707 } 708 } 709 710 /* rev1 devices are apparently only on some 15xx */ 711 #ifdef CONFIG_ARCH_OMAP15XX 712 713 static irqreturn_t 714 omap_i2c_omap1_isr(int this_irq, void *dev_id) 715 { 716 struct omap_i2c_dev *dev = dev_id; 717 u16 iv, w; 718 719 if (pm_runtime_suspended(dev->dev)) 720 return IRQ_NONE; 721 722 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); 723 switch (iv) { 724 case 0x00: /* None */ 725 break; 726 case 0x01: /* Arbitration lost */ 727 dev_err(dev->dev, "Arbitration lost\n"); 728 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL); 729 break; 730 case 0x02: /* No acknowledgement */ 731 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK); 732 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP); 733 break; 734 case 0x03: /* Register access ready */ 735 omap_i2c_complete_cmd(dev, 0); 736 break; 737 case 0x04: /* Receive data ready */ 738 if (dev->buf_len) { 739 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); 740 *dev->buf++ = w; 741 dev->buf_len--; 742 if (dev->buf_len) { 743 *dev->buf++ = w >> 8; 744 dev->buf_len--; 745 } 746 } else 747 dev_err(dev->dev, "RRDY IRQ while no data requested\n"); 748 break; 749 case 0x05: /* Transmit data ready */ 750 if (dev->buf_len) { 751 w = *dev->buf++; 752 dev->buf_len--; 753 if (dev->buf_len) { 754 w |= *dev->buf++ << 8; 755 dev->buf_len--; 756 } 757 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); 758 } else 759 dev_err(dev->dev, "XRDY IRQ while no data to send\n"); 760 break; 761 default: 762 return IRQ_NONE; 763 } 764 765 return IRQ_HANDLED; 766 } 767 #else 768 #define omap_i2c_omap1_isr NULL 769 #endif 770 771 /* 772 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing 773 * data to DATA_REG. Otherwise some data bytes can be lost while transferring 774 * them from the memory to the I2C interface. 775 */ 776 static int errata_omap3_i462(struct omap_i2c_dev *dev) 777 { 778 unsigned long timeout = 10000; 779 u16 stat; 780 781 do { 782 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); 783 if (stat & OMAP_I2C_STAT_XUDF) 784 break; 785 786 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) { 787 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY | 788 OMAP_I2C_STAT_XDR)); 789 if (stat & OMAP_I2C_STAT_NACK) { 790 dev->cmd_err |= OMAP_I2C_STAT_NACK; 791 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK); 792 } 793 794 if (stat & OMAP_I2C_STAT_AL) { 795 dev_err(dev->dev, "Arbitration lost\n"); 796 dev->cmd_err |= OMAP_I2C_STAT_AL; 797 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK); 798 } 799 800 return -EIO; 801 } 802 803 cpu_relax(); 804 } while (--timeout); 805 806 if (!timeout) { 807 dev_err(dev->dev, "timeout waiting on XUDF bit\n"); 808 return 0; 809 } 810 811 return 0; 812 } 813 814 static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes, 815 bool is_rdr) 816 { 817 u16 w; 818 819 while (num_bytes--) { 820 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); 821 *dev->buf++ = w; 822 dev->buf_len--; 823 824 /* 825 * Data reg in 2430, omap3 and 826 * omap4 is 8 bit wide 827 */ 828 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) { 829 *dev->buf++ = w >> 8; 830 dev->buf_len--; 831 } 832 } 833 } 834 835 static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes, 836 bool is_xdr) 837 { 838 u16 w; 839 840 while (num_bytes--) { 841 w = *dev->buf++; 842 dev->buf_len--; 843 844 /* 845 * Data reg in 2430, omap3 and 846 * omap4 is 8 bit wide 847 */ 848 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) { 849 w |= *dev->buf++ << 8; 850 dev->buf_len--; 851 } 852 853 if (dev->errata & I2C_OMAP_ERRATA_I462) { 854 int ret; 855 856 ret = errata_omap3_i462(dev); 857 if (ret < 0) 858 return ret; 859 } 860 861 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); 862 } 863 864 return 0; 865 } 866 867 static irqreturn_t 868 omap_i2c_isr(int irq, void *dev_id) 869 { 870 struct omap_i2c_dev *dev = dev_id; 871 irqreturn_t ret = IRQ_HANDLED; 872 u16 mask; 873 u16 stat; 874 875 spin_lock(&dev->lock); 876 mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); 877 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); 878 879 if (stat & mask) 880 ret = IRQ_WAKE_THREAD; 881 882 spin_unlock(&dev->lock); 883 884 return ret; 885 } 886 887 static irqreturn_t 888 omap_i2c_isr_thread(int this_irq, void *dev_id) 889 { 890 struct omap_i2c_dev *dev = dev_id; 891 unsigned long flags; 892 u16 bits; 893 u16 stat; 894 int err = 0, count = 0; 895 896 spin_lock_irqsave(&dev->lock, flags); 897 do { 898 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); 899 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); 900 stat &= bits; 901 902 /* If we're in receiver mode, ignore XDR/XRDY */ 903 if (dev->receiver) 904 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY); 905 else 906 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY); 907 908 if (!stat) { 909 /* my work here is done */ 910 goto out; 911 } 912 913 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat); 914 if (count++ == 100) { 915 dev_warn(dev->dev, "Too much work in one IRQ\n"); 916 break; 917 } 918 919 if (stat & OMAP_I2C_STAT_NACK) { 920 err |= OMAP_I2C_STAT_NACK; 921 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK); 922 break; 923 } 924 925 if (stat & OMAP_I2C_STAT_AL) { 926 dev_err(dev->dev, "Arbitration lost\n"); 927 err |= OMAP_I2C_STAT_AL; 928 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL); 929 break; 930 } 931 932 /* 933 * ProDB0017052: Clear ARDY bit twice 934 */ 935 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK | 936 OMAP_I2C_STAT_AL)) { 937 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY | 938 OMAP_I2C_STAT_RDR | 939 OMAP_I2C_STAT_XRDY | 940 OMAP_I2C_STAT_XDR | 941 OMAP_I2C_STAT_ARDY)); 942 break; 943 } 944 945 if (stat & OMAP_I2C_STAT_RDR) { 946 u8 num_bytes = 1; 947 948 if (dev->fifo_size) 949 num_bytes = dev->buf_len; 950 951 omap_i2c_receive_data(dev, num_bytes, true); 952 953 if (dev->errata & I2C_OMAP_ERRATA_I207) 954 i2c_omap_errata_i207(dev, stat); 955 956 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR); 957 break; 958 } 959 960 if (stat & OMAP_I2C_STAT_RRDY) { 961 u8 num_bytes = 1; 962 963 if (dev->threshold) 964 num_bytes = dev->threshold; 965 966 omap_i2c_receive_data(dev, num_bytes, false); 967 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY); 968 continue; 969 } 970 971 if (stat & OMAP_I2C_STAT_XDR) { 972 u8 num_bytes = 1; 973 int ret; 974 975 if (dev->fifo_size) 976 num_bytes = dev->buf_len; 977 978 ret = omap_i2c_transmit_data(dev, num_bytes, true); 979 if (ret < 0) 980 break; 981 982 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR); 983 break; 984 } 985 986 if (stat & OMAP_I2C_STAT_XRDY) { 987 u8 num_bytes = 1; 988 int ret; 989 990 if (dev->threshold) 991 num_bytes = dev->threshold; 992 993 ret = omap_i2c_transmit_data(dev, num_bytes, false); 994 if (ret < 0) 995 break; 996 997 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY); 998 continue; 999 } 1000 1001 if (stat & OMAP_I2C_STAT_ROVR) { 1002 dev_err(dev->dev, "Receive overrun\n"); 1003 err |= OMAP_I2C_STAT_ROVR; 1004 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR); 1005 break; 1006 } 1007 1008 if (stat & OMAP_I2C_STAT_XUDF) { 1009 dev_err(dev->dev, "Transmit underflow\n"); 1010 err |= OMAP_I2C_STAT_XUDF; 1011 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF); 1012 break; 1013 } 1014 } while (stat); 1015 1016 omap_i2c_complete_cmd(dev, err); 1017 1018 out: 1019 spin_unlock_irqrestore(&dev->lock, flags); 1020 1021 return IRQ_HANDLED; 1022 } 1023 1024 static const struct i2c_algorithm omap_i2c_algo = { 1025 .master_xfer = omap_i2c_xfer, 1026 .functionality = omap_i2c_func, 1027 }; 1028 1029 #ifdef CONFIG_OF 1030 static struct omap_i2c_bus_platform_data omap3_pdata = { 1031 .rev = OMAP_I2C_IP_VERSION_1, 1032 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 1033 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | 1034 OMAP_I2C_FLAG_BUS_SHIFT_2, 1035 }; 1036 1037 static struct omap_i2c_bus_platform_data omap4_pdata = { 1038 .rev = OMAP_I2C_IP_VERSION_2, 1039 }; 1040 1041 static const struct of_device_id omap_i2c_of_match[] = { 1042 { 1043 .compatible = "ti,omap4-i2c", 1044 .data = &omap4_pdata, 1045 }, 1046 { 1047 .compatible = "ti,omap3-i2c", 1048 .data = &omap3_pdata, 1049 }, 1050 { }, 1051 }; 1052 MODULE_DEVICE_TABLE(of, omap_i2c_of_match); 1053 #endif 1054 1055 static int __devinit 1056 omap_i2c_probe(struct platform_device *pdev) 1057 { 1058 struct omap_i2c_dev *dev; 1059 struct i2c_adapter *adap; 1060 struct resource *mem; 1061 const struct omap_i2c_bus_platform_data *pdata = 1062 pdev->dev.platform_data; 1063 struct device_node *node = pdev->dev.of_node; 1064 const struct of_device_id *match; 1065 int irq; 1066 int r; 1067 1068 /* NOTE: driver uses the static register mapping */ 1069 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1070 if (!mem) { 1071 dev_err(&pdev->dev, "no mem resource?\n"); 1072 return -ENODEV; 1073 } 1074 1075 irq = platform_get_irq(pdev, 0); 1076 if (irq < 0) { 1077 dev_err(&pdev->dev, "no irq resource?\n"); 1078 return irq; 1079 } 1080 1081 dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL); 1082 if (!dev) { 1083 dev_err(&pdev->dev, "Menory allocation failed\n"); 1084 return -ENOMEM; 1085 } 1086 1087 dev->base = devm_request_and_ioremap(&pdev->dev, mem); 1088 if (!dev->base) { 1089 dev_err(&pdev->dev, "I2C region already claimed\n"); 1090 return -ENOMEM; 1091 } 1092 1093 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev); 1094 if (match) { 1095 u32 freq = 100000; /* default to 100000 Hz */ 1096 1097 pdata = match->data; 1098 dev->dtrev = pdata->rev; 1099 dev->flags = pdata->flags; 1100 1101 of_property_read_u32(node, "clock-frequency", &freq); 1102 /* convert DT freq value in Hz into kHz for speed */ 1103 dev->speed = freq / 1000; 1104 } else if (pdata != NULL) { 1105 dev->speed = pdata->clkrate; 1106 dev->flags = pdata->flags; 1107 dev->dtrev = pdata->rev; 1108 } 1109 1110 dev->dev = &pdev->dev; 1111 dev->irq = irq; 1112 1113 spin_lock_init(&dev->lock); 1114 1115 platform_set_drvdata(pdev, dev); 1116 init_completion(&dev->cmd_complete); 1117 1118 dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3; 1119 1120 if (dev->dtrev == OMAP_I2C_IP_VERSION_2) 1121 dev->regs = (u8 *)reg_map_ip_v2; 1122 else 1123 dev->regs = (u8 *)reg_map_ip_v1; 1124 1125 pm_runtime_enable(dev->dev); 1126 pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT); 1127 pm_runtime_use_autosuspend(dev->dev); 1128 1129 r = pm_runtime_get_sync(dev->dev); 1130 if (IS_ERR_VALUE(r)) 1131 goto err_free_mem; 1132 1133 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff; 1134 1135 dev->errata = 0; 1136 1137 if (dev->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207) 1138 dev->errata |= I2C_OMAP_ERRATA_I207; 1139 1140 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530) 1141 dev->errata |= I2C_OMAP_ERRATA_I462; 1142 1143 if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) { 1144 u16 s; 1145 1146 /* Set up the fifo size - Get total size */ 1147 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3; 1148 dev->fifo_size = 0x8 << s; 1149 1150 /* 1151 * Set up notification threshold as half the total available 1152 * size. This is to ensure that we can handle the status on int 1153 * call back latencies. 1154 */ 1155 1156 dev->fifo_size = (dev->fifo_size / 2); 1157 1158 if (dev->rev < OMAP_I2C_REV_ON_3630_4430) 1159 dev->b_hw = 1; /* Enable hardware fixes */ 1160 1161 /* calculate wakeup latency constraint for MPU */ 1162 dev->latency = (1000000 * dev->fifo_size) / 1163 (1000 * dev->speed / 8); 1164 } 1165 1166 /* reset ASAP, clearing any IRQs */ 1167 omap_i2c_init(dev); 1168 1169 if (dev->rev < OMAP_I2C_OMAP1_REV_2) 1170 r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr, 1171 IRQF_NO_SUSPEND, pdev->name, dev); 1172 else 1173 r = devm_request_threaded_irq(&pdev->dev, dev->irq, 1174 omap_i2c_isr, omap_i2c_isr_thread, 1175 IRQF_NO_SUSPEND | IRQF_ONESHOT, 1176 pdev->name, dev); 1177 1178 if (r) { 1179 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq); 1180 goto err_unuse_clocks; 1181 } 1182 1183 adap = &dev->adapter; 1184 i2c_set_adapdata(adap, dev); 1185 adap->owner = THIS_MODULE; 1186 adap->class = I2C_CLASS_HWMON; 1187 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name)); 1188 adap->algo = &omap_i2c_algo; 1189 adap->dev.parent = &pdev->dev; 1190 adap->dev.of_node = pdev->dev.of_node; 1191 1192 /* i2c device drivers may be active on return from add_adapter() */ 1193 adap->nr = pdev->id; 1194 r = i2c_add_numbered_adapter(adap); 1195 if (r) { 1196 dev_err(dev->dev, "failure adding adapter\n"); 1197 goto err_unuse_clocks; 1198 } 1199 1200 dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", adap->nr, 1201 dev->dtrev, dev->rev >> 4, dev->rev & 0xf, dev->speed); 1202 1203 of_i2c_register_devices(adap); 1204 1205 pm_runtime_mark_last_busy(dev->dev); 1206 pm_runtime_put_autosuspend(dev->dev); 1207 1208 return 0; 1209 1210 err_unuse_clocks: 1211 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 1212 pm_runtime_put(dev->dev); 1213 pm_runtime_disable(&pdev->dev); 1214 err_free_mem: 1215 platform_set_drvdata(pdev, NULL); 1216 1217 return r; 1218 } 1219 1220 static int __devexit omap_i2c_remove(struct platform_device *pdev) 1221 { 1222 struct omap_i2c_dev *dev = platform_get_drvdata(pdev); 1223 int ret; 1224 1225 platform_set_drvdata(pdev, NULL); 1226 1227 i2c_del_adapter(&dev->adapter); 1228 ret = pm_runtime_get_sync(&pdev->dev); 1229 if (IS_ERR_VALUE(ret)) 1230 return ret; 1231 1232 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 1233 pm_runtime_put(&pdev->dev); 1234 pm_runtime_disable(&pdev->dev); 1235 return 0; 1236 } 1237 1238 #ifdef CONFIG_PM 1239 #ifdef CONFIG_PM_RUNTIME 1240 static int omap_i2c_runtime_suspend(struct device *dev) 1241 { 1242 struct platform_device *pdev = to_platform_device(dev); 1243 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev); 1244 u16 iv; 1245 1246 _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG); 1247 1248 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0); 1249 1250 if (_dev->rev < OMAP_I2C_OMAP1_REV_2) { 1251 iv = omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */ 1252 } else { 1253 omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate); 1254 1255 /* Flush posted write */ 1256 omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG); 1257 } 1258 1259 return 0; 1260 } 1261 1262 static int omap_i2c_runtime_resume(struct device *dev) 1263 { 1264 struct platform_device *pdev = to_platform_device(dev); 1265 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev); 1266 1267 if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) { 1268 omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, 0); 1269 omap_i2c_write_reg(_dev, OMAP_I2C_PSC_REG, _dev->pscstate); 1270 omap_i2c_write_reg(_dev, OMAP_I2C_SCLL_REG, _dev->scllstate); 1271 omap_i2c_write_reg(_dev, OMAP_I2C_SCLH_REG, _dev->sclhstate); 1272 omap_i2c_write_reg(_dev, OMAP_I2C_BUF_REG, _dev->bufstate); 1273 omap_i2c_write_reg(_dev, OMAP_I2C_SYSC_REG, _dev->syscstate); 1274 omap_i2c_write_reg(_dev, OMAP_I2C_WE_REG, _dev->westate); 1275 omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); 1276 } 1277 1278 /* 1279 * Don't write to this register if the IE state is 0 as it can 1280 * cause deadlock. 1281 */ 1282 if (_dev->iestate) 1283 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, _dev->iestate); 1284 1285 return 0; 1286 } 1287 #endif /* CONFIG_PM_RUNTIME */ 1288 1289 static struct dev_pm_ops omap_i2c_pm_ops = { 1290 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend, 1291 omap_i2c_runtime_resume, NULL) 1292 }; 1293 #define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops) 1294 #else 1295 #define OMAP_I2C_PM_OPS NULL 1296 #endif /* CONFIG_PM */ 1297 1298 static struct platform_driver omap_i2c_driver = { 1299 .probe = omap_i2c_probe, 1300 .remove = __devexit_p(omap_i2c_remove), 1301 .driver = { 1302 .name = "omap_i2c", 1303 .owner = THIS_MODULE, 1304 .pm = OMAP_I2C_PM_OPS, 1305 .of_match_table = of_match_ptr(omap_i2c_of_match), 1306 }, 1307 }; 1308 1309 /* I2C may be needed to bring up other drivers */ 1310 static int __init 1311 omap_i2c_init_driver(void) 1312 { 1313 return platform_driver_register(&omap_i2c_driver); 1314 } 1315 subsys_initcall(omap_i2c_init_driver); 1316 1317 static void __exit omap_i2c_exit_driver(void) 1318 { 1319 platform_driver_unregister(&omap_i2c_driver); 1320 } 1321 module_exit(omap_i2c_exit_driver); 1322 1323 MODULE_AUTHOR("MontaVista Software, Inc. (and others)"); 1324 MODULE_DESCRIPTION("TI OMAP I2C bus adapter"); 1325 MODULE_LICENSE("GPL"); 1326 MODULE_ALIAS("platform:omap_i2c"); 1327