1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * TI OMAP I2C master mode driver
4 *
5 * Copyright (C) 2003 MontaVista Software, Inc.
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2004 - 2007 Texas Instruments.
8 *
9 * Originally written by MontaVista Software, Inc.
10 * Additional contributions by:
11 * Tony Lindgren <tony@atomide.com>
12 * Imre Deak <imre.deak@nokia.com>
13 * Juha Yrjölä <juha.yrjola@solidboot.com>
14 * Syed Khasim <x0khasim@ti.com>
15 * Nishant Menon <nm@ti.com>
16 */
17
18 #include <linux/module.h>
19 #include <linux/delay.h>
20 #include <linux/i2c.h>
21 #include <linux/err.h>
22 #include <linux/interrupt.h>
23 #include <linux/completion.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
26 #include <linux/io.h>
27 #include <linux/mux/consumer.h>
28 #include <linux/of.h>
29 #include <linux/slab.h>
30 #include <linux/platform_data/i2c-omap.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/pinctrl/consumer.h>
33 #include <linux/property.h>
34
35 /* I2C controller revisions */
36 #define OMAP_I2C_OMAP1_REV_2 0x20
37
38 /* I2C controller revisions present on specific hardware */
39 #define OMAP_I2C_REV_ON_2430 0x00000036
40 #define OMAP_I2C_REV_ON_3430_3530 0x0000003C
41 #define OMAP_I2C_REV_ON_3630 0x00000040
42 #define OMAP_I2C_REV_ON_4430_PLUS 0x50400002
43
44 /* timeout waiting for the controller to respond */
45 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
46
47 /* timeout for pm runtime autosuspend */
48 #define OMAP_I2C_PM_TIMEOUT 1000 /* ms */
49
50 /* timeout for making decision on bus free status */
51 #define OMAP_I2C_BUS_FREE_TIMEOUT (msecs_to_jiffies(10))
52
53 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
54 enum {
55 OMAP_I2C_REV_REG = 0,
56 OMAP_I2C_IE_REG,
57 OMAP_I2C_STAT_REG,
58 OMAP_I2C_IV_REG,
59 OMAP_I2C_WE_REG,
60 OMAP_I2C_SYSS_REG,
61 OMAP_I2C_BUF_REG,
62 OMAP_I2C_CNT_REG,
63 OMAP_I2C_DATA_REG,
64 OMAP_I2C_SYSC_REG,
65 OMAP_I2C_CON_REG,
66 OMAP_I2C_OA_REG,
67 OMAP_I2C_SA_REG,
68 OMAP_I2C_PSC_REG,
69 OMAP_I2C_SCLL_REG,
70 OMAP_I2C_SCLH_REG,
71 OMAP_I2C_SYSTEST_REG,
72 OMAP_I2C_BUFSTAT_REG,
73 /* only on OMAP4430 */
74 OMAP_I2C_IP_V2_REVNB_LO,
75 OMAP_I2C_IP_V2_REVNB_HI,
76 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
77 OMAP_I2C_IP_V2_IRQENABLE_SET,
78 OMAP_I2C_IP_V2_IRQENABLE_CLR,
79 };
80
81 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
82 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
83 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
84 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
85 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
86 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
87 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
88 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
89
90 /* I2C Status Register (OMAP_I2C_STAT): */
91 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
92 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
93 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
94 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
95 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
96 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
97 #define OMAP_I2C_STAT_BF (1 << 8) /* Bus Free */
98 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
99 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
100 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
101 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
102 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
103
104 /* I2C WE wakeup enable register */
105 #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
106 #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
107 #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
108 #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
109 #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
110 #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
111 #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
112 #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
113 #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
114 #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
115
116 #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
117 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
118 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
119 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
120 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
121
122 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
123 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
124 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
125 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
126 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
127
128 /* I2C Configuration Register (OMAP_I2C_CON): */
129 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
130 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
131 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
132 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
133 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
134 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
135 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
136 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
137 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
138 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
139
140 /* I2C SCL time value when Master */
141 #define OMAP_I2C_SCLL_HSSCLL 8
142 #define OMAP_I2C_SCLH_HSSCLH 8
143
144 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
145 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
146 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
147 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
148 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
149 /* Functional mode */
150 #define OMAP_I2C_SYSTEST_SCL_I_FUNC (1 << 8) /* SCL line input value */
151 #define OMAP_I2C_SYSTEST_SCL_O_FUNC (1 << 7) /* SCL line output value */
152 #define OMAP_I2C_SYSTEST_SDA_I_FUNC (1 << 6) /* SDA line input value */
153 #define OMAP_I2C_SYSTEST_SDA_O_FUNC (1 << 5) /* SDA line output value */
154 /* SDA/SCL IO mode */
155 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
156 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
157 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
158 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
159
160 /* OCP_SYSSTATUS bit definitions */
161 #define SYSS_RESETDONE_MASK (1 << 0)
162
163 /* OCP_SYSCONFIG bit definitions */
164 #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
165 #define SYSC_SIDLEMODE_MASK (0x3 << 3)
166 #define SYSC_ENAWAKEUP_MASK (1 << 2)
167 #define SYSC_SOFTRESET_MASK (1 << 1)
168 #define SYSC_AUTOIDLE_MASK (1 << 0)
169
170 #define SYSC_IDLEMODE_SMART 0x2
171 #define SYSC_CLOCKACTIVITY_FCLK 0x2
172
173 /* Errata definitions */
174 #define I2C_OMAP_ERRATA_I207 (1 << 0)
175 #define I2C_OMAP_ERRATA_I462 (1 << 1)
176
177 #define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF
178
179 struct omap_i2c_dev {
180 struct device *dev;
181 void __iomem *base; /* virtual */
182 int irq;
183 int reg_shift; /* bit shift for I2C register addresses */
184 struct completion cmd_complete;
185 struct resource *ioarea;
186 u32 latency; /* maximum mpu wkup latency */
187 void (*set_mpu_wkup_lat)(struct device *dev,
188 long latency);
189 u32 speed; /* Speed of bus in kHz */
190 u32 flags;
191 u16 scheme;
192 u16 cmd_err;
193 u8 *buf;
194 u8 *regs;
195 size_t buf_len;
196 struct i2c_adapter adapter;
197 u8 threshold;
198 u8 fifo_size; /* use as flag and value
199 * fifo_size==0 implies no fifo
200 * if set, should be trsh+1
201 */
202 u32 rev;
203 unsigned b_hw:1; /* bad h/w fixes */
204 unsigned bb_valid:1; /* true when BB-bit reflects
205 * the I2C bus state
206 */
207 unsigned receiver:1; /* true when we're in receiver mode */
208 u16 iestate; /* Saved interrupt register */
209 u16 pscstate;
210 u16 scllstate;
211 u16 sclhstate;
212 u16 syscstate;
213 u16 westate;
214 u16 errata;
215 struct mux_state *mux_state;
216 };
217
218 static const u8 reg_map_ip_v1[] = {
219 [OMAP_I2C_REV_REG] = 0x00,
220 [OMAP_I2C_IE_REG] = 0x01,
221 [OMAP_I2C_STAT_REG] = 0x02,
222 [OMAP_I2C_IV_REG] = 0x03,
223 [OMAP_I2C_WE_REG] = 0x03,
224 [OMAP_I2C_SYSS_REG] = 0x04,
225 [OMAP_I2C_BUF_REG] = 0x05,
226 [OMAP_I2C_CNT_REG] = 0x06,
227 [OMAP_I2C_DATA_REG] = 0x07,
228 [OMAP_I2C_SYSC_REG] = 0x08,
229 [OMAP_I2C_CON_REG] = 0x09,
230 [OMAP_I2C_OA_REG] = 0x0a,
231 [OMAP_I2C_SA_REG] = 0x0b,
232 [OMAP_I2C_PSC_REG] = 0x0c,
233 [OMAP_I2C_SCLL_REG] = 0x0d,
234 [OMAP_I2C_SCLH_REG] = 0x0e,
235 [OMAP_I2C_SYSTEST_REG] = 0x0f,
236 [OMAP_I2C_BUFSTAT_REG] = 0x10,
237 };
238
239 static const u8 reg_map_ip_v2[] = {
240 [OMAP_I2C_REV_REG] = 0x04,
241 [OMAP_I2C_IE_REG] = 0x2c,
242 [OMAP_I2C_STAT_REG] = 0x28,
243 [OMAP_I2C_IV_REG] = 0x34,
244 [OMAP_I2C_WE_REG] = 0x34,
245 [OMAP_I2C_SYSS_REG] = 0x90,
246 [OMAP_I2C_BUF_REG] = 0x94,
247 [OMAP_I2C_CNT_REG] = 0x98,
248 [OMAP_I2C_DATA_REG] = 0x9c,
249 [OMAP_I2C_SYSC_REG] = 0x10,
250 [OMAP_I2C_CON_REG] = 0xa4,
251 [OMAP_I2C_OA_REG] = 0xa8,
252 [OMAP_I2C_SA_REG] = 0xac,
253 [OMAP_I2C_PSC_REG] = 0xb0,
254 [OMAP_I2C_SCLL_REG] = 0xb4,
255 [OMAP_I2C_SCLH_REG] = 0xb8,
256 [OMAP_I2C_SYSTEST_REG] = 0xbC,
257 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
258 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
259 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
260 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
261 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
262 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
263 };
264
265 static int omap_i2c_xfer_data(struct omap_i2c_dev *omap);
266
omap_i2c_write_reg(struct omap_i2c_dev * omap,int reg,u16 val)267 static inline void omap_i2c_write_reg(struct omap_i2c_dev *omap,
268 int reg, u16 val)
269 {
270 writew_relaxed(val, omap->base +
271 (omap->regs[reg] << omap->reg_shift));
272 }
273
omap_i2c_read_reg(struct omap_i2c_dev * omap,int reg)274 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *omap, int reg)
275 {
276 return readw_relaxed(omap->base +
277 (omap->regs[reg] << omap->reg_shift));
278 }
279
__omap_i2c_init(struct omap_i2c_dev * omap)280 static void __omap_i2c_init(struct omap_i2c_dev *omap)
281 {
282
283 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
284
285 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
286 omap_i2c_write_reg(omap, OMAP_I2C_PSC_REG, omap->pscstate);
287
288 /* SCL low and high time values */
289 omap_i2c_write_reg(omap, OMAP_I2C_SCLL_REG, omap->scllstate);
290 omap_i2c_write_reg(omap, OMAP_I2C_SCLH_REG, omap->sclhstate);
291 if (omap->rev >= OMAP_I2C_REV_ON_3430_3530)
292 omap_i2c_write_reg(omap, OMAP_I2C_WE_REG, omap->westate);
293
294 /* Take the I2C module out of reset: */
295 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
296
297 /*
298 * NOTE: right after setting CON_EN, STAT_BB could be 0 while the
299 * bus is busy. It will be changed to 1 on the next IP FCLK clock.
300 * udelay(1) will be enough to fix that.
301 */
302
303 /*
304 * Don't write to this register if the IE state is 0 as it can
305 * cause deadlock.
306 */
307 if (omap->iestate)
308 omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, omap->iestate);
309 }
310
omap_i2c_reset(struct omap_i2c_dev * omap)311 static int omap_i2c_reset(struct omap_i2c_dev *omap)
312 {
313 unsigned long timeout;
314 u16 sysc;
315
316 if (omap->rev >= OMAP_I2C_OMAP1_REV_2) {
317 sysc = omap_i2c_read_reg(omap, OMAP_I2C_SYSC_REG);
318
319 /* Disable I2C controller before soft reset */
320 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG,
321 omap_i2c_read_reg(omap, OMAP_I2C_CON_REG) &
322 ~(OMAP_I2C_CON_EN));
323
324 omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
325 /* For some reason we need to set the EN bit before the
326 * reset done bit gets set. */
327 timeout = jiffies + OMAP_I2C_TIMEOUT;
328 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
329 while (!(omap_i2c_read_reg(omap, OMAP_I2C_SYSS_REG) &
330 SYSS_RESETDONE_MASK)) {
331 if (time_after(jiffies, timeout)) {
332 dev_warn(omap->dev, "timeout waiting "
333 "for controller reset\n");
334 return -ETIMEDOUT;
335 }
336 msleep(1);
337 }
338
339 /* SYSC register is cleared by the reset; rewrite it */
340 omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, sysc);
341
342 if (omap->rev > OMAP_I2C_REV_ON_3430_3530) {
343 /* Schedule I2C-bus monitoring on the next transfer */
344 omap->bb_valid = 0;
345 }
346 }
347
348 return 0;
349 }
350
omap_i2c_init(struct omap_i2c_dev * omap)351 static int omap_i2c_init(struct omap_i2c_dev *omap)
352 {
353 u16 psc = 0, scll = 0, sclh = 0;
354 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
355 unsigned long fclk_rate = 12000000;
356 unsigned long internal_clk = 0;
357 struct clk *fclk;
358 int error;
359
360 if (omap->rev >= OMAP_I2C_REV_ON_3430_3530) {
361 /*
362 * Enabling all wakup sources to stop I2C freezing on
363 * WFI instruction.
364 * REVISIT: Some wkup sources might not be needed.
365 */
366 omap->westate = OMAP_I2C_WE_ALL;
367 }
368
369 if (omap->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
370 /*
371 * The I2C functional clock is the armxor_ck, so there's
372 * no need to get "armxor_ck" separately. Now, if OMAP2420
373 * always returns 12MHz for the functional clock, we can
374 * do this bit unconditionally.
375 */
376 fclk = clk_get(omap->dev, "fck");
377 if (IS_ERR(fclk)) {
378 error = PTR_ERR(fclk);
379 dev_err(omap->dev, "could not get fck: %i\n", error);
380
381 return error;
382 }
383
384 fclk_rate = clk_get_rate(fclk);
385 clk_put(fclk);
386
387 /* TRM for 5912 says the I2C clock must be prescaled to be
388 * between 7 - 12 MHz. The XOR input clock is typically
389 * 12, 13 or 19.2 MHz. So we should have code that produces:
390 *
391 * XOR MHz Divider Prescaler
392 * 12 1 0
393 * 13 2 1
394 * 19.2 2 1
395 */
396 if (fclk_rate > 12000000)
397 psc = fclk_rate / 12000000;
398 }
399
400 if (!(omap->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
401
402 /*
403 * HSI2C controller internal clk rate should be 19.2 Mhz for
404 * HS and for all modes on 2430. On 34xx we can use lower rate
405 * to get longer filter period for better noise suppression.
406 * The filter is iclk (fclk for HS) period.
407 */
408 if (omap->speed > 400 ||
409 omap->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
410 internal_clk = 19200;
411 else if (omap->speed > 100)
412 internal_clk = 9600;
413 else
414 internal_clk = 4000;
415 fclk = clk_get(omap->dev, "fck");
416 if (IS_ERR(fclk)) {
417 error = PTR_ERR(fclk);
418 dev_err(omap->dev, "could not get fck: %i\n", error);
419
420 return error;
421 }
422 fclk_rate = clk_get_rate(fclk) / 1000;
423 clk_put(fclk);
424
425 /* Compute prescaler divisor */
426 psc = fclk_rate / internal_clk;
427 psc = psc - 1;
428
429 /* If configured for High Speed */
430 if (omap->speed > 400) {
431 unsigned long scl;
432
433 /* For first phase of HS mode */
434 scl = internal_clk / 400;
435 fsscll = scl - (scl / 3) - 7;
436 fssclh = (scl / 3) - 5;
437
438 /* For second phase of HS mode */
439 scl = fclk_rate / omap->speed;
440 hsscll = scl - (scl / 3) - 7;
441 hssclh = (scl / 3) - 5;
442 } else if (omap->speed > 100) {
443 unsigned long scl;
444
445 /* Fast mode */
446 scl = internal_clk / omap->speed;
447 fsscll = scl - (scl / 3) - 7;
448 fssclh = (scl / 3) - 5;
449 } else {
450 /* Standard mode */
451 fsscll = internal_clk / (omap->speed * 2) - 7;
452 fssclh = internal_clk / (omap->speed * 2) - 5;
453 }
454 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
455 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
456 } else {
457 /* Program desired operating rate */
458 fclk_rate /= (psc + 1) * 1000;
459 if (psc > 2)
460 psc = 2;
461 scll = fclk_rate / (omap->speed * 2) - 7 + psc;
462 sclh = fclk_rate / (omap->speed * 2) - 7 + psc;
463 }
464
465 omap->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
466 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
467 OMAP_I2C_IE_AL) | ((omap->fifo_size) ?
468 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
469
470 omap->pscstate = psc;
471 omap->scllstate = scll;
472 omap->sclhstate = sclh;
473
474 if (omap->rev <= OMAP_I2C_REV_ON_3430_3530) {
475 /* Not implemented */
476 omap->bb_valid = 1;
477 }
478
479 __omap_i2c_init(omap);
480
481 return 0;
482 }
483
484 /*
485 * Try bus recovery, but only if SDA is actually low.
486 */
omap_i2c_recover_bus(struct omap_i2c_dev * omap)487 static int omap_i2c_recover_bus(struct omap_i2c_dev *omap)
488 {
489 u16 systest;
490
491 systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG);
492 if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&
493 (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC))
494 return 0; /* bus seems to already be fine */
495 if (!(systest & OMAP_I2C_SYSTEST_SCL_I_FUNC))
496 return -EBUSY; /* recovery would not fix SCL */
497 return i2c_recover_bus(&omap->adapter);
498 }
499
500 /*
501 * Waiting on Bus Busy
502 */
omap_i2c_wait_for_bb(struct omap_i2c_dev * omap)503 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *omap)
504 {
505 unsigned long timeout;
506
507 timeout = jiffies + OMAP_I2C_TIMEOUT;
508 while (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
509 if (time_after(jiffies, timeout))
510 return omap_i2c_recover_bus(omap);
511 msleep(1);
512 }
513
514 return 0;
515 }
516
517 /*
518 * Wait while BB-bit doesn't reflect the I2C bus state
519 *
520 * In a multimaster environment, after IP software reset, BB-bit value doesn't
521 * correspond to the current bus state. It may happen what BB-bit will be 0,
522 * while the bus is busy due to another I2C master activity.
523 * Here are BB-bit values after reset:
524 * SDA SCL BB NOTES
525 * 0 0 0 1, 2
526 * 1 0 0 1, 2
527 * 0 1 1
528 * 1 1 0 3
529 * Later, if IP detect SDA=0 and SCL=1 (ACK) or SDA 1->0 while SCL=1 (START)
530 * combinations on the bus, it set BB-bit to 1.
531 * If IP detect SDA 0->1 while SCL=1 (STOP) combination on the bus,
532 * it set BB-bit to 0 and BF to 1.
533 * BB and BF bits correctly tracks the bus state while IP is suspended
534 * BB bit became valid on the next FCLK clock after CON_EN bit set
535 *
536 * NOTES:
537 * 1. Any transfer started when BB=0 and bus is busy wouldn't be
538 * completed by IP and results in controller timeout.
539 * 2. Any transfer started when BB=0 and SCL=0 results in IP
540 * starting to drive SDA low. In that case IP corrupt data
541 * on the bus.
542 * 3. Any transfer started in the middle of another master's transfer
543 * results in unpredictable results and data corruption
544 */
omap_i2c_wait_for_bb_valid(struct omap_i2c_dev * omap)545 static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *omap)
546 {
547 unsigned long bus_free_timeout = 0;
548 unsigned long timeout;
549 int bus_free = 0;
550 u16 stat, systest;
551
552 if (omap->bb_valid)
553 return 0;
554
555 timeout = jiffies + OMAP_I2C_TIMEOUT;
556 while (1) {
557 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
558 /*
559 * We will see BB or BF event in a case IP had detected any
560 * activity on the I2C bus. Now IP correctly tracks the bus
561 * state. BB-bit value is valid.
562 */
563 if (stat & (OMAP_I2C_STAT_BB | OMAP_I2C_STAT_BF))
564 break;
565
566 /*
567 * Otherwise, we must look signals on the bus to make
568 * the right decision.
569 */
570 systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG);
571 if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&
572 (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) {
573 if (!bus_free) {
574 bus_free_timeout = jiffies +
575 OMAP_I2C_BUS_FREE_TIMEOUT;
576 bus_free = 1;
577 }
578
579 /*
580 * SDA and SCL lines was high for 10 ms without bus
581 * activity detected. The bus is free. Consider
582 * BB-bit value is valid.
583 */
584 if (time_after(jiffies, bus_free_timeout))
585 break;
586 } else {
587 bus_free = 0;
588 }
589
590 if (time_after(jiffies, timeout)) {
591 /*
592 * SDA or SCL were low for the entire timeout without
593 * any activity detected. Most likely, a slave is
594 * locking up the bus with no master driving the clock.
595 */
596 dev_warn(omap->dev, "timeout waiting for bus ready\n");
597 return omap_i2c_recover_bus(omap);
598 }
599
600 msleep(1);
601 }
602
603 omap->bb_valid = 1;
604 return 0;
605 }
606
omap_i2c_resize_fifo(struct omap_i2c_dev * omap,u8 size,bool is_rx)607 static void omap_i2c_resize_fifo(struct omap_i2c_dev *omap, u8 size, bool is_rx)
608 {
609 u16 buf;
610
611 if (omap->flags & OMAP_I2C_FLAG_NO_FIFO)
612 return;
613
614 /*
615 * Set up notification threshold based on message size. We're doing
616 * this to try and avoid draining feature as much as possible. Whenever
617 * we have big messages to transfer (bigger than our total fifo size)
618 * then we might use draining feature to transfer the remaining bytes.
619 */
620
621 omap->threshold = clamp(size, (u8) 1, omap->fifo_size);
622
623 buf = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
624
625 if (is_rx) {
626 /* Clear RX Threshold */
627 buf &= ~(0x3f << 8);
628 buf |= ((omap->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
629 } else {
630 /* Clear TX Threshold */
631 buf &= ~0x3f;
632 buf |= (omap->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
633 }
634
635 omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, buf);
636
637 if (omap->rev < OMAP_I2C_REV_ON_3630)
638 omap->b_hw = 1; /* Enable hardware fixes */
639
640 /* calculate wakeup latency constraint for MPU */
641 if (omap->set_mpu_wkup_lat != NULL)
642 omap->latency = (1000000 * omap->threshold) /
643 (1000 * omap->speed / 8);
644 }
645
omap_i2c_wait(struct omap_i2c_dev * omap)646 static void omap_i2c_wait(struct omap_i2c_dev *omap)
647 {
648 u16 stat;
649 u16 mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
650 int count = 0;
651
652 do {
653 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
654 count++;
655 } while (!(stat & mask) && count < 5);
656 }
657
658 /*
659 * Low level master read/write transaction.
660 */
omap_i2c_xfer_msg(struct i2c_adapter * adap,struct i2c_msg * msg,int stop,bool polling)661 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
662 struct i2c_msg *msg, int stop, bool polling)
663 {
664 struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
665 unsigned long time_left;
666 u16 w;
667 int ret;
668
669 dev_dbg(omap->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
670 msg->addr, msg->len, msg->flags, stop);
671
672 omap->receiver = !!(msg->flags & I2C_M_RD);
673 omap_i2c_resize_fifo(omap, msg->len, omap->receiver);
674
675 omap_i2c_write_reg(omap, OMAP_I2C_SA_REG, msg->addr);
676
677 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
678 omap->buf = msg->buf;
679 omap->buf_len = msg->len;
680
681 /* make sure writes to omap->buf_len are ordered */
682 barrier();
683
684 omap_i2c_write_reg(omap, OMAP_I2C_CNT_REG, omap->buf_len);
685
686 /* Clear the FIFO Buffers */
687 w = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
688 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
689 omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, w);
690
691 if (!polling)
692 reinit_completion(&omap->cmd_complete);
693 omap->cmd_err = 0;
694
695 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
696
697 /* High speed configuration */
698 if (omap->speed > 400)
699 w |= OMAP_I2C_CON_OPMODE_HS;
700
701 if (msg->flags & I2C_M_STOP)
702 stop = 1;
703 if (msg->flags & I2C_M_TEN)
704 w |= OMAP_I2C_CON_XA;
705 if (!(msg->flags & I2C_M_RD))
706 w |= OMAP_I2C_CON_TRX;
707
708 if (!omap->b_hw && stop)
709 w |= OMAP_I2C_CON_STP;
710 /*
711 * NOTE: STAT_BB bit could became 1 here if another master occupy
712 * the bus. IP successfully complete transfer when the bus will be
713 * free again (BB reset to 0).
714 */
715 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
716
717 /*
718 * Don't write stt and stp together on some hardware.
719 */
720 if (omap->b_hw && stop) {
721 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
722 u16 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
723 while (con & OMAP_I2C_CON_STT) {
724 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
725
726 /* Let the user know if i2c is in a bad state */
727 if (time_after(jiffies, delay)) {
728 dev_err(omap->dev, "controller timed out "
729 "waiting for start condition to finish\n");
730 return -ETIMEDOUT;
731 }
732 cpu_relax();
733 }
734
735 w |= OMAP_I2C_CON_STP;
736 w &= ~OMAP_I2C_CON_STT;
737 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
738 }
739
740 /*
741 * REVISIT: We should abort the transfer on signals, but the bus goes
742 * into arbitration and we're currently unable to recover from it.
743 */
744 if (!polling) {
745 time_left = wait_for_completion_timeout(&omap->cmd_complete,
746 OMAP_I2C_TIMEOUT);
747 } else {
748 do {
749 omap_i2c_wait(omap);
750 ret = omap_i2c_xfer_data(omap);
751 } while (ret == -EAGAIN);
752
753 time_left = !ret;
754 }
755
756 if (time_left == 0) {
757 omap_i2c_reset(omap);
758 __omap_i2c_init(omap);
759 return -ETIMEDOUT;
760 }
761
762 if (likely(!omap->cmd_err))
763 return 0;
764
765 /* We have an error */
766 if (omap->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) {
767 omap_i2c_reset(omap);
768 __omap_i2c_init(omap);
769 return -EIO;
770 }
771
772 if (omap->cmd_err & OMAP_I2C_STAT_AL)
773 return -EAGAIN;
774
775 if (omap->cmd_err & OMAP_I2C_STAT_NACK) {
776 if (msg->flags & I2C_M_IGNORE_NAK)
777 return 0;
778
779 w = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
780 w |= OMAP_I2C_CON_STP;
781 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
782 return -EREMOTEIO;
783 }
784 return -EIO;
785 }
786
787
788 /*
789 * Prepare controller for a transaction and call omap_i2c_xfer_msg
790 * to do the work during IRQ processing.
791 */
792 static int
omap_i2c_xfer_common(struct i2c_adapter * adap,struct i2c_msg msgs[],int num,bool polling)793 omap_i2c_xfer_common(struct i2c_adapter *adap, struct i2c_msg msgs[], int num,
794 bool polling)
795 {
796 struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
797 int i;
798 int r;
799
800 r = pm_runtime_get_sync(omap->dev);
801 if (r < 0)
802 goto out;
803
804 r = omap_i2c_wait_for_bb_valid(omap);
805 if (r < 0)
806 goto out;
807
808 r = omap_i2c_wait_for_bb(omap);
809 if (r < 0)
810 goto out;
811
812 if (omap->set_mpu_wkup_lat != NULL)
813 omap->set_mpu_wkup_lat(omap->dev, omap->latency);
814
815 for (i = 0; i < num; i++) {
816 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)),
817 polling);
818 if (r != 0)
819 break;
820 }
821
822 if (r == 0)
823 r = num;
824
825 omap_i2c_wait_for_bb(omap);
826
827 if (omap->set_mpu_wkup_lat != NULL)
828 omap->set_mpu_wkup_lat(omap->dev, -1);
829
830 out:
831 pm_runtime_put_autosuspend(omap->dev);
832 return r;
833 }
834
835 static int
omap_i2c_xfer_irq(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)836 omap_i2c_xfer_irq(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
837 {
838 return omap_i2c_xfer_common(adap, msgs, num, false);
839 }
840
841 static int
omap_i2c_xfer_polling(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)842 omap_i2c_xfer_polling(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
843 {
844 return omap_i2c_xfer_common(adap, msgs, num, true);
845 }
846
847 static u32
omap_i2c_func(struct i2c_adapter * adap)848 omap_i2c_func(struct i2c_adapter *adap)
849 {
850 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
851 I2C_FUNC_PROTOCOL_MANGLING;
852 }
853
854 static inline void
omap_i2c_complete_cmd(struct omap_i2c_dev * omap,u16 err)855 omap_i2c_complete_cmd(struct omap_i2c_dev *omap, u16 err)
856 {
857 omap->cmd_err |= err;
858 complete(&omap->cmd_complete);
859 }
860
861 static inline void
omap_i2c_ack_stat(struct omap_i2c_dev * omap,u16 stat)862 omap_i2c_ack_stat(struct omap_i2c_dev *omap, u16 stat)
863 {
864 omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, stat);
865 }
866
i2c_omap_errata_i207(struct omap_i2c_dev * omap,u16 stat)867 static inline void i2c_omap_errata_i207(struct omap_i2c_dev *omap, u16 stat)
868 {
869 /*
870 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
871 * Not applicable for OMAP4.
872 * Under certain rare conditions, RDR could be set again
873 * when the bus is busy, then ignore the interrupt and
874 * clear the interrupt.
875 */
876 if (stat & OMAP_I2C_STAT_RDR) {
877 /* Step 1: If RDR is set, clear it */
878 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
879
880 /* Step 2: */
881 if (!(omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
882 & OMAP_I2C_STAT_BB)) {
883
884 /* Step 3: */
885 if (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
886 & OMAP_I2C_STAT_RDR) {
887 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
888 dev_dbg(omap->dev, "RDR when bus is busy.\n");
889 }
890
891 }
892 }
893 }
894
895 /* rev1 devices are apparently only on some 15xx */
896 #ifdef CONFIG_ARCH_OMAP15XX
897
898 static irqreturn_t
omap_i2c_omap1_isr(int this_irq,void * dev_id)899 omap_i2c_omap1_isr(int this_irq, void *dev_id)
900 {
901 struct omap_i2c_dev *omap = dev_id;
902 u16 iv, w;
903
904 if (pm_runtime_suspended(omap->dev))
905 return IRQ_NONE;
906
907 iv = omap_i2c_read_reg(omap, OMAP_I2C_IV_REG);
908 switch (iv) {
909 case 0x00: /* None */
910 break;
911 case 0x01: /* Arbitration lost */
912 dev_err(omap->dev, "Arbitration lost\n");
913 omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_AL);
914 break;
915 case 0x02: /* No acknowledgement */
916 omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_NACK);
917 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
918 break;
919 case 0x03: /* Register access ready */
920 omap_i2c_complete_cmd(omap, 0);
921 break;
922 case 0x04: /* Receive data ready */
923 if (omap->buf_len) {
924 w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
925 *omap->buf++ = w;
926 omap->buf_len--;
927 if (omap->buf_len) {
928 *omap->buf++ = w >> 8;
929 omap->buf_len--;
930 }
931 } else
932 dev_err(omap->dev, "RRDY IRQ while no data requested\n");
933 break;
934 case 0x05: /* Transmit data ready */
935 if (omap->buf_len) {
936 w = *omap->buf++;
937 omap->buf_len--;
938 if (omap->buf_len) {
939 w |= *omap->buf++ << 8;
940 omap->buf_len--;
941 }
942 omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
943 } else
944 dev_err(omap->dev, "XRDY IRQ while no data to send\n");
945 break;
946 default:
947 return IRQ_NONE;
948 }
949
950 return IRQ_HANDLED;
951 }
952 #else
953 #define omap_i2c_omap1_isr NULL
954 #endif
955
956 /*
957 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
958 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
959 * them from the memory to the I2C interface.
960 */
errata_omap3_i462(struct omap_i2c_dev * omap)961 static int errata_omap3_i462(struct omap_i2c_dev *omap)
962 {
963 unsigned long timeout = 10000;
964 u16 stat;
965
966 do {
967 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
968 if (stat & OMAP_I2C_STAT_XUDF)
969 break;
970
971 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
972 omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_XRDY |
973 OMAP_I2C_STAT_XDR));
974 if (stat & OMAP_I2C_STAT_NACK) {
975 omap->cmd_err |= OMAP_I2C_STAT_NACK;
976 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
977 }
978
979 if (stat & OMAP_I2C_STAT_AL) {
980 dev_err(omap->dev, "Arbitration lost\n");
981 omap->cmd_err |= OMAP_I2C_STAT_AL;
982 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
983 }
984
985 return -EIO;
986 }
987
988 cpu_relax();
989 } while (--timeout);
990
991 if (!timeout) {
992 dev_err(omap->dev, "timeout waiting on XUDF bit\n");
993 return 0;
994 }
995
996 return 0;
997 }
998
omap_i2c_receive_data(struct omap_i2c_dev * omap,u8 num_bytes,bool is_rdr)999 static void omap_i2c_receive_data(struct omap_i2c_dev *omap, u8 num_bytes,
1000 bool is_rdr)
1001 {
1002 u16 w;
1003
1004 while (num_bytes--) {
1005 w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
1006 *omap->buf++ = w;
1007 omap->buf_len--;
1008
1009 /*
1010 * Data reg in 2430, omap3 and
1011 * omap4 is 8 bit wide
1012 */
1013 if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
1014 *omap->buf++ = w >> 8;
1015 omap->buf_len--;
1016 }
1017 }
1018 }
1019
omap_i2c_transmit_data(struct omap_i2c_dev * omap,u8 num_bytes,bool is_xdr)1020 static int omap_i2c_transmit_data(struct omap_i2c_dev *omap, u8 num_bytes,
1021 bool is_xdr)
1022 {
1023 u16 w;
1024
1025 while (num_bytes--) {
1026 w = *omap->buf++;
1027 omap->buf_len--;
1028
1029 /*
1030 * Data reg in 2430, omap3 and
1031 * omap4 is 8 bit wide
1032 */
1033 if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
1034 w |= *omap->buf++ << 8;
1035 omap->buf_len--;
1036 }
1037
1038 if (omap->errata & I2C_OMAP_ERRATA_I462) {
1039 int ret;
1040
1041 ret = errata_omap3_i462(omap);
1042 if (ret < 0)
1043 return ret;
1044 }
1045
1046 omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
1047 }
1048
1049 return 0;
1050 }
1051
omap_i2c_xfer_data(struct omap_i2c_dev * omap)1052 static int omap_i2c_xfer_data(struct omap_i2c_dev *omap)
1053 {
1054 u16 bits;
1055 u16 stat;
1056 int err = 0, count = 0;
1057
1058 do {
1059 bits = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1060 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
1061 stat &= bits;
1062
1063 /* If we're in receiver mode, ignore XDR/XRDY */
1064 if (omap->receiver)
1065 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
1066 else
1067 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
1068
1069 if (!stat) {
1070 /* my work here is done */
1071 err = -EAGAIN;
1072 break;
1073 }
1074
1075 dev_dbg(omap->dev, "IRQ (ISR = 0x%04x)\n", stat);
1076 if (count++ == 100) {
1077 dev_warn(omap->dev, "Too much work in one IRQ\n");
1078 break;
1079 }
1080
1081 if (stat & OMAP_I2C_STAT_NACK) {
1082 omap->cmd_err |= OMAP_I2C_STAT_NACK;
1083 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
1084
1085 if (!(stat & ~OMAP_I2C_STAT_NACK)) {
1086 err = -EAGAIN;
1087 break;
1088 }
1089 }
1090
1091 if (stat & OMAP_I2C_STAT_AL) {
1092 dev_err(omap->dev, "Arbitration lost\n");
1093 err |= OMAP_I2C_STAT_AL;
1094 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
1095 }
1096
1097 /*
1098 * ProDB0017052: Clear ARDY bit twice
1099 */
1100 if (stat & OMAP_I2C_STAT_ARDY)
1101 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ARDY);
1102
1103 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
1104 OMAP_I2C_STAT_AL)) {
1105 omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_RRDY |
1106 OMAP_I2C_STAT_RDR |
1107 OMAP_I2C_STAT_XRDY |
1108 OMAP_I2C_STAT_XDR |
1109 OMAP_I2C_STAT_ARDY));
1110 break;
1111 }
1112
1113 if (stat & OMAP_I2C_STAT_RDR) {
1114 u8 num_bytes = 1;
1115
1116 if (omap->fifo_size)
1117 num_bytes = omap->buf_len;
1118
1119 if (omap->errata & I2C_OMAP_ERRATA_I207) {
1120 i2c_omap_errata_i207(omap, stat);
1121 num_bytes = (omap_i2c_read_reg(omap,
1122 OMAP_I2C_BUFSTAT_REG) >> 8) & 0x3F;
1123 }
1124
1125 omap_i2c_receive_data(omap, num_bytes, true);
1126 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
1127 continue;
1128 }
1129
1130 if (stat & OMAP_I2C_STAT_RRDY) {
1131 u8 num_bytes = 1;
1132
1133 if (omap->threshold)
1134 num_bytes = omap->threshold;
1135
1136 omap_i2c_receive_data(omap, num_bytes, false);
1137 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RRDY);
1138 continue;
1139 }
1140
1141 if (stat & OMAP_I2C_STAT_XDR) {
1142 u8 num_bytes = 1;
1143 int ret;
1144
1145 if (omap->fifo_size)
1146 num_bytes = omap->buf_len;
1147
1148 ret = omap_i2c_transmit_data(omap, num_bytes, true);
1149 if (ret < 0)
1150 break;
1151
1152 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XDR);
1153 continue;
1154 }
1155
1156 if (stat & OMAP_I2C_STAT_XRDY) {
1157 u8 num_bytes = 1;
1158 int ret;
1159
1160 if (omap->threshold)
1161 num_bytes = omap->threshold;
1162
1163 ret = omap_i2c_transmit_data(omap, num_bytes, false);
1164 if (ret < 0)
1165 break;
1166
1167 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XRDY);
1168 continue;
1169 }
1170
1171 if (stat & OMAP_I2C_STAT_ROVR) {
1172 dev_err(omap->dev, "Receive overrun\n");
1173 err |= OMAP_I2C_STAT_ROVR;
1174 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ROVR);
1175 break;
1176 }
1177
1178 if (stat & OMAP_I2C_STAT_XUDF) {
1179 dev_err(omap->dev, "Transmit underflow\n");
1180 err |= OMAP_I2C_STAT_XUDF;
1181 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XUDF);
1182 break;
1183 }
1184 } while (stat);
1185
1186 return err;
1187 }
1188
1189 static irqreturn_t
omap_i2c_isr_thread(int this_irq,void * dev_id)1190 omap_i2c_isr_thread(int this_irq, void *dev_id)
1191 {
1192 int ret;
1193 struct omap_i2c_dev *omap = dev_id;
1194
1195 ret = omap_i2c_xfer_data(omap);
1196 if (ret != -EAGAIN)
1197 omap_i2c_complete_cmd(omap, ret);
1198
1199 return IRQ_HANDLED;
1200 }
1201
1202 static const struct i2c_algorithm omap_i2c_algo = {
1203 .xfer = omap_i2c_xfer_irq,
1204 .xfer_atomic = omap_i2c_xfer_polling,
1205 .functionality = omap_i2c_func,
1206 };
1207
1208 static const struct i2c_adapter_quirks omap_i2c_quirks = {
1209 .flags = I2C_AQ_NO_ZERO_LEN,
1210 };
1211
1212 #ifdef CONFIG_OF
1213 static struct omap_i2c_bus_platform_data omap2420_pdata = {
1214 .rev = OMAP_I2C_IP_VERSION_1,
1215 .flags = OMAP_I2C_FLAG_NO_FIFO |
1216 OMAP_I2C_FLAG_SIMPLE_CLOCK |
1217 OMAP_I2C_FLAG_16BIT_DATA_REG |
1218 OMAP_I2C_FLAG_BUS_SHIFT_2,
1219 };
1220
1221 static struct omap_i2c_bus_platform_data omap2430_pdata = {
1222 .rev = OMAP_I2C_IP_VERSION_1,
1223 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
1224 OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
1225 };
1226
1227 static struct omap_i2c_bus_platform_data omap3_pdata = {
1228 .rev = OMAP_I2C_IP_VERSION_1,
1229 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
1230 };
1231
1232 static struct omap_i2c_bus_platform_data omap4_pdata = {
1233 .rev = OMAP_I2C_IP_VERSION_2,
1234 };
1235
1236 static const struct of_device_id omap_i2c_of_match[] = {
1237 {
1238 .compatible = "ti,omap4-i2c",
1239 .data = &omap4_pdata,
1240 },
1241 {
1242 .compatible = "ti,omap3-i2c",
1243 .data = &omap3_pdata,
1244 },
1245 {
1246 .compatible = "ti,omap2430-i2c",
1247 .data = &omap2430_pdata,
1248 },
1249 {
1250 .compatible = "ti,omap2420-i2c",
1251 .data = &omap2420_pdata,
1252 },
1253 { }
1254 };
1255 MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1256 #endif
1257
1258 #define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14)
1259
1260 #define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
1261 #define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)
1262
1263 #define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
1264 #define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
1265 #define OMAP_I2C_SCHEME_0 0
1266 #define OMAP_I2C_SCHEME_1 1
1267
omap_i2c_get_scl(struct i2c_adapter * adap)1268 static int omap_i2c_get_scl(struct i2c_adapter *adap)
1269 {
1270 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1271 u32 reg;
1272
1273 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1274
1275 return reg & OMAP_I2C_SYSTEST_SCL_I_FUNC;
1276 }
1277
omap_i2c_get_sda(struct i2c_adapter * adap)1278 static int omap_i2c_get_sda(struct i2c_adapter *adap)
1279 {
1280 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1281 u32 reg;
1282
1283 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1284
1285 return reg & OMAP_I2C_SYSTEST_SDA_I_FUNC;
1286 }
1287
omap_i2c_set_scl(struct i2c_adapter * adap,int val)1288 static void omap_i2c_set_scl(struct i2c_adapter *adap, int val)
1289 {
1290 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1291 u32 reg;
1292
1293 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1294 if (val)
1295 reg |= OMAP_I2C_SYSTEST_SCL_O;
1296 else
1297 reg &= ~OMAP_I2C_SYSTEST_SCL_O;
1298 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1299 }
1300
omap_i2c_prepare_recovery(struct i2c_adapter * adap)1301 static void omap_i2c_prepare_recovery(struct i2c_adapter *adap)
1302 {
1303 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1304 u32 reg;
1305
1306 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1307 /* enable test mode */
1308 reg |= OMAP_I2C_SYSTEST_ST_EN;
1309 /* select SDA/SCL IO mode */
1310 reg |= 3 << OMAP_I2C_SYSTEST_TMODE_SHIFT;
1311 /* set SCL to high-impedance state (reset value is 0) */
1312 reg |= OMAP_I2C_SYSTEST_SCL_O;
1313 /* set SDA to high-impedance state (reset value is 0) */
1314 reg |= OMAP_I2C_SYSTEST_SDA_O;
1315 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1316 }
1317
omap_i2c_unprepare_recovery(struct i2c_adapter * adap)1318 static void omap_i2c_unprepare_recovery(struct i2c_adapter *adap)
1319 {
1320 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1321 u32 reg;
1322
1323 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1324 /* restore reset values */
1325 reg &= ~OMAP_I2C_SYSTEST_ST_EN;
1326 reg &= ~OMAP_I2C_SYSTEST_TMODE_MASK;
1327 reg &= ~OMAP_I2C_SYSTEST_SCL_O;
1328 reg &= ~OMAP_I2C_SYSTEST_SDA_O;
1329 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1330 }
1331
1332 static struct i2c_bus_recovery_info omap_i2c_bus_recovery_info = {
1333 .get_scl = omap_i2c_get_scl,
1334 .get_sda = omap_i2c_get_sda,
1335 .set_scl = omap_i2c_set_scl,
1336 .prepare_recovery = omap_i2c_prepare_recovery,
1337 .unprepare_recovery = omap_i2c_unprepare_recovery,
1338 .recover_bus = i2c_generic_scl_recovery,
1339 };
1340
1341 static int
omap_i2c_probe(struct platform_device * pdev)1342 omap_i2c_probe(struct platform_device *pdev)
1343 {
1344 struct omap_i2c_dev *omap;
1345 struct i2c_adapter *adap;
1346 const struct omap_i2c_bus_platform_data *pdata =
1347 dev_get_platdata(&pdev->dev);
1348 struct device_node *node = pdev->dev.of_node;
1349 int irq;
1350 int r;
1351 u32 rev;
1352 u16 minor, major;
1353
1354 irq = platform_get_irq(pdev, 0);
1355 if (irq < 0)
1356 return irq;
1357
1358 omap = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
1359 if (!omap)
1360 return -ENOMEM;
1361
1362 omap->base = devm_platform_ioremap_resource(pdev, 0);
1363 if (IS_ERR(omap->base))
1364 return PTR_ERR(omap->base);
1365
1366 if (pdev->dev.of_node) {
1367 u32 freq = I2C_MAX_STANDARD_MODE_FREQ;
1368
1369 pdata = device_get_match_data(&pdev->dev);
1370 omap->flags = pdata->flags;
1371
1372 of_property_read_u32(node, "clock-frequency", &freq);
1373 /* convert DT freq value in Hz into kHz for speed */
1374 omap->speed = freq / 1000;
1375 } else if (pdata != NULL) {
1376 omap->speed = pdata->clkrate;
1377 omap->flags = pdata->flags;
1378 omap->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1379 }
1380
1381 omap->dev = &pdev->dev;
1382 omap->irq = irq;
1383
1384 platform_set_drvdata(pdev, omap);
1385 init_completion(&omap->cmd_complete);
1386
1387 omap->reg_shift = (omap->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
1388
1389 pm_runtime_enable(omap->dev);
1390 pm_runtime_set_autosuspend_delay(omap->dev, OMAP_I2C_PM_TIMEOUT);
1391 pm_runtime_use_autosuspend(omap->dev);
1392
1393 r = pm_runtime_resume_and_get(omap->dev);
1394 if (r < 0)
1395 goto err_disable_pm;
1396
1397 /*
1398 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
1399 * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
1400 * Also since the omap_i2c_read_reg uses reg_map_ip_* a
1401 * readw_relaxed is done.
1402 */
1403 rev = readw_relaxed(omap->base + 0x04);
1404
1405 omap->scheme = OMAP_I2C_SCHEME(rev);
1406 switch (omap->scheme) {
1407 case OMAP_I2C_SCHEME_0:
1408 omap->regs = (u8 *)reg_map_ip_v1;
1409 omap->rev = omap_i2c_read_reg(omap, OMAP_I2C_REV_REG);
1410 minor = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
1411 major = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
1412 break;
1413 case OMAP_I2C_SCHEME_1:
1414 default:
1415 omap->regs = (u8 *)reg_map_ip_v2;
1416 rev = (rev << 16) |
1417 omap_i2c_read_reg(omap, OMAP_I2C_IP_V2_REVNB_LO);
1418 minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
1419 major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
1420 omap->rev = rev;
1421 }
1422
1423 omap->errata = 0;
1424
1425 if (omap->rev >= OMAP_I2C_REV_ON_2430 &&
1426 omap->rev < OMAP_I2C_REV_ON_4430_PLUS)
1427 omap->errata |= I2C_OMAP_ERRATA_I207;
1428
1429 if (omap->rev <= OMAP_I2C_REV_ON_3430_3530)
1430 omap->errata |= I2C_OMAP_ERRATA_I462;
1431
1432 if (!(omap->flags & OMAP_I2C_FLAG_NO_FIFO)) {
1433 u16 s;
1434
1435 /* Set up the fifo size - Get total size */
1436 s = (omap_i2c_read_reg(omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1437 omap->fifo_size = 0x8 << s;
1438
1439 /*
1440 * Set up notification threshold as half the total available
1441 * size. This is to ensure that we can handle the status on int
1442 * call back latencies.
1443 */
1444
1445 omap->fifo_size = (omap->fifo_size / 2);
1446
1447 if (omap->rev < OMAP_I2C_REV_ON_3630)
1448 omap->b_hw = 1; /* Enable hardware fixes */
1449
1450 /* calculate wakeup latency constraint for MPU */
1451 if (omap->set_mpu_wkup_lat != NULL)
1452 omap->latency = (1000000 * omap->fifo_size) /
1453 (1000 * omap->speed / 8);
1454 }
1455
1456 if (of_property_present(node, "mux-states")) {
1457 struct mux_state *mux_state;
1458
1459 mux_state = devm_mux_state_get(&pdev->dev, NULL);
1460 if (IS_ERR(mux_state)) {
1461 r = PTR_ERR(mux_state);
1462 dev_dbg(&pdev->dev, "failed to get I2C mux: %d\n", r);
1463 goto err_put_pm;
1464 }
1465 omap->mux_state = mux_state;
1466 r = mux_state_select(omap->mux_state);
1467 if (r) {
1468 dev_err(&pdev->dev, "failed to select I2C mux: %d\n", r);
1469 goto err_put_pm;
1470 }
1471 }
1472
1473 /* reset ASAP, clearing any IRQs */
1474 r = omap_i2c_init(omap);
1475 if (r)
1476 goto err_mux_state_deselect;
1477
1478 if (omap->rev < OMAP_I2C_OMAP1_REV_2)
1479 r = devm_request_irq(&pdev->dev, omap->irq, omap_i2c_omap1_isr,
1480 IRQF_NO_SUSPEND, pdev->name, omap);
1481 else
1482 r = devm_request_threaded_irq(&pdev->dev, omap->irq,
1483 NULL, omap_i2c_isr_thread,
1484 IRQF_NO_SUSPEND | IRQF_ONESHOT,
1485 pdev->name, omap);
1486
1487 if (r) {
1488 dev_err(omap->dev, "failure requesting irq %i\n", omap->irq);
1489 goto err_unuse_clocks;
1490 }
1491
1492 adap = &omap->adapter;
1493 i2c_set_adapdata(adap, omap);
1494 adap->owner = THIS_MODULE;
1495 adap->class = I2C_CLASS_DEPRECATED;
1496 strscpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1497 adap->algo = &omap_i2c_algo;
1498 adap->quirks = &omap_i2c_quirks;
1499 adap->dev.parent = &pdev->dev;
1500 adap->dev.of_node = pdev->dev.of_node;
1501 adap->bus_recovery_info = &omap_i2c_bus_recovery_info;
1502
1503 /* i2c device drivers may be active on return from add_adapter() */
1504 adap->nr = pdev->id;
1505 r = i2c_add_numbered_adapter(adap);
1506 if (r)
1507 goto err_unuse_clocks;
1508
1509 dev_info(omap->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
1510 major, minor, omap->speed);
1511
1512 pm_runtime_put_autosuspend(omap->dev);
1513
1514 return 0;
1515
1516 err_unuse_clocks:
1517 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
1518 err_mux_state_deselect:
1519 if (omap->mux_state)
1520 mux_state_deselect(omap->mux_state);
1521 err_put_pm:
1522 pm_runtime_put_sync(omap->dev);
1523 err_disable_pm:
1524 pm_runtime_dont_use_autosuspend(omap->dev);
1525 pm_runtime_disable(&pdev->dev);
1526
1527 return r;
1528 }
1529
omap_i2c_remove(struct platform_device * pdev)1530 static void omap_i2c_remove(struct platform_device *pdev)
1531 {
1532 struct omap_i2c_dev *omap = platform_get_drvdata(pdev);
1533 int ret;
1534
1535 i2c_del_adapter(&omap->adapter);
1536
1537 if (omap->mux_state)
1538 mux_state_deselect(omap->mux_state);
1539
1540 ret = pm_runtime_get_sync(&pdev->dev);
1541 if (ret < 0)
1542 dev_err(omap->dev, "Failed to resume hardware, skip disable\n");
1543 else
1544 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
1545
1546 pm_runtime_dont_use_autosuspend(&pdev->dev);
1547 pm_runtime_put_sync(&pdev->dev);
1548 pm_runtime_disable(&pdev->dev);
1549 }
1550
omap_i2c_runtime_suspend(struct device * dev)1551 static int omap_i2c_runtime_suspend(struct device *dev)
1552 {
1553 struct omap_i2c_dev *omap = dev_get_drvdata(dev);
1554
1555 omap->iestate = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1556
1557 if (omap->scheme == OMAP_I2C_SCHEME_0)
1558 omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, 0);
1559 else
1560 omap_i2c_write_reg(omap, OMAP_I2C_IP_V2_IRQENABLE_CLR,
1561 OMAP_I2C_IP_V2_INTERRUPTS_MASK);
1562
1563 if (omap->rev < OMAP_I2C_OMAP1_REV_2) {
1564 omap_i2c_read_reg(omap, OMAP_I2C_IV_REG); /* Read clears */
1565 } else {
1566 omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, omap->iestate);
1567
1568 /* Flush posted write */
1569 omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
1570 }
1571
1572 pinctrl_pm_select_sleep_state(dev);
1573
1574 return 0;
1575 }
1576
omap_i2c_runtime_resume(struct device * dev)1577 static int omap_i2c_runtime_resume(struct device *dev)
1578 {
1579 struct omap_i2c_dev *omap = dev_get_drvdata(dev);
1580
1581 pinctrl_pm_select_default_state(dev);
1582
1583 if (!omap->regs)
1584 return 0;
1585
1586 __omap_i2c_init(omap);
1587
1588 return 0;
1589 }
1590
omap_i2c_suspend(struct device * dev)1591 static int omap_i2c_suspend(struct device *dev)
1592 {
1593 /*
1594 * If the controller is autosuspended, there is no way to wakeup it once
1595 * runtime pm is disabled (in suspend_late()).
1596 * But a device may need the controller up during suspend_noirq() or
1597 * resume_noirq().
1598 * Wakeup the controller while runtime pm is enabled, so it is available
1599 * until its suspend_noirq(), and from resume_noirq().
1600 */
1601 return pm_runtime_resume_and_get(dev);
1602 }
1603
omap_i2c_resume(struct device * dev)1604 static int omap_i2c_resume(struct device *dev)
1605 {
1606 pm_runtime_put_autosuspend(dev);
1607
1608 return 0;
1609 }
1610
1611 static const struct dev_pm_ops omap_i2c_pm_ops = {
1612 NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1613 pm_runtime_force_resume)
1614 SYSTEM_SLEEP_PM_OPS(omap_i2c_suspend, omap_i2c_resume)
1615 RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1616 omap_i2c_runtime_resume, NULL)
1617 };
1618
1619 static struct platform_driver omap_i2c_driver = {
1620 .probe = omap_i2c_probe,
1621 .remove = omap_i2c_remove,
1622 .driver = {
1623 .name = "omap_i2c",
1624 .pm = pm_ptr(&omap_i2c_pm_ops),
1625 .of_match_table = of_match_ptr(omap_i2c_of_match),
1626 },
1627 };
1628
1629 /* I2C may be needed to bring up other drivers */
1630 static int __init
omap_i2c_init_driver(void)1631 omap_i2c_init_driver(void)
1632 {
1633 return platform_driver_register(&omap_i2c_driver);
1634 }
1635 subsys_initcall(omap_i2c_init_driver);
1636
omap_i2c_exit_driver(void)1637 static void __exit omap_i2c_exit_driver(void)
1638 {
1639 platform_driver_unregister(&omap_i2c_driver);
1640 }
1641 module_exit(omap_i2c_exit_driver);
1642
1643 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1644 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1645 MODULE_LICENSE("GPL");
1646 MODULE_ALIAS("platform:omap_i2c");
1647