1 /* 2 * (C) Copyright 2009-2010 3 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com 4 * 5 * Portions Copyright (C) 2010 - 2016 Cavium, Inc. 6 * 7 * This file contains the shared part of the driver for the i2c adapter in 8 * Cavium Networks' OCTEON processors and ThunderX SOCs. 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/i2c.h> 17 #include <linux/interrupt.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 21 #include "i2c-octeon-core.h" 22 23 /* interrupt service routine */ 24 irqreturn_t octeon_i2c_isr(int irq, void *dev_id) 25 { 26 struct octeon_i2c *i2c = dev_id; 27 28 i2c->int_disable(i2c); 29 wake_up(&i2c->queue); 30 31 return IRQ_HANDLED; 32 } 33 34 static bool octeon_i2c_test_iflg(struct octeon_i2c *i2c) 35 { 36 return (octeon_i2c_ctl_read(i2c) & TWSI_CTL_IFLG); 37 } 38 39 /** 40 * octeon_i2c_wait - wait for the IFLG to be set 41 * @i2c: The struct octeon_i2c 42 * 43 * Returns 0 on success, otherwise a negative errno. 44 */ 45 static int octeon_i2c_wait(struct octeon_i2c *i2c) 46 { 47 long time_left; 48 49 /* 50 * Some chip revisions don't assert the irq in the interrupt 51 * controller. So we must poll for the IFLG change. 52 */ 53 if (i2c->broken_irq_mode) { 54 u64 end = get_jiffies_64() + i2c->adap.timeout; 55 56 while (!octeon_i2c_test_iflg(i2c) && 57 time_before64(get_jiffies_64(), end)) 58 usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT); 59 60 return octeon_i2c_test_iflg(i2c) ? 0 : -ETIMEDOUT; 61 } 62 63 i2c->int_enable(i2c); 64 time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c), 65 i2c->adap.timeout); 66 i2c->int_disable(i2c); 67 68 if (i2c->broken_irq_check && !time_left && 69 octeon_i2c_test_iflg(i2c)) { 70 dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n"); 71 i2c->broken_irq_mode = true; 72 return 0; 73 } 74 75 if (!time_left) 76 return -ETIMEDOUT; 77 78 return 0; 79 } 80 81 static bool octeon_i2c_hlc_test_valid(struct octeon_i2c *i2c) 82 { 83 return (__raw_readq(i2c->twsi_base + SW_TWSI(i2c)) & SW_TWSI_V) == 0; 84 } 85 86 static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c) 87 { 88 /* clear ST/TS events, listen for neither */ 89 octeon_i2c_write_int(i2c, TWSI_INT_ST_INT | TWSI_INT_TS_INT); 90 } 91 92 /* 93 * Cleanup low-level state & enable high-level controller. 94 */ 95 static void octeon_i2c_hlc_enable(struct octeon_i2c *i2c) 96 { 97 int try = 0; 98 u64 val; 99 100 if (i2c->hlc_enabled) 101 return; 102 i2c->hlc_enabled = true; 103 104 while (1) { 105 val = octeon_i2c_ctl_read(i2c); 106 if (!(val & (TWSI_CTL_STA | TWSI_CTL_STP))) 107 break; 108 109 /* clear IFLG event */ 110 if (val & TWSI_CTL_IFLG) 111 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); 112 113 if (try++ > 100) { 114 pr_err("%s: giving up\n", __func__); 115 break; 116 } 117 118 /* spin until any start/stop has finished */ 119 udelay(10); 120 } 121 octeon_i2c_ctl_write(i2c, TWSI_CTL_CE | TWSI_CTL_AAK | TWSI_CTL_ENAB); 122 } 123 124 static void octeon_i2c_hlc_disable(struct octeon_i2c *i2c) 125 { 126 if (!i2c->hlc_enabled) 127 return; 128 129 i2c->hlc_enabled = false; 130 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); 131 } 132 133 /** 134 * octeon_i2c_hlc_wait - wait for an HLC operation to complete 135 * @i2c: The struct octeon_i2c 136 * 137 * Returns 0 on success, otherwise -ETIMEDOUT. 138 */ 139 static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c) 140 { 141 int time_left; 142 143 /* 144 * Some cn38xx boards don't assert the irq in the interrupt 145 * controller. So we must poll for the valid bit change. 146 */ 147 if (i2c->broken_irq_mode) { 148 u64 end = get_jiffies_64() + i2c->adap.timeout; 149 150 while (!octeon_i2c_hlc_test_valid(i2c) && 151 time_before64(get_jiffies_64(), end)) 152 usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT); 153 154 return octeon_i2c_hlc_test_valid(i2c) ? 0 : -ETIMEDOUT; 155 } 156 157 i2c->hlc_int_enable(i2c); 158 time_left = wait_event_timeout(i2c->queue, 159 octeon_i2c_hlc_test_valid(i2c), 160 i2c->adap.timeout); 161 i2c->hlc_int_disable(i2c); 162 if (!time_left) 163 octeon_i2c_hlc_int_clear(i2c); 164 165 if (i2c->broken_irq_check && !time_left && 166 octeon_i2c_hlc_test_valid(i2c)) { 167 dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n"); 168 i2c->broken_irq_mode = true; 169 return 0; 170 } 171 172 if (!time_left) 173 return -ETIMEDOUT; 174 return 0; 175 } 176 177 static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read) 178 { 179 u8 stat; 180 181 /* 182 * This is ugly... in HLC mode the status is not in the status register 183 * but in the lower 8 bits of SW_TWSI. 184 */ 185 if (i2c->hlc_enabled) 186 stat = __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); 187 else 188 stat = octeon_i2c_stat_read(i2c); 189 190 switch (stat) { 191 /* Everything is fine */ 192 case STAT_IDLE: 193 case STAT_AD2W_ACK: 194 case STAT_RXADDR_ACK: 195 case STAT_TXADDR_ACK: 196 case STAT_TXDATA_ACK: 197 return 0; 198 199 /* ACK allowed on pre-terminal bytes only */ 200 case STAT_RXDATA_ACK: 201 if (!final_read) 202 return 0; 203 return -EIO; 204 205 /* NAK allowed on terminal byte only */ 206 case STAT_RXDATA_NAK: 207 if (final_read) 208 return 0; 209 return -EIO; 210 211 /* Arbitration lost */ 212 case STAT_LOST_ARB_38: 213 case STAT_LOST_ARB_68: 214 case STAT_LOST_ARB_78: 215 case STAT_LOST_ARB_B0: 216 return -EAGAIN; 217 218 /* Being addressed as slave, should back off & listen */ 219 case STAT_SLAVE_60: 220 case STAT_SLAVE_70: 221 case STAT_GENDATA_ACK: 222 case STAT_GENDATA_NAK: 223 return -EOPNOTSUPP; 224 225 /* Core busy as slave */ 226 case STAT_SLAVE_80: 227 case STAT_SLAVE_88: 228 case STAT_SLAVE_A0: 229 case STAT_SLAVE_A8: 230 case STAT_SLAVE_LOST: 231 case STAT_SLAVE_NAK: 232 case STAT_SLAVE_ACK: 233 return -EOPNOTSUPP; 234 235 case STAT_TXDATA_NAK: 236 case STAT_BUS_ERROR: 237 return -EIO; 238 case STAT_TXADDR_NAK: 239 case STAT_RXADDR_NAK: 240 case STAT_AD2W_NAK: 241 return -ENXIO; 242 default: 243 dev_err(i2c->dev, "unhandled state: %d\n", stat); 244 return -EIO; 245 } 246 } 247 248 static int octeon_i2c_recovery(struct octeon_i2c *i2c) 249 { 250 int ret; 251 252 ret = i2c_recover_bus(&i2c->adap); 253 if (ret) 254 /* recover failed, try hardware re-init */ 255 ret = octeon_i2c_init_lowlevel(i2c); 256 return ret; 257 } 258 259 /** 260 * octeon_i2c_start - send START to the bus 261 * @i2c: The struct octeon_i2c 262 * 263 * Returns 0 on success, otherwise a negative errno. 264 */ 265 static int octeon_i2c_start(struct octeon_i2c *i2c) 266 { 267 int ret; 268 u8 stat; 269 270 octeon_i2c_hlc_disable(i2c); 271 272 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STA); 273 ret = octeon_i2c_wait(i2c); 274 if (ret) 275 goto error; 276 277 stat = octeon_i2c_stat_read(i2c); 278 if (stat == STAT_START || stat == STAT_REP_START) 279 /* START successful, bail out */ 280 return 0; 281 282 error: 283 /* START failed, try to recover */ 284 ret = octeon_i2c_recovery(i2c); 285 return (ret) ? ret : -EAGAIN; 286 } 287 288 /* send STOP to the bus */ 289 static void octeon_i2c_stop(struct octeon_i2c *i2c) 290 { 291 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STP); 292 } 293 294 /** 295 * octeon_i2c_read - receive data from the bus via low-level controller 296 * @i2c: The struct octeon_i2c 297 * @target: Target address 298 * @data: Pointer to the location to store the data 299 * @rlength: Length of the data 300 * @recv_len: flag for length byte 301 * 302 * The address is sent over the bus, then the data is read. 303 * 304 * Returns 0 on success, otherwise a negative errno. 305 */ 306 static int octeon_i2c_read(struct octeon_i2c *i2c, int target, 307 u8 *data, u16 *rlength, bool recv_len) 308 { 309 int i, result, length = *rlength; 310 bool final_read = false; 311 312 octeon_i2c_data_write(i2c, (target << 1) | 1); 313 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); 314 315 result = octeon_i2c_wait(i2c); 316 if (result) 317 return result; 318 319 /* address OK ? */ 320 result = octeon_i2c_check_status(i2c, false); 321 if (result) 322 return result; 323 324 for (i = 0; i < length; i++) { 325 /* 326 * For the last byte to receive TWSI_CTL_AAK must not be set. 327 * 328 * A special case is I2C_M_RECV_LEN where we don't know the 329 * additional length yet. If recv_len is set we assume we're 330 * not reading the final byte and therefore need to set 331 * TWSI_CTL_AAK. 332 */ 333 if ((i + 1 == length) && !(recv_len && i == 0)) 334 final_read = true; 335 336 /* clear iflg to allow next event */ 337 if (final_read) 338 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); 339 else 340 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_AAK); 341 342 result = octeon_i2c_wait(i2c); 343 if (result) 344 return result; 345 346 data[i] = octeon_i2c_data_read(i2c, &result); 347 if (result) 348 return result; 349 if (recv_len && i == 0) { 350 if (data[i] > I2C_SMBUS_BLOCK_MAX) 351 return -EPROTO; 352 length += data[i]; 353 } 354 355 result = octeon_i2c_check_status(i2c, final_read); 356 if (result) 357 return result; 358 } 359 *rlength = length; 360 return 0; 361 } 362 363 /** 364 * octeon_i2c_write - send data to the bus via low-level controller 365 * @i2c: The struct octeon_i2c 366 * @target: Target address 367 * @data: Pointer to the data to be sent 368 * @length: Length of the data 369 * 370 * The address is sent over the bus, then the data. 371 * 372 * Returns 0 on success, otherwise a negative errno. 373 */ 374 static int octeon_i2c_write(struct octeon_i2c *i2c, int target, 375 const u8 *data, int length) 376 { 377 int i, result; 378 379 octeon_i2c_data_write(i2c, target << 1); 380 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); 381 382 result = octeon_i2c_wait(i2c); 383 if (result) 384 return result; 385 386 for (i = 0; i < length; i++) { 387 result = octeon_i2c_check_status(i2c, false); 388 if (result) 389 return result; 390 391 octeon_i2c_data_write(i2c, data[i]); 392 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); 393 394 result = octeon_i2c_wait(i2c); 395 if (result) 396 return result; 397 } 398 399 return 0; 400 } 401 402 /* high-level-controller pure read of up to 8 bytes */ 403 static int octeon_i2c_hlc_read(struct octeon_i2c *i2c, struct i2c_msg *msgs) 404 { 405 int i, j, ret = 0; 406 u64 cmd; 407 408 octeon_i2c_hlc_enable(i2c); 409 octeon_i2c_hlc_int_clear(i2c); 410 411 cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR; 412 /* SIZE */ 413 cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT; 414 /* A */ 415 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT; 416 417 if (msgs[0].flags & I2C_M_TEN) 418 cmd |= SW_TWSI_OP_10; 419 else 420 cmd |= SW_TWSI_OP_7; 421 422 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c)); 423 ret = octeon_i2c_hlc_wait(i2c); 424 if (ret) 425 goto err; 426 427 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); 428 if ((cmd & SW_TWSI_R) == 0) 429 return octeon_i2c_check_status(i2c, false); 430 431 for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--) 432 msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff; 433 434 if (msgs[0].len > 4) { 435 cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c)); 436 for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--) 437 msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff; 438 } 439 440 err: 441 return ret; 442 } 443 444 /* high-level-controller pure write of up to 8 bytes */ 445 static int octeon_i2c_hlc_write(struct octeon_i2c *i2c, struct i2c_msg *msgs) 446 { 447 int i, j, ret = 0; 448 u64 cmd; 449 450 octeon_i2c_hlc_enable(i2c); 451 octeon_i2c_hlc_int_clear(i2c); 452 453 cmd = SW_TWSI_V | SW_TWSI_SOVR; 454 /* SIZE */ 455 cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT; 456 /* A */ 457 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT; 458 459 if (msgs[0].flags & I2C_M_TEN) 460 cmd |= SW_TWSI_OP_10; 461 else 462 cmd |= SW_TWSI_OP_7; 463 464 for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--) 465 cmd |= (u64)msgs[0].buf[j] << (8 * i); 466 467 if (msgs[0].len > 4) { 468 u64 ext = 0; 469 470 for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--) 471 ext |= (u64)msgs[0].buf[j] << (8 * i); 472 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c)); 473 } 474 475 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c)); 476 ret = octeon_i2c_hlc_wait(i2c); 477 if (ret) 478 goto err; 479 480 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); 481 if ((cmd & SW_TWSI_R) == 0) 482 return octeon_i2c_check_status(i2c, false); 483 484 err: 485 return ret; 486 } 487 488 /* high-level-controller composite write+read, msg0=addr, msg1=data */ 489 static int octeon_i2c_hlc_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs) 490 { 491 int i, j, ret = 0; 492 u64 cmd; 493 494 octeon_i2c_hlc_enable(i2c); 495 496 cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR; 497 /* SIZE */ 498 cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT; 499 /* A */ 500 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT; 501 502 if (msgs[0].flags & I2C_M_TEN) 503 cmd |= SW_TWSI_OP_10_IA; 504 else 505 cmd |= SW_TWSI_OP_7_IA; 506 507 if (msgs[0].len == 2) { 508 u64 ext = 0; 509 510 cmd |= SW_TWSI_EIA; 511 ext = (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT; 512 cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT; 513 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c)); 514 } else { 515 cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT; 516 } 517 518 octeon_i2c_hlc_int_clear(i2c); 519 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c)); 520 521 ret = octeon_i2c_hlc_wait(i2c); 522 if (ret) 523 goto err; 524 525 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); 526 if ((cmd & SW_TWSI_R) == 0) 527 return octeon_i2c_check_status(i2c, false); 528 529 for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--) 530 msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff; 531 532 if (msgs[1].len > 4) { 533 cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c)); 534 for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--) 535 msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff; 536 } 537 538 err: 539 return ret; 540 } 541 542 /* high-level-controller composite write+write, m[0]len<=2, m[1]len<=8 */ 543 static int octeon_i2c_hlc_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msgs) 544 { 545 bool set_ext = false; 546 int i, j, ret = 0; 547 u64 cmd, ext = 0; 548 549 octeon_i2c_hlc_enable(i2c); 550 551 cmd = SW_TWSI_V | SW_TWSI_SOVR; 552 /* SIZE */ 553 cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT; 554 /* A */ 555 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT; 556 557 if (msgs[0].flags & I2C_M_TEN) 558 cmd |= SW_TWSI_OP_10_IA; 559 else 560 cmd |= SW_TWSI_OP_7_IA; 561 562 if (msgs[0].len == 2) { 563 cmd |= SW_TWSI_EIA; 564 ext |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT; 565 set_ext = true; 566 cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT; 567 } else { 568 cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT; 569 } 570 571 for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--) 572 cmd |= (u64)msgs[1].buf[j] << (8 * i); 573 574 if (msgs[1].len > 4) { 575 for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--) 576 ext |= (u64)msgs[1].buf[j] << (8 * i); 577 set_ext = true; 578 } 579 if (set_ext) 580 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c)); 581 582 octeon_i2c_hlc_int_clear(i2c); 583 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c)); 584 585 ret = octeon_i2c_hlc_wait(i2c); 586 if (ret) 587 goto err; 588 589 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); 590 if ((cmd & SW_TWSI_R) == 0) 591 return octeon_i2c_check_status(i2c, false); 592 593 err: 594 return ret; 595 } 596 597 /** 598 * octeon_i2c_xfer - The driver's master_xfer function 599 * @adap: Pointer to the i2c_adapter structure 600 * @msgs: Pointer to the messages to be processed 601 * @num: Length of the MSGS array 602 * 603 * Returns the number of messages processed, or a negative errno on failure. 604 */ 605 int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 606 { 607 struct octeon_i2c *i2c = i2c_get_adapdata(adap); 608 int i, ret = 0; 609 610 if (num == 1) { 611 if (msgs[0].len > 0 && msgs[0].len <= 8) { 612 if (msgs[0].flags & I2C_M_RD) 613 ret = octeon_i2c_hlc_read(i2c, msgs); 614 else 615 ret = octeon_i2c_hlc_write(i2c, msgs); 616 goto out; 617 } 618 } else if (num == 2) { 619 if ((msgs[0].flags & I2C_M_RD) == 0 && 620 (msgs[1].flags & I2C_M_RECV_LEN) == 0 && 621 msgs[0].len > 0 && msgs[0].len <= 2 && 622 msgs[1].len > 0 && msgs[1].len <= 8 && 623 msgs[0].addr == msgs[1].addr) { 624 if (msgs[1].flags & I2C_M_RD) 625 ret = octeon_i2c_hlc_comp_read(i2c, msgs); 626 else 627 ret = octeon_i2c_hlc_comp_write(i2c, msgs); 628 goto out; 629 } 630 } 631 632 for (i = 0; ret == 0 && i < num; i++) { 633 struct i2c_msg *pmsg = &msgs[i]; 634 635 /* zero-length messages are not supported */ 636 if (!pmsg->len) { 637 ret = -EOPNOTSUPP; 638 break; 639 } 640 641 ret = octeon_i2c_start(i2c); 642 if (ret) 643 return ret; 644 645 if (pmsg->flags & I2C_M_RD) 646 ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf, 647 &pmsg->len, pmsg->flags & I2C_M_RECV_LEN); 648 else 649 ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf, 650 pmsg->len); 651 } 652 octeon_i2c_stop(i2c); 653 out: 654 return (ret != 0) ? ret : num; 655 } 656 657 /* calculate and set clock divisors */ 658 void octeon_i2c_set_clock(struct octeon_i2c *i2c) 659 { 660 int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff; 661 int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000; 662 663 for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) { 664 /* 665 * An mdiv value of less than 2 seems to not work well 666 * with ds1337 RTCs, so we constrain it to larger values. 667 */ 668 for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) { 669 /* 670 * For given ndiv and mdiv values check the 671 * two closest thp values. 672 */ 673 tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10; 674 tclk *= (1 << ndiv_idx); 675 thp_base = (i2c->sys_freq / (tclk * 2)) - 1; 676 677 for (inc = 0; inc <= 1; inc++) { 678 thp_idx = thp_base + inc; 679 if (thp_idx < 5 || thp_idx > 0xff) 680 continue; 681 682 foscl = i2c->sys_freq / (2 * (thp_idx + 1)); 683 foscl = foscl / (1 << ndiv_idx); 684 foscl = foscl / (mdiv_idx + 1) / 10; 685 diff = abs(foscl - i2c->twsi_freq); 686 if (diff < delta_hz) { 687 delta_hz = diff; 688 thp = thp_idx; 689 mdiv = mdiv_idx; 690 ndiv = ndiv_idx; 691 } 692 } 693 } 694 } 695 octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp); 696 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv); 697 } 698 699 int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c) 700 { 701 u8 status = 0; 702 int tries; 703 704 /* reset controller */ 705 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0); 706 707 for (tries = 10; tries && status != STAT_IDLE; tries--) { 708 udelay(1); 709 status = octeon_i2c_stat_read(i2c); 710 if (status == STAT_IDLE) 711 break; 712 } 713 714 if (status != STAT_IDLE) { 715 dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", 716 __func__, status); 717 return -EIO; 718 } 719 720 /* toggle twice to force both teardowns */ 721 octeon_i2c_hlc_enable(i2c); 722 octeon_i2c_hlc_disable(i2c); 723 return 0; 724 } 725 726 static int octeon_i2c_get_scl(struct i2c_adapter *adap) 727 { 728 struct octeon_i2c *i2c = i2c_get_adapdata(adap); 729 u64 state; 730 731 state = octeon_i2c_read_int(i2c); 732 return state & TWSI_INT_SCL; 733 } 734 735 static void octeon_i2c_set_scl(struct i2c_adapter *adap, int val) 736 { 737 struct octeon_i2c *i2c = i2c_get_adapdata(adap); 738 739 octeon_i2c_write_int(i2c, val ? 0 : TWSI_INT_SCL_OVR); 740 } 741 742 static int octeon_i2c_get_sda(struct i2c_adapter *adap) 743 { 744 struct octeon_i2c *i2c = i2c_get_adapdata(adap); 745 u64 state; 746 747 state = octeon_i2c_read_int(i2c); 748 return state & TWSI_INT_SDA; 749 } 750 751 static void octeon_i2c_prepare_recovery(struct i2c_adapter *adap) 752 { 753 struct octeon_i2c *i2c = i2c_get_adapdata(adap); 754 755 octeon_i2c_hlc_disable(i2c); 756 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0); 757 /* wait for software reset to settle */ 758 udelay(5); 759 760 /* 761 * Bring control register to a good state regardless 762 * of HLC state. 763 */ 764 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); 765 766 octeon_i2c_write_int(i2c, 0); 767 } 768 769 static void octeon_i2c_unprepare_recovery(struct i2c_adapter *adap) 770 { 771 struct octeon_i2c *i2c = i2c_get_adapdata(adap); 772 773 /* 774 * Generate STOP to finish the unfinished transaction. 775 * Can't generate STOP via the TWSI CTL register 776 * since it could bring the TWSI controller into an inoperable state. 777 */ 778 octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR | TWSI_INT_SCL_OVR); 779 udelay(5); 780 octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR); 781 udelay(5); 782 octeon_i2c_write_int(i2c, 0); 783 } 784 785 struct i2c_bus_recovery_info octeon_i2c_recovery_info = { 786 .recover_bus = i2c_generic_scl_recovery, 787 .get_scl = octeon_i2c_get_scl, 788 .set_scl = octeon_i2c_set_scl, 789 .get_sda = octeon_i2c_get_sda, 790 .prepare_recovery = octeon_i2c_prepare_recovery, 791 .unprepare_recovery = octeon_i2c_unprepare_recovery, 792 }; 793