1 /* 2 * (C) Copyright 2009-2010 3 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com 4 * 5 * Portions Copyright (C) 2010 - 2016 Cavium, Inc. 6 * 7 * This file contains the shared part of the driver for the i2c adapter in 8 * Cavium Networks' OCTEON processors and ThunderX SOCs. 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/i2c.h> 17 #include <linux/interrupt.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 21 #include "i2c-octeon-core.h" 22 23 /* interrupt service routine */ 24 irqreturn_t octeon_i2c_isr(int irq, void *dev_id) 25 { 26 struct octeon_i2c *i2c = dev_id; 27 28 i2c->int_disable(i2c); 29 wake_up(&i2c->queue); 30 31 return IRQ_HANDLED; 32 } 33 34 static bool octeon_i2c_test_iflg(struct octeon_i2c *i2c) 35 { 36 return (octeon_i2c_ctl_read(i2c) & TWSI_CTL_IFLG); 37 } 38 39 /** 40 * octeon_i2c_wait - wait for the IFLG to be set 41 * @i2c: The struct octeon_i2c 42 * 43 * Returns 0 on success, otherwise a negative errno. 44 */ 45 static int octeon_i2c_wait(struct octeon_i2c *i2c) 46 { 47 long time_left; 48 49 /* 50 * Some chip revisions don't assert the irq in the interrupt 51 * controller. So we must poll for the IFLG change. 52 */ 53 if (i2c->broken_irq_mode) { 54 u64 end = get_jiffies_64() + i2c->adap.timeout; 55 56 while (!octeon_i2c_test_iflg(i2c) && 57 time_before64(get_jiffies_64(), end)) 58 usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT); 59 60 return octeon_i2c_test_iflg(i2c) ? 0 : -ETIMEDOUT; 61 } 62 63 i2c->int_enable(i2c); 64 time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c), 65 i2c->adap.timeout); 66 i2c->int_disable(i2c); 67 68 if (i2c->broken_irq_check && !time_left && 69 octeon_i2c_test_iflg(i2c)) { 70 dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n"); 71 i2c->broken_irq_mode = true; 72 return 0; 73 } 74 75 if (!time_left) 76 return -ETIMEDOUT; 77 78 return 0; 79 } 80 81 static bool octeon_i2c_hlc_test_valid(struct octeon_i2c *i2c) 82 { 83 return (__raw_readq(i2c->twsi_base + SW_TWSI(i2c)) & SW_TWSI_V) == 0; 84 } 85 86 static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c) 87 { 88 /* clear ST/TS events, listen for neither */ 89 octeon_i2c_write_int(i2c, TWSI_INT_ST_INT | TWSI_INT_TS_INT); 90 } 91 92 /* 93 * Cleanup low-level state & enable high-level controller. 94 */ 95 static void octeon_i2c_hlc_enable(struct octeon_i2c *i2c) 96 { 97 int try = 0; 98 u64 val; 99 100 if (i2c->hlc_enabled) 101 return; 102 i2c->hlc_enabled = true; 103 104 while (1) { 105 val = octeon_i2c_ctl_read(i2c); 106 if (!(val & (TWSI_CTL_STA | TWSI_CTL_STP))) 107 break; 108 109 /* clear IFLG event */ 110 if (val & TWSI_CTL_IFLG) 111 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); 112 113 if (try++ > 100) { 114 pr_err("%s: giving up\n", __func__); 115 break; 116 } 117 118 /* spin until any start/stop has finished */ 119 udelay(10); 120 } 121 octeon_i2c_ctl_write(i2c, TWSI_CTL_CE | TWSI_CTL_AAK | TWSI_CTL_ENAB); 122 } 123 124 static void octeon_i2c_hlc_disable(struct octeon_i2c *i2c) 125 { 126 if (!i2c->hlc_enabled) 127 return; 128 129 i2c->hlc_enabled = false; 130 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); 131 } 132 133 /** 134 * octeon_i2c_hlc_wait - wait for an HLC operation to complete 135 * @i2c: The struct octeon_i2c 136 * 137 * Returns 0 on success, otherwise -ETIMEDOUT. 138 */ 139 static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c) 140 { 141 int time_left; 142 143 /* 144 * Some cn38xx boards don't assert the irq in the interrupt 145 * controller. So we must poll for the valid bit change. 146 */ 147 if (i2c->broken_irq_mode) { 148 u64 end = get_jiffies_64() + i2c->adap.timeout; 149 150 while (!octeon_i2c_hlc_test_valid(i2c) && 151 time_before64(get_jiffies_64(), end)) 152 usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT); 153 154 return octeon_i2c_hlc_test_valid(i2c) ? 0 : -ETIMEDOUT; 155 } 156 157 i2c->hlc_int_enable(i2c); 158 time_left = wait_event_timeout(i2c->queue, 159 octeon_i2c_hlc_test_valid(i2c), 160 i2c->adap.timeout); 161 i2c->hlc_int_disable(i2c); 162 if (!time_left) 163 octeon_i2c_hlc_int_clear(i2c); 164 165 if (i2c->broken_irq_check && !time_left && 166 octeon_i2c_hlc_test_valid(i2c)) { 167 dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n"); 168 i2c->broken_irq_mode = true; 169 return 0; 170 } 171 172 if (!time_left) 173 return -ETIMEDOUT; 174 return 0; 175 } 176 177 static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read) 178 { 179 u8 stat; 180 181 /* 182 * This is ugly... in HLC mode the status is not in the status register 183 * but in the lower 8 bits of SW_TWSI. 184 */ 185 if (i2c->hlc_enabled) 186 stat = __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); 187 else 188 stat = octeon_i2c_stat_read(i2c); 189 190 switch (stat) { 191 /* Everything is fine */ 192 case STAT_IDLE: 193 case STAT_AD2W_ACK: 194 case STAT_RXADDR_ACK: 195 case STAT_TXADDR_ACK: 196 case STAT_TXDATA_ACK: 197 return 0; 198 199 /* ACK allowed on pre-terminal bytes only */ 200 case STAT_RXDATA_ACK: 201 if (!final_read) 202 return 0; 203 return -EIO; 204 205 /* NAK allowed on terminal byte only */ 206 case STAT_RXDATA_NAK: 207 if (final_read) 208 return 0; 209 return -EIO; 210 211 /* Arbitration lost */ 212 case STAT_LOST_ARB_38: 213 case STAT_LOST_ARB_68: 214 case STAT_LOST_ARB_78: 215 case STAT_LOST_ARB_B0: 216 return -EAGAIN; 217 218 /* Being addressed as slave, should back off & listen */ 219 case STAT_SLAVE_60: 220 case STAT_SLAVE_70: 221 case STAT_GENDATA_ACK: 222 case STAT_GENDATA_NAK: 223 return -EOPNOTSUPP; 224 225 /* Core busy as slave */ 226 case STAT_SLAVE_80: 227 case STAT_SLAVE_88: 228 case STAT_SLAVE_A0: 229 case STAT_SLAVE_A8: 230 case STAT_SLAVE_LOST: 231 case STAT_SLAVE_NAK: 232 case STAT_SLAVE_ACK: 233 return -EOPNOTSUPP; 234 235 case STAT_TXDATA_NAK: 236 return -EIO; 237 case STAT_TXADDR_NAK: 238 case STAT_RXADDR_NAK: 239 case STAT_AD2W_NAK: 240 return -ENXIO; 241 default: 242 dev_err(i2c->dev, "unhandled state: %d\n", stat); 243 return -EIO; 244 } 245 } 246 247 static int octeon_i2c_recovery(struct octeon_i2c *i2c) 248 { 249 int ret; 250 251 ret = i2c_recover_bus(&i2c->adap); 252 if (ret) 253 /* recover failed, try hardware re-init */ 254 ret = octeon_i2c_init_lowlevel(i2c); 255 return ret; 256 } 257 258 /** 259 * octeon_i2c_start - send START to the bus 260 * @i2c: The struct octeon_i2c 261 * 262 * Returns 0 on success, otherwise a negative errno. 263 */ 264 static int octeon_i2c_start(struct octeon_i2c *i2c) 265 { 266 int ret; 267 u8 stat; 268 269 octeon_i2c_hlc_disable(i2c); 270 271 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STA); 272 ret = octeon_i2c_wait(i2c); 273 if (ret) 274 goto error; 275 276 stat = octeon_i2c_stat_read(i2c); 277 if (stat == STAT_START || stat == STAT_REP_START) 278 /* START successful, bail out */ 279 return 0; 280 281 error: 282 /* START failed, try to recover */ 283 ret = octeon_i2c_recovery(i2c); 284 return (ret) ? ret : -EAGAIN; 285 } 286 287 /* send STOP to the bus */ 288 static void octeon_i2c_stop(struct octeon_i2c *i2c) 289 { 290 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STP); 291 } 292 293 /** 294 * octeon_i2c_read - receive data from the bus via low-level controller 295 * @i2c: The struct octeon_i2c 296 * @target: Target address 297 * @data: Pointer to the location to store the data 298 * @rlength: Length of the data 299 * @recv_len: flag for length byte 300 * 301 * The address is sent over the bus, then the data is read. 302 * 303 * Returns 0 on success, otherwise a negative errno. 304 */ 305 static int octeon_i2c_read(struct octeon_i2c *i2c, int target, 306 u8 *data, u16 *rlength, bool recv_len) 307 { 308 int i, result, length = *rlength; 309 bool final_read = false; 310 311 octeon_i2c_data_write(i2c, (target << 1) | 1); 312 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); 313 314 result = octeon_i2c_wait(i2c); 315 if (result) 316 return result; 317 318 /* address OK ? */ 319 result = octeon_i2c_check_status(i2c, false); 320 if (result) 321 return result; 322 323 for (i = 0; i < length; i++) { 324 /* 325 * For the last byte to receive TWSI_CTL_AAK must not be set. 326 * 327 * A special case is I2C_M_RECV_LEN where we don't know the 328 * additional length yet. If recv_len is set we assume we're 329 * not reading the final byte and therefore need to set 330 * TWSI_CTL_AAK. 331 */ 332 if ((i + 1 == length) && !(recv_len && i == 0)) 333 final_read = true; 334 335 /* clear iflg to allow next event */ 336 if (final_read) 337 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); 338 else 339 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_AAK); 340 341 result = octeon_i2c_wait(i2c); 342 if (result) 343 return result; 344 345 data[i] = octeon_i2c_data_read(i2c); 346 if (recv_len && i == 0) { 347 if (data[i] > I2C_SMBUS_BLOCK_MAX + 1) 348 return -EPROTO; 349 length += data[i]; 350 } 351 352 result = octeon_i2c_check_status(i2c, final_read); 353 if (result) 354 return result; 355 } 356 *rlength = length; 357 return 0; 358 } 359 360 /** 361 * octeon_i2c_write - send data to the bus via low-level controller 362 * @i2c: The struct octeon_i2c 363 * @target: Target address 364 * @data: Pointer to the data to be sent 365 * @length: Length of the data 366 * 367 * The address is sent over the bus, then the data. 368 * 369 * Returns 0 on success, otherwise a negative errno. 370 */ 371 static int octeon_i2c_write(struct octeon_i2c *i2c, int target, 372 const u8 *data, int length) 373 { 374 int i, result; 375 376 octeon_i2c_data_write(i2c, target << 1); 377 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); 378 379 result = octeon_i2c_wait(i2c); 380 if (result) 381 return result; 382 383 for (i = 0; i < length; i++) { 384 result = octeon_i2c_check_status(i2c, false); 385 if (result) 386 return result; 387 388 octeon_i2c_data_write(i2c, data[i]); 389 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); 390 391 result = octeon_i2c_wait(i2c); 392 if (result) 393 return result; 394 } 395 396 return 0; 397 } 398 399 /* high-level-controller pure read of up to 8 bytes */ 400 static int octeon_i2c_hlc_read(struct octeon_i2c *i2c, struct i2c_msg *msgs) 401 { 402 int i, j, ret = 0; 403 u64 cmd; 404 405 octeon_i2c_hlc_enable(i2c); 406 octeon_i2c_hlc_int_clear(i2c); 407 408 cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR; 409 /* SIZE */ 410 cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT; 411 /* A */ 412 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT; 413 414 if (msgs[0].flags & I2C_M_TEN) 415 cmd |= SW_TWSI_OP_10; 416 else 417 cmd |= SW_TWSI_OP_7; 418 419 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c)); 420 ret = octeon_i2c_hlc_wait(i2c); 421 if (ret) 422 goto err; 423 424 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); 425 if ((cmd & SW_TWSI_R) == 0) 426 return octeon_i2c_check_status(i2c, false); 427 428 for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--) 429 msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff; 430 431 if (msgs[0].len > 4) { 432 cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c)); 433 for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--) 434 msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff; 435 } 436 437 err: 438 return ret; 439 } 440 441 /* high-level-controller pure write of up to 8 bytes */ 442 static int octeon_i2c_hlc_write(struct octeon_i2c *i2c, struct i2c_msg *msgs) 443 { 444 int i, j, ret = 0; 445 u64 cmd; 446 447 octeon_i2c_hlc_enable(i2c); 448 octeon_i2c_hlc_int_clear(i2c); 449 450 cmd = SW_TWSI_V | SW_TWSI_SOVR; 451 /* SIZE */ 452 cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT; 453 /* A */ 454 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT; 455 456 if (msgs[0].flags & I2C_M_TEN) 457 cmd |= SW_TWSI_OP_10; 458 else 459 cmd |= SW_TWSI_OP_7; 460 461 for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--) 462 cmd |= (u64)msgs[0].buf[j] << (8 * i); 463 464 if (msgs[0].len > 4) { 465 u64 ext = 0; 466 467 for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--) 468 ext |= (u64)msgs[0].buf[j] << (8 * i); 469 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c)); 470 } 471 472 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c)); 473 ret = octeon_i2c_hlc_wait(i2c); 474 if (ret) 475 goto err; 476 477 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); 478 if ((cmd & SW_TWSI_R) == 0) 479 return octeon_i2c_check_status(i2c, false); 480 481 err: 482 return ret; 483 } 484 485 /* high-level-controller composite write+read, msg0=addr, msg1=data */ 486 static int octeon_i2c_hlc_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs) 487 { 488 int i, j, ret = 0; 489 u64 cmd; 490 491 octeon_i2c_hlc_enable(i2c); 492 493 cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR; 494 /* SIZE */ 495 cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT; 496 /* A */ 497 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT; 498 499 if (msgs[0].flags & I2C_M_TEN) 500 cmd |= SW_TWSI_OP_10_IA; 501 else 502 cmd |= SW_TWSI_OP_7_IA; 503 504 if (msgs[0].len == 2) { 505 u64 ext = 0; 506 507 cmd |= SW_TWSI_EIA; 508 ext = (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT; 509 cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT; 510 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c)); 511 } else { 512 cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT; 513 } 514 515 octeon_i2c_hlc_int_clear(i2c); 516 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c)); 517 518 ret = octeon_i2c_hlc_wait(i2c); 519 if (ret) 520 goto err; 521 522 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); 523 if ((cmd & SW_TWSI_R) == 0) 524 return octeon_i2c_check_status(i2c, false); 525 526 for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--) 527 msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff; 528 529 if (msgs[1].len > 4) { 530 cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c)); 531 for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--) 532 msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff; 533 } 534 535 err: 536 return ret; 537 } 538 539 /* high-level-controller composite write+write, m[0]len<=2, m[1]len<=8 */ 540 static int octeon_i2c_hlc_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msgs) 541 { 542 bool set_ext = false; 543 int i, j, ret = 0; 544 u64 cmd, ext = 0; 545 546 octeon_i2c_hlc_enable(i2c); 547 548 cmd = SW_TWSI_V | SW_TWSI_SOVR; 549 /* SIZE */ 550 cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT; 551 /* A */ 552 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT; 553 554 if (msgs[0].flags & I2C_M_TEN) 555 cmd |= SW_TWSI_OP_10_IA; 556 else 557 cmd |= SW_TWSI_OP_7_IA; 558 559 if (msgs[0].len == 2) { 560 cmd |= SW_TWSI_EIA; 561 ext |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT; 562 set_ext = true; 563 cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT; 564 } else { 565 cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT; 566 } 567 568 for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--) 569 cmd |= (u64)msgs[1].buf[j] << (8 * i); 570 571 if (msgs[1].len > 4) { 572 for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--) 573 ext |= (u64)msgs[1].buf[j] << (8 * i); 574 set_ext = true; 575 } 576 if (set_ext) 577 octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c)); 578 579 octeon_i2c_hlc_int_clear(i2c); 580 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c)); 581 582 ret = octeon_i2c_hlc_wait(i2c); 583 if (ret) 584 goto err; 585 586 cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); 587 if ((cmd & SW_TWSI_R) == 0) 588 return octeon_i2c_check_status(i2c, false); 589 590 err: 591 return ret; 592 } 593 594 /** 595 * octeon_i2c_xfer - The driver's master_xfer function 596 * @adap: Pointer to the i2c_adapter structure 597 * @msgs: Pointer to the messages to be processed 598 * @num: Length of the MSGS array 599 * 600 * Returns the number of messages processed, or a negative errno on failure. 601 */ 602 int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 603 { 604 struct octeon_i2c *i2c = i2c_get_adapdata(adap); 605 int i, ret = 0; 606 607 if (num == 1) { 608 if (msgs[0].len > 0 && msgs[0].len <= 8) { 609 if (msgs[0].flags & I2C_M_RD) 610 ret = octeon_i2c_hlc_read(i2c, msgs); 611 else 612 ret = octeon_i2c_hlc_write(i2c, msgs); 613 goto out; 614 } 615 } else if (num == 2) { 616 if ((msgs[0].flags & I2C_M_RD) == 0 && 617 (msgs[1].flags & I2C_M_RECV_LEN) == 0 && 618 msgs[0].len > 0 && msgs[0].len <= 2 && 619 msgs[1].len > 0 && msgs[1].len <= 8 && 620 msgs[0].addr == msgs[1].addr) { 621 if (msgs[1].flags & I2C_M_RD) 622 ret = octeon_i2c_hlc_comp_read(i2c, msgs); 623 else 624 ret = octeon_i2c_hlc_comp_write(i2c, msgs); 625 goto out; 626 } 627 } 628 629 for (i = 0; ret == 0 && i < num; i++) { 630 struct i2c_msg *pmsg = &msgs[i]; 631 632 /* zero-length messages are not supported */ 633 if (!pmsg->len) { 634 ret = -EOPNOTSUPP; 635 break; 636 } 637 638 ret = octeon_i2c_start(i2c); 639 if (ret) 640 return ret; 641 642 if (pmsg->flags & I2C_M_RD) 643 ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf, 644 &pmsg->len, pmsg->flags & I2C_M_RECV_LEN); 645 else 646 ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf, 647 pmsg->len); 648 } 649 octeon_i2c_stop(i2c); 650 out: 651 return (ret != 0) ? ret : num; 652 } 653 654 /* calculate and set clock divisors */ 655 void octeon_i2c_set_clock(struct octeon_i2c *i2c) 656 { 657 int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff; 658 int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000; 659 660 for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) { 661 /* 662 * An mdiv value of less than 2 seems to not work well 663 * with ds1337 RTCs, so we constrain it to larger values. 664 */ 665 for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) { 666 /* 667 * For given ndiv and mdiv values check the 668 * two closest thp values. 669 */ 670 tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10; 671 tclk *= (1 << ndiv_idx); 672 thp_base = (i2c->sys_freq / (tclk * 2)) - 1; 673 674 for (inc = 0; inc <= 1; inc++) { 675 thp_idx = thp_base + inc; 676 if (thp_idx < 5 || thp_idx > 0xff) 677 continue; 678 679 foscl = i2c->sys_freq / (2 * (thp_idx + 1)); 680 foscl = foscl / (1 << ndiv_idx); 681 foscl = foscl / (mdiv_idx + 1) / 10; 682 diff = abs(foscl - i2c->twsi_freq); 683 if (diff < delta_hz) { 684 delta_hz = diff; 685 thp = thp_idx; 686 mdiv = mdiv_idx; 687 ndiv = ndiv_idx; 688 } 689 } 690 } 691 } 692 octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp); 693 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv); 694 } 695 696 int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c) 697 { 698 u8 status = 0; 699 int tries; 700 701 /* reset controller */ 702 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0); 703 704 for (tries = 10; tries && status != STAT_IDLE; tries--) { 705 udelay(1); 706 status = octeon_i2c_stat_read(i2c); 707 if (status == STAT_IDLE) 708 break; 709 } 710 711 if (status != STAT_IDLE) { 712 dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", 713 __func__, status); 714 return -EIO; 715 } 716 717 /* toggle twice to force both teardowns */ 718 octeon_i2c_hlc_enable(i2c); 719 octeon_i2c_hlc_disable(i2c); 720 return 0; 721 } 722 723 static int octeon_i2c_get_scl(struct i2c_adapter *adap) 724 { 725 struct octeon_i2c *i2c = i2c_get_adapdata(adap); 726 u64 state; 727 728 state = octeon_i2c_read_int(i2c); 729 return state & TWSI_INT_SCL; 730 } 731 732 static void octeon_i2c_set_scl(struct i2c_adapter *adap, int val) 733 { 734 struct octeon_i2c *i2c = i2c_get_adapdata(adap); 735 736 octeon_i2c_write_int(i2c, val ? 0 : TWSI_INT_SCL_OVR); 737 } 738 739 static int octeon_i2c_get_sda(struct i2c_adapter *adap) 740 { 741 struct octeon_i2c *i2c = i2c_get_adapdata(adap); 742 u64 state; 743 744 state = octeon_i2c_read_int(i2c); 745 return state & TWSI_INT_SDA; 746 } 747 748 static void octeon_i2c_prepare_recovery(struct i2c_adapter *adap) 749 { 750 struct octeon_i2c *i2c = i2c_get_adapdata(adap); 751 752 octeon_i2c_hlc_disable(i2c); 753 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0); 754 /* wait for software reset to settle */ 755 udelay(5); 756 757 /* 758 * Bring control register to a good state regardless 759 * of HLC state. 760 */ 761 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); 762 763 octeon_i2c_write_int(i2c, 0); 764 } 765 766 static void octeon_i2c_unprepare_recovery(struct i2c_adapter *adap) 767 { 768 struct octeon_i2c *i2c = i2c_get_adapdata(adap); 769 770 /* 771 * Generate STOP to finish the unfinished transaction. 772 * Can't generate STOP via the TWSI CTL register 773 * since it could bring the TWSI controller into an inoperable state. 774 */ 775 octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR | TWSI_INT_SCL_OVR); 776 udelay(5); 777 octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR); 778 udelay(5); 779 octeon_i2c_write_int(i2c, 0); 780 } 781 782 struct i2c_bus_recovery_info octeon_i2c_recovery_info = { 783 .recover_bus = i2c_generic_scl_recovery, 784 .get_scl = octeon_i2c_get_scl, 785 .set_scl = octeon_i2c_set_scl, 786 .get_sda = octeon_i2c_get_sda, 787 .prepare_recovery = octeon_i2c_prepare_recovery, 788 .unprepare_recovery = octeon_i2c_unprepare_recovery, 789 }; 790