1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller 4 * (https://opencores.org/project/i2c/overview) 5 * 6 * Peter Korsgaard <peter@korsgaard.com> 7 * 8 * Support for the GRLIB port of the controller by 9 * Andreas Larsson <andreas@gaisler.com> 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/err.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/errno.h> 18 #include <linux/platform_device.h> 19 #include <linux/i2c.h> 20 #include <linux/interrupt.h> 21 #include <linux/wait.h> 22 #include <linux/platform_data/i2c-ocores.h> 23 #include <linux/slab.h> 24 #include <linux/io.h> 25 #include <linux/log2.h> 26 #include <linux/spinlock.h> 27 #include <linux/iopoll.h> 28 #include <linux/jiffies.h> 29 30 /* 31 * 'process_lock' exists because ocores_process() and ocores_process_timeout() 32 * can't run in parallel. 33 */ 34 struct ocores_i2c { 35 void __iomem *base; 36 u32 reg_shift; 37 u32 reg_io_width; 38 unsigned long flags; 39 wait_queue_head_t wait; 40 struct i2c_adapter adap; 41 struct i2c_msg *msg; 42 int pos; 43 int nmsgs; 44 int state; /* see STATE_ */ 45 spinlock_t process_lock; 46 struct clk *clk; 47 int ip_clock_khz; 48 int bus_clock_khz; 49 void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value); 50 u8 (*getreg)(struct ocores_i2c *i2c, int reg); 51 }; 52 53 /* registers */ 54 #define OCI2C_PRELOW 0 55 #define OCI2C_PREHIGH 1 56 #define OCI2C_CONTROL 2 57 #define OCI2C_DATA 3 58 #define OCI2C_CMD 4 /* write only */ 59 #define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */ 60 61 #define OCI2C_CTRL_IEN 0x40 62 #define OCI2C_CTRL_EN 0x80 63 64 #define OCI2C_CMD_START 0x91 65 #define OCI2C_CMD_STOP 0x41 66 #define OCI2C_CMD_READ 0x21 67 #define OCI2C_CMD_WRITE 0x11 68 #define OCI2C_CMD_READ_ACK 0x21 69 #define OCI2C_CMD_READ_NACK 0x29 70 #define OCI2C_CMD_IACK 0x01 71 72 #define OCI2C_STAT_IF 0x01 73 #define OCI2C_STAT_TIP 0x02 74 #define OCI2C_STAT_ARBLOST 0x20 75 #define OCI2C_STAT_BUSY 0x40 76 #define OCI2C_STAT_NACK 0x80 77 78 #define STATE_DONE 0 79 #define STATE_START 1 80 #define STATE_WRITE 2 81 #define STATE_READ 3 82 #define STATE_ERROR 4 83 84 #define TYPE_OCORES 0 85 #define TYPE_GRLIB 1 86 87 #define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */ 88 89 static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value) 90 { 91 iowrite8(value, i2c->base + (reg << i2c->reg_shift)); 92 } 93 94 static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value) 95 { 96 iowrite16(value, i2c->base + (reg << i2c->reg_shift)); 97 } 98 99 static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value) 100 { 101 iowrite32(value, i2c->base + (reg << i2c->reg_shift)); 102 } 103 104 static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value) 105 { 106 iowrite16be(value, i2c->base + (reg << i2c->reg_shift)); 107 } 108 109 static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value) 110 { 111 iowrite32be(value, i2c->base + (reg << i2c->reg_shift)); 112 } 113 114 static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg) 115 { 116 return ioread8(i2c->base + (reg << i2c->reg_shift)); 117 } 118 119 static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg) 120 { 121 return ioread16(i2c->base + (reg << i2c->reg_shift)); 122 } 123 124 static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg) 125 { 126 return ioread32(i2c->base + (reg << i2c->reg_shift)); 127 } 128 129 static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg) 130 { 131 return ioread16be(i2c->base + (reg << i2c->reg_shift)); 132 } 133 134 static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg) 135 { 136 return ioread32be(i2c->base + (reg << i2c->reg_shift)); 137 } 138 139 static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value) 140 { 141 i2c->setreg(i2c, reg, value); 142 } 143 144 static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg) 145 { 146 return i2c->getreg(i2c, reg); 147 } 148 149 static void ocores_process(struct ocores_i2c *i2c, u8 stat) 150 { 151 struct i2c_msg *msg = i2c->msg; 152 unsigned long flags; 153 154 /* 155 * If we spin here is because we are in timeout, so we are going 156 * to be in STATE_ERROR. See ocores_process_timeout() 157 */ 158 spin_lock_irqsave(&i2c->process_lock, flags); 159 160 if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) { 161 /* stop has been sent */ 162 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); 163 wake_up(&i2c->wait); 164 goto out; 165 } 166 167 /* error? */ 168 if (stat & OCI2C_STAT_ARBLOST) { 169 i2c->state = STATE_ERROR; 170 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 171 goto out; 172 } 173 174 if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) { 175 i2c->state = 176 (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; 177 178 if (stat & OCI2C_STAT_NACK) { 179 i2c->state = STATE_ERROR; 180 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 181 goto out; 182 } 183 } else { 184 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA); 185 } 186 187 /* end of msg? */ 188 if (i2c->pos == msg->len) { 189 i2c->nmsgs--; 190 i2c->msg++; 191 i2c->pos = 0; 192 msg = i2c->msg; 193 194 if (i2c->nmsgs) { /* end? */ 195 /* send start? */ 196 if (!(msg->flags & I2C_M_NOSTART)) { 197 u8 addr = i2c_8bit_addr_from_msg(msg); 198 199 i2c->state = STATE_START; 200 201 oc_setreg(i2c, OCI2C_DATA, addr); 202 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); 203 goto out; 204 } 205 i2c->state = (msg->flags & I2C_M_RD) 206 ? STATE_READ : STATE_WRITE; 207 } else { 208 i2c->state = STATE_DONE; 209 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 210 goto out; 211 } 212 } 213 214 if (i2c->state == STATE_READ) { 215 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ? 216 OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK); 217 } else { 218 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]); 219 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE); 220 } 221 222 out: 223 spin_unlock_irqrestore(&i2c->process_lock, flags); 224 } 225 226 static irqreturn_t ocores_isr(int irq, void *dev_id) 227 { 228 struct ocores_i2c *i2c = dev_id; 229 u8 stat = oc_getreg(i2c, OCI2C_STATUS); 230 231 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) { 232 if ((stat & OCI2C_STAT_IF) && !(stat & OCI2C_STAT_BUSY)) 233 return IRQ_NONE; 234 } else if (!(stat & OCI2C_STAT_IF)) { 235 return IRQ_NONE; 236 } 237 ocores_process(i2c, stat); 238 239 return IRQ_HANDLED; 240 } 241 242 /** 243 * ocores_process_timeout() - Process timeout event 244 * @i2c: ocores I2C device instance 245 */ 246 static void ocores_process_timeout(struct ocores_i2c *i2c) 247 { 248 unsigned long flags; 249 250 spin_lock_irqsave(&i2c->process_lock, flags); 251 i2c->state = STATE_ERROR; 252 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 253 spin_unlock_irqrestore(&i2c->process_lock, flags); 254 } 255 256 /** 257 * ocores_wait() - Wait until something change in a given register 258 * @i2c: ocores I2C device instance 259 * @reg: register to query 260 * @mask: bitmask to apply on register value 261 * @val: expected result 262 * @timeout_us: timeout in microseconds 263 * 264 * Timeout is necessary to avoid to stay here forever when the chip 265 * does not answer correctly. 266 * 267 * Return: 0 on success, -ETIMEDOUT on timeout 268 */ 269 static int ocores_wait(struct ocores_i2c *i2c, 270 int reg, u8 mask, u8 val, 271 unsigned long timeout_us) 272 { 273 u8 status; 274 275 return read_poll_timeout_atomic(oc_getreg, status, 276 (status & mask) == val, 277 0, timeout_us, false, 278 i2c, reg); 279 } 280 281 /** 282 * ocores_poll_wait() - Wait until is possible to process some data 283 * @i2c: ocores I2C device instance 284 * 285 * Used when the device is in polling mode (interrupts disabled). 286 * 287 * Return: 0 on success, -ETIMEDOUT on timeout 288 */ 289 static int ocores_poll_wait(struct ocores_i2c *i2c) 290 { 291 u8 mask; 292 int err; 293 294 if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) { 295 /* transfer is over */ 296 mask = OCI2C_STAT_BUSY; 297 } else { 298 /* on going transfer */ 299 mask = OCI2C_STAT_TIP; 300 /* 301 * We wait for the data to be transferred (8bit), 302 * then we start polling on the ACK/NACK bit 303 */ 304 udelay((8 * 1000) / i2c->bus_clock_khz); 305 } 306 307 /* 308 * once we are here we expect to get the expected result immediately 309 * so if after 1ms we timeout then something is broken. 310 */ 311 err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, 1000); 312 if (err) 313 dev_warn(i2c->adap.dev.parent, 314 "%s: STATUS timeout, bit 0x%x did not clear in 1ms\n", 315 __func__, mask); 316 return err; 317 } 318 319 /** 320 * ocores_process_polling() - It handles an IRQ-less transfer 321 * @i2c: ocores I2C device instance 322 * 323 * Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same 324 * (only that IRQ are not produced). This means that we can re-use entirely 325 * ocores_isr(), we just add our polling code around it. 326 * 327 * It can run in atomic context 328 * 329 * Return: 0 on success, -ETIMEDOUT on timeout 330 */ 331 static int ocores_process_polling(struct ocores_i2c *i2c) 332 { 333 irqreturn_t ret; 334 int err = 0; 335 336 while (1) { 337 err = ocores_poll_wait(i2c); 338 if (err) 339 break; /* timeout */ 340 341 ret = ocores_isr(-1, i2c); 342 if (ret == IRQ_NONE) 343 break; /* all messages have been transferred */ 344 else { 345 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) 346 if (i2c->state == STATE_DONE) 347 break; 348 } 349 } 350 351 return err; 352 } 353 354 static int ocores_xfer_core(struct ocores_i2c *i2c, 355 struct i2c_msg *msgs, int num, 356 bool polling) 357 { 358 int ret = 0; 359 u8 ctrl; 360 361 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 362 if (polling) 363 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN); 364 else 365 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN); 366 367 i2c->msg = msgs; 368 i2c->pos = 0; 369 i2c->nmsgs = num; 370 i2c->state = STATE_START; 371 372 oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg)); 373 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); 374 375 if (polling) { 376 ret = ocores_process_polling(i2c); 377 } else { 378 if (wait_event_timeout(i2c->wait, 379 (i2c->state == STATE_ERROR) || 380 (i2c->state == STATE_DONE), HZ) == 0) 381 ret = -ETIMEDOUT; 382 } 383 if (ret) { 384 ocores_process_timeout(i2c); 385 return ret; 386 } 387 388 return (i2c->state == STATE_DONE) ? num : -EIO; 389 } 390 391 static int ocores_xfer_polling(struct i2c_adapter *adap, 392 struct i2c_msg *msgs, int num) 393 { 394 return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, true); 395 } 396 397 static int ocores_xfer(struct i2c_adapter *adap, 398 struct i2c_msg *msgs, int num) 399 { 400 return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, false); 401 } 402 403 static int ocores_init(struct device *dev, struct ocores_i2c *i2c) 404 { 405 int prescale; 406 int diff; 407 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 408 409 /* make sure the device is disabled */ 410 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN); 411 oc_setreg(i2c, OCI2C_CONTROL, ctrl); 412 413 prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1; 414 prescale = clamp(prescale, 0, 0xffff); 415 416 diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz; 417 if (abs(diff) > i2c->bus_clock_khz / 10) { 418 dev_err(dev, 419 "Unsupported clock settings: core: %d KHz, bus: %d KHz\n", 420 i2c->ip_clock_khz, i2c->bus_clock_khz); 421 return -EINVAL; 422 } 423 424 oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff); 425 oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8); 426 427 /* Init the device */ 428 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN); 429 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); 430 431 return 0; 432 } 433 434 435 static u32 ocores_func(struct i2c_adapter *adap) 436 { 437 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 438 } 439 440 static struct i2c_algorithm ocores_algorithm = { 441 .xfer = ocores_xfer, 442 .xfer_atomic = ocores_xfer_polling, 443 .functionality = ocores_func, 444 }; 445 446 static const struct i2c_adapter ocores_adapter = { 447 .owner = THIS_MODULE, 448 .name = "i2c-ocores", 449 .class = I2C_CLASS_DEPRECATED, 450 .algo = &ocores_algorithm, 451 }; 452 453 static const struct of_device_id ocores_i2c_match[] = { 454 { 455 .compatible = "opencores,i2c-ocores", 456 .data = (void *)TYPE_OCORES, 457 }, 458 { 459 .compatible = "aeroflexgaisler,i2cmst", 460 .data = (void *)TYPE_GRLIB, 461 }, 462 { 463 .compatible = "sifive,fu540-c000-i2c", 464 }, 465 { 466 .compatible = "sifive,i2c0", 467 }, 468 {}, 469 }; 470 MODULE_DEVICE_TABLE(of, ocores_i2c_match); 471 472 #ifdef CONFIG_OF 473 /* 474 * Read and write functions for the GRLIB port of the controller. Registers are 475 * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one 476 * register. The subsequent registers have their offsets decreased accordingly. 477 */ 478 static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg) 479 { 480 u32 rd; 481 int rreg = reg; 482 483 if (reg != OCI2C_PRELOW) 484 rreg--; 485 rd = ioread32be(i2c->base + (rreg << i2c->reg_shift)); 486 if (reg == OCI2C_PREHIGH) 487 return (u8)(rd >> 8); 488 else 489 return (u8)rd; 490 } 491 492 static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value) 493 { 494 u32 curr, wr; 495 int rreg = reg; 496 497 if (reg != OCI2C_PRELOW) 498 rreg--; 499 if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) { 500 curr = ioread32be(i2c->base + (rreg << i2c->reg_shift)); 501 if (reg == OCI2C_PRELOW) 502 wr = (curr & 0xff00) | value; 503 else 504 wr = (((u32)value) << 8) | (curr & 0xff); 505 } else { 506 wr = value; 507 } 508 iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift)); 509 } 510 511 static int ocores_i2c_of_probe(struct platform_device *pdev, 512 struct ocores_i2c *i2c) 513 { 514 struct device_node *np = pdev->dev.of_node; 515 const struct of_device_id *match; 516 u32 val; 517 u32 clock_frequency; 518 bool clock_frequency_present; 519 520 if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) { 521 /* no 'reg-shift', check for deprecated 'regstep' */ 522 if (!of_property_read_u32(np, "regstep", &val)) { 523 if (!is_power_of_2(val)) { 524 dev_err(&pdev->dev, "invalid regstep %d\n", 525 val); 526 return -EINVAL; 527 } 528 i2c->reg_shift = ilog2(val); 529 dev_warn(&pdev->dev, 530 "regstep property deprecated, use reg-shift\n"); 531 } 532 } 533 534 clock_frequency_present = !of_property_read_u32(np, "clock-frequency", 535 &clock_frequency); 536 i2c->bus_clock_khz = 100; 537 538 i2c->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); 539 if (IS_ERR(i2c->clk)) 540 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk), 541 "devm_clk_get_optional_enabled failed\n"); 542 543 i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000; 544 if (clock_frequency_present) 545 i2c->bus_clock_khz = clock_frequency / 1000; 546 if (i2c->ip_clock_khz == 0) { 547 if (of_property_read_u32(np, "opencores,ip-clock-frequency", 548 &val)) { 549 if (!clock_frequency_present) { 550 dev_err(&pdev->dev, 551 "Missing required parameter 'opencores,ip-clock-frequency'\n"); 552 return -ENODEV; 553 } 554 i2c->ip_clock_khz = clock_frequency / 1000; 555 dev_warn(&pdev->dev, 556 "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n"); 557 } else { 558 i2c->ip_clock_khz = val / 1000; 559 if (clock_frequency_present) 560 i2c->bus_clock_khz = clock_frequency / 1000; 561 } 562 } 563 564 of_property_read_u32(pdev->dev.of_node, "reg-io-width", 565 &i2c->reg_io_width); 566 567 match = of_match_node(ocores_i2c_match, pdev->dev.of_node); 568 if (match && (long)match->data == TYPE_GRLIB) { 569 dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n"); 570 i2c->setreg = oc_setreg_grlib; 571 i2c->getreg = oc_getreg_grlib; 572 } 573 574 return 0; 575 } 576 #else 577 #define ocores_i2c_of_probe(pdev, i2c) -ENODEV 578 #endif 579 580 static int ocores_i2c_probe(struct platform_device *pdev) 581 { 582 struct ocores_i2c *i2c; 583 struct ocores_i2c_platform_data *pdata; 584 struct resource *res; 585 int irq; 586 int ret; 587 int i; 588 589 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 590 if (!i2c) 591 return -ENOMEM; 592 593 spin_lock_init(&i2c->process_lock); 594 595 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 596 if (res) { 597 i2c->base = devm_ioremap_resource(&pdev->dev, res); 598 if (IS_ERR(i2c->base)) 599 return PTR_ERR(i2c->base); 600 } else { 601 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 602 if (!res) 603 return -EINVAL; 604 if (!devm_request_region(&pdev->dev, res->start, 605 resource_size(res), 606 pdev->name)) { 607 dev_err(&pdev->dev, "Can't get I/O resource.\n"); 608 return -EBUSY; 609 } 610 i2c->base = devm_ioport_map(&pdev->dev, res->start, 611 resource_size(res)); 612 if (!i2c->base) { 613 dev_err(&pdev->dev, "Can't map I/O resource.\n"); 614 return -EBUSY; 615 } 616 i2c->reg_io_width = 1; 617 } 618 619 pdata = dev_get_platdata(&pdev->dev); 620 if (pdata) { 621 i2c->reg_shift = pdata->reg_shift; 622 i2c->reg_io_width = pdata->reg_io_width; 623 i2c->ip_clock_khz = pdata->clock_khz; 624 if (pdata->bus_khz) 625 i2c->bus_clock_khz = pdata->bus_khz; 626 else 627 i2c->bus_clock_khz = 100; 628 } else { 629 ret = ocores_i2c_of_probe(pdev, i2c); 630 if (ret) 631 return ret; 632 } 633 634 if (i2c->reg_io_width == 0) 635 i2c->reg_io_width = 1; /* Set to default value */ 636 637 if (!i2c->setreg || !i2c->getreg) { 638 bool be = pdata ? pdata->big_endian : 639 of_device_is_big_endian(pdev->dev.of_node); 640 641 switch (i2c->reg_io_width) { 642 case 1: 643 i2c->setreg = oc_setreg_8; 644 i2c->getreg = oc_getreg_8; 645 break; 646 647 case 2: 648 i2c->setreg = be ? oc_setreg_16be : oc_setreg_16; 649 i2c->getreg = be ? oc_getreg_16be : oc_getreg_16; 650 break; 651 652 case 4: 653 i2c->setreg = be ? oc_setreg_32be : oc_setreg_32; 654 i2c->getreg = be ? oc_getreg_32be : oc_getreg_32; 655 break; 656 657 default: 658 dev_err(&pdev->dev, "Unsupported I/O width (%d)\n", 659 i2c->reg_io_width); 660 return -EINVAL; 661 } 662 } 663 664 init_waitqueue_head(&i2c->wait); 665 666 irq = platform_get_irq_optional(pdev, 0); 667 /* 668 * Since the SoC does have an interrupt, its DT has an interrupt 669 * property - But this should be bypassed as the IRQ logic in this 670 * SoC is broken. 671 */ 672 if (of_device_is_compatible(pdev->dev.of_node, 673 "sifive,fu540-c000-i2c")) { 674 i2c->flags |= OCORES_FLAG_BROKEN_IRQ; 675 irq = -ENXIO; 676 } 677 678 if (irq == -ENXIO) { 679 ocores_algorithm.xfer = ocores_xfer_polling; 680 } else { 681 if (irq < 0) 682 return irq; 683 } 684 685 if (ocores_algorithm.xfer != ocores_xfer_polling) { 686 ret = devm_request_any_context_irq(&pdev->dev, irq, 687 ocores_isr, 0, 688 pdev->name, i2c); 689 if (ret) { 690 dev_err(&pdev->dev, "Cannot claim IRQ\n"); 691 return ret; 692 } 693 } 694 695 ret = ocores_init(&pdev->dev, i2c); 696 if (ret) 697 return ret; 698 699 /* hook up driver to tree */ 700 platform_set_drvdata(pdev, i2c); 701 i2c->adap = ocores_adapter; 702 i2c_set_adapdata(&i2c->adap, i2c); 703 i2c->adap.dev.parent = &pdev->dev; 704 i2c->adap.dev.of_node = pdev->dev.of_node; 705 706 /* add i2c adapter to i2c tree */ 707 ret = i2c_add_adapter(&i2c->adap); 708 if (ret) 709 return ret; 710 711 /* add in known devices to the bus */ 712 if (pdata) { 713 for (i = 0; i < pdata->num_devices; i++) 714 i2c_new_client_device(&i2c->adap, pdata->devices + i); 715 } 716 717 return 0; 718 } 719 720 static void ocores_i2c_remove(struct platform_device *pdev) 721 { 722 struct ocores_i2c *i2c = platform_get_drvdata(pdev); 723 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 724 725 /* disable i2c logic */ 726 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN); 727 oc_setreg(i2c, OCI2C_CONTROL, ctrl); 728 729 /* remove adapter & data */ 730 i2c_del_adapter(&i2c->adap); 731 } 732 733 static int ocores_i2c_suspend(struct device *dev) 734 { 735 struct ocores_i2c *i2c = dev_get_drvdata(dev); 736 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 737 738 /* make sure the device is disabled */ 739 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN); 740 oc_setreg(i2c, OCI2C_CONTROL, ctrl); 741 742 clk_disable_unprepare(i2c->clk); 743 return 0; 744 } 745 746 static int ocores_i2c_resume(struct device *dev) 747 { 748 struct ocores_i2c *i2c = dev_get_drvdata(dev); 749 unsigned long rate; 750 int ret; 751 752 ret = clk_prepare_enable(i2c->clk); 753 if (ret) 754 return dev_err_probe(dev, ret, "clk_prepare_enable failed\n"); 755 rate = clk_get_rate(i2c->clk) / 1000; 756 if (rate) 757 i2c->ip_clock_khz = rate; 758 return ocores_init(dev, i2c); 759 } 760 761 static DEFINE_NOIRQ_DEV_PM_OPS(ocores_i2c_pm, 762 ocores_i2c_suspend, ocores_i2c_resume); 763 764 static struct platform_driver ocores_i2c_driver = { 765 .probe = ocores_i2c_probe, 766 .remove = ocores_i2c_remove, 767 .driver = { 768 .name = "ocores-i2c", 769 .of_match_table = ocores_i2c_match, 770 .pm = pm_sleep_ptr(&ocores_i2c_pm), 771 }, 772 }; 773 774 module_platform_driver(ocores_i2c_driver); 775 776 MODULE_AUTHOR("Peter Korsgaard <peter@korsgaard.com>"); 777 MODULE_DESCRIPTION("OpenCores I2C bus driver"); 778 MODULE_LICENSE("GPL"); 779 MODULE_ALIAS("platform:ocores-i2c"); 780