1 /* 2 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller 3 * (http://www.opencores.org/projects.cgi/web/i2c/overview). 4 * 5 * Peter Korsgaard <jacmet@sunsite.dk> 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/init.h> 15 #include <linux/errno.h> 16 #include <linux/platform_device.h> 17 #include <linux/i2c.h> 18 #include <linux/interrupt.h> 19 #include <linux/wait.h> 20 #include <linux/i2c-ocores.h> 21 #include <linux/slab.h> 22 #include <linux/io.h> 23 #include <linux/of_i2c.h> 24 #include <linux/log2.h> 25 26 struct ocores_i2c { 27 void __iomem *base; 28 u32 reg_shift; 29 u32 reg_io_width; 30 wait_queue_head_t wait; 31 struct i2c_adapter adap; 32 struct i2c_msg *msg; 33 int pos; 34 int nmsgs; 35 int state; /* see STATE_ */ 36 int clock_khz; 37 }; 38 39 /* registers */ 40 #define OCI2C_PRELOW 0 41 #define OCI2C_PREHIGH 1 42 #define OCI2C_CONTROL 2 43 #define OCI2C_DATA 3 44 #define OCI2C_CMD 4 /* write only */ 45 #define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */ 46 47 #define OCI2C_CTRL_IEN 0x40 48 #define OCI2C_CTRL_EN 0x80 49 50 #define OCI2C_CMD_START 0x91 51 #define OCI2C_CMD_STOP 0x41 52 #define OCI2C_CMD_READ 0x21 53 #define OCI2C_CMD_WRITE 0x11 54 #define OCI2C_CMD_READ_ACK 0x21 55 #define OCI2C_CMD_READ_NACK 0x29 56 #define OCI2C_CMD_IACK 0x01 57 58 #define OCI2C_STAT_IF 0x01 59 #define OCI2C_STAT_TIP 0x02 60 #define OCI2C_STAT_ARBLOST 0x20 61 #define OCI2C_STAT_BUSY 0x40 62 #define OCI2C_STAT_NACK 0x80 63 64 #define STATE_DONE 0 65 #define STATE_START 1 66 #define STATE_WRITE 2 67 #define STATE_READ 3 68 #define STATE_ERROR 4 69 70 static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value) 71 { 72 if (i2c->reg_io_width == 4) 73 iowrite32(value, i2c->base + (reg << i2c->reg_shift)); 74 else if (i2c->reg_io_width == 2) 75 iowrite16(value, i2c->base + (reg << i2c->reg_shift)); 76 else 77 iowrite8(value, i2c->base + (reg << i2c->reg_shift)); 78 } 79 80 static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg) 81 { 82 if (i2c->reg_io_width == 4) 83 return ioread32(i2c->base + (reg << i2c->reg_shift)); 84 else if (i2c->reg_io_width == 2) 85 return ioread16(i2c->base + (reg << i2c->reg_shift)); 86 else 87 return ioread8(i2c->base + (reg << i2c->reg_shift)); 88 } 89 90 static void ocores_process(struct ocores_i2c *i2c) 91 { 92 struct i2c_msg *msg = i2c->msg; 93 u8 stat = oc_getreg(i2c, OCI2C_STATUS); 94 95 if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) { 96 /* stop has been sent */ 97 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); 98 wake_up(&i2c->wait); 99 return; 100 } 101 102 /* error? */ 103 if (stat & OCI2C_STAT_ARBLOST) { 104 i2c->state = STATE_ERROR; 105 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 106 return; 107 } 108 109 if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) { 110 i2c->state = 111 (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; 112 113 if (stat & OCI2C_STAT_NACK) { 114 i2c->state = STATE_ERROR; 115 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 116 return; 117 } 118 } else 119 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA); 120 121 /* end of msg? */ 122 if (i2c->pos == msg->len) { 123 i2c->nmsgs--; 124 i2c->msg++; 125 i2c->pos = 0; 126 msg = i2c->msg; 127 128 if (i2c->nmsgs) { /* end? */ 129 /* send start? */ 130 if (!(msg->flags & I2C_M_NOSTART)) { 131 u8 addr = (msg->addr << 1); 132 133 if (msg->flags & I2C_M_RD) 134 addr |= 1; 135 136 i2c->state = STATE_START; 137 138 oc_setreg(i2c, OCI2C_DATA, addr); 139 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); 140 return; 141 } else 142 i2c->state = (msg->flags & I2C_M_RD) 143 ? STATE_READ : STATE_WRITE; 144 } else { 145 i2c->state = STATE_DONE; 146 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); 147 return; 148 } 149 } 150 151 if (i2c->state == STATE_READ) { 152 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ? 153 OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK); 154 } else { 155 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]); 156 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE); 157 } 158 } 159 160 static irqreturn_t ocores_isr(int irq, void *dev_id) 161 { 162 struct ocores_i2c *i2c = dev_id; 163 164 ocores_process(i2c); 165 166 return IRQ_HANDLED; 167 } 168 169 static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 170 { 171 struct ocores_i2c *i2c = i2c_get_adapdata(adap); 172 173 i2c->msg = msgs; 174 i2c->pos = 0; 175 i2c->nmsgs = num; 176 i2c->state = STATE_START; 177 178 oc_setreg(i2c, OCI2C_DATA, 179 (i2c->msg->addr << 1) | 180 ((i2c->msg->flags & I2C_M_RD) ? 1:0)); 181 182 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); 183 184 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || 185 (i2c->state == STATE_DONE), HZ)) 186 return (i2c->state == STATE_DONE) ? num : -EIO; 187 else 188 return -ETIMEDOUT; 189 } 190 191 static void ocores_init(struct ocores_i2c *i2c) 192 { 193 int prescale; 194 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 195 196 /* make sure the device is disabled */ 197 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); 198 199 prescale = (i2c->clock_khz / (5*100)) - 1; 200 oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff); 201 oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8); 202 203 /* Init the device */ 204 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); 205 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN); 206 } 207 208 209 static u32 ocores_func(struct i2c_adapter *adap) 210 { 211 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 212 } 213 214 static const struct i2c_algorithm ocores_algorithm = { 215 .master_xfer = ocores_xfer, 216 .functionality = ocores_func, 217 }; 218 219 static struct i2c_adapter ocores_adapter = { 220 .owner = THIS_MODULE, 221 .name = "i2c-ocores", 222 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, 223 .algo = &ocores_algorithm, 224 }; 225 226 #ifdef CONFIG_OF 227 static int ocores_i2c_of_probe(struct platform_device *pdev, 228 struct ocores_i2c *i2c) 229 { 230 struct device_node *np = pdev->dev.of_node; 231 u32 val; 232 233 if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) { 234 /* no 'reg-shift', check for deprecated 'regstep' */ 235 if (!of_property_read_u32(np, "regstep", &val)) { 236 if (!is_power_of_2(val)) { 237 dev_err(&pdev->dev, "invalid regstep %d\n", 238 val); 239 return -EINVAL; 240 } 241 i2c->reg_shift = ilog2(val); 242 dev_warn(&pdev->dev, 243 "regstep property deprecated, use reg-shift\n"); 244 } 245 } 246 247 if (of_property_read_u32(np, "clock-frequency", &val)) { 248 dev_err(&pdev->dev, 249 "Missing required parameter 'clock-frequency'\n"); 250 return -ENODEV; 251 } 252 i2c->clock_khz = val / 1000; 253 254 of_property_read_u32(pdev->dev.of_node, "reg-io-width", 255 &i2c->reg_io_width); 256 return 0; 257 } 258 #else 259 #define ocores_i2c_of_probe(pdev,i2c) -ENODEV 260 #endif 261 262 static int __devinit ocores_i2c_probe(struct platform_device *pdev) 263 { 264 struct ocores_i2c *i2c; 265 struct ocores_i2c_platform_data *pdata; 266 struct resource *res, *res2; 267 int ret; 268 int i; 269 270 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 271 if (!res) 272 return -ENODEV; 273 274 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 275 if (!res2) 276 return -ENODEV; 277 278 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 279 if (!i2c) 280 return -ENOMEM; 281 282 if (!devm_request_mem_region(&pdev->dev, res->start, 283 resource_size(res), pdev->name)) { 284 dev_err(&pdev->dev, "Memory region busy\n"); 285 return -EBUSY; 286 } 287 288 i2c->base = devm_ioremap_nocache(&pdev->dev, res->start, 289 resource_size(res)); 290 if (!i2c->base) { 291 dev_err(&pdev->dev, "Unable to map registers\n"); 292 return -EIO; 293 } 294 295 pdata = pdev->dev.platform_data; 296 if (pdata) { 297 i2c->reg_shift = pdata->reg_shift; 298 i2c->reg_io_width = pdata->reg_io_width; 299 i2c->clock_khz = pdata->clock_khz; 300 } else { 301 ret = ocores_i2c_of_probe(pdev, i2c); 302 if (ret) 303 return ret; 304 } 305 306 if (i2c->reg_io_width == 0) 307 i2c->reg_io_width = 1; /* Set to default value */ 308 309 ocores_init(i2c); 310 311 init_waitqueue_head(&i2c->wait); 312 ret = devm_request_irq(&pdev->dev, res2->start, ocores_isr, 0, 313 pdev->name, i2c); 314 if (ret) { 315 dev_err(&pdev->dev, "Cannot claim IRQ\n"); 316 return ret; 317 } 318 319 /* hook up driver to tree */ 320 platform_set_drvdata(pdev, i2c); 321 i2c->adap = ocores_adapter; 322 i2c_set_adapdata(&i2c->adap, i2c); 323 i2c->adap.dev.parent = &pdev->dev; 324 i2c->adap.dev.of_node = pdev->dev.of_node; 325 326 /* add i2c adapter to i2c tree */ 327 ret = i2c_add_adapter(&i2c->adap); 328 if (ret) { 329 dev_err(&pdev->dev, "Failed to add adapter\n"); 330 return ret; 331 } 332 333 /* add in known devices to the bus */ 334 if (pdata) { 335 for (i = 0; i < pdata->num_devices; i++) 336 i2c_new_device(&i2c->adap, pdata->devices + i); 337 } else { 338 of_i2c_register_devices(&i2c->adap); 339 } 340 341 return 0; 342 } 343 344 static int __devexit ocores_i2c_remove(struct platform_device *pdev) 345 { 346 struct ocores_i2c *i2c = platform_get_drvdata(pdev); 347 348 /* disable i2c logic */ 349 oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL) 350 & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); 351 352 /* remove adapter & data */ 353 i2c_del_adapter(&i2c->adap); 354 platform_set_drvdata(pdev, NULL); 355 356 return 0; 357 } 358 359 #ifdef CONFIG_PM 360 static int ocores_i2c_suspend(struct device *dev) 361 { 362 struct ocores_i2c *i2c = dev_get_drvdata(dev); 363 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 364 365 /* make sure the device is disabled */ 366 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); 367 368 return 0; 369 } 370 371 static int ocores_i2c_resume(struct device *dev) 372 { 373 struct ocores_i2c *i2c = dev_get_drvdata(dev); 374 375 ocores_init(i2c); 376 377 return 0; 378 } 379 380 static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume); 381 #define OCORES_I2C_PM (&ocores_i2c_pm) 382 #else 383 #define OCORES_I2C_PM NULL 384 #endif 385 386 static struct of_device_id ocores_i2c_match[] = { 387 { .compatible = "opencores,i2c-ocores", }, 388 {}, 389 }; 390 MODULE_DEVICE_TABLE(of, ocores_i2c_match); 391 392 static struct platform_driver ocores_i2c_driver = { 393 .probe = ocores_i2c_probe, 394 .remove = __devexit_p(ocores_i2c_remove), 395 .driver = { 396 .owner = THIS_MODULE, 397 .name = "ocores-i2c", 398 .of_match_table = ocores_i2c_match, 399 .pm = OCORES_I2C_PM, 400 }, 401 }; 402 403 module_platform_driver(ocores_i2c_driver); 404 405 MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>"); 406 MODULE_DESCRIPTION("OpenCores I2C bus driver"); 407 MODULE_LICENSE("GPL"); 408 MODULE_ALIAS("platform:ocores-i2c"); 409