1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Nvidia GPU I2C controller Driver 4 * 5 * Copyright (C) 2018 NVIDIA Corporation. All rights reserved. 6 * Author: Ajay Gupta <ajayg@nvidia.com> 7 */ 8 #include <linux/delay.h> 9 #include <linux/i2c.h> 10 #include <linux/interrupt.h> 11 #include <linux/iopoll.h> 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm.h> 16 #include <linux/pm_runtime.h> 17 18 #include <asm/unaligned.h> 19 20 /* I2C definitions */ 21 #define I2C_MST_CNTL 0x00 22 #define I2C_MST_CNTL_GEN_START BIT(0) 23 #define I2C_MST_CNTL_GEN_STOP BIT(1) 24 #define I2C_MST_CNTL_CMD_READ (1 << 2) 25 #define I2C_MST_CNTL_CMD_WRITE (2 << 2) 26 #define I2C_MST_CNTL_BURST_SIZE_SHIFT 6 27 #define I2C_MST_CNTL_GEN_NACK BIT(28) 28 #define I2C_MST_CNTL_STATUS GENMASK(30, 29) 29 #define I2C_MST_CNTL_STATUS_OKAY (0 << 29) 30 #define I2C_MST_CNTL_STATUS_NO_ACK (1 << 29) 31 #define I2C_MST_CNTL_STATUS_TIMEOUT (2 << 29) 32 #define I2C_MST_CNTL_STATUS_BUS_BUSY (3 << 29) 33 #define I2C_MST_CNTL_CYCLE_TRIGGER BIT(31) 34 35 #define I2C_MST_ADDR 0x04 36 37 #define I2C_MST_I2C0_TIMING 0x08 38 #define I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ 0x10e 39 #define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT 16 40 #define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX 255 41 #define I2C_MST_I2C0_TIMING_TIMEOUT_CHECK BIT(24) 42 43 #define I2C_MST_DATA 0x0c 44 45 #define I2C_MST_HYBRID_PADCTL 0x20 46 #define I2C_MST_HYBRID_PADCTL_MODE_I2C BIT(0) 47 #define I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV BIT(14) 48 #define I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV BIT(15) 49 50 struct gpu_i2c_dev { 51 struct device *dev; 52 void __iomem *regs; 53 struct i2c_adapter adapter; 54 struct i2c_board_info *gpu_ccgx_ucsi; 55 struct i2c_client *ccgx_client; 56 }; 57 58 static void gpu_enable_i2c_bus(struct gpu_i2c_dev *i2cd) 59 { 60 u32 val; 61 62 /* enable I2C */ 63 val = readl(i2cd->regs + I2C_MST_HYBRID_PADCTL); 64 val |= I2C_MST_HYBRID_PADCTL_MODE_I2C | 65 I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV | 66 I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV; 67 writel(val, i2cd->regs + I2C_MST_HYBRID_PADCTL); 68 69 /* enable 100KHZ mode */ 70 val = I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ; 71 val |= (I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX 72 << I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT); 73 val |= I2C_MST_I2C0_TIMING_TIMEOUT_CHECK; 74 writel(val, i2cd->regs + I2C_MST_I2C0_TIMING); 75 } 76 77 static int gpu_i2c_check_status(struct gpu_i2c_dev *i2cd) 78 { 79 u32 val; 80 int ret; 81 82 ret = readl_poll_timeout(i2cd->regs + I2C_MST_CNTL, val, 83 !(val & I2C_MST_CNTL_CYCLE_TRIGGER) || 84 (val & I2C_MST_CNTL_STATUS) != I2C_MST_CNTL_STATUS_BUS_BUSY, 85 500, 1000 * USEC_PER_MSEC); 86 87 if (ret) { 88 dev_err(i2cd->dev, "i2c timeout error %x\n", val); 89 return -ETIMEDOUT; 90 } 91 92 val = readl(i2cd->regs + I2C_MST_CNTL); 93 switch (val & I2C_MST_CNTL_STATUS) { 94 case I2C_MST_CNTL_STATUS_OKAY: 95 return 0; 96 case I2C_MST_CNTL_STATUS_NO_ACK: 97 return -ENXIO; 98 case I2C_MST_CNTL_STATUS_TIMEOUT: 99 return -ETIMEDOUT; 100 default: 101 return 0; 102 } 103 } 104 105 static int gpu_i2c_read(struct gpu_i2c_dev *i2cd, u8 *data, u16 len) 106 { 107 int status; 108 u32 val; 109 110 val = I2C_MST_CNTL_GEN_START | I2C_MST_CNTL_CMD_READ | 111 (len << I2C_MST_CNTL_BURST_SIZE_SHIFT) | 112 I2C_MST_CNTL_CYCLE_TRIGGER | I2C_MST_CNTL_GEN_NACK; 113 writel(val, i2cd->regs + I2C_MST_CNTL); 114 115 status = gpu_i2c_check_status(i2cd); 116 if (status < 0) 117 return status; 118 119 val = readl(i2cd->regs + I2C_MST_DATA); 120 switch (len) { 121 case 1: 122 data[0] = val; 123 break; 124 case 2: 125 put_unaligned_be16(val, data); 126 break; 127 case 3: 128 put_unaligned_be16(val >> 8, data); 129 data[2] = val; 130 break; 131 case 4: 132 put_unaligned_be32(val, data); 133 break; 134 default: 135 break; 136 } 137 return status; 138 } 139 140 static int gpu_i2c_start(struct gpu_i2c_dev *i2cd) 141 { 142 writel(I2C_MST_CNTL_GEN_START, i2cd->regs + I2C_MST_CNTL); 143 return gpu_i2c_check_status(i2cd); 144 } 145 146 static int gpu_i2c_stop(struct gpu_i2c_dev *i2cd) 147 { 148 writel(I2C_MST_CNTL_GEN_STOP, i2cd->regs + I2C_MST_CNTL); 149 return gpu_i2c_check_status(i2cd); 150 } 151 152 static int gpu_i2c_write(struct gpu_i2c_dev *i2cd, u8 data) 153 { 154 u32 val; 155 156 writel(data, i2cd->regs + I2C_MST_DATA); 157 158 val = I2C_MST_CNTL_CMD_WRITE | (1 << I2C_MST_CNTL_BURST_SIZE_SHIFT); 159 writel(val, i2cd->regs + I2C_MST_CNTL); 160 161 return gpu_i2c_check_status(i2cd); 162 } 163 164 static int gpu_i2c_master_xfer(struct i2c_adapter *adap, 165 struct i2c_msg *msgs, int num) 166 { 167 struct gpu_i2c_dev *i2cd = i2c_get_adapdata(adap); 168 int status, status2; 169 bool send_stop = true; 170 int i, j; 171 172 /* 173 * The controller supports maximum 4 byte read due to known 174 * limitation of sending STOP after every read. 175 */ 176 pm_runtime_get_sync(i2cd->dev); 177 for (i = 0; i < num; i++) { 178 if (msgs[i].flags & I2C_M_RD) { 179 /* program client address before starting read */ 180 writel(msgs[i].addr, i2cd->regs + I2C_MST_ADDR); 181 /* gpu_i2c_read has implicit start */ 182 status = gpu_i2c_read(i2cd, msgs[i].buf, msgs[i].len); 183 if (status < 0) 184 goto exit; 185 } else { 186 u8 addr = i2c_8bit_addr_from_msg(msgs + i); 187 188 status = gpu_i2c_start(i2cd); 189 if (status < 0) { 190 if (i == 0) 191 send_stop = false; 192 goto exit; 193 } 194 195 status = gpu_i2c_write(i2cd, addr); 196 if (status < 0) 197 goto exit; 198 199 for (j = 0; j < msgs[i].len; j++) { 200 status = gpu_i2c_write(i2cd, msgs[i].buf[j]); 201 if (status < 0) 202 goto exit; 203 } 204 } 205 } 206 send_stop = false; 207 status = gpu_i2c_stop(i2cd); 208 if (status < 0) 209 goto exit; 210 211 status = i; 212 exit: 213 if (send_stop) { 214 status2 = gpu_i2c_stop(i2cd); 215 if (status2 < 0) 216 dev_err(i2cd->dev, "i2c stop failed %d\n", status2); 217 } 218 pm_runtime_mark_last_busy(i2cd->dev); 219 pm_runtime_put_autosuspend(i2cd->dev); 220 return status; 221 } 222 223 static const struct i2c_adapter_quirks gpu_i2c_quirks = { 224 .max_read_len = 4, 225 .max_comb_2nd_msg_len = 4, 226 .flags = I2C_AQ_COMB_WRITE_THEN_READ, 227 }; 228 229 static u32 gpu_i2c_functionality(struct i2c_adapter *adap) 230 { 231 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 232 } 233 234 static const struct i2c_algorithm gpu_i2c_algorithm = { 235 .master_xfer = gpu_i2c_master_xfer, 236 .functionality = gpu_i2c_functionality, 237 }; 238 239 /* 240 * This driver is for Nvidia GPU cards with USB Type-C interface. 241 * We want to identify the cards using vendor ID and class code only 242 * to avoid dependency of adding product id for any new card which 243 * requires this driver. 244 * Currently there is no class code defined for UCSI device over PCI 245 * so using UNKNOWN class for now and it will be updated when UCSI 246 * over PCI gets a class code. 247 * There is no other NVIDIA cards with UNKNOWN class code. Even if the 248 * driver gets loaded for an undesired card then eventually i2c_read() 249 * (initiated from UCSI i2c_client) will timeout or UCSI commands will 250 * timeout. 251 */ 252 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80 253 static const struct pci_device_id gpu_i2c_ids[] = { 254 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 255 PCI_CLASS_SERIAL_UNKNOWN << 8, 0xffffff00}, 256 { } 257 }; 258 MODULE_DEVICE_TABLE(pci, gpu_i2c_ids); 259 260 static const struct property_entry ccgx_props[] = { 261 /* Use FW built for NVIDIA (nv) only */ 262 PROPERTY_ENTRY_U16("ccgx,firmware-build", ('n' << 8) | 'v'), 263 { } 264 }; 265 266 static int gpu_populate_client(struct gpu_i2c_dev *i2cd, int irq) 267 { 268 i2cd->gpu_ccgx_ucsi = devm_kzalloc(i2cd->dev, 269 sizeof(*i2cd->gpu_ccgx_ucsi), 270 GFP_KERNEL); 271 if (!i2cd->gpu_ccgx_ucsi) 272 return -ENOMEM; 273 274 strlcpy(i2cd->gpu_ccgx_ucsi->type, "ccgx-ucsi", 275 sizeof(i2cd->gpu_ccgx_ucsi->type)); 276 i2cd->gpu_ccgx_ucsi->addr = 0x8; 277 i2cd->gpu_ccgx_ucsi->irq = irq; 278 i2cd->gpu_ccgx_ucsi->properties = ccgx_props; 279 i2cd->ccgx_client = i2c_new_client_device(&i2cd->adapter, i2cd->gpu_ccgx_ucsi); 280 return PTR_ERR_OR_ZERO(i2cd->ccgx_client); 281 } 282 283 static int gpu_i2c_probe(struct pci_dev *pdev, const struct pci_device_id *id) 284 { 285 struct gpu_i2c_dev *i2cd; 286 int status; 287 288 i2cd = devm_kzalloc(&pdev->dev, sizeof(*i2cd), GFP_KERNEL); 289 if (!i2cd) 290 return -ENOMEM; 291 292 i2cd->dev = &pdev->dev; 293 dev_set_drvdata(&pdev->dev, i2cd); 294 295 status = pcim_enable_device(pdev); 296 if (status < 0) { 297 dev_err(&pdev->dev, "pcim_enable_device failed %d\n", status); 298 return status; 299 } 300 301 pci_set_master(pdev); 302 303 i2cd->regs = pcim_iomap(pdev, 0, 0); 304 if (!i2cd->regs) { 305 dev_err(&pdev->dev, "pcim_iomap failed\n"); 306 return -ENOMEM; 307 } 308 309 status = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 310 if (status < 0) { 311 dev_err(&pdev->dev, "pci_alloc_irq_vectors err %d\n", status); 312 return status; 313 } 314 315 gpu_enable_i2c_bus(i2cd); 316 317 i2c_set_adapdata(&i2cd->adapter, i2cd); 318 i2cd->adapter.owner = THIS_MODULE; 319 strlcpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter", 320 sizeof(i2cd->adapter.name)); 321 i2cd->adapter.algo = &gpu_i2c_algorithm; 322 i2cd->adapter.quirks = &gpu_i2c_quirks; 323 i2cd->adapter.dev.parent = &pdev->dev; 324 status = i2c_add_adapter(&i2cd->adapter); 325 if (status < 0) 326 goto free_irq_vectors; 327 328 status = gpu_populate_client(i2cd, pdev->irq); 329 if (status < 0) { 330 dev_err(&pdev->dev, "gpu_populate_client failed %d\n", status); 331 goto del_adapter; 332 } 333 334 pm_runtime_set_autosuspend_delay(&pdev->dev, 3000); 335 pm_runtime_use_autosuspend(&pdev->dev); 336 pm_runtime_put_autosuspend(&pdev->dev); 337 pm_runtime_allow(&pdev->dev); 338 339 return 0; 340 341 del_adapter: 342 i2c_del_adapter(&i2cd->adapter); 343 free_irq_vectors: 344 pci_free_irq_vectors(pdev); 345 return status; 346 } 347 348 static void gpu_i2c_remove(struct pci_dev *pdev) 349 { 350 struct gpu_i2c_dev *i2cd = dev_get_drvdata(&pdev->dev); 351 352 pm_runtime_get_noresume(i2cd->dev); 353 i2c_del_adapter(&i2cd->adapter); 354 pci_free_irq_vectors(pdev); 355 } 356 357 /* 358 * We need gpu_i2c_suspend() even if it is stub, for runtime pm to work 359 * correctly. Without it, lspci shows runtime pm status as "D0" for the card. 360 * Documentation/power/pci.rst also insists for driver to provide this. 361 */ 362 static __maybe_unused int gpu_i2c_suspend(struct device *dev) 363 { 364 return 0; 365 } 366 367 static __maybe_unused int gpu_i2c_resume(struct device *dev) 368 { 369 struct gpu_i2c_dev *i2cd = dev_get_drvdata(dev); 370 371 gpu_enable_i2c_bus(i2cd); 372 /* 373 * Runtime resume ccgx client so that it can see for any 374 * connector change event. Old ccg firmware has known 375 * issue of not triggering interrupt when a device is 376 * connected to runtime resume the controller. 377 */ 378 pm_request_resume(&i2cd->ccgx_client->dev); 379 return 0; 380 } 381 382 static UNIVERSAL_DEV_PM_OPS(gpu_i2c_driver_pm, gpu_i2c_suspend, gpu_i2c_resume, 383 NULL); 384 385 static struct pci_driver gpu_i2c_driver = { 386 .name = "nvidia-gpu", 387 .id_table = gpu_i2c_ids, 388 .probe = gpu_i2c_probe, 389 .remove = gpu_i2c_remove, 390 .driver = { 391 .pm = &gpu_i2c_driver_pm, 392 }, 393 }; 394 395 module_pci_driver(gpu_i2c_driver); 396 397 MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>"); 398 MODULE_DESCRIPTION("Nvidia GPU I2C controller Driver"); 399 MODULE_LICENSE("GPL v2"); 400