xref: /linux/drivers/i2c/busses/i2c-npcm7xx.c (revision d163d60258c755845cbc9cfe0e45fca71e649488)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Nuvoton NPCM7xx I2C Controller driver
4  *
5  * Copyright (C) 2020 Nuvoton Technologies tali.perry@nuvoton.com
6  */
7 #include <linux/bitfield.h>
8 #include <linux/clk.h>
9 #include <linux/debugfs.h>
10 #include <linux/errno.h>
11 #include <linux/i2c.h>
12 #include <linux/interrupt.h>
13 #include <linux/iopoll.h>
14 #include <linux/irq.h>
15 #include <linux/jiffies.h>
16 #include <linux/kernel.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 
23 enum i2c_mode {
24 	I2C_MASTER,
25 	I2C_SLAVE,
26 };
27 
28 /*
29  * External I2C Interface driver xfer indication values, which indicate status
30  * of the bus.
31  */
32 enum i2c_state_ind {
33 	I2C_NO_STATUS_IND = 0,
34 	I2C_SLAVE_RCV_IND,
35 	I2C_SLAVE_XMIT_IND,
36 	I2C_SLAVE_XMIT_MISSING_DATA_IND,
37 	I2C_SLAVE_RESTART_IND,
38 	I2C_SLAVE_DONE_IND,
39 	I2C_MASTER_DONE_IND,
40 	I2C_NACK_IND,
41 	I2C_BUS_ERR_IND,
42 	I2C_WAKE_UP_IND,
43 	I2C_BLOCK_BYTES_ERR_IND,
44 	I2C_SLAVE_RCV_MISSING_DATA_IND,
45 };
46 
47 /*
48  * Operation type values (used to define the operation currently running)
49  * module is interrupt driven, on each interrupt the current operation is
50  * checked to see if the module is currently reading or writing.
51  */
52 enum i2c_oper {
53 	I2C_NO_OPER = 0,
54 	I2C_WRITE_OPER,
55 	I2C_READ_OPER,
56 };
57 
58 /* I2C Bank (module had 2 banks of registers) */
59 enum i2c_bank {
60 	I2C_BANK_0 = 0,
61 	I2C_BANK_1,
62 };
63 
64 /* Internal I2C states values (for the I2C module state machine). */
65 enum i2c_state {
66 	I2C_DISABLE = 0,
67 	I2C_IDLE,
68 	I2C_MASTER_START,
69 	I2C_SLAVE_MATCH,
70 	I2C_OPER_STARTED,
71 	I2C_STOP_PENDING,
72 };
73 
74 #if IS_ENABLED(CONFIG_I2C_SLAVE)
75 /* Module supports setting multiple own slave addresses */
76 enum i2c_addr {
77 	I2C_SLAVE_ADDR1 = 0,
78 	I2C_SLAVE_ADDR2,
79 	I2C_SLAVE_ADDR3,
80 	I2C_SLAVE_ADDR4,
81 	I2C_SLAVE_ADDR5,
82 	I2C_SLAVE_ADDR6,
83 	I2C_SLAVE_ADDR7,
84 	I2C_SLAVE_ADDR8,
85 	I2C_SLAVE_ADDR9,
86 	I2C_SLAVE_ADDR10,
87 	I2C_GC_ADDR,
88 	I2C_ARP_ADDR,
89 };
90 #endif
91 
92 /* init register and default value required to enable module */
93 #define NPCM_I2CSEGCTL			0xE4
94 
95 /* Common regs */
96 #define NPCM_I2CSDA			0x00
97 #define NPCM_I2CST			0x02
98 #define NPCM_I2CCST			0x04
99 #define NPCM_I2CCTL1			0x06
100 #define NPCM_I2CADDR1			0x08
101 #define NPCM_I2CCTL2			0x0A
102 #define NPCM_I2CADDR2			0x0C
103 #define NPCM_I2CCTL3			0x0E
104 #define NPCM_I2CCST2			0x18
105 #define NPCM_I2CCST3			0x19
106 #define I2C_VER				0x1F
107 
108 /* BANK 0 regs */
109 #define NPCM_I2CADDR3			0x10
110 #define NPCM_I2CADDR7			0x11
111 #define NPCM_I2CADDR4			0x12
112 #define NPCM_I2CADDR8			0x13
113 #define NPCM_I2CADDR5			0x14
114 #define NPCM_I2CADDR9			0x15
115 #define NPCM_I2CADDR6			0x16
116 #define NPCM_I2CADDR10			0x17
117 #define NPCM_I2CCTL4			0x1A
118 #define NPCM_I2CCTL5			0x1B
119 #define NPCM_I2CSCLLT			0x1C /* SCL Low Time */
120 #define NPCM_I2CFIF_CTL			0x1D /* FIFO Control */
121 #define NPCM_I2CSCLHT			0x1E /* SCL High Time */
122 
123 /* BANK 1 regs */
124 #define NPCM_I2CFIF_CTS			0x10 /* Both FIFOs Control and Status */
125 #define NPCM_I2CTXF_CTL			0x12 /* Tx-FIFO Control */
126 #define NPCM_I2CT_OUT			0x14 /* Bus T.O. */
127 #define NPCM_I2CPEC			0x16 /* PEC Data */
128 #define NPCM_I2CTXF_STS			0x1A /* Tx-FIFO Status */
129 #define NPCM_I2CRXF_STS			0x1C /* Rx-FIFO Status */
130 #define NPCM_I2CRXF_CTL			0x1E /* Rx-FIFO Control */
131 
132 #if IS_ENABLED(CONFIG_I2C_SLAVE)
133 /*
134  * npcm_i2caddr array:
135  * The module supports having multiple own slave addresses.
136  * Since the addr regs are sprinkled all over the address space,
137  * use this array to get the address or each register.
138  */
139 #define I2C_NUM_OWN_ADDR 2
140 #define I2C_NUM_OWN_ADDR_SUPPORTED 2
141 
142 static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = {
143 	NPCM_I2CADDR1, NPCM_I2CADDR2,
144 };
145 #endif
146 
147 /* NPCM_I2CST reg fields */
148 #define NPCM_I2CST_XMIT			BIT(0)	/* Transmit mode */
149 #define NPCM_I2CST_MASTER		BIT(1)	/* Master mode */
150 #define NPCM_I2CST_NMATCH		BIT(2)	/* New match */
151 #define NPCM_I2CST_STASTR		BIT(3)	/* Stall after start */
152 #define NPCM_I2CST_NEGACK		BIT(4)	/* Negative ACK */
153 #define NPCM_I2CST_BER			BIT(5)	/* Bus error */
154 #define NPCM_I2CST_SDAST		BIT(6)	/* SDA status */
155 #define NPCM_I2CST_SLVSTP		BIT(7)	/* Slave stop */
156 
157 /* NPCM_I2CCST reg fields */
158 #define NPCM_I2CCST_BUSY		BIT(0)	/* Busy */
159 #define NPCM_I2CCST_BB			BIT(1)	/* Bus busy */
160 #define NPCM_I2CCST_MATCH		BIT(2)	/* Address match */
161 #define NPCM_I2CCST_GCMATCH		BIT(3)	/* Global call match */
162 #define NPCM_I2CCST_TSDA		BIT(4)	/* Test SDA line */
163 #define NPCM_I2CCST_TGSCL		BIT(5)	/* Toggle SCL line */
164 #define NPCM_I2CCST_MATCHAF		BIT(6)	/* Match address field */
165 #define NPCM_I2CCST_ARPMATCH		BIT(7)	/* ARP address match */
166 
167 /* NPCM_I2CCTL1 reg fields */
168 #define NPCM_I2CCTL1_START		BIT(0)	/* Generate start condition */
169 #define NPCM_I2CCTL1_STOP		BIT(1)	/* Generate stop condition */
170 #define NPCM_I2CCTL1_INTEN		BIT(2)	/* Interrupt enable */
171 #define NPCM_I2CCTL1_EOBINTE		BIT(3)
172 #define NPCM_I2CCTL1_ACK		BIT(4)
173 #define NPCM_I2CCTL1_GCMEN		BIT(5)	/* Global call match enable */
174 #define NPCM_I2CCTL1_NMINTE		BIT(6)	/* New match interrupt enable */
175 #define NPCM_I2CCTL1_STASTRE		BIT(7)	/* Stall after start enable */
176 
177 /* RW1S fields (inside a RW reg): */
178 #define NPCM_I2CCTL1_RWS   \
179 	(NPCM_I2CCTL1_START | NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK)
180 
181 /* npcm_i2caddr reg fields */
182 #define NPCM_I2CADDR_A			GENMASK(6, 0)	/* Address */
183 #define NPCM_I2CADDR_SAEN		BIT(7)		/* Slave address enable */
184 
185 /* NPCM_I2CCTL2 reg fields */
186 #define I2CCTL2_ENABLE			BIT(0)		/* Module enable */
187 #define I2CCTL2_SCLFRQ6_0		GENMASK(7, 1)	/* Bits 0:6 of frequency divisor */
188 
189 /* NPCM_I2CCTL3 reg fields */
190 #define I2CCTL3_SCLFRQ8_7		GENMASK(1, 0)	/* Bits 7:8 of frequency divisor */
191 #define I2CCTL3_ARPMEN			BIT(2)	/* ARP match enable */
192 #define I2CCTL3_IDL_START		BIT(3)
193 #define I2CCTL3_400K_MODE		BIT(4)
194 #define I2CCTL3_BNK_SEL			BIT(5)
195 #define I2CCTL3_SDA_LVL			BIT(6)
196 #define I2CCTL3_SCL_LVL			BIT(7)
197 
198 /* NPCM_I2CCST2 reg fields */
199 #define NPCM_I2CCST2_MATCHA1F		BIT(0)
200 #define NPCM_I2CCST2_MATCHA2F		BIT(1)
201 #define NPCM_I2CCST2_MATCHA3F		BIT(2)
202 #define NPCM_I2CCST2_MATCHA4F		BIT(3)
203 #define NPCM_I2CCST2_MATCHA5F		BIT(4)
204 #define NPCM_I2CCST2_MATCHA6F		BIT(5)
205 #define NPCM_I2CCST2_MATCHA7F		BIT(5)
206 #define NPCM_I2CCST2_INTSTS		BIT(7)
207 
208 /* NPCM_I2CCST3 reg fields */
209 #define NPCM_I2CCST3_MATCHA8F		BIT(0)
210 #define NPCM_I2CCST3_MATCHA9F		BIT(1)
211 #define NPCM_I2CCST3_MATCHA10F		BIT(2)
212 #define NPCM_I2CCST3_EO_BUSY		BIT(7)
213 
214 /* NPCM_I2CCTL4 reg fields */
215 #define I2CCTL4_HLDT			GENMASK(5, 0)
216 #define I2CCTL4_LVL_WE			BIT(7)
217 
218 /* NPCM_I2CCTL5 reg fields */
219 #define I2CCTL5_DBNCT			GENMASK(3, 0)
220 
221 /* NPCM_I2CFIF_CTS reg fields */
222 #define NPCM_I2CFIF_CTS_RXF_TXE		BIT(1)
223 #define NPCM_I2CFIF_CTS_RFTE_IE		BIT(3)
224 #define NPCM_I2CFIF_CTS_CLR_FIFO	BIT(6)
225 #define NPCM_I2CFIF_CTS_SLVRSTR		BIT(7)
226 
227 /* NPCM_I2CTXF_CTL reg field */
228 #define NPCM_I2CTXF_CTL_THR_TXIE	BIT(6)
229 
230 /* NPCM_I2CT_OUT reg fields */
231 #define NPCM_I2CT_OUT_TO_CKDIV		GENMASK(5, 0)
232 #define NPCM_I2CT_OUT_T_OUTIE		BIT(6)
233 #define NPCM_I2CT_OUT_T_OUTST		BIT(7)
234 
235 /* NPCM_I2CTXF_STS reg fields */
236 #define NPCM_I2CTXF_STS_TX_THST		BIT(6)
237 
238 /* NPCM_I2CRXF_STS reg fields */
239 #define NPCM_I2CRXF_STS_RX_THST		BIT(6)
240 
241 /* NPCM_I2CFIF_CTL reg fields */
242 #define NPCM_I2CFIF_CTL_FIFO_EN		BIT(4)
243 
244 /* NPCM_I2CRXF_CTL reg fields */
245 #define NPCM_I2CRXF_CTL_THR_RXIE	BIT(6)
246 
247 #define MAX_I2C_HW_FIFO_SIZE		32
248 
249 /* I2C_VER reg fields */
250 #define I2C_VER_VERSION			GENMASK(6, 0)
251 #define I2C_VER_FIFO_EN			BIT(7)
252 
253 /* stall/stuck timeout in us */
254 #define DEFAULT_STALL_COUNT		25
255 
256 /* SCLFRQ field position */
257 #define SCLFRQ_0_TO_6			GENMASK(6, 0)
258 #define SCLFRQ_7_TO_8			GENMASK(8, 7)
259 
260 /* supported clk settings. values in Hz. */
261 #define I2C_FREQ_MIN_HZ			10000
262 #define I2C_FREQ_MAX_HZ			I2C_MAX_FAST_MODE_PLUS_FREQ
263 
264 struct npcm_i2c_data {
265 	u8 fifo_size;
266 	u32 segctl_init_val;
267 	u8 txf_sts_tx_bytes;
268 	u8 rxf_sts_rx_bytes;
269 	u8 rxf_ctl_last_pec;
270 };
271 
272 static const struct npcm_i2c_data npxm7xx_i2c_data = {
273 	.fifo_size = 16,
274 	.segctl_init_val = 0x0333F000,
275 	.txf_sts_tx_bytes = GENMASK(4, 0),
276 	.rxf_sts_rx_bytes = GENMASK(4, 0),
277 	.rxf_ctl_last_pec = BIT(5),
278 };
279 
280 static const struct npcm_i2c_data npxm8xx_i2c_data = {
281 	.fifo_size = 32,
282 	.segctl_init_val = 0x9333F000,
283 	.txf_sts_tx_bytes = GENMASK(5, 0),
284 	.rxf_sts_rx_bytes = GENMASK(5, 0),
285 	.rxf_ctl_last_pec = BIT(7),
286 };
287 
288 /* Status of one I2C module */
289 struct npcm_i2c {
290 	struct i2c_adapter adap;
291 	struct device *dev;
292 	unsigned char __iomem *reg;
293 	const struct npcm_i2c_data *data;
294 	spinlock_t lock;   /* IRQ synchronization */
295 	struct completion cmd_complete;
296 	int cmd_err;
297 	struct i2c_msg *msgs;
298 	int msgs_num;
299 	int num;
300 	u32 apb_clk;
301 	struct i2c_bus_recovery_info rinfo;
302 	enum i2c_state state;
303 	enum i2c_oper operation;
304 	enum i2c_mode master_or_slave;
305 	enum i2c_state_ind stop_ind;
306 	u8 dest_addr;
307 	u8 *rd_buf;
308 	u16 rd_size;
309 	u16 rd_ind;
310 	u8 *wr_buf;
311 	u16 wr_size;
312 	u16 wr_ind;
313 	bool fifo_use;
314 	u16 PEC_mask; /* PEC bit mask per slave address */
315 	bool PEC_use;
316 	bool read_block_use;
317 	unsigned long int_time_stamp;
318 	unsigned long bus_freq; /* in Hz */
319 #if IS_ENABLED(CONFIG_I2C_SLAVE)
320 	u8 own_slave_addr;
321 	struct i2c_client *slave;
322 	int slv_rd_size;
323 	int slv_rd_ind;
324 	int slv_wr_size;
325 	int slv_wr_ind;
326 	u8 slv_rd_buf[MAX_I2C_HW_FIFO_SIZE];
327 	u8 slv_wr_buf[MAX_I2C_HW_FIFO_SIZE];
328 #endif
329 	u64 ber_cnt;
330 	u64 rec_succ_cnt;
331 	u64 rec_fail_cnt;
332 	u64 nack_cnt;
333 	u64 timeout_cnt;
334 	u64 tx_complete_cnt;
335 };
336 
337 static inline void npcm_i2c_select_bank(struct npcm_i2c *bus,
338 					enum i2c_bank bank)
339 {
340 	u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
341 
342 	if (bank == I2C_BANK_0)
343 		i2cctl3 = i2cctl3 & ~I2CCTL3_BNK_SEL;
344 	else
345 		i2cctl3 = i2cctl3 | I2CCTL3_BNK_SEL;
346 	iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
347 }
348 
349 static void npcm_i2c_init_params(struct npcm_i2c *bus)
350 {
351 	bus->stop_ind = I2C_NO_STATUS_IND;
352 	bus->rd_size = 0;
353 	bus->wr_size = 0;
354 	bus->rd_ind = 0;
355 	bus->wr_ind = 0;
356 	bus->read_block_use = false;
357 	bus->int_time_stamp = 0;
358 	bus->PEC_use = false;
359 	bus->PEC_mask = 0;
360 #if IS_ENABLED(CONFIG_I2C_SLAVE)
361 	if (bus->slave)
362 		bus->master_or_slave = I2C_SLAVE;
363 #endif
364 }
365 
366 static inline void npcm_i2c_wr_byte(struct npcm_i2c *bus, u8 data)
367 {
368 	iowrite8(data, bus->reg + NPCM_I2CSDA);
369 }
370 
371 static inline u8 npcm_i2c_rd_byte(struct npcm_i2c *bus)
372 {
373 	return ioread8(bus->reg + NPCM_I2CSDA);
374 }
375 
376 static int npcm_i2c_get_SCL(struct i2c_adapter *_adap)
377 {
378 	struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
379 
380 	return !!(I2CCTL3_SCL_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
381 }
382 
383 static int npcm_i2c_get_SDA(struct i2c_adapter *_adap)
384 {
385 	struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
386 
387 	return !!(I2CCTL3_SDA_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
388 }
389 
390 static inline u16 npcm_i2c_get_index(struct npcm_i2c *bus)
391 {
392 	if (bus->operation == I2C_READ_OPER)
393 		return bus->rd_ind;
394 	if (bus->operation == I2C_WRITE_OPER)
395 		return bus->wr_ind;
396 	return 0;
397 }
398 
399 /* quick protocol (just address) */
400 static inline bool npcm_i2c_is_quick(struct npcm_i2c *bus)
401 {
402 	return bus->wr_size == 0 && bus->rd_size == 0;
403 }
404 
405 static void npcm_i2c_disable(struct npcm_i2c *bus)
406 {
407 	u8 i2cctl2;
408 
409 #if IS_ENABLED(CONFIG_I2C_SLAVE)
410 	int i;
411 
412 	/* Slave addresses removal */
413 	for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++)
414 		iowrite8(0, bus->reg + npcm_i2caddr[i]);
415 
416 #endif
417 	/* Disable module */
418 	i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
419 	i2cctl2 = i2cctl2 & ~I2CCTL2_ENABLE;
420 	iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
421 
422 	bus->state = I2C_DISABLE;
423 }
424 
425 static void npcm_i2c_enable(struct npcm_i2c *bus)
426 {
427 	u8 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
428 
429 	i2cctl2 = i2cctl2 | I2CCTL2_ENABLE;
430 	iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
431 	bus->state = I2C_IDLE;
432 }
433 
434 /* enable\disable end of busy (EOB) interrupts */
435 static inline void npcm_i2c_eob_int(struct npcm_i2c *bus, bool enable)
436 {
437 	u8 val;
438 
439 	/* Clear EO_BUSY pending bit: */
440 	val = ioread8(bus->reg + NPCM_I2CCST3);
441 	val = val | NPCM_I2CCST3_EO_BUSY;
442 	iowrite8(val, bus->reg + NPCM_I2CCST3);
443 
444 	val = ioread8(bus->reg + NPCM_I2CCTL1);
445 	val &= ~NPCM_I2CCTL1_RWS;
446 	if (enable)
447 		val |= NPCM_I2CCTL1_EOBINTE;
448 	else
449 		val &= ~NPCM_I2CCTL1_EOBINTE;
450 	iowrite8(val, bus->reg + NPCM_I2CCTL1);
451 }
452 
453 static inline bool npcm_i2c_tx_fifo_empty(struct npcm_i2c *bus)
454 {
455 	u8 tx_fifo_sts;
456 
457 	tx_fifo_sts = ioread8(bus->reg + NPCM_I2CTXF_STS);
458 	/* check if TX FIFO is not empty */
459 	if ((tx_fifo_sts & bus->data->txf_sts_tx_bytes) == 0)
460 		return false;
461 
462 	/* check if TX FIFO status bit is set: */
463 	return !!FIELD_GET(NPCM_I2CTXF_STS_TX_THST, tx_fifo_sts);
464 }
465 
466 static inline bool npcm_i2c_rx_fifo_full(struct npcm_i2c *bus)
467 {
468 	u8 rx_fifo_sts;
469 
470 	rx_fifo_sts = ioread8(bus->reg + NPCM_I2CRXF_STS);
471 	/* check if RX FIFO is not empty: */
472 	if ((rx_fifo_sts & bus->data->rxf_sts_rx_bytes) == 0)
473 		return false;
474 
475 	/* check if rx fifo full status is set: */
476 	return !!FIELD_GET(NPCM_I2CRXF_STS_RX_THST, rx_fifo_sts);
477 }
478 
479 static inline void npcm_i2c_clear_fifo_int(struct npcm_i2c *bus)
480 {
481 	u8 val;
482 
483 	val = ioread8(bus->reg + NPCM_I2CFIF_CTS);
484 	val = (val & NPCM_I2CFIF_CTS_SLVRSTR) | NPCM_I2CFIF_CTS_RXF_TXE;
485 	iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
486 }
487 
488 static inline void npcm_i2c_clear_tx_fifo(struct npcm_i2c *bus)
489 {
490 	u8 val;
491 
492 	val = ioread8(bus->reg + NPCM_I2CTXF_STS);
493 	val = val | NPCM_I2CTXF_STS_TX_THST;
494 	iowrite8(val, bus->reg + NPCM_I2CTXF_STS);
495 }
496 
497 static inline void npcm_i2c_clear_rx_fifo(struct npcm_i2c *bus)
498 {
499 	u8 val;
500 
501 	val = ioread8(bus->reg + NPCM_I2CRXF_STS);
502 	val = val | NPCM_I2CRXF_STS_RX_THST;
503 	iowrite8(val, bus->reg + NPCM_I2CRXF_STS);
504 }
505 
506 static void npcm_i2c_int_enable(struct npcm_i2c *bus, bool enable)
507 {
508 	u8 val;
509 
510 	val = ioread8(bus->reg + NPCM_I2CCTL1);
511 	val &= ~NPCM_I2CCTL1_RWS;
512 	if (enable)
513 		val |= NPCM_I2CCTL1_INTEN;
514 	else
515 		val &= ~NPCM_I2CCTL1_INTEN;
516 	iowrite8(val, bus->reg + NPCM_I2CCTL1);
517 }
518 
519 static inline void npcm_i2c_master_start(struct npcm_i2c *bus)
520 {
521 	u8 val;
522 
523 	val = ioread8(bus->reg + NPCM_I2CCTL1);
524 	val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK);
525 	val |= NPCM_I2CCTL1_START;
526 	iowrite8(val, bus->reg + NPCM_I2CCTL1);
527 }
528 
529 static inline void npcm_i2c_master_stop(struct npcm_i2c *bus)
530 {
531 	u8 val;
532 
533 	/*
534 	 * override HW issue: I2C may fail to supply stop condition in Master
535 	 * Write operation.
536 	 * Need to delay at least 5 us from the last int, before issueing a stop
537 	 */
538 	udelay(10); /* function called from interrupt, can't sleep */
539 	val = ioread8(bus->reg + NPCM_I2CCTL1);
540 	val &= ~(NPCM_I2CCTL1_START | NPCM_I2CCTL1_ACK);
541 	val |= NPCM_I2CCTL1_STOP;
542 	iowrite8(val, bus->reg + NPCM_I2CCTL1);
543 
544 	if (!bus->fifo_use)
545 		return;
546 
547 	npcm_i2c_select_bank(bus, I2C_BANK_1);
548 
549 	if (bus->operation == I2C_READ_OPER)
550 		npcm_i2c_clear_rx_fifo(bus);
551 	else
552 		npcm_i2c_clear_tx_fifo(bus);
553 	npcm_i2c_clear_fifo_int(bus);
554 	iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
555 }
556 
557 static inline void npcm_i2c_stall_after_start(struct npcm_i2c *bus, bool stall)
558 {
559 	u8 val;
560 
561 	val = ioread8(bus->reg + NPCM_I2CCTL1);
562 	val &= ~NPCM_I2CCTL1_RWS;
563 	if (stall)
564 		val |= NPCM_I2CCTL1_STASTRE;
565 	else
566 		val &= ~NPCM_I2CCTL1_STASTRE;
567 	iowrite8(val, bus->reg + NPCM_I2CCTL1);
568 }
569 
570 static inline void npcm_i2c_nack(struct npcm_i2c *bus)
571 {
572 	u8 val;
573 
574 	val = ioread8(bus->reg + NPCM_I2CCTL1);
575 	val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_START);
576 	val |= NPCM_I2CCTL1_ACK;
577 	iowrite8(val, bus->reg + NPCM_I2CCTL1);
578 }
579 
580 static inline void npcm_i2c_clear_master_status(struct npcm_i2c *bus)
581 {
582 	u8 val;
583 
584 	/* Clear NEGACK, STASTR and BER bits */
585 	val = NPCM_I2CST_BER | NPCM_I2CST_NEGACK | NPCM_I2CST_STASTR;
586 	iowrite8(val, bus->reg + NPCM_I2CST);
587 }
588 
589 #if IS_ENABLED(CONFIG_I2C_SLAVE)
590 static void npcm_i2c_slave_int_enable(struct npcm_i2c *bus, bool enable)
591 {
592 	u8 i2cctl1;
593 
594 	/* enable interrupt on slave match: */
595 	i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
596 	i2cctl1 &= ~NPCM_I2CCTL1_RWS;
597 	if (enable)
598 		i2cctl1 |= NPCM_I2CCTL1_NMINTE;
599 	else
600 		i2cctl1 &= ~NPCM_I2CCTL1_NMINTE;
601 	iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
602 }
603 
604 static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type,
605 				 u8 addr, bool enable)
606 {
607 	u8 i2cctl1;
608 	u8 i2cctl3;
609 	u8 sa_reg;
610 
611 	sa_reg = (addr & 0x7F) | FIELD_PREP(NPCM_I2CADDR_SAEN, enable);
612 	if (addr_type == I2C_GC_ADDR) {
613 		i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
614 		if (enable)
615 			i2cctl1 |= NPCM_I2CCTL1_GCMEN;
616 		else
617 			i2cctl1 &= ~NPCM_I2CCTL1_GCMEN;
618 		iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
619 		return 0;
620 	} else if (addr_type == I2C_ARP_ADDR) {
621 		i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
622 		if (enable)
623 			i2cctl3 |= I2CCTL3_ARPMEN;
624 		else
625 			i2cctl3 &= ~I2CCTL3_ARPMEN;
626 		iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
627 		return 0;
628 	}
629 	if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10)
630 		dev_err(bus->dev, "try to enable more than 2 SA not supported\n");
631 
632 	if (addr_type >= I2C_ARP_ADDR)
633 		return -EFAULT;
634 
635 	/* Set and enable the address */
636 	iowrite8(sa_reg, bus->reg + npcm_i2caddr[addr_type]);
637 	npcm_i2c_slave_int_enable(bus, enable);
638 
639 	return 0;
640 }
641 #endif
642 
643 static void npcm_i2c_reset(struct npcm_i2c *bus)
644 {
645 	/*
646 	 * Save I2CCTL1 relevant bits. It is being cleared when the module
647 	 *  is disabled.
648 	 */
649 	u8 i2cctl1;
650 #if IS_ENABLED(CONFIG_I2C_SLAVE)
651 	u8 addr;
652 #endif
653 
654 	i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
655 
656 	npcm_i2c_disable(bus);
657 	npcm_i2c_enable(bus);
658 
659 	/* Restore NPCM_I2CCTL1 Status */
660 	i2cctl1 &= ~NPCM_I2CCTL1_RWS;
661 	iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
662 
663 	/* Clear BB (BUS BUSY) bit */
664 	iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
665 	iowrite8(0xFF, bus->reg + NPCM_I2CST);
666 
667 	/* Clear and disable EOB */
668 	npcm_i2c_eob_int(bus, false);
669 
670 	/* Clear all fifo bits: */
671 	iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
672 
673 #if IS_ENABLED(CONFIG_I2C_SLAVE)
674 	if (bus->slave) {
675 		addr = bus->slave->addr;
676 		npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, addr, true);
677 	}
678 #endif
679 
680 	/* Clear status bits for spurious interrupts */
681 	npcm_i2c_clear_master_status(bus);
682 
683 	bus->state = I2C_IDLE;
684 }
685 
686 static inline bool npcm_i2c_is_master(struct npcm_i2c *bus)
687 {
688 	return !!FIELD_GET(NPCM_I2CST_MASTER, ioread8(bus->reg + NPCM_I2CST));
689 }
690 
691 static void npcm_i2c_callback(struct npcm_i2c *bus,
692 			      enum i2c_state_ind op_status, u16 info)
693 {
694 	struct i2c_msg *msgs;
695 	int msgs_num;
696 	bool do_complete = false;
697 
698 	msgs = bus->msgs;
699 	msgs_num = bus->msgs_num;
700 	/*
701 	 * check that transaction was not timed-out, and msgs still
702 	 * holds a valid value.
703 	 */
704 	if (!msgs)
705 		return;
706 
707 	if (completion_done(&bus->cmd_complete))
708 		return;
709 
710 	switch (op_status) {
711 	case I2C_MASTER_DONE_IND:
712 		bus->cmd_err = bus->msgs_num;
713 		if (bus->tx_complete_cnt < ULLONG_MAX)
714 			bus->tx_complete_cnt++;
715 		fallthrough;
716 	case I2C_BLOCK_BYTES_ERR_IND:
717 		/* Master tx finished and all transmit bytes were sent */
718 		if (bus->msgs) {
719 			if (msgs[0].flags & I2C_M_RD)
720 				msgs[0].len = info;
721 			else if (msgs_num == 2 &&
722 				 msgs[1].flags & I2C_M_RD)
723 				msgs[1].len = info;
724 		}
725 		do_complete = true;
726 		break;
727 	case I2C_NACK_IND:
728 		/* MASTER transmit got a NACK before tx all bytes */
729 		bus->cmd_err = -ENXIO;
730 		do_complete = true;
731 		break;
732 	case I2C_BUS_ERR_IND:
733 		/* Bus error */
734 		bus->cmd_err = -EAGAIN;
735 		do_complete = true;
736 		break;
737 	case I2C_WAKE_UP_IND:
738 		/* I2C wake up */
739 		break;
740 	default:
741 		break;
742 	}
743 
744 	bus->operation = I2C_NO_OPER;
745 #if IS_ENABLED(CONFIG_I2C_SLAVE)
746 	if (bus->slave)
747 		bus->master_or_slave = I2C_SLAVE;
748 #endif
749 	if (do_complete)
750 		complete(&bus->cmd_complete);
751 }
752 
753 static u8 npcm_i2c_fifo_usage(struct npcm_i2c *bus)
754 {
755 	if (bus->operation == I2C_WRITE_OPER)
756 		return (bus->data->txf_sts_tx_bytes &
757 			ioread8(bus->reg + NPCM_I2CTXF_STS));
758 	if (bus->operation == I2C_READ_OPER)
759 		return (bus->data->rxf_sts_rx_bytes &
760 			ioread8(bus->reg + NPCM_I2CRXF_STS));
761 	return 0;
762 }
763 
764 static void npcm_i2c_write_to_fifo_master(struct npcm_i2c *bus, u16 max_bytes)
765 {
766 	u8 size_free_fifo;
767 
768 	/*
769 	 * Fill the FIFO, while the FIFO is not full and there are more bytes
770 	 * to write
771 	 */
772 	size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus);
773 	while (max_bytes-- && size_free_fifo) {
774 		if (bus->wr_ind < bus->wr_size)
775 			npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
776 		else
777 			npcm_i2c_wr_byte(bus, 0xFF);
778 		size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus);
779 	}
780 }
781 
782 /*
783  * npcm_i2c_set_fifo:
784  * configure the FIFO before using it. If nread is -1 RX FIFO will not be
785  * configured. same for nwrite
786  */
787 static void npcm_i2c_set_fifo(struct npcm_i2c *bus, int nread, int nwrite)
788 {
789 	u8 rxf_ctl = 0;
790 
791 	if (!bus->fifo_use)
792 		return;
793 	npcm_i2c_select_bank(bus, I2C_BANK_1);
794 	npcm_i2c_clear_tx_fifo(bus);
795 	npcm_i2c_clear_rx_fifo(bus);
796 
797 	/* configure RX FIFO */
798 	if (nread > 0) {
799 		rxf_ctl = min_t(int, nread, bus->data->fifo_size);
800 
801 		/* set LAST bit. if LAST is set next FIFO packet is nacked */
802 		if (nread <= bus->data->fifo_size)
803 			rxf_ctl |= bus->data->rxf_ctl_last_pec;
804 
805 		/*
806 		 * if we are about to read the first byte in blk rd mode,
807 		 * don't NACK it. If slave returns zero size HW can't NACK
808 		 * it immediately, it will read extra byte and then NACK.
809 		 */
810 		if (bus->rd_ind == 0 && bus->read_block_use) {
811 			/* set fifo to read one byte, no last: */
812 			rxf_ctl = 1;
813 		}
814 
815 		/* set fifo size: */
816 		iowrite8(rxf_ctl, bus->reg + NPCM_I2CRXF_CTL);
817 	}
818 
819 	/* configure TX FIFO */
820 	if (nwrite > 0) {
821 		if (nwrite > bus->data->fifo_size)
822 			/* data to send is more then FIFO size. */
823 			iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CTXF_CTL);
824 		else
825 			iowrite8(nwrite, bus->reg + NPCM_I2CTXF_CTL);
826 
827 		npcm_i2c_clear_tx_fifo(bus);
828 	}
829 }
830 
831 static void npcm_i2c_read_fifo(struct npcm_i2c *bus, u8 bytes_in_fifo)
832 {
833 	u8 data;
834 
835 	while (bytes_in_fifo--) {
836 		data = npcm_i2c_rd_byte(bus);
837 		if (bus->rd_ind < bus->rd_size)
838 			bus->rd_buf[bus->rd_ind++] = data;
839 	}
840 }
841 
842 static void npcm_i2c_master_abort(struct npcm_i2c *bus)
843 {
844 	/* Only current master is allowed to issue a stop condition */
845 	if (!npcm_i2c_is_master(bus))
846 		return;
847 
848 	npcm_i2c_eob_int(bus, true);
849 	npcm_i2c_master_stop(bus);
850 	npcm_i2c_clear_master_status(bus);
851 }
852 
853 #if IS_ENABLED(CONFIG_I2C_SLAVE)
854 static u8 npcm_i2c_get_slave_addr(struct npcm_i2c *bus, enum i2c_addr addr_type)
855 {
856 	u8 slave_add;
857 
858 	if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10)
859 		dev_err(bus->dev, "get slave: try to use more than 2 SA not supported\n");
860 
861 	slave_add = ioread8(bus->reg + npcm_i2caddr[(int)addr_type]);
862 
863 	return slave_add;
864 }
865 
866 static int npcm_i2c_remove_slave_addr(struct npcm_i2c *bus, u8 slave_add)
867 {
868 	int i;
869 
870 	/* Set the enable bit */
871 	slave_add |= 0x80;
872 
873 	for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++) {
874 		if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add)
875 			iowrite8(0, bus->reg + npcm_i2caddr[i]);
876 	}
877 
878 	return 0;
879 }
880 
881 static void npcm_i2c_write_fifo_slave(struct npcm_i2c *bus, u16 max_bytes)
882 {
883 	/*
884 	 * Fill the FIFO, while the FIFO is not full and there are more bytes
885 	 * to write
886 	 */
887 	npcm_i2c_clear_fifo_int(bus);
888 	npcm_i2c_clear_tx_fifo(bus);
889 	iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
890 	while (max_bytes-- && bus->data->fifo_size != npcm_i2c_fifo_usage(bus)) {
891 		if (bus->slv_wr_size <= 0)
892 			break;
893 		bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1);
894 		npcm_i2c_wr_byte(bus, bus->slv_wr_buf[bus->slv_wr_ind]);
895 		bus->slv_wr_ind++;
896 		bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1);
897 		bus->slv_wr_size--;
898 	}
899 }
900 
901 static void npcm_i2c_read_fifo_slave(struct npcm_i2c *bus, u8 bytes_in_fifo)
902 {
903 	u8 data;
904 
905 	if (!bus->slave)
906 		return;
907 
908 	while (bytes_in_fifo--) {
909 		data = npcm_i2c_rd_byte(bus);
910 
911 		bus->slv_rd_ind = bus->slv_rd_ind & (bus->data->fifo_size - 1);
912 		bus->slv_rd_buf[bus->slv_rd_ind] = data;
913 		bus->slv_rd_ind++;
914 
915 		/* 1st byte is length in block protocol: */
916 		if (bus->slv_rd_ind == 1 && bus->read_block_use)
917 			bus->slv_rd_size = data + bus->PEC_use + 1;
918 	}
919 }
920 
921 static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus)
922 {
923 	int i;
924 	u8 value;
925 	int ind;
926 	int ret = bus->slv_wr_ind;
927 
928 	/* fill a cyclic buffer */
929 	for (i = 0; i < bus->data->fifo_size; i++) {
930 		if (bus->slv_wr_size >= bus->data->fifo_size)
931 			break;
932 		if (bus->state == I2C_SLAVE_MATCH) {
933 			i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value);
934 			bus->state = I2C_OPER_STARTED;
935 		} else {
936 			i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value);
937 		}
938 		ind = (bus->slv_wr_ind + bus->slv_wr_size) & (bus->data->fifo_size - 1);
939 		bus->slv_wr_buf[ind] = value;
940 		bus->slv_wr_size++;
941 	}
942 	return bus->data->fifo_size - ret;
943 }
944 
945 static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus)
946 {
947 	int i;
948 
949 	for (i = 0; i < bus->slv_rd_ind; i++)
950 		i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED,
951 				&bus->slv_rd_buf[i]);
952 	/*
953 	 * once we send bytes up, need to reset the counter of the wr buf
954 	 * got data from master (new offset in device), ignore wr fifo:
955 	 */
956 	if (bus->slv_rd_ind) {
957 		bus->slv_wr_size = 0;
958 		bus->slv_wr_ind = 0;
959 	}
960 
961 	bus->slv_rd_ind = 0;
962 	bus->slv_rd_size = bus->adap.quirks->max_read_len;
963 
964 	npcm_i2c_clear_fifo_int(bus);
965 	npcm_i2c_clear_rx_fifo(bus);
966 }
967 
968 static void npcm_i2c_slave_receive(struct npcm_i2c *bus, u16 nread,
969 				   u8 *read_data)
970 {
971 	bus->state = I2C_OPER_STARTED;
972 	bus->operation = I2C_READ_OPER;
973 	bus->slv_rd_size = nread;
974 	bus->slv_rd_ind = 0;
975 
976 	iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
977 	iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL);
978 	npcm_i2c_clear_tx_fifo(bus);
979 	npcm_i2c_clear_rx_fifo(bus);
980 }
981 
982 static void npcm_i2c_slave_xmit(struct npcm_i2c *bus, u16 nwrite,
983 				u8 *write_data)
984 {
985 	if (nwrite == 0)
986 		return;
987 
988 	bus->operation = I2C_WRITE_OPER;
989 
990 	/* get the next buffer */
991 	npcm_i2c_slave_get_wr_buf(bus);
992 	npcm_i2c_write_fifo_slave(bus, nwrite);
993 }
994 
995 /*
996  * npcm_i2c_slave_wr_buf_sync:
997  * currently slave IF only supports single byte operations.
998  * in order to utilize the npcm HW FIFO, the driver will ask for 16 bytes
999  * at a time, pack them in buffer, and then transmit them all together
1000  * to the FIFO and onward to the bus.
1001  * NACK on read will be once reached to bus->adap->quirks->max_read_len.
1002  * sending a NACK wherever the backend requests for it is not supported.
1003  * the next two functions allow reading to local buffer before writing it all
1004  * to the HW FIFO.
1005  */
1006 static void npcm_i2c_slave_wr_buf_sync(struct npcm_i2c *bus)
1007 {
1008 	int left_in_fifo;
1009 
1010 	left_in_fifo = bus->data->txf_sts_tx_bytes &
1011 			ioread8(bus->reg + NPCM_I2CTXF_STS);
1012 
1013 	/* fifo already full: */
1014 	if (left_in_fifo >= bus->data->fifo_size ||
1015 	    bus->slv_wr_size >= bus->data->fifo_size)
1016 		return;
1017 
1018 	/* update the wr fifo index back to the untransmitted bytes: */
1019 	bus->slv_wr_ind = bus->slv_wr_ind - left_in_fifo;
1020 	bus->slv_wr_size = bus->slv_wr_size + left_in_fifo;
1021 
1022 	if (bus->slv_wr_ind < 0)
1023 		bus->slv_wr_ind += bus->data->fifo_size;
1024 }
1025 
1026 static void npcm_i2c_slave_rd_wr(struct npcm_i2c *bus)
1027 {
1028 	if (NPCM_I2CST_XMIT & ioread8(bus->reg + NPCM_I2CST)) {
1029 		/*
1030 		 * Slave got an address match with direction bit 1 so it should
1031 		 * transmit data. Write till the master will NACK
1032 		 */
1033 		bus->operation = I2C_WRITE_OPER;
1034 		npcm_i2c_slave_xmit(bus, bus->adap.quirks->max_write_len,
1035 				    bus->slv_wr_buf);
1036 	} else {
1037 		/*
1038 		 * Slave got an address match with direction bit 0 so it should
1039 		 * receive data.
1040 		 * this module does not support saying no to bytes.
1041 		 * it will always ACK.
1042 		 */
1043 		bus->operation = I2C_READ_OPER;
1044 		npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1045 		bus->stop_ind = I2C_SLAVE_RCV_IND;
1046 		npcm_i2c_slave_send_rd_buf(bus);
1047 		npcm_i2c_slave_receive(bus, bus->adap.quirks->max_read_len,
1048 				       bus->slv_rd_buf);
1049 	}
1050 }
1051 
1052 static irqreturn_t npcm_i2c_int_slave_handler(struct npcm_i2c *bus)
1053 {
1054 	u8 val;
1055 	irqreturn_t ret = IRQ_NONE;
1056 	u8 i2cst = ioread8(bus->reg + NPCM_I2CST);
1057 
1058 	/* Slave: A NACK has occurred */
1059 	if (NPCM_I2CST_NEGACK & i2cst) {
1060 		bus->stop_ind = I2C_NACK_IND;
1061 		npcm_i2c_slave_wr_buf_sync(bus);
1062 		if (bus->fifo_use)
1063 			/* clear the FIFO */
1064 			iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
1065 				 bus->reg + NPCM_I2CFIF_CTS);
1066 
1067 		/* In slave write, NACK is OK, otherwise it is a problem */
1068 		bus->stop_ind = I2C_NO_STATUS_IND;
1069 		bus->operation = I2C_NO_OPER;
1070 		bus->own_slave_addr = 0xFF;
1071 
1072 		/*
1073 		 * Slave has to wait for STOP to decide this is the end
1074 		 * of the transaction. tx is not yet considered as done
1075 		 */
1076 		iowrite8(NPCM_I2CST_NEGACK, bus->reg + NPCM_I2CST);
1077 
1078 		ret = IRQ_HANDLED;
1079 	}
1080 
1081 	/* Slave mode: a Bus Error (BER) has been identified */
1082 	if (NPCM_I2CST_BER & i2cst) {
1083 		/*
1084 		 * Check whether bus arbitration or Start or Stop during data
1085 		 * xfer bus arbitration problem should not result in recovery
1086 		 */
1087 		bus->stop_ind = I2C_BUS_ERR_IND;
1088 
1089 		/* wait for bus busy before clear fifo */
1090 		iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1091 
1092 		bus->state = I2C_IDLE;
1093 
1094 		/*
1095 		 * in BER case we might get 2 interrupts: one for slave one for
1096 		 * master ( for a channel which is master\slave switching)
1097 		 */
1098 		if (completion_done(&bus->cmd_complete) == false) {
1099 			bus->cmd_err = -EIO;
1100 			complete(&bus->cmd_complete);
1101 		}
1102 		bus->own_slave_addr = 0xFF;
1103 		iowrite8(NPCM_I2CST_BER, bus->reg + NPCM_I2CST);
1104 		ret = IRQ_HANDLED;
1105 	}
1106 
1107 	/* A Slave Stop Condition has been identified */
1108 	if (NPCM_I2CST_SLVSTP & i2cst) {
1109 		u8 bytes_in_fifo = npcm_i2c_fifo_usage(bus);
1110 
1111 		bus->stop_ind = I2C_SLAVE_DONE_IND;
1112 
1113 		if (bus->operation == I2C_READ_OPER)
1114 			npcm_i2c_read_fifo_slave(bus, bytes_in_fifo);
1115 
1116 		/* if the buffer is empty nothing will be sent */
1117 		npcm_i2c_slave_send_rd_buf(bus);
1118 
1119 		/* Slave done transmitting or receiving */
1120 		bus->stop_ind = I2C_NO_STATUS_IND;
1121 
1122 		/*
1123 		 * Note, just because we got here, it doesn't mean we through
1124 		 * away the wr buffer.
1125 		 * we keep it until the next received offset.
1126 		 */
1127 		bus->operation = I2C_NO_OPER;
1128 		bus->own_slave_addr = 0xFF;
1129 		i2c_slave_event(bus->slave, I2C_SLAVE_STOP, 0);
1130 		iowrite8(NPCM_I2CST_SLVSTP, bus->reg + NPCM_I2CST);
1131 		if (bus->fifo_use) {
1132 			npcm_i2c_clear_fifo_int(bus);
1133 			npcm_i2c_clear_rx_fifo(bus);
1134 			npcm_i2c_clear_tx_fifo(bus);
1135 
1136 			iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
1137 				 bus->reg + NPCM_I2CFIF_CTS);
1138 		}
1139 		bus->state = I2C_IDLE;
1140 		ret = IRQ_HANDLED;
1141 	}
1142 
1143 	/* restart condition occurred and Rx-FIFO was not empty */
1144 	if (bus->fifo_use && FIELD_GET(NPCM_I2CFIF_CTS_SLVRSTR,
1145 				       ioread8(bus->reg + NPCM_I2CFIF_CTS))) {
1146 		bus->stop_ind = I2C_SLAVE_RESTART_IND;
1147 		bus->master_or_slave = I2C_SLAVE;
1148 		if (bus->operation == I2C_READ_OPER)
1149 			npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1150 		bus->operation = I2C_WRITE_OPER;
1151 		iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1152 		val = NPCM_I2CFIF_CTS_CLR_FIFO | NPCM_I2CFIF_CTS_SLVRSTR |
1153 		      NPCM_I2CFIF_CTS_RXF_TXE;
1154 		iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
1155 		npcm_i2c_slave_rd_wr(bus);
1156 		ret = IRQ_HANDLED;
1157 	}
1158 
1159 	/* A Slave Address Match has been identified */
1160 	if (NPCM_I2CST_NMATCH & i2cst) {
1161 		u8 info = 0;
1162 
1163 		/* Address match automatically implies slave mode */
1164 		bus->master_or_slave = I2C_SLAVE;
1165 		npcm_i2c_clear_fifo_int(bus);
1166 		npcm_i2c_clear_rx_fifo(bus);
1167 		npcm_i2c_clear_tx_fifo(bus);
1168 		iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1169 		iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL);
1170 		if (NPCM_I2CST_XMIT & i2cst) {
1171 			bus->operation = I2C_WRITE_OPER;
1172 		} else {
1173 			i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_REQUESTED,
1174 					&info);
1175 			bus->operation = I2C_READ_OPER;
1176 		}
1177 		if (bus->own_slave_addr == 0xFF) {
1178 			/* Check which type of address match */
1179 			val = ioread8(bus->reg + NPCM_I2CCST);
1180 			if (NPCM_I2CCST_MATCH & val) {
1181 				u16 addr;
1182 				enum i2c_addr eaddr;
1183 				u8 i2ccst2;
1184 				u8 i2ccst3;
1185 
1186 				i2ccst3 = ioread8(bus->reg + NPCM_I2CCST3);
1187 				i2ccst2 = ioread8(bus->reg + NPCM_I2CCST2);
1188 
1189 				/*
1190 				 * the i2c module can response to 10 own SA.
1191 				 * check which one was addressed by the master.
1192 				 * respond to the first one.
1193 				 */
1194 				addr = ((i2ccst3 & 0x07) << 7) |
1195 					(i2ccst2 & 0x7F);
1196 				info = ffs(addr);
1197 				eaddr = (enum i2c_addr)info;
1198 				addr = npcm_i2c_get_slave_addr(bus, eaddr);
1199 				addr &= 0x7F;
1200 				bus->own_slave_addr = addr;
1201 				if (bus->PEC_mask & BIT(info))
1202 					bus->PEC_use = true;
1203 				else
1204 					bus->PEC_use = false;
1205 			} else {
1206 				if (NPCM_I2CCST_GCMATCH & val)
1207 					bus->own_slave_addr = 0;
1208 				if (NPCM_I2CCST_ARPMATCH & val)
1209 					bus->own_slave_addr = 0x61;
1210 			}
1211 		} else {
1212 			/*
1213 			 *  Slave match can happen in two options:
1214 			 *  1. Start, SA, read (slave read without further ado)
1215 			 *  2. Start, SA, read, data, restart, SA, read,  ...
1216 			 *     (slave read in fragmented mode)
1217 			 *  3. Start, SA, write, data, restart, SA, read, ..
1218 			 *     (regular write-read mode)
1219 			 */
1220 			if ((bus->state == I2C_OPER_STARTED &&
1221 			     bus->operation == I2C_READ_OPER &&
1222 			     bus->stop_ind == I2C_SLAVE_XMIT_IND) ||
1223 			     bus->stop_ind == I2C_SLAVE_RCV_IND) {
1224 				/* slave tx after slave rx w/o STOP */
1225 				bus->stop_ind = I2C_SLAVE_RESTART_IND;
1226 			}
1227 		}
1228 
1229 		if (NPCM_I2CST_XMIT & i2cst)
1230 			bus->stop_ind = I2C_SLAVE_XMIT_IND;
1231 		else
1232 			bus->stop_ind = I2C_SLAVE_RCV_IND;
1233 		bus->state = I2C_SLAVE_MATCH;
1234 		npcm_i2c_slave_rd_wr(bus);
1235 		iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1236 		ret = IRQ_HANDLED;
1237 	}
1238 
1239 	/* Slave SDA status is set - tx or rx */
1240 	if ((NPCM_I2CST_SDAST & i2cst) ||
1241 	    (bus->fifo_use &&
1242 	    (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1243 		npcm_i2c_slave_rd_wr(bus);
1244 		iowrite8(NPCM_I2CST_SDAST, bus->reg + NPCM_I2CST);
1245 		ret = IRQ_HANDLED;
1246 	} /* SDAST */
1247 
1248 	/*
1249 	 * If irq is not one of the above, make sure EOB is disabled and all
1250 	 * status bits are cleared.
1251 	 */
1252 	if (ret == IRQ_NONE) {
1253 		npcm_i2c_eob_int(bus, false);
1254 		npcm_i2c_clear_master_status(bus);
1255 	}
1256 
1257 	return IRQ_HANDLED;
1258 }
1259 
1260 static int npcm_i2c_reg_slave(struct i2c_client *client)
1261 {
1262 	unsigned long lock_flags;
1263 	struct npcm_i2c *bus = i2c_get_adapdata(client->adapter);
1264 
1265 	bus->slave = client;
1266 
1267 	if (client->flags & I2C_CLIENT_TEN)
1268 		return -EAFNOSUPPORT;
1269 
1270 	spin_lock_irqsave(&bus->lock, lock_flags);
1271 
1272 	npcm_i2c_init_params(bus);
1273 	bus->slv_rd_size = 0;
1274 	bus->slv_wr_size = 0;
1275 	bus->slv_rd_ind = 0;
1276 	bus->slv_wr_ind = 0;
1277 	if (client->flags & I2C_CLIENT_PEC)
1278 		bus->PEC_use = true;
1279 
1280 	dev_info(bus->dev, "i2c%d register slave SA=0x%x, PEC=%d\n", bus->num,
1281 		 client->addr, bus->PEC_use);
1282 
1283 	npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, client->addr, true);
1284 	npcm_i2c_clear_fifo_int(bus);
1285 	npcm_i2c_clear_rx_fifo(bus);
1286 	npcm_i2c_clear_tx_fifo(bus);
1287 	npcm_i2c_slave_int_enable(bus, true);
1288 
1289 	spin_unlock_irqrestore(&bus->lock, lock_flags);
1290 	return 0;
1291 }
1292 
1293 static int npcm_i2c_unreg_slave(struct i2c_client *client)
1294 {
1295 	struct npcm_i2c *bus = client->adapter->algo_data;
1296 	unsigned long lock_flags;
1297 
1298 	spin_lock_irqsave(&bus->lock, lock_flags);
1299 	if (!bus->slave) {
1300 		spin_unlock_irqrestore(&bus->lock, lock_flags);
1301 		return -EINVAL;
1302 	}
1303 	npcm_i2c_slave_int_enable(bus, false);
1304 	npcm_i2c_remove_slave_addr(bus, client->addr);
1305 	bus->slave = NULL;
1306 	spin_unlock_irqrestore(&bus->lock, lock_flags);
1307 	return 0;
1308 }
1309 #endif /* CONFIG_I2C_SLAVE */
1310 
1311 static void npcm_i2c_master_fifo_read(struct npcm_i2c *bus)
1312 {
1313 	int rcount;
1314 	int fifo_bytes;
1315 	enum i2c_state_ind ind = I2C_MASTER_DONE_IND;
1316 
1317 	fifo_bytes = npcm_i2c_fifo_usage(bus);
1318 	rcount = bus->rd_size - bus->rd_ind;
1319 
1320 	/*
1321 	 * In order not to change the RX_TRH during transaction (we found that
1322 	 * this might be problematic if it takes too much time to read the FIFO)
1323 	 * we read the data in the following way. If the number of bytes to
1324 	 * read == FIFO Size + C (where C < FIFO Size)then first read C bytes
1325 	 * and in the next int we read rest of the data.
1326 	 */
1327 	if (rcount < (2 * bus->data->fifo_size) && rcount > bus->data->fifo_size)
1328 		fifo_bytes = rcount - bus->data->fifo_size;
1329 
1330 	if (rcount <= fifo_bytes) {
1331 		/* last bytes are about to be read - end of tx */
1332 		bus->state = I2C_STOP_PENDING;
1333 		bus->stop_ind = ind;
1334 		npcm_i2c_eob_int(bus, true);
1335 		/* Stop should be set before reading last byte. */
1336 		npcm_i2c_master_stop(bus);
1337 		npcm_i2c_read_fifo(bus, fifo_bytes);
1338 	} else {
1339 		npcm_i2c_read_fifo(bus, fifo_bytes);
1340 		rcount = bus->rd_size - bus->rd_ind;
1341 		npcm_i2c_set_fifo(bus, rcount, -1);
1342 	}
1343 }
1344 
1345 static void npcm_i2c_irq_master_handler_write(struct npcm_i2c *bus)
1346 {
1347 	u16 wcount;
1348 
1349 	if (bus->fifo_use)
1350 		npcm_i2c_clear_tx_fifo(bus); /* clear the TX fifo status bit */
1351 
1352 	/* Master write operation - last byte handling */
1353 	if (bus->wr_ind == bus->wr_size) {
1354 		if (bus->fifo_use && npcm_i2c_fifo_usage(bus) > 0)
1355 			/*
1356 			 * No more bytes to send (to add to the FIFO),
1357 			 * however the FIFO is not empty yet. It is
1358 			 * still in the middle of tx. Currently there's nothing
1359 			 * to do except for waiting to the end of the tx
1360 			 * We will get an int when the FIFO will get empty.
1361 			 */
1362 			return;
1363 
1364 		if (bus->rd_size == 0) {
1365 			/* all bytes have been written, in wr only operation */
1366 			npcm_i2c_eob_int(bus, true);
1367 			bus->state = I2C_STOP_PENDING;
1368 			bus->stop_ind = I2C_MASTER_DONE_IND;
1369 			npcm_i2c_master_stop(bus);
1370 			/* Clear SDA Status bit (by writing dummy byte) */
1371 			npcm_i2c_wr_byte(bus, 0xFF);
1372 
1373 		} else {
1374 			/* last write-byte written on previous int - restart */
1375 			npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1376 			/* Generate repeated start upon next write to SDA */
1377 			npcm_i2c_master_start(bus);
1378 
1379 			/*
1380 			 * Receiving one byte only - stall after successful
1381 			 * completion of send address byte. If we NACK here, and
1382 			 * slave doesn't ACK the address, we might
1383 			 * unintentionally NACK the next multi-byte read.
1384 			 */
1385 			if (bus->rd_size == 1)
1386 				npcm_i2c_stall_after_start(bus, true);
1387 
1388 			/* Next int will occur on read */
1389 			bus->operation = I2C_READ_OPER;
1390 			/* send the slave address in read direction */
1391 			npcm_i2c_wr_byte(bus, bus->dest_addr | 0x1);
1392 		}
1393 	} else {
1394 		/* write next byte not last byte and not slave address */
1395 		if (!bus->fifo_use || bus->wr_size == 1) {
1396 			npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
1397 		} else {
1398 			wcount = bus->wr_size - bus->wr_ind;
1399 			npcm_i2c_set_fifo(bus, -1, wcount);
1400 			if (wcount)
1401 				npcm_i2c_write_to_fifo_master(bus, wcount);
1402 		}
1403 	}
1404 }
1405 
1406 static void npcm_i2c_irq_master_handler_read(struct npcm_i2c *bus)
1407 {
1408 	u16 block_extra_bytes_size;
1409 	u8 data;
1410 
1411 	/* added bytes to the packet: */
1412 	block_extra_bytes_size = bus->read_block_use + bus->PEC_use;
1413 
1414 	/*
1415 	 * Perform master read, distinguishing between last byte and the rest of
1416 	 * the bytes. The last byte should be read when the clock is stopped
1417 	 */
1418 	if (bus->rd_ind == 0) { /* first byte handling: */
1419 		if (bus->read_block_use) {
1420 			/* first byte in block protocol is the size: */
1421 			data = npcm_i2c_rd_byte(bus);
1422 			data = clamp_val(data, 1, I2C_SMBUS_BLOCK_MAX);
1423 			bus->rd_size = data + block_extra_bytes_size;
1424 			bus->rd_buf[bus->rd_ind++] = data;
1425 
1426 			/* clear RX FIFO interrupt status: */
1427 			if (bus->fifo_use) {
1428 				data = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1429 				data = data | NPCM_I2CFIF_CTS_RXF_TXE;
1430 				iowrite8(data, bus->reg + NPCM_I2CFIF_CTS);
1431 			}
1432 
1433 			npcm_i2c_set_fifo(bus, bus->rd_size - 1, -1);
1434 			npcm_i2c_stall_after_start(bus, false);
1435 		} else {
1436 			npcm_i2c_clear_tx_fifo(bus);
1437 			npcm_i2c_master_fifo_read(bus);
1438 		}
1439 	} else {
1440 		if (bus->rd_size == block_extra_bytes_size &&
1441 		    bus->read_block_use) {
1442 			bus->state = I2C_STOP_PENDING;
1443 			bus->stop_ind = I2C_BLOCK_BYTES_ERR_IND;
1444 			bus->cmd_err = -EIO;
1445 			npcm_i2c_eob_int(bus, true);
1446 			npcm_i2c_master_stop(bus);
1447 			npcm_i2c_read_fifo(bus, npcm_i2c_fifo_usage(bus));
1448 		} else {
1449 			npcm_i2c_master_fifo_read(bus);
1450 		}
1451 	}
1452 }
1453 
1454 static void npcm_i2c_irq_handle_nmatch(struct npcm_i2c *bus)
1455 {
1456 	iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1457 	npcm_i2c_nack(bus);
1458 	bus->stop_ind = I2C_BUS_ERR_IND;
1459 	npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1460 }
1461 
1462 /* A NACK has occurred */
1463 static void npcm_i2c_irq_handle_nack(struct npcm_i2c *bus)
1464 {
1465 	u8 val;
1466 
1467 	if (bus->nack_cnt < ULLONG_MAX)
1468 		bus->nack_cnt++;
1469 
1470 	if (bus->fifo_use) {
1471 		/*
1472 		 * if there are still untransmitted bytes in TX FIFO
1473 		 * reduce them from wr_ind
1474 		 */
1475 		if (bus->operation == I2C_WRITE_OPER)
1476 			bus->wr_ind -= npcm_i2c_fifo_usage(bus);
1477 
1478 		/* clear the FIFO */
1479 		iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1480 	}
1481 
1482 	/* In master write operation, got unexpected NACK */
1483 	bus->stop_ind = I2C_NACK_IND;
1484 	/* Only current master is allowed to issue Stop Condition */
1485 	if (npcm_i2c_is_master(bus)) {
1486 		/* stopping in the middle */
1487 		npcm_i2c_eob_int(bus, false);
1488 		npcm_i2c_master_stop(bus);
1489 
1490 		/* Clear SDA Status bit (by reading dummy byte) */
1491 		npcm_i2c_rd_byte(bus);
1492 
1493 		/*
1494 		 * The bus is released from stall only after the SW clears
1495 		 * NEGACK bit. Then a Stop condition is sent.
1496 		 */
1497 		npcm_i2c_clear_master_status(bus);
1498 		readx_poll_timeout_atomic(ioread8, bus->reg + NPCM_I2CCST, val,
1499 					  !(val & NPCM_I2CCST_BUSY), 10, 200);
1500 		/* Verify no status bits are still set after bus is released */
1501 		npcm_i2c_clear_master_status(bus);
1502 	}
1503 	bus->state = I2C_IDLE;
1504 
1505 	/*
1506 	 * In Master mode, NACK should be cleared only after STOP.
1507 	 * In such case, the bus is released from stall only after the
1508 	 * software clears NACK bit. Then a Stop condition is sent.
1509 	 */
1510 	npcm_i2c_callback(bus, bus->stop_ind, bus->wr_ind);
1511 }
1512 
1513 	/* Master mode: a Bus Error has been identified */
1514 static void npcm_i2c_irq_handle_ber(struct npcm_i2c *bus)
1515 {
1516 	if (bus->ber_cnt < ULLONG_MAX)
1517 		bus->ber_cnt++;
1518 	bus->stop_ind = I2C_BUS_ERR_IND;
1519 	if (npcm_i2c_is_master(bus)) {
1520 		npcm_i2c_master_abort(bus);
1521 	} else {
1522 		npcm_i2c_clear_master_status(bus);
1523 
1524 		/* Clear BB (BUS BUSY) bit */
1525 		iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1526 
1527 		bus->cmd_err = -EAGAIN;
1528 		npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1529 	}
1530 	bus->state = I2C_IDLE;
1531 }
1532 
1533 	/* EOB: a master End Of Busy (meaning STOP completed) */
1534 static void npcm_i2c_irq_handle_eob(struct npcm_i2c *bus)
1535 {
1536 	npcm_i2c_eob_int(bus, false);
1537 	bus->state = I2C_IDLE;
1538 	npcm_i2c_callback(bus, bus->stop_ind, bus->rd_ind);
1539 }
1540 
1541 /* Address sent and requested stall occurred (Master mode) */
1542 static void npcm_i2c_irq_handle_stall_after_start(struct npcm_i2c *bus)
1543 {
1544 	if (npcm_i2c_is_quick(bus)) {
1545 		bus->state = I2C_STOP_PENDING;
1546 		bus->stop_ind = I2C_MASTER_DONE_IND;
1547 		npcm_i2c_eob_int(bus, true);
1548 		npcm_i2c_master_stop(bus);
1549 	} else if ((bus->rd_size == 1) && !bus->read_block_use) {
1550 		/*
1551 		 * Receiving one byte only - set NACK after ensuring
1552 		 * slave ACKed the address byte.
1553 		 */
1554 		npcm_i2c_nack(bus);
1555 	}
1556 
1557 	/* Reset stall-after-address-byte */
1558 	npcm_i2c_stall_after_start(bus, false);
1559 
1560 	/* Clear stall only after setting STOP */
1561 	iowrite8(NPCM_I2CST_STASTR, bus->reg + NPCM_I2CST);
1562 }
1563 
1564 /* SDA status is set - TX or RX, master */
1565 static void npcm_i2c_irq_handle_sda(struct npcm_i2c *bus, u8 i2cst)
1566 {
1567 	u8 fif_cts;
1568 
1569 	if (!npcm_i2c_is_master(bus))
1570 		return;
1571 
1572 	if (bus->state == I2C_IDLE) {
1573 		bus->stop_ind = I2C_WAKE_UP_IND;
1574 
1575 		if (npcm_i2c_is_quick(bus) || bus->read_block_use)
1576 			/*
1577 			 * Need to stall after successful
1578 			 * completion of sending address byte
1579 			 */
1580 			npcm_i2c_stall_after_start(bus, true);
1581 		else
1582 			npcm_i2c_stall_after_start(bus, false);
1583 
1584 		/*
1585 		 * Receiving one byte only - stall after successful completion
1586 		 * of sending address byte If we NACK here, and slave doesn't
1587 		 * ACK the address, we might unintentionally NACK the next
1588 		 * multi-byte read
1589 		 */
1590 		if (bus->wr_size == 0 && bus->rd_size == 1)
1591 			npcm_i2c_stall_after_start(bus, true);
1592 
1593 		/* Initiate I2C master tx */
1594 
1595 		/* select bank 1 for FIFO regs */
1596 		npcm_i2c_select_bank(bus, I2C_BANK_1);
1597 
1598 		fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1599 		fif_cts = fif_cts & ~NPCM_I2CFIF_CTS_SLVRSTR;
1600 
1601 		/* clear FIFO and relevant status bits. */
1602 		fif_cts = fif_cts | NPCM_I2CFIF_CTS_CLR_FIFO;
1603 		iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1604 
1605 		/* re-enable */
1606 		fif_cts = fif_cts | NPCM_I2CFIF_CTS_RXF_TXE;
1607 		iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1608 
1609 		/*
1610 		 * Configure the FIFO threshold:
1611 		 * according to the needed # of bytes to read.
1612 		 * Note: due to HW limitation can't config the rx fifo before it
1613 		 * got and ACK on the restart. LAST bit will not be reset unless
1614 		 * RX completed. It will stay set on the next tx.
1615 		 */
1616 		if (bus->wr_size)
1617 			npcm_i2c_set_fifo(bus, -1, bus->wr_size);
1618 		else
1619 			npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1620 
1621 		bus->state = I2C_OPER_STARTED;
1622 
1623 		if (npcm_i2c_is_quick(bus) || bus->wr_size)
1624 			npcm_i2c_wr_byte(bus, bus->dest_addr);
1625 		else
1626 			npcm_i2c_wr_byte(bus, bus->dest_addr | BIT(0));
1627 	/* SDA interrupt, after start\restart */
1628 	} else {
1629 		if (NPCM_I2CST_XMIT & i2cst) {
1630 			bus->operation = I2C_WRITE_OPER;
1631 			npcm_i2c_irq_master_handler_write(bus);
1632 		} else {
1633 			bus->operation = I2C_READ_OPER;
1634 			npcm_i2c_irq_master_handler_read(bus);
1635 		}
1636 	}
1637 }
1638 
1639 static int npcm_i2c_int_master_handler(struct npcm_i2c *bus)
1640 {
1641 	u8 i2cst;
1642 	int ret = -EIO;
1643 
1644 	i2cst = ioread8(bus->reg + NPCM_I2CST);
1645 
1646 	if (FIELD_GET(NPCM_I2CST_NMATCH, i2cst)) {
1647 		npcm_i2c_irq_handle_nmatch(bus);
1648 		return 0;
1649 	}
1650 	/* A NACK has occurred */
1651 	if (FIELD_GET(NPCM_I2CST_NEGACK, i2cst)) {
1652 		npcm_i2c_irq_handle_nack(bus);
1653 		return 0;
1654 	}
1655 
1656 	/* Master mode: a Bus Error has been identified */
1657 	if (FIELD_GET(NPCM_I2CST_BER, i2cst)) {
1658 		npcm_i2c_irq_handle_ber(bus);
1659 		return 0;
1660 	}
1661 
1662 	/* EOB: a master End Of Busy (meaning STOP completed) */
1663 	if ((FIELD_GET(NPCM_I2CCTL1_EOBINTE,
1664 		       ioread8(bus->reg + NPCM_I2CCTL1)) == 1) &&
1665 	    (FIELD_GET(NPCM_I2CCST3_EO_BUSY,
1666 		       ioread8(bus->reg + NPCM_I2CCST3)))) {
1667 		npcm_i2c_irq_handle_eob(bus);
1668 		return 0;
1669 	}
1670 
1671 	/* Address sent and requested stall occurred (Master mode) */
1672 	if (FIELD_GET(NPCM_I2CST_STASTR, i2cst)) {
1673 		npcm_i2c_irq_handle_stall_after_start(bus);
1674 		ret = 0;
1675 	}
1676 
1677 	/* SDA status is set - TX or RX, master */
1678 	if (FIELD_GET(NPCM_I2CST_SDAST, i2cst) ||
1679 	    (bus->fifo_use &&
1680 	    (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1681 		npcm_i2c_irq_handle_sda(bus, i2cst);
1682 		ret = 0;
1683 	}
1684 
1685 	return ret;
1686 }
1687 
1688 /* recovery using TGCLK functionality of the module */
1689 static int npcm_i2c_recovery_tgclk(struct i2c_adapter *_adap)
1690 {
1691 	u8               val;
1692 	u8               fif_cts;
1693 	bool             done = false;
1694 	int              status = -ENOTRECOVERABLE;
1695 	struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1696 	/* Allow 3 bytes (27 toggles) to be read from the slave: */
1697 	int              iter = 27;
1698 
1699 	if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1)) {
1700 		dev_dbg(bus->dev, "bus%d-0x%x recovery skipped, bus not stuck",
1701 			bus->num, bus->dest_addr);
1702 		npcm_i2c_reset(bus);
1703 		return 0;
1704 	}
1705 
1706 	npcm_i2c_int_enable(bus, false);
1707 	npcm_i2c_disable(bus);
1708 	npcm_i2c_enable(bus);
1709 	iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1710 	npcm_i2c_clear_tx_fifo(bus);
1711 	npcm_i2c_clear_rx_fifo(bus);
1712 	iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1713 	iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1714 	npcm_i2c_stall_after_start(bus, false);
1715 
1716 	/* select bank 1 for FIFO regs */
1717 	npcm_i2c_select_bank(bus, I2C_BANK_1);
1718 
1719 	/* clear FIFO and relevant status bits. */
1720 	fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1721 	fif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
1722 	fif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
1723 	iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1724 	npcm_i2c_set_fifo(bus, -1, 0);
1725 
1726 	/* Repeat the following sequence until SDA is released */
1727 	do {
1728 		/* Issue a single SCL toggle */
1729 		iowrite8(NPCM_I2CCST_TGSCL, bus->reg + NPCM_I2CCST);
1730 		usleep_range(20, 30);
1731 		/* If SDA line is inactive (high), stop */
1732 		if (npcm_i2c_get_SDA(_adap)) {
1733 			done = true;
1734 			status = 0;
1735 		}
1736 	} while (!done && iter--);
1737 
1738 	/* If SDA line is released: send start-addr-stop, to re-sync. */
1739 	if (npcm_i2c_get_SDA(_adap)) {
1740 		/* Send an address byte in write direction: */
1741 		npcm_i2c_wr_byte(bus, bus->dest_addr);
1742 		npcm_i2c_master_start(bus);
1743 		/* Wait until START condition is sent */
1744 		status = readx_poll_timeout(npcm_i2c_get_SCL, _adap, val, !val,
1745 					    20, 200);
1746 		/* If START condition was sent */
1747 		if (npcm_i2c_is_master(bus) > 0) {
1748 			usleep_range(20, 30);
1749 			npcm_i2c_master_stop(bus);
1750 			usleep_range(200, 500);
1751 		}
1752 	}
1753 	npcm_i2c_reset(bus);
1754 	npcm_i2c_int_enable(bus, true);
1755 
1756 	if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1))
1757 		status = 0;
1758 	else
1759 		status = -ENOTRECOVERABLE;
1760 	if (status) {
1761 		if (bus->rec_fail_cnt < ULLONG_MAX)
1762 			bus->rec_fail_cnt++;
1763 	} else {
1764 		if (bus->rec_succ_cnt < ULLONG_MAX)
1765 			bus->rec_succ_cnt++;
1766 	}
1767 	return status;
1768 }
1769 
1770 /* recovery using bit banging functionality of the module */
1771 static void npcm_i2c_recovery_init(struct i2c_adapter *_adap)
1772 {
1773 	struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1774 	struct i2c_bus_recovery_info *rinfo = &bus->rinfo;
1775 
1776 	rinfo->recover_bus = npcm_i2c_recovery_tgclk;
1777 
1778 	/*
1779 	 * npcm i2c HW allows direct reading of SCL and SDA.
1780 	 * However, it does not support setting SCL and SDA directly.
1781 	 * The recovery function can toggle SCL when SDA is low (but not set)
1782 	 * Getter functions used internally, and can be used externally.
1783 	 */
1784 	rinfo->get_scl = npcm_i2c_get_SCL;
1785 	rinfo->get_sda = npcm_i2c_get_SDA;
1786 	_adap->bus_recovery_info = rinfo;
1787 }
1788 
1789 /* SCLFRQ min/max field values */
1790 #define SCLFRQ_MIN  10
1791 #define SCLFRQ_MAX  511
1792 #define clk_coef(freq, mul)	DIV_ROUND_UP((freq) * (mul), 1000000)
1793 
1794 /*
1795  * npcm_i2c_init_clk: init HW timing parameters.
1796  * NPCM7XX i2c module timing parameters are dependent on module core clk (APB)
1797  * and bus frequency.
1798  * 100kHz bus requires tSCL = 4 * SCLFRQ * tCLK. LT and HT are symmetric.
1799  * 400kHz bus requires asymmetric HT and LT. A different equation is recommended
1800  * by the HW designer, given core clock range (equations in comments below).
1801  *
1802  */
1803 static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz)
1804 {
1805 	u32  k1 = 0;
1806 	u32  k2 = 0;
1807 	u8   dbnct = 0;
1808 	u32  sclfrq = 0;
1809 	u8   hldt = 7;
1810 	u8   fast_mode = 0;
1811 	u32  src_clk_khz;
1812 	u32  bus_freq_khz;
1813 
1814 	src_clk_khz = bus->apb_clk / 1000;
1815 	bus_freq_khz = bus_freq_hz / 1000;
1816 	bus->bus_freq = bus_freq_hz;
1817 
1818 	/* 100KHz and below: */
1819 	if (bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) {
1820 		sclfrq = src_clk_khz / (bus_freq_khz * 4);
1821 
1822 		if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX)
1823 			return -EDOM;
1824 
1825 		if (src_clk_khz >= 40000)
1826 			hldt = 17;
1827 		else if (src_clk_khz >= 12500)
1828 			hldt = 15;
1829 		else
1830 			hldt = 7;
1831 	}
1832 
1833 	/* 400KHz: */
1834 	else if (bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) {
1835 		sclfrq = 0;
1836 		fast_mode = I2CCTL3_400K_MODE;
1837 
1838 		if (src_clk_khz < 7500)
1839 			/* 400KHZ cannot be supported for core clock < 7.5MHz */
1840 			return -EDOM;
1841 
1842 		else if (src_clk_khz >= 50000) {
1843 			k1 = 80;
1844 			k2 = 48;
1845 			hldt = 12;
1846 			dbnct = 7;
1847 		}
1848 
1849 		/* Master or Slave with frequency > 25MHz */
1850 		else if (src_clk_khz > 25000) {
1851 			hldt = clk_coef(src_clk_khz, 300) + 7;
1852 			k1 = clk_coef(src_clk_khz, 1600);
1853 			k2 = clk_coef(src_clk_khz, 900);
1854 		}
1855 	}
1856 
1857 	/* 1MHz: */
1858 	else if (bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) {
1859 		sclfrq = 0;
1860 		fast_mode = I2CCTL3_400K_MODE;
1861 
1862 		/* 1MHZ cannot be supported for core clock < 24 MHz */
1863 		if (src_clk_khz < 24000)
1864 			return -EDOM;
1865 
1866 		k1 = clk_coef(src_clk_khz, 620);
1867 		k2 = clk_coef(src_clk_khz, 380);
1868 
1869 		/* Core clk > 40 MHz */
1870 		if (src_clk_khz > 40000) {
1871 			/*
1872 			 * Set HLDT:
1873 			 * SDA hold time:  (HLDT-7) * T(CLK) >= 120
1874 			 * HLDT = 120/T(CLK) + 7 = 120 * FREQ(CLK) + 7
1875 			 */
1876 			hldt = clk_coef(src_clk_khz, 120) + 7;
1877 		} else {
1878 			hldt = 7;
1879 			dbnct = 2;
1880 		}
1881 	}
1882 
1883 	/* Frequency larger than 1 MHz is not supported */
1884 	else
1885 		return -EINVAL;
1886 
1887 	if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
1888 		k1 = round_up(k1, 2);
1889 		k2 = round_up(k2 + 1, 2);
1890 		if (k1 < SCLFRQ_MIN || k1 > SCLFRQ_MAX ||
1891 		    k2 < SCLFRQ_MIN || k2 > SCLFRQ_MAX)
1892 			return -EDOM;
1893 	}
1894 
1895 	/* write sclfrq value. bits [6:0] are in I2CCTL2 reg */
1896 	iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, sclfrq & 0x7F),
1897 		 bus->reg + NPCM_I2CCTL2);
1898 
1899 	/* bits [8:7] are in I2CCTL3 reg */
1900 	iowrite8(fast_mode | FIELD_PREP(I2CCTL3_SCLFRQ8_7, (sclfrq >> 7) & 0x3),
1901 		 bus->reg + NPCM_I2CCTL3);
1902 
1903 	/* Select Bank 0 to access NPCM_I2CCTL4/NPCM_I2CCTL5 */
1904 	npcm_i2c_select_bank(bus, I2C_BANK_0);
1905 
1906 	if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
1907 		/*
1908 		 * Set SCL Low/High Time:
1909 		 * k1 = 2 * SCLLT7-0 -> Low Time  = k1 / 2
1910 		 * k2 = 2 * SCLLT7-0 -> High Time = k2 / 2
1911 		 */
1912 		iowrite8(k1 / 2, bus->reg + NPCM_I2CSCLLT);
1913 		iowrite8(k2 / 2, bus->reg + NPCM_I2CSCLHT);
1914 
1915 		iowrite8(dbnct, bus->reg + NPCM_I2CCTL5);
1916 	}
1917 
1918 	iowrite8(hldt, bus->reg + NPCM_I2CCTL4);
1919 
1920 	/* Return to Bank 1, and stay there by default: */
1921 	npcm_i2c_select_bank(bus, I2C_BANK_1);
1922 
1923 	return 0;
1924 }
1925 
1926 static int npcm_i2c_init_module(struct npcm_i2c *bus, enum i2c_mode mode,
1927 				u32 bus_freq_hz)
1928 {
1929 	u8 val;
1930 	int ret;
1931 
1932 	/* Check whether module already enabled or frequency is out of bounds */
1933 	if ((bus->state != I2C_DISABLE && bus->state != I2C_IDLE) ||
1934 	    bus_freq_hz < I2C_FREQ_MIN_HZ || bus_freq_hz > I2C_FREQ_MAX_HZ)
1935 		return -EINVAL;
1936 
1937 	npcm_i2c_int_enable(bus, false);
1938 	npcm_i2c_disable(bus);
1939 
1940 	/* Configure FIFO mode : */
1941 	if (FIELD_GET(I2C_VER_FIFO_EN, ioread8(bus->reg + I2C_VER))) {
1942 		bus->fifo_use = true;
1943 		npcm_i2c_select_bank(bus, I2C_BANK_0);
1944 		val = ioread8(bus->reg + NPCM_I2CFIF_CTL);
1945 		val |= NPCM_I2CFIF_CTL_FIFO_EN;
1946 		iowrite8(val, bus->reg + NPCM_I2CFIF_CTL);
1947 		npcm_i2c_select_bank(bus, I2C_BANK_1);
1948 	} else {
1949 		bus->fifo_use = false;
1950 	}
1951 
1952 	/* Configure I2C module clock frequency */
1953 	ret = npcm_i2c_init_clk(bus, bus_freq_hz);
1954 	if (ret) {
1955 		dev_err(bus->dev, "npcm_i2c_init_clk failed\n");
1956 		return ret;
1957 	}
1958 
1959 	/* Enable module (before configuring CTL1) */
1960 	npcm_i2c_enable(bus);
1961 	bus->state = I2C_IDLE;
1962 	val = ioread8(bus->reg + NPCM_I2CCTL1);
1963 	val = (val | NPCM_I2CCTL1_NMINTE) & ~NPCM_I2CCTL1_RWS;
1964 	iowrite8(val, bus->reg + NPCM_I2CCTL1);
1965 
1966 	npcm_i2c_reset(bus);
1967 
1968 	/* Check HW is OK: SDA and SCL should be high at this point. */
1969 	if ((npcm_i2c_get_SDA(&bus->adap) == 0) || (npcm_i2c_get_SCL(&bus->adap) == 0)) {
1970 		dev_err(bus->dev, "I2C%d init fail: lines are low\n", bus->num);
1971 		dev_err(bus->dev, "SDA=%d SCL=%d\n", npcm_i2c_get_SDA(&bus->adap),
1972 			npcm_i2c_get_SCL(&bus->adap));
1973 		return -ENXIO;
1974 	}
1975 
1976 	npcm_i2c_int_enable(bus, true);
1977 	return 0;
1978 }
1979 
1980 static int __npcm_i2c_init(struct npcm_i2c *bus, struct platform_device *pdev)
1981 {
1982 	u32 clk_freq_hz;
1983 	int ret;
1984 
1985 	/* Initialize the internal data structures */
1986 	bus->state = I2C_DISABLE;
1987 	bus->master_or_slave = I2C_SLAVE;
1988 	bus->int_time_stamp = 0;
1989 #if IS_ENABLED(CONFIG_I2C_SLAVE)
1990 	bus->slave = NULL;
1991 #endif
1992 
1993 	ret = device_property_read_u32(&pdev->dev, "clock-frequency",
1994 				       &clk_freq_hz);
1995 	if (ret) {
1996 		dev_info(&pdev->dev, "Could not read clock-frequency property");
1997 		clk_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
1998 	}
1999 
2000 	ret = npcm_i2c_init_module(bus, I2C_MASTER, clk_freq_hz);
2001 	if (ret) {
2002 		dev_err(&pdev->dev, "npcm_i2c_init_module failed\n");
2003 		return ret;
2004 	}
2005 
2006 	return 0;
2007 }
2008 
2009 static irqreturn_t npcm_i2c_bus_irq(int irq, void *dev_id)
2010 {
2011 	struct npcm_i2c *bus = dev_id;
2012 
2013 	if (npcm_i2c_is_master(bus))
2014 		bus->master_or_slave = I2C_MASTER;
2015 
2016 	if (bus->master_or_slave == I2C_MASTER) {
2017 		bus->int_time_stamp = jiffies;
2018 		if (!npcm_i2c_int_master_handler(bus))
2019 			return IRQ_HANDLED;
2020 	}
2021 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2022 	if (bus->slave) {
2023 		bus->master_or_slave = I2C_SLAVE;
2024 		if (npcm_i2c_int_slave_handler(bus))
2025 			return IRQ_HANDLED;
2026 	}
2027 #endif
2028 	/* Clear status bits for spurious interrupts */
2029 	npcm_i2c_clear_master_status(bus);
2030 
2031 	return IRQ_HANDLED;
2032 }
2033 
2034 static bool npcm_i2c_master_start_xmit(struct npcm_i2c *bus,
2035 				       u8 slave_addr, u16 nwrite, u16 nread,
2036 				       u8 *write_data, u8 *read_data,
2037 				       bool use_PEC, bool use_read_block)
2038 {
2039 	if (bus->state != I2C_IDLE) {
2040 		bus->cmd_err = -EBUSY;
2041 		return false;
2042 	}
2043 	bus->dest_addr = slave_addr << 1;
2044 	bus->wr_buf = write_data;
2045 	bus->wr_size = nwrite;
2046 	bus->wr_ind = 0;
2047 	bus->rd_buf = read_data;
2048 	bus->rd_size = nread;
2049 	bus->rd_ind = 0;
2050 	bus->PEC_use = 0;
2051 
2052 	/* for tx PEC is appended to buffer from i2c IF. PEC flag is ignored */
2053 	if (nread)
2054 		bus->PEC_use = use_PEC;
2055 
2056 	bus->read_block_use = use_read_block;
2057 	if (nread && !nwrite)
2058 		bus->operation = I2C_READ_OPER;
2059 	else
2060 		bus->operation = I2C_WRITE_OPER;
2061 	if (bus->fifo_use) {
2062 		u8 i2cfif_cts;
2063 
2064 		npcm_i2c_select_bank(bus, I2C_BANK_1);
2065 		/* clear FIFO and relevant status bits. */
2066 		i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
2067 		i2cfif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
2068 		i2cfif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
2069 		iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS);
2070 	}
2071 
2072 	bus->state = I2C_IDLE;
2073 	npcm_i2c_stall_after_start(bus, true);
2074 	npcm_i2c_master_start(bus);
2075 	return true;
2076 }
2077 
2078 static int npcm_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
2079 				int num)
2080 {
2081 	struct npcm_i2c *bus = container_of(adap, struct npcm_i2c, adap);
2082 	struct i2c_msg *msg0, *msg1;
2083 	unsigned long time_left, flags;
2084 	u16 nwrite, nread;
2085 	u8 *write_data, *read_data;
2086 	u8 slave_addr;
2087 	unsigned long timeout;
2088 	bool read_block = false;
2089 	bool read_PEC = false;
2090 	u8 bus_busy;
2091 	unsigned long timeout_usec;
2092 
2093 	if (bus->state == I2C_DISABLE) {
2094 		dev_err(bus->dev, "I2C%d module is disabled", bus->num);
2095 		return -EINVAL;
2096 	}
2097 
2098 	msg0 = &msgs[0];
2099 	slave_addr = msg0->addr;
2100 	if (msg0->flags & I2C_M_RD) { /* read */
2101 		nwrite = 0;
2102 		write_data = NULL;
2103 		read_data = msg0->buf;
2104 		if (msg0->flags & I2C_M_RECV_LEN) {
2105 			nread = 1;
2106 			read_block = true;
2107 			if (msg0->flags & I2C_CLIENT_PEC)
2108 				read_PEC = true;
2109 		} else {
2110 			nread = msg0->len;
2111 		}
2112 	} else { /* write */
2113 		nwrite = msg0->len;
2114 		write_data = msg0->buf;
2115 		nread = 0;
2116 		read_data = NULL;
2117 		if (num == 2) {
2118 			msg1 = &msgs[1];
2119 			read_data = msg1->buf;
2120 			if (msg1->flags & I2C_M_RECV_LEN) {
2121 				nread = 1;
2122 				read_block = true;
2123 				if (msg1->flags & I2C_CLIENT_PEC)
2124 					read_PEC = true;
2125 			} else {
2126 				nread = msg1->len;
2127 				read_block = false;
2128 			}
2129 		}
2130 	}
2131 
2132 	/*
2133 	 * Adaptive TimeOut: estimated time in usec + 100% margin:
2134 	 * 2: double the timeout for clock stretching case
2135 	 * 9: bits per transaction (including the ack/nack)
2136 	 */
2137 	timeout_usec = (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + nwrite);
2138 	timeout = max_t(unsigned long, bus->adap.timeout, usecs_to_jiffies(timeout_usec));
2139 	if (nwrite >= 32 * 1024 || nread >= 32 * 1024) {
2140 		dev_err(bus->dev, "i2c%d buffer too big\n", bus->num);
2141 		return -EINVAL;
2142 	}
2143 
2144 	time_left = jiffies + timeout + 1;
2145 	do {
2146 		/*
2147 		 * we must clear slave address immediately when the bus is not
2148 		 * busy, so we spinlock it, but we don't keep the lock for the
2149 		 * entire while since it is too long.
2150 		 */
2151 		spin_lock_irqsave(&bus->lock, flags);
2152 		bus_busy = ioread8(bus->reg + NPCM_I2CCST) & NPCM_I2CCST_BB;
2153 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2154 		if (!bus_busy && bus->slave)
2155 			iowrite8((bus->slave->addr & 0x7F),
2156 				 bus->reg + NPCM_I2CADDR1);
2157 #endif
2158 		spin_unlock_irqrestore(&bus->lock, flags);
2159 
2160 	} while (time_is_after_jiffies(time_left) && bus_busy);
2161 
2162 	if (bus_busy) {
2163 		iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
2164 		npcm_i2c_reset(bus);
2165 		i2c_recover_bus(adap);
2166 		return -EAGAIN;
2167 	}
2168 
2169 	npcm_i2c_init_params(bus);
2170 	bus->dest_addr = slave_addr;
2171 	bus->msgs = msgs;
2172 	bus->msgs_num = num;
2173 	bus->cmd_err = 0;
2174 	bus->read_block_use = read_block;
2175 
2176 	reinit_completion(&bus->cmd_complete);
2177 
2178 	npcm_i2c_int_enable(bus, true);
2179 
2180 	if (npcm_i2c_master_start_xmit(bus, slave_addr, nwrite, nread,
2181 				       write_data, read_data, read_PEC,
2182 				       read_block)) {
2183 		time_left = wait_for_completion_timeout(&bus->cmd_complete,
2184 							timeout);
2185 
2186 		if (time_left == 0) {
2187 			if (bus->timeout_cnt < ULLONG_MAX)
2188 				bus->timeout_cnt++;
2189 			if (bus->master_or_slave == I2C_MASTER) {
2190 				i2c_recover_bus(adap);
2191 				bus->cmd_err = -EIO;
2192 				bus->state = I2C_IDLE;
2193 			}
2194 		}
2195 	}
2196 
2197 	/* if there was BER, check if need to recover the bus: */
2198 	if (bus->cmd_err == -EAGAIN)
2199 		bus->cmd_err = i2c_recover_bus(adap);
2200 
2201 	/*
2202 	 * After any type of error, check if LAST bit is still set,
2203 	 * due to a HW issue.
2204 	 * It cannot be cleared without resetting the module.
2205 	 */
2206 	else if (bus->cmd_err &&
2207 		 (bus->data->rxf_ctl_last_pec & ioread8(bus->reg + NPCM_I2CRXF_CTL)))
2208 		npcm_i2c_reset(bus);
2209 
2210 	/* After any xfer, successful or not, stall and EOB must be disabled */
2211 	npcm_i2c_stall_after_start(bus, false);
2212 	npcm_i2c_eob_int(bus, false);
2213 
2214 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2215 	/* reenable slave if it was enabled */
2216 	if (bus->slave)
2217 		iowrite8((bus->slave->addr & 0x7F) | NPCM_I2CADDR_SAEN,
2218 			 bus->reg + NPCM_I2CADDR1);
2219 #else
2220 	npcm_i2c_int_enable(bus, false);
2221 #endif
2222 	return bus->cmd_err;
2223 }
2224 
2225 static u32 npcm_i2c_functionality(struct i2c_adapter *adap)
2226 {
2227 	return I2C_FUNC_I2C |
2228 	       I2C_FUNC_SMBUS_EMUL |
2229 	       I2C_FUNC_SMBUS_BLOCK_DATA |
2230 	       I2C_FUNC_SMBUS_PEC |
2231 	       I2C_FUNC_SLAVE;
2232 }
2233 
2234 static const struct i2c_adapter_quirks npcm_i2c_quirks = {
2235 	.max_read_len = 32768,
2236 	.max_write_len = 32768,
2237 	.flags = I2C_AQ_COMB_WRITE_THEN_READ,
2238 };
2239 
2240 static const struct i2c_algorithm npcm_i2c_algo = {
2241 	.master_xfer = npcm_i2c_master_xfer,
2242 	.functionality = npcm_i2c_functionality,
2243 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2244 	.reg_slave	= npcm_i2c_reg_slave,
2245 	.unreg_slave	= npcm_i2c_unreg_slave,
2246 #endif
2247 };
2248 
2249 static void npcm_i2c_init_debugfs(struct platform_device *pdev,
2250 				  struct npcm_i2c *bus)
2251 {
2252 	debugfs_create_u64("ber_cnt", 0444, bus->adap.debugfs, &bus->ber_cnt);
2253 	debugfs_create_u64("nack_cnt", 0444, bus->adap.debugfs, &bus->nack_cnt);
2254 	debugfs_create_u64("rec_succ_cnt", 0444, bus->adap.debugfs, &bus->rec_succ_cnt);
2255 	debugfs_create_u64("rec_fail_cnt", 0444, bus->adap.debugfs, &bus->rec_fail_cnt);
2256 	debugfs_create_u64("timeout_cnt", 0444, bus->adap.debugfs, &bus->timeout_cnt);
2257 	debugfs_create_u64("tx_complete_cnt", 0444, bus->adap.debugfs, &bus->tx_complete_cnt);
2258 }
2259 
2260 static int npcm_i2c_probe_bus(struct platform_device *pdev)
2261 {
2262 	struct device_node *np = pdev->dev.of_node;
2263 	static struct regmap *gcr_regmap;
2264 	struct device *dev = &pdev->dev;
2265 	struct i2c_adapter *adap;
2266 	struct npcm_i2c *bus;
2267 	struct clk *i2c_clk;
2268 	int irq;
2269 	int ret;
2270 
2271 	bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
2272 	if (!bus)
2273 		return -ENOMEM;
2274 
2275 	bus->dev = &pdev->dev;
2276 
2277 	bus->data = of_device_get_match_data(dev);
2278 	if (!bus->data) {
2279 		dev_err(dev, "OF data missing\n");
2280 		return -EINVAL;
2281 	}
2282 
2283 	bus->num = of_alias_get_id(pdev->dev.of_node, "i2c");
2284 	/* core clk must be acquired to calculate module timing settings */
2285 	i2c_clk = devm_clk_get(&pdev->dev, NULL);
2286 	if (IS_ERR(i2c_clk))
2287 		return PTR_ERR(i2c_clk);
2288 	bus->apb_clk = clk_get_rate(i2c_clk);
2289 
2290 	gcr_regmap = syscon_regmap_lookup_by_phandle(np, "nuvoton,sys-mgr");
2291 	if (IS_ERR(gcr_regmap))
2292 		gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
2293 
2294 	if (IS_ERR(gcr_regmap))
2295 		return PTR_ERR(gcr_regmap);
2296 	regmap_write(gcr_regmap, NPCM_I2CSEGCTL, bus->data->segctl_init_val);
2297 
2298 	bus->reg = devm_platform_ioremap_resource(pdev, 0);
2299 	if (IS_ERR(bus->reg))
2300 		return PTR_ERR(bus->reg);
2301 
2302 	spin_lock_init(&bus->lock);
2303 	init_completion(&bus->cmd_complete);
2304 
2305 	adap = &bus->adap;
2306 	adap->owner = THIS_MODULE;
2307 	adap->retries = 3;
2308 	adap->timeout = msecs_to_jiffies(35);
2309 	adap->algo = &npcm_i2c_algo;
2310 	adap->quirks = &npcm_i2c_quirks;
2311 	adap->algo_data = bus;
2312 	adap->dev.parent = &pdev->dev;
2313 	adap->dev.of_node = pdev->dev.of_node;
2314 	adap->nr = pdev->id;
2315 
2316 	irq = platform_get_irq(pdev, 0);
2317 	if (irq < 0)
2318 		return irq;
2319 
2320 	ret = devm_request_irq(bus->dev, irq, npcm_i2c_bus_irq, 0,
2321 			       dev_name(bus->dev), bus);
2322 	if (ret)
2323 		return ret;
2324 
2325 	ret = __npcm_i2c_init(bus, pdev);
2326 	if (ret)
2327 		return ret;
2328 
2329 	npcm_i2c_recovery_init(adap);
2330 
2331 	i2c_set_adapdata(adap, bus);
2332 
2333 	snprintf(bus->adap.name, sizeof(bus->adap.name), "npcm_i2c_%d",
2334 		 bus->num);
2335 	ret = i2c_add_numbered_adapter(&bus->adap);
2336 	if (ret)
2337 		return ret;
2338 
2339 	platform_set_drvdata(pdev, bus);
2340 	npcm_i2c_init_debugfs(pdev, bus);
2341 	return 0;
2342 }
2343 
2344 static void npcm_i2c_remove_bus(struct platform_device *pdev)
2345 {
2346 	unsigned long lock_flags;
2347 	struct npcm_i2c *bus = platform_get_drvdata(pdev);
2348 
2349 	spin_lock_irqsave(&bus->lock, lock_flags);
2350 	npcm_i2c_disable(bus);
2351 	spin_unlock_irqrestore(&bus->lock, lock_flags);
2352 	i2c_del_adapter(&bus->adap);
2353 }
2354 
2355 static const struct of_device_id npcm_i2c_bus_of_table[] = {
2356 	{ .compatible = "nuvoton,npcm750-i2c", .data = &npxm7xx_i2c_data },
2357 	{ .compatible = "nuvoton,npcm845-i2c", .data = &npxm8xx_i2c_data },
2358 	{}
2359 };
2360 MODULE_DEVICE_TABLE(of, npcm_i2c_bus_of_table);
2361 
2362 static struct platform_driver npcm_i2c_bus_driver = {
2363 	.probe = npcm_i2c_probe_bus,
2364 	.remove_new = npcm_i2c_remove_bus,
2365 	.driver = {
2366 		.name = "nuvoton-i2c",
2367 		.of_match_table = npcm_i2c_bus_of_table,
2368 	}
2369 };
2370 
2371 module_platform_driver(npcm_i2c_bus_driver);
2372 
2373 MODULE_AUTHOR("Avi Fishman <avi.fishman@gmail.com>");
2374 MODULE_AUTHOR("Tali Perry <tali.perry@nuvoton.com>");
2375 MODULE_AUTHOR("Tyrone Ting <kfting@nuvoton.com>");
2376 MODULE_DESCRIPTION("Nuvoton I2C Bus Driver");
2377 MODULE_LICENSE("GPL v2");
2378