1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Nuvoton NPCM7xx I2C Controller driver 4 * 5 * Copyright (C) 2020 Nuvoton Technologies tali.perry@nuvoton.com 6 */ 7 #include <linux/bitfield.h> 8 #include <linux/clk.h> 9 #include <linux/debugfs.h> 10 #include <linux/errno.h> 11 #include <linux/i2c.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/irq.h> 15 #include <linux/jiffies.h> 16 #include <linux/kernel.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/regmap.h> 22 23 enum i2c_mode { 24 I2C_MASTER, 25 I2C_SLAVE, 26 }; 27 28 /* 29 * External I2C Interface driver xfer indication values, which indicate status 30 * of the bus. 31 */ 32 enum i2c_state_ind { 33 I2C_NO_STATUS_IND = 0, 34 I2C_SLAVE_RCV_IND, 35 I2C_SLAVE_XMIT_IND, 36 I2C_SLAVE_XMIT_MISSING_DATA_IND, 37 I2C_SLAVE_RESTART_IND, 38 I2C_SLAVE_DONE_IND, 39 I2C_MASTER_DONE_IND, 40 I2C_NACK_IND, 41 I2C_BUS_ERR_IND, 42 I2C_WAKE_UP_IND, 43 I2C_BLOCK_BYTES_ERR_IND, 44 I2C_SLAVE_RCV_MISSING_DATA_IND, 45 }; 46 47 /* 48 * Operation type values (used to define the operation currently running) 49 * module is interrupt driven, on each interrupt the current operation is 50 * checked to see if the module is currently reading or writing. 51 */ 52 enum i2c_oper { 53 I2C_NO_OPER = 0, 54 I2C_WRITE_OPER, 55 I2C_READ_OPER, 56 }; 57 58 /* I2C Bank (module had 2 banks of registers) */ 59 enum i2c_bank { 60 I2C_BANK_0 = 0, 61 I2C_BANK_1, 62 }; 63 64 /* Internal I2C states values (for the I2C module state machine). */ 65 enum i2c_state { 66 I2C_DISABLE = 0, 67 I2C_IDLE, 68 I2C_MASTER_START, 69 I2C_SLAVE_MATCH, 70 I2C_OPER_STARTED, 71 I2C_STOP_PENDING, 72 }; 73 74 #if IS_ENABLED(CONFIG_I2C_SLAVE) 75 /* Module supports setting multiple own slave addresses */ 76 enum i2c_addr { 77 I2C_SLAVE_ADDR1 = 0, 78 I2C_SLAVE_ADDR2, 79 I2C_SLAVE_ADDR3, 80 I2C_SLAVE_ADDR4, 81 I2C_SLAVE_ADDR5, 82 I2C_SLAVE_ADDR6, 83 I2C_SLAVE_ADDR7, 84 I2C_SLAVE_ADDR8, 85 I2C_SLAVE_ADDR9, 86 I2C_SLAVE_ADDR10, 87 I2C_GC_ADDR, 88 I2C_ARP_ADDR, 89 }; 90 #endif 91 92 /* init register and default value required to enable module */ 93 #define NPCM_I2CSEGCTL 0xE4 94 95 /* Common regs */ 96 #define NPCM_I2CSDA 0x00 97 #define NPCM_I2CST 0x02 98 #define NPCM_I2CCST 0x04 99 #define NPCM_I2CCTL1 0x06 100 #define NPCM_I2CADDR1 0x08 101 #define NPCM_I2CCTL2 0x0A 102 #define NPCM_I2CADDR2 0x0C 103 #define NPCM_I2CCTL3 0x0E 104 #define NPCM_I2CCST2 0x18 105 #define NPCM_I2CCST3 0x19 106 #define I2C_VER 0x1F 107 108 /* BANK 0 regs */ 109 #define NPCM_I2CADDR3 0x10 110 #define NPCM_I2CADDR7 0x11 111 #define NPCM_I2CADDR4 0x12 112 #define NPCM_I2CADDR8 0x13 113 #define NPCM_I2CADDR5 0x14 114 #define NPCM_I2CADDR9 0x15 115 #define NPCM_I2CADDR6 0x16 116 #define NPCM_I2CADDR10 0x17 117 #define NPCM_I2CCTL4 0x1A 118 #define NPCM_I2CCTL5 0x1B 119 #define NPCM_I2CSCLLT 0x1C /* SCL Low Time */ 120 #define NPCM_I2CFIF_CTL 0x1D /* FIFO Control */ 121 #define NPCM_I2CSCLHT 0x1E /* SCL High Time */ 122 123 /* BANK 1 regs */ 124 #define NPCM_I2CFIF_CTS 0x10 /* Both FIFOs Control and Status */ 125 #define NPCM_I2CTXF_CTL 0x12 /* Tx-FIFO Control */ 126 #define NPCM_I2CT_OUT 0x14 /* Bus T.O. */ 127 #define NPCM_I2CPEC 0x16 /* PEC Data */ 128 #define NPCM_I2CTXF_STS 0x1A /* Tx-FIFO Status */ 129 #define NPCM_I2CRXF_STS 0x1C /* Rx-FIFO Status */ 130 #define NPCM_I2CRXF_CTL 0x1E /* Rx-FIFO Control */ 131 132 #if IS_ENABLED(CONFIG_I2C_SLAVE) 133 /* 134 * npcm_i2caddr array: 135 * The module supports having multiple own slave addresses. 136 * Since the addr regs are sprinkled all over the address space, 137 * use this array to get the address or each register. 138 */ 139 #define I2C_NUM_OWN_ADDR 10 140 #define I2C_NUM_OWN_ADDR_SUPPORTED 2 141 142 static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = { 143 NPCM_I2CADDR1, NPCM_I2CADDR2, NPCM_I2CADDR3, NPCM_I2CADDR4, 144 NPCM_I2CADDR5, NPCM_I2CADDR6, NPCM_I2CADDR7, NPCM_I2CADDR8, 145 NPCM_I2CADDR9, NPCM_I2CADDR10, 146 }; 147 #endif 148 149 /* NPCM_I2CST reg fields */ 150 #define NPCM_I2CST_XMIT BIT(0) /* Transmit mode */ 151 #define NPCM_I2CST_MASTER BIT(1) /* Master mode */ 152 #define NPCM_I2CST_NMATCH BIT(2) /* New match */ 153 #define NPCM_I2CST_STASTR BIT(3) /* Stall after start */ 154 #define NPCM_I2CST_NEGACK BIT(4) /* Negative ACK */ 155 #define NPCM_I2CST_BER BIT(5) /* Bus error */ 156 #define NPCM_I2CST_SDAST BIT(6) /* SDA status */ 157 #define NPCM_I2CST_SLVSTP BIT(7) /* Slave stop */ 158 159 /* NPCM_I2CCST reg fields */ 160 #define NPCM_I2CCST_BUSY BIT(0) /* Busy */ 161 #define NPCM_I2CCST_BB BIT(1) /* Bus busy */ 162 #define NPCM_I2CCST_MATCH BIT(2) /* Address match */ 163 #define NPCM_I2CCST_GCMATCH BIT(3) /* Global call match */ 164 #define NPCM_I2CCST_TSDA BIT(4) /* Test SDA line */ 165 #define NPCM_I2CCST_TGSCL BIT(5) /* Toggle SCL line */ 166 #define NPCM_I2CCST_MATCHAF BIT(6) /* Match address field */ 167 #define NPCM_I2CCST_ARPMATCH BIT(7) /* ARP address match */ 168 169 /* NPCM_I2CCTL1 reg fields */ 170 #define NPCM_I2CCTL1_START BIT(0) /* Generate start condition */ 171 #define NPCM_I2CCTL1_STOP BIT(1) /* Generate stop condition */ 172 #define NPCM_I2CCTL1_INTEN BIT(2) /* Interrupt enable */ 173 #define NPCM_I2CCTL1_EOBINTE BIT(3) 174 #define NPCM_I2CCTL1_ACK BIT(4) 175 #define NPCM_I2CCTL1_GCMEN BIT(5) /* Global call match enable */ 176 #define NPCM_I2CCTL1_NMINTE BIT(6) /* New match interrupt enable */ 177 #define NPCM_I2CCTL1_STASTRE BIT(7) /* Stall after start enable */ 178 179 /* RW1S fields (inside a RW reg): */ 180 #define NPCM_I2CCTL1_RWS \ 181 (NPCM_I2CCTL1_START | NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK) 182 183 /* npcm_i2caddr reg fields */ 184 #define NPCM_I2CADDR_A GENMASK(6, 0) /* Address */ 185 #define NPCM_I2CADDR_SAEN BIT(7) /* Slave address enable */ 186 187 /* NPCM_I2CCTL2 reg fields */ 188 #define I2CCTL2_ENABLE BIT(0) /* Module enable */ 189 #define I2CCTL2_SCLFRQ6_0 GENMASK(7, 1) /* Bits 0:6 of frequency divisor */ 190 191 /* NPCM_I2CCTL3 reg fields */ 192 #define I2CCTL3_SCLFRQ8_7 GENMASK(1, 0) /* Bits 7:8 of frequency divisor */ 193 #define I2CCTL3_ARPMEN BIT(2) /* ARP match enable */ 194 #define I2CCTL3_IDL_START BIT(3) 195 #define I2CCTL3_400K_MODE BIT(4) 196 #define I2CCTL3_BNK_SEL BIT(5) 197 #define I2CCTL3_SDA_LVL BIT(6) 198 #define I2CCTL3_SCL_LVL BIT(7) 199 200 /* NPCM_I2CCST2 reg fields */ 201 #define NPCM_I2CCST2_MATCHA1F BIT(0) 202 #define NPCM_I2CCST2_MATCHA2F BIT(1) 203 #define NPCM_I2CCST2_MATCHA3F BIT(2) 204 #define NPCM_I2CCST2_MATCHA4F BIT(3) 205 #define NPCM_I2CCST2_MATCHA5F BIT(4) 206 #define NPCM_I2CCST2_MATCHA6F BIT(5) 207 #define NPCM_I2CCST2_MATCHA7F BIT(5) 208 #define NPCM_I2CCST2_INTSTS BIT(7) 209 210 /* NPCM_I2CCST3 reg fields */ 211 #define NPCM_I2CCST3_MATCHA8F BIT(0) 212 #define NPCM_I2CCST3_MATCHA9F BIT(1) 213 #define NPCM_I2CCST3_MATCHA10F BIT(2) 214 #define NPCM_I2CCST3_EO_BUSY BIT(7) 215 216 /* NPCM_I2CCTL4 reg fields */ 217 #define I2CCTL4_HLDT GENMASK(5, 0) 218 #define I2CCTL4_LVL_WE BIT(7) 219 220 /* NPCM_I2CCTL5 reg fields */ 221 #define I2CCTL5_DBNCT GENMASK(3, 0) 222 223 /* NPCM_I2CFIF_CTS reg fields */ 224 #define NPCM_I2CFIF_CTS_RXF_TXE BIT(1) 225 #define NPCM_I2CFIF_CTS_RFTE_IE BIT(3) 226 #define NPCM_I2CFIF_CTS_CLR_FIFO BIT(6) 227 #define NPCM_I2CFIF_CTS_SLVRSTR BIT(7) 228 229 /* NPCM_I2CTXF_CTL reg field */ 230 #define NPCM_I2CTXF_CTL_THR_TXIE BIT(6) 231 232 /* NPCM_I2CT_OUT reg fields */ 233 #define NPCM_I2CT_OUT_TO_CKDIV GENMASK(5, 0) 234 #define NPCM_I2CT_OUT_T_OUTIE BIT(6) 235 #define NPCM_I2CT_OUT_T_OUTST BIT(7) 236 237 /* NPCM_I2CTXF_STS reg fields */ 238 #define NPCM_I2CTXF_STS_TX_THST BIT(6) 239 240 /* NPCM_I2CRXF_STS reg fields */ 241 #define NPCM_I2CRXF_STS_RX_THST BIT(6) 242 243 /* NPCM_I2CFIF_CTL reg fields */ 244 #define NPCM_I2CFIF_CTL_FIFO_EN BIT(4) 245 246 /* NPCM_I2CRXF_CTL reg fields */ 247 #define NPCM_I2CRXF_CTL_THR_RXIE BIT(6) 248 249 #define MAX_I2C_HW_FIFO_SIZE 32 250 251 /* I2C_VER reg fields */ 252 #define I2C_VER_VERSION GENMASK(6, 0) 253 #define I2C_VER_FIFO_EN BIT(7) 254 255 /* stall/stuck timeout in us */ 256 #define DEFAULT_STALL_COUNT 25 257 258 /* SCLFRQ field position */ 259 #define SCLFRQ_0_TO_6 GENMASK(6, 0) 260 #define SCLFRQ_7_TO_8 GENMASK(8, 7) 261 262 /* supported clk settings. values in Hz. */ 263 #define I2C_FREQ_MIN_HZ 10000 264 #define I2C_FREQ_MAX_HZ I2C_MAX_FAST_MODE_PLUS_FREQ 265 266 struct npcm_i2c_data { 267 u8 fifo_size; 268 u32 segctl_init_val; 269 u8 txf_sts_tx_bytes; 270 u8 rxf_sts_rx_bytes; 271 u8 rxf_ctl_last_pec; 272 }; 273 274 static const struct npcm_i2c_data npxm7xx_i2c_data = { 275 .fifo_size = 16, 276 .segctl_init_val = 0x0333F000, 277 .txf_sts_tx_bytes = GENMASK(4, 0), 278 .rxf_sts_rx_bytes = GENMASK(4, 0), 279 .rxf_ctl_last_pec = BIT(5), 280 }; 281 282 static const struct npcm_i2c_data npxm8xx_i2c_data = { 283 .fifo_size = 32, 284 .segctl_init_val = 0x9333F000, 285 .txf_sts_tx_bytes = GENMASK(5, 0), 286 .rxf_sts_rx_bytes = GENMASK(5, 0), 287 .rxf_ctl_last_pec = BIT(7), 288 }; 289 290 /* Status of one I2C module */ 291 struct npcm_i2c { 292 struct i2c_adapter adap; 293 struct device *dev; 294 unsigned char __iomem *reg; 295 const struct npcm_i2c_data *data; 296 spinlock_t lock; /* IRQ synchronization */ 297 struct completion cmd_complete; 298 int cmd_err; 299 struct i2c_msg *msgs; 300 int msgs_num; 301 int num; 302 u32 apb_clk; 303 struct i2c_bus_recovery_info rinfo; 304 enum i2c_state state; 305 enum i2c_oper operation; 306 enum i2c_mode master_or_slave; 307 enum i2c_state_ind stop_ind; 308 u8 dest_addr; 309 u8 *rd_buf; 310 u16 rd_size; 311 u16 rd_ind; 312 u8 *wr_buf; 313 u16 wr_size; 314 u16 wr_ind; 315 bool fifo_use; 316 u16 PEC_mask; /* PEC bit mask per slave address */ 317 bool PEC_use; 318 bool read_block_use; 319 unsigned long int_time_stamp; 320 unsigned long bus_freq; /* in Hz */ 321 #if IS_ENABLED(CONFIG_I2C_SLAVE) 322 u8 own_slave_addr; 323 struct i2c_client *slave; 324 int slv_rd_size; 325 int slv_rd_ind; 326 int slv_wr_size; 327 int slv_wr_ind; 328 u8 slv_rd_buf[MAX_I2C_HW_FIFO_SIZE]; 329 u8 slv_wr_buf[MAX_I2C_HW_FIFO_SIZE]; 330 #endif 331 u64 ber_cnt; 332 u64 rec_succ_cnt; 333 u64 rec_fail_cnt; 334 u64 nack_cnt; 335 u64 timeout_cnt; 336 u64 tx_complete_cnt; 337 }; 338 339 static inline void npcm_i2c_select_bank(struct npcm_i2c *bus, 340 enum i2c_bank bank) 341 { 342 u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3); 343 344 if (bank == I2C_BANK_0) 345 i2cctl3 = i2cctl3 & ~I2CCTL3_BNK_SEL; 346 else 347 i2cctl3 = i2cctl3 | I2CCTL3_BNK_SEL; 348 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3); 349 } 350 351 static void npcm_i2c_init_params(struct npcm_i2c *bus) 352 { 353 bus->stop_ind = I2C_NO_STATUS_IND; 354 bus->rd_size = 0; 355 bus->wr_size = 0; 356 bus->rd_ind = 0; 357 bus->wr_ind = 0; 358 bus->read_block_use = false; 359 bus->int_time_stamp = 0; 360 bus->PEC_use = false; 361 bus->PEC_mask = 0; 362 #if IS_ENABLED(CONFIG_I2C_SLAVE) 363 if (bus->slave) 364 bus->master_or_slave = I2C_SLAVE; 365 #endif 366 } 367 368 static inline void npcm_i2c_wr_byte(struct npcm_i2c *bus, u8 data) 369 { 370 iowrite8(data, bus->reg + NPCM_I2CSDA); 371 } 372 373 static inline u8 npcm_i2c_rd_byte(struct npcm_i2c *bus) 374 { 375 return ioread8(bus->reg + NPCM_I2CSDA); 376 } 377 378 static int npcm_i2c_get_SCL(struct i2c_adapter *_adap) 379 { 380 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap); 381 382 return !!(I2CCTL3_SCL_LVL & ioread8(bus->reg + NPCM_I2CCTL3)); 383 } 384 385 static int npcm_i2c_get_SDA(struct i2c_adapter *_adap) 386 { 387 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap); 388 389 return !!(I2CCTL3_SDA_LVL & ioread8(bus->reg + NPCM_I2CCTL3)); 390 } 391 392 static inline u16 npcm_i2c_get_index(struct npcm_i2c *bus) 393 { 394 if (bus->operation == I2C_READ_OPER) 395 return bus->rd_ind; 396 if (bus->operation == I2C_WRITE_OPER) 397 return bus->wr_ind; 398 return 0; 399 } 400 401 /* quick protocol (just address) */ 402 static inline bool npcm_i2c_is_quick(struct npcm_i2c *bus) 403 { 404 return bus->wr_size == 0 && bus->rd_size == 0; 405 } 406 407 static void npcm_i2c_disable(struct npcm_i2c *bus) 408 { 409 u8 i2cctl2; 410 411 #if IS_ENABLED(CONFIG_I2C_SLAVE) 412 int i; 413 414 /* Slave addresses removal */ 415 for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++) 416 iowrite8(0, bus->reg + npcm_i2caddr[i]); 417 418 #endif 419 /* Disable module */ 420 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2); 421 i2cctl2 = i2cctl2 & ~I2CCTL2_ENABLE; 422 iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2); 423 424 bus->state = I2C_DISABLE; 425 } 426 427 static void npcm_i2c_enable(struct npcm_i2c *bus) 428 { 429 u8 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2); 430 431 i2cctl2 = i2cctl2 | I2CCTL2_ENABLE; 432 iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2); 433 bus->state = I2C_IDLE; 434 } 435 436 /* enable\disable end of busy (EOB) interrupts */ 437 static inline void npcm_i2c_eob_int(struct npcm_i2c *bus, bool enable) 438 { 439 u8 val; 440 441 /* Clear EO_BUSY pending bit: */ 442 val = ioread8(bus->reg + NPCM_I2CCST3); 443 val = val | NPCM_I2CCST3_EO_BUSY; 444 iowrite8(val, bus->reg + NPCM_I2CCST3); 445 446 val = ioread8(bus->reg + NPCM_I2CCTL1); 447 val &= ~NPCM_I2CCTL1_RWS; 448 if (enable) 449 val |= NPCM_I2CCTL1_EOBINTE; 450 else 451 val &= ~NPCM_I2CCTL1_EOBINTE; 452 iowrite8(val, bus->reg + NPCM_I2CCTL1); 453 } 454 455 static inline bool npcm_i2c_tx_fifo_empty(struct npcm_i2c *bus) 456 { 457 u8 tx_fifo_sts; 458 459 tx_fifo_sts = ioread8(bus->reg + NPCM_I2CTXF_STS); 460 /* check if TX FIFO is not empty */ 461 if ((tx_fifo_sts & bus->data->txf_sts_tx_bytes) == 0) 462 return false; 463 464 /* check if TX FIFO status bit is set: */ 465 return !!FIELD_GET(NPCM_I2CTXF_STS_TX_THST, tx_fifo_sts); 466 } 467 468 static inline bool npcm_i2c_rx_fifo_full(struct npcm_i2c *bus) 469 { 470 u8 rx_fifo_sts; 471 472 rx_fifo_sts = ioread8(bus->reg + NPCM_I2CRXF_STS); 473 /* check if RX FIFO is not empty: */ 474 if ((rx_fifo_sts & bus->data->rxf_sts_rx_bytes) == 0) 475 return false; 476 477 /* check if rx fifo full status is set: */ 478 return !!FIELD_GET(NPCM_I2CRXF_STS_RX_THST, rx_fifo_sts); 479 } 480 481 static inline void npcm_i2c_clear_fifo_int(struct npcm_i2c *bus) 482 { 483 u8 val; 484 485 val = ioread8(bus->reg + NPCM_I2CFIF_CTS); 486 val = (val & NPCM_I2CFIF_CTS_SLVRSTR) | NPCM_I2CFIF_CTS_RXF_TXE; 487 iowrite8(val, bus->reg + NPCM_I2CFIF_CTS); 488 } 489 490 static inline void npcm_i2c_clear_tx_fifo(struct npcm_i2c *bus) 491 { 492 u8 val; 493 494 val = ioread8(bus->reg + NPCM_I2CTXF_STS); 495 val = val | NPCM_I2CTXF_STS_TX_THST; 496 iowrite8(val, bus->reg + NPCM_I2CTXF_STS); 497 } 498 499 static inline void npcm_i2c_clear_rx_fifo(struct npcm_i2c *bus) 500 { 501 u8 val; 502 503 val = ioread8(bus->reg + NPCM_I2CRXF_STS); 504 val = val | NPCM_I2CRXF_STS_RX_THST; 505 iowrite8(val, bus->reg + NPCM_I2CRXF_STS); 506 } 507 508 static void npcm_i2c_int_enable(struct npcm_i2c *bus, bool enable) 509 { 510 u8 val; 511 512 val = ioread8(bus->reg + NPCM_I2CCTL1); 513 val &= ~NPCM_I2CCTL1_RWS; 514 if (enable) 515 val |= NPCM_I2CCTL1_INTEN; 516 else 517 val &= ~NPCM_I2CCTL1_INTEN; 518 iowrite8(val, bus->reg + NPCM_I2CCTL1); 519 } 520 521 static inline void npcm_i2c_master_start(struct npcm_i2c *bus) 522 { 523 u8 val; 524 525 val = ioread8(bus->reg + NPCM_I2CCTL1); 526 val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK); 527 val |= NPCM_I2CCTL1_START; 528 iowrite8(val, bus->reg + NPCM_I2CCTL1); 529 } 530 531 static inline void npcm_i2c_master_stop(struct npcm_i2c *bus) 532 { 533 u8 val; 534 535 /* 536 * override HW issue: I2C may fail to supply stop condition in Master 537 * Write operation. 538 * Need to delay at least 5 us from the last int, before issueing a stop 539 */ 540 udelay(10); /* function called from interrupt, can't sleep */ 541 val = ioread8(bus->reg + NPCM_I2CCTL1); 542 val &= ~(NPCM_I2CCTL1_START | NPCM_I2CCTL1_ACK); 543 val |= NPCM_I2CCTL1_STOP; 544 iowrite8(val, bus->reg + NPCM_I2CCTL1); 545 546 if (!bus->fifo_use) 547 return; 548 549 npcm_i2c_select_bank(bus, I2C_BANK_1); 550 551 if (bus->operation == I2C_READ_OPER) 552 npcm_i2c_clear_rx_fifo(bus); 553 else 554 npcm_i2c_clear_tx_fifo(bus); 555 npcm_i2c_clear_fifo_int(bus); 556 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); 557 } 558 559 static inline void npcm_i2c_stall_after_start(struct npcm_i2c *bus, bool stall) 560 { 561 u8 val; 562 563 val = ioread8(bus->reg + NPCM_I2CCTL1); 564 val &= ~NPCM_I2CCTL1_RWS; 565 if (stall) 566 val |= NPCM_I2CCTL1_STASTRE; 567 else 568 val &= ~NPCM_I2CCTL1_STASTRE; 569 iowrite8(val, bus->reg + NPCM_I2CCTL1); 570 } 571 572 static inline void npcm_i2c_nack(struct npcm_i2c *bus) 573 { 574 u8 val; 575 576 val = ioread8(bus->reg + NPCM_I2CCTL1); 577 val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_START); 578 val |= NPCM_I2CCTL1_ACK; 579 iowrite8(val, bus->reg + NPCM_I2CCTL1); 580 } 581 582 static inline void npcm_i2c_clear_master_status(struct npcm_i2c *bus) 583 { 584 u8 val; 585 586 /* Clear NEGACK, STASTR and BER bits */ 587 val = NPCM_I2CST_BER | NPCM_I2CST_NEGACK | NPCM_I2CST_STASTR; 588 iowrite8(val, bus->reg + NPCM_I2CST); 589 } 590 591 #if IS_ENABLED(CONFIG_I2C_SLAVE) 592 static void npcm_i2c_slave_int_enable(struct npcm_i2c *bus, bool enable) 593 { 594 u8 i2cctl1; 595 596 /* enable interrupt on slave match: */ 597 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1); 598 i2cctl1 &= ~NPCM_I2CCTL1_RWS; 599 if (enable) 600 i2cctl1 |= NPCM_I2CCTL1_NMINTE; 601 else 602 i2cctl1 &= ~NPCM_I2CCTL1_NMINTE; 603 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1); 604 } 605 606 static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type, 607 u8 addr, bool enable) 608 { 609 u8 i2cctl1; 610 u8 i2cctl3; 611 u8 sa_reg; 612 613 sa_reg = (addr & 0x7F) | FIELD_PREP(NPCM_I2CADDR_SAEN, enable); 614 if (addr_type == I2C_GC_ADDR) { 615 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1); 616 if (enable) 617 i2cctl1 |= NPCM_I2CCTL1_GCMEN; 618 else 619 i2cctl1 &= ~NPCM_I2CCTL1_GCMEN; 620 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1); 621 return 0; 622 } else if (addr_type == I2C_ARP_ADDR) { 623 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3); 624 if (enable) 625 i2cctl3 |= I2CCTL3_ARPMEN; 626 else 627 i2cctl3 &= ~I2CCTL3_ARPMEN; 628 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3); 629 return 0; 630 } 631 if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10) 632 dev_err(bus->dev, "try to enable more than 2 SA not supported\n"); 633 634 if (addr_type >= I2C_ARP_ADDR) 635 return -EFAULT; 636 637 /* Set and enable the address */ 638 iowrite8(sa_reg, bus->reg + npcm_i2caddr[addr_type]); 639 npcm_i2c_slave_int_enable(bus, enable); 640 641 return 0; 642 } 643 #endif 644 645 static void npcm_i2c_reset(struct npcm_i2c *bus) 646 { 647 /* 648 * Save I2CCTL1 relevant bits. It is being cleared when the module 649 * is disabled. 650 */ 651 u8 i2cctl1; 652 #if IS_ENABLED(CONFIG_I2C_SLAVE) 653 u8 addr; 654 #endif 655 656 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1); 657 658 npcm_i2c_disable(bus); 659 npcm_i2c_enable(bus); 660 661 /* Restore NPCM_I2CCTL1 Status */ 662 i2cctl1 &= ~NPCM_I2CCTL1_RWS; 663 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1); 664 665 /* Clear BB (BUS BUSY) bit */ 666 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST); 667 iowrite8(0xFF, bus->reg + NPCM_I2CST); 668 669 /* Clear and disable EOB */ 670 npcm_i2c_eob_int(bus, false); 671 672 /* Clear all fifo bits: */ 673 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS); 674 675 #if IS_ENABLED(CONFIG_I2C_SLAVE) 676 if (bus->slave) { 677 addr = bus->slave->addr; 678 npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, addr, true); 679 } 680 #endif 681 682 /* Clear status bits for spurious interrupts */ 683 npcm_i2c_clear_master_status(bus); 684 685 bus->state = I2C_IDLE; 686 } 687 688 static inline bool npcm_i2c_is_master(struct npcm_i2c *bus) 689 { 690 return !!FIELD_GET(NPCM_I2CST_MASTER, ioread8(bus->reg + NPCM_I2CST)); 691 } 692 693 static void npcm_i2c_callback(struct npcm_i2c *bus, 694 enum i2c_state_ind op_status, u16 info) 695 { 696 struct i2c_msg *msgs; 697 int msgs_num; 698 bool do_complete = false; 699 700 msgs = bus->msgs; 701 msgs_num = bus->msgs_num; 702 /* 703 * check that transaction was not timed-out, and msgs still 704 * holds a valid value. 705 */ 706 if (!msgs) 707 return; 708 709 if (completion_done(&bus->cmd_complete)) 710 return; 711 712 switch (op_status) { 713 case I2C_MASTER_DONE_IND: 714 bus->cmd_err = bus->msgs_num; 715 if (bus->tx_complete_cnt < ULLONG_MAX) 716 bus->tx_complete_cnt++; 717 fallthrough; 718 case I2C_BLOCK_BYTES_ERR_IND: 719 /* Master tx finished and all transmit bytes were sent */ 720 if (bus->msgs) { 721 if (msgs[0].flags & I2C_M_RD) 722 msgs[0].len = info; 723 else if (msgs_num == 2 && 724 msgs[1].flags & I2C_M_RD) 725 msgs[1].len = info; 726 } 727 do_complete = true; 728 break; 729 case I2C_NACK_IND: 730 /* MASTER transmit got a NACK before tx all bytes */ 731 bus->cmd_err = -ENXIO; 732 do_complete = true; 733 break; 734 case I2C_BUS_ERR_IND: 735 /* Bus error */ 736 bus->cmd_err = -EAGAIN; 737 do_complete = true; 738 break; 739 case I2C_WAKE_UP_IND: 740 /* I2C wake up */ 741 break; 742 default: 743 break; 744 } 745 746 bus->operation = I2C_NO_OPER; 747 #if IS_ENABLED(CONFIG_I2C_SLAVE) 748 if (bus->slave) 749 bus->master_or_slave = I2C_SLAVE; 750 #endif 751 if (do_complete) 752 complete(&bus->cmd_complete); 753 } 754 755 static u8 npcm_i2c_fifo_usage(struct npcm_i2c *bus) 756 { 757 if (bus->operation == I2C_WRITE_OPER) 758 return (bus->data->txf_sts_tx_bytes & 759 ioread8(bus->reg + NPCM_I2CTXF_STS)); 760 if (bus->operation == I2C_READ_OPER) 761 return (bus->data->rxf_sts_rx_bytes & 762 ioread8(bus->reg + NPCM_I2CRXF_STS)); 763 return 0; 764 } 765 766 static void npcm_i2c_write_to_fifo_master(struct npcm_i2c *bus, u16 max_bytes) 767 { 768 u8 size_free_fifo; 769 770 /* 771 * Fill the FIFO, while the FIFO is not full and there are more bytes 772 * to write 773 */ 774 size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus); 775 while (max_bytes-- && size_free_fifo) { 776 if (bus->wr_ind < bus->wr_size) 777 npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]); 778 else 779 npcm_i2c_wr_byte(bus, 0xFF); 780 size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus); 781 } 782 } 783 784 /* 785 * npcm_i2c_set_fifo: 786 * configure the FIFO before using it. If nread is -1 RX FIFO will not be 787 * configured. same for nwrite 788 */ 789 static void npcm_i2c_set_fifo(struct npcm_i2c *bus, int nread, int nwrite) 790 { 791 u8 rxf_ctl = 0; 792 793 if (!bus->fifo_use) 794 return; 795 npcm_i2c_select_bank(bus, I2C_BANK_1); 796 npcm_i2c_clear_tx_fifo(bus); 797 npcm_i2c_clear_rx_fifo(bus); 798 799 /* configure RX FIFO */ 800 if (nread > 0) { 801 rxf_ctl = min_t(int, nread, bus->data->fifo_size); 802 803 /* set LAST bit. if LAST is set next FIFO packet is nacked */ 804 if (nread <= bus->data->fifo_size) 805 rxf_ctl |= bus->data->rxf_ctl_last_pec; 806 807 /* 808 * if we are about to read the first byte in blk rd mode, 809 * don't NACK it. If slave returns zero size HW can't NACK 810 * it immediately, it will read extra byte and then NACK. 811 */ 812 if (bus->rd_ind == 0 && bus->read_block_use) { 813 /* set fifo to read one byte, no last: */ 814 rxf_ctl = 1; 815 } 816 817 /* set fifo size: */ 818 iowrite8(rxf_ctl, bus->reg + NPCM_I2CRXF_CTL); 819 } 820 821 /* configure TX FIFO */ 822 if (nwrite > 0) { 823 if (nwrite > bus->data->fifo_size) 824 /* data to send is more then FIFO size. */ 825 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CTXF_CTL); 826 else 827 iowrite8(nwrite, bus->reg + NPCM_I2CTXF_CTL); 828 829 npcm_i2c_clear_tx_fifo(bus); 830 } 831 } 832 833 static void npcm_i2c_read_fifo(struct npcm_i2c *bus, u8 bytes_in_fifo) 834 { 835 u8 data; 836 837 while (bytes_in_fifo--) { 838 data = npcm_i2c_rd_byte(bus); 839 if (bus->rd_ind < bus->rd_size) 840 bus->rd_buf[bus->rd_ind++] = data; 841 } 842 } 843 844 static void npcm_i2c_master_abort(struct npcm_i2c *bus) 845 { 846 /* Only current master is allowed to issue a stop condition */ 847 if (!npcm_i2c_is_master(bus)) 848 return; 849 850 npcm_i2c_eob_int(bus, true); 851 npcm_i2c_master_stop(bus); 852 npcm_i2c_clear_master_status(bus); 853 } 854 855 #if IS_ENABLED(CONFIG_I2C_SLAVE) 856 static u8 npcm_i2c_get_slave_addr(struct npcm_i2c *bus, enum i2c_addr addr_type) 857 { 858 u8 slave_add; 859 860 if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10) 861 dev_err(bus->dev, "get slave: try to use more than 2 SA not supported\n"); 862 863 slave_add = ioread8(bus->reg + npcm_i2caddr[(int)addr_type]); 864 865 return slave_add; 866 } 867 868 static int npcm_i2c_remove_slave_addr(struct npcm_i2c *bus, u8 slave_add) 869 { 870 int i; 871 872 /* Set the enable bit */ 873 slave_add |= 0x80; 874 875 for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++) { 876 if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add) 877 iowrite8(0, bus->reg + npcm_i2caddr[i]); 878 } 879 880 return 0; 881 } 882 883 static void npcm_i2c_write_fifo_slave(struct npcm_i2c *bus, u16 max_bytes) 884 { 885 /* 886 * Fill the FIFO, while the FIFO is not full and there are more bytes 887 * to write 888 */ 889 npcm_i2c_clear_fifo_int(bus); 890 npcm_i2c_clear_tx_fifo(bus); 891 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); 892 while (max_bytes-- && bus->data->fifo_size != npcm_i2c_fifo_usage(bus)) { 893 if (bus->slv_wr_size <= 0) 894 break; 895 bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1); 896 npcm_i2c_wr_byte(bus, bus->slv_wr_buf[bus->slv_wr_ind]); 897 bus->slv_wr_ind++; 898 bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1); 899 bus->slv_wr_size--; 900 } 901 } 902 903 static void npcm_i2c_read_fifo_slave(struct npcm_i2c *bus, u8 bytes_in_fifo) 904 { 905 u8 data; 906 907 if (!bus->slave) 908 return; 909 910 while (bytes_in_fifo--) { 911 data = npcm_i2c_rd_byte(bus); 912 913 bus->slv_rd_ind = bus->slv_rd_ind & (bus->data->fifo_size - 1); 914 bus->slv_rd_buf[bus->slv_rd_ind] = data; 915 bus->slv_rd_ind++; 916 917 /* 1st byte is length in block protocol: */ 918 if (bus->slv_rd_ind == 1 && bus->read_block_use) 919 bus->slv_rd_size = data + bus->PEC_use + 1; 920 } 921 } 922 923 static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus) 924 { 925 int i; 926 u8 value; 927 int ind; 928 int ret = bus->slv_wr_ind; 929 930 /* fill a cyclic buffer */ 931 for (i = 0; i < bus->data->fifo_size; i++) { 932 if (bus->slv_wr_size >= bus->data->fifo_size) 933 break; 934 if (bus->state == I2C_SLAVE_MATCH) { 935 i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value); 936 bus->state = I2C_OPER_STARTED; 937 } else { 938 i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value); 939 } 940 ind = (bus->slv_wr_ind + bus->slv_wr_size) & (bus->data->fifo_size - 1); 941 bus->slv_wr_buf[ind] = value; 942 bus->slv_wr_size++; 943 } 944 return bus->data->fifo_size - ret; 945 } 946 947 static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus) 948 { 949 int i; 950 951 for (i = 0; i < bus->slv_rd_ind; i++) 952 i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED, 953 &bus->slv_rd_buf[i]); 954 /* 955 * once we send bytes up, need to reset the counter of the wr buf 956 * got data from master (new offset in device), ignore wr fifo: 957 */ 958 if (bus->slv_rd_ind) { 959 bus->slv_wr_size = 0; 960 bus->slv_wr_ind = 0; 961 } 962 963 bus->slv_rd_ind = 0; 964 bus->slv_rd_size = bus->adap.quirks->max_read_len; 965 966 npcm_i2c_clear_fifo_int(bus); 967 npcm_i2c_clear_rx_fifo(bus); 968 } 969 970 static void npcm_i2c_slave_receive(struct npcm_i2c *bus, u16 nread, 971 u8 *read_data) 972 { 973 bus->state = I2C_OPER_STARTED; 974 bus->operation = I2C_READ_OPER; 975 bus->slv_rd_size = nread; 976 bus->slv_rd_ind = 0; 977 978 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); 979 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL); 980 npcm_i2c_clear_tx_fifo(bus); 981 npcm_i2c_clear_rx_fifo(bus); 982 } 983 984 static void npcm_i2c_slave_xmit(struct npcm_i2c *bus, u16 nwrite, 985 u8 *write_data) 986 { 987 if (nwrite == 0) 988 return; 989 990 bus->operation = I2C_WRITE_OPER; 991 992 /* get the next buffer */ 993 npcm_i2c_slave_get_wr_buf(bus); 994 npcm_i2c_write_fifo_slave(bus, nwrite); 995 } 996 997 /* 998 * npcm_i2c_slave_wr_buf_sync: 999 * currently slave IF only supports single byte operations. 1000 * in order to utilize the npcm HW FIFO, the driver will ask for 16 bytes 1001 * at a time, pack them in buffer, and then transmit them all together 1002 * to the FIFO and onward to the bus. 1003 * NACK on read will be once reached to bus->adap->quirks->max_read_len. 1004 * sending a NACK wherever the backend requests for it is not supported. 1005 * the next two functions allow reading to local buffer before writing it all 1006 * to the HW FIFO. 1007 */ 1008 static void npcm_i2c_slave_wr_buf_sync(struct npcm_i2c *bus) 1009 { 1010 int left_in_fifo; 1011 1012 left_in_fifo = bus->data->txf_sts_tx_bytes & 1013 ioread8(bus->reg + NPCM_I2CTXF_STS); 1014 1015 /* fifo already full: */ 1016 if (left_in_fifo >= bus->data->fifo_size || 1017 bus->slv_wr_size >= bus->data->fifo_size) 1018 return; 1019 1020 /* update the wr fifo index back to the untransmitted bytes: */ 1021 bus->slv_wr_ind = bus->slv_wr_ind - left_in_fifo; 1022 bus->slv_wr_size = bus->slv_wr_size + left_in_fifo; 1023 1024 if (bus->slv_wr_ind < 0) 1025 bus->slv_wr_ind += bus->data->fifo_size; 1026 } 1027 1028 static void npcm_i2c_slave_rd_wr(struct npcm_i2c *bus) 1029 { 1030 if (NPCM_I2CST_XMIT & ioread8(bus->reg + NPCM_I2CST)) { 1031 /* 1032 * Slave got an address match with direction bit 1 so it should 1033 * transmit data. Write till the master will NACK 1034 */ 1035 bus->operation = I2C_WRITE_OPER; 1036 npcm_i2c_slave_xmit(bus, bus->adap.quirks->max_write_len, 1037 bus->slv_wr_buf); 1038 } else { 1039 /* 1040 * Slave got an address match with direction bit 0 so it should 1041 * receive data. 1042 * this module does not support saying no to bytes. 1043 * it will always ACK. 1044 */ 1045 bus->operation = I2C_READ_OPER; 1046 npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus)); 1047 bus->stop_ind = I2C_SLAVE_RCV_IND; 1048 npcm_i2c_slave_send_rd_buf(bus); 1049 npcm_i2c_slave_receive(bus, bus->adap.quirks->max_read_len, 1050 bus->slv_rd_buf); 1051 } 1052 } 1053 1054 static irqreturn_t npcm_i2c_int_slave_handler(struct npcm_i2c *bus) 1055 { 1056 u8 val; 1057 irqreturn_t ret = IRQ_NONE; 1058 u8 i2cst = ioread8(bus->reg + NPCM_I2CST); 1059 1060 /* Slave: A NACK has occurred */ 1061 if (NPCM_I2CST_NEGACK & i2cst) { 1062 bus->stop_ind = I2C_NACK_IND; 1063 npcm_i2c_slave_wr_buf_sync(bus); 1064 if (bus->fifo_use) 1065 /* clear the FIFO */ 1066 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, 1067 bus->reg + NPCM_I2CFIF_CTS); 1068 1069 /* In slave write, NACK is OK, otherwise it is a problem */ 1070 bus->stop_ind = I2C_NO_STATUS_IND; 1071 bus->operation = I2C_NO_OPER; 1072 bus->own_slave_addr = 0xFF; 1073 1074 /* 1075 * Slave has to wait for STOP to decide this is the end 1076 * of the transaction. tx is not yet considered as done 1077 */ 1078 iowrite8(NPCM_I2CST_NEGACK, bus->reg + NPCM_I2CST); 1079 1080 ret = IRQ_HANDLED; 1081 } 1082 1083 /* Slave mode: a Bus Error (BER) has been identified */ 1084 if (NPCM_I2CST_BER & i2cst) { 1085 /* 1086 * Check whether bus arbitration or Start or Stop during data 1087 * xfer bus arbitration problem should not result in recovery 1088 */ 1089 bus->stop_ind = I2C_BUS_ERR_IND; 1090 1091 /* wait for bus busy before clear fifo */ 1092 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS); 1093 1094 bus->state = I2C_IDLE; 1095 1096 /* 1097 * in BER case we might get 2 interrupts: one for slave one for 1098 * master ( for a channel which is master\slave switching) 1099 */ 1100 if (completion_done(&bus->cmd_complete) == false) { 1101 bus->cmd_err = -EIO; 1102 complete(&bus->cmd_complete); 1103 } 1104 bus->own_slave_addr = 0xFF; 1105 iowrite8(NPCM_I2CST_BER, bus->reg + NPCM_I2CST); 1106 ret = IRQ_HANDLED; 1107 } 1108 1109 /* A Slave Stop Condition has been identified */ 1110 if (NPCM_I2CST_SLVSTP & i2cst) { 1111 u8 bytes_in_fifo = npcm_i2c_fifo_usage(bus); 1112 1113 bus->stop_ind = I2C_SLAVE_DONE_IND; 1114 1115 if (bus->operation == I2C_READ_OPER) 1116 npcm_i2c_read_fifo_slave(bus, bytes_in_fifo); 1117 1118 /* if the buffer is empty nothing will be sent */ 1119 npcm_i2c_slave_send_rd_buf(bus); 1120 1121 /* Slave done transmitting or receiving */ 1122 bus->stop_ind = I2C_NO_STATUS_IND; 1123 1124 /* 1125 * Note, just because we got here, it doesn't mean we through 1126 * away the wr buffer. 1127 * we keep it until the next received offset. 1128 */ 1129 bus->operation = I2C_NO_OPER; 1130 bus->own_slave_addr = 0xFF; 1131 i2c_slave_event(bus->slave, I2C_SLAVE_STOP, 0); 1132 iowrite8(NPCM_I2CST_SLVSTP, bus->reg + NPCM_I2CST); 1133 if (bus->fifo_use) { 1134 npcm_i2c_clear_fifo_int(bus); 1135 npcm_i2c_clear_rx_fifo(bus); 1136 npcm_i2c_clear_tx_fifo(bus); 1137 1138 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, 1139 bus->reg + NPCM_I2CFIF_CTS); 1140 } 1141 bus->state = I2C_IDLE; 1142 ret = IRQ_HANDLED; 1143 } 1144 1145 /* restart condition occurred and Rx-FIFO was not empty */ 1146 if (bus->fifo_use && FIELD_GET(NPCM_I2CFIF_CTS_SLVRSTR, 1147 ioread8(bus->reg + NPCM_I2CFIF_CTS))) { 1148 bus->stop_ind = I2C_SLAVE_RESTART_IND; 1149 bus->master_or_slave = I2C_SLAVE; 1150 if (bus->operation == I2C_READ_OPER) 1151 npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus)); 1152 bus->operation = I2C_WRITE_OPER; 1153 iowrite8(0, bus->reg + NPCM_I2CRXF_CTL); 1154 val = NPCM_I2CFIF_CTS_CLR_FIFO | NPCM_I2CFIF_CTS_SLVRSTR | 1155 NPCM_I2CFIF_CTS_RXF_TXE; 1156 iowrite8(val, bus->reg + NPCM_I2CFIF_CTS); 1157 npcm_i2c_slave_rd_wr(bus); 1158 ret = IRQ_HANDLED; 1159 } 1160 1161 /* A Slave Address Match has been identified */ 1162 if (NPCM_I2CST_NMATCH & i2cst) { 1163 u8 info = 0; 1164 1165 /* Address match automatically implies slave mode */ 1166 bus->master_or_slave = I2C_SLAVE; 1167 npcm_i2c_clear_fifo_int(bus); 1168 npcm_i2c_clear_rx_fifo(bus); 1169 npcm_i2c_clear_tx_fifo(bus); 1170 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); 1171 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL); 1172 if (NPCM_I2CST_XMIT & i2cst) { 1173 bus->operation = I2C_WRITE_OPER; 1174 } else { 1175 i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_REQUESTED, 1176 &info); 1177 bus->operation = I2C_READ_OPER; 1178 } 1179 if (bus->own_slave_addr == 0xFF) { 1180 /* Check which type of address match */ 1181 val = ioread8(bus->reg + NPCM_I2CCST); 1182 if (NPCM_I2CCST_MATCH & val) { 1183 u16 addr; 1184 enum i2c_addr eaddr; 1185 u8 i2ccst2; 1186 u8 i2ccst3; 1187 1188 i2ccst3 = ioread8(bus->reg + NPCM_I2CCST3); 1189 i2ccst2 = ioread8(bus->reg + NPCM_I2CCST2); 1190 1191 /* 1192 * the i2c module can response to 10 own SA. 1193 * check which one was addressed by the master. 1194 * respond to the first one. 1195 */ 1196 addr = ((i2ccst3 & 0x07) << 7) | 1197 (i2ccst2 & 0x7F); 1198 info = ffs(addr); 1199 eaddr = (enum i2c_addr)info; 1200 addr = npcm_i2c_get_slave_addr(bus, eaddr); 1201 addr &= 0x7F; 1202 bus->own_slave_addr = addr; 1203 if (bus->PEC_mask & BIT(info)) 1204 bus->PEC_use = true; 1205 else 1206 bus->PEC_use = false; 1207 } else { 1208 if (NPCM_I2CCST_GCMATCH & val) 1209 bus->own_slave_addr = 0; 1210 if (NPCM_I2CCST_ARPMATCH & val) 1211 bus->own_slave_addr = 0x61; 1212 } 1213 } else { 1214 /* 1215 * Slave match can happen in two options: 1216 * 1. Start, SA, read (slave read without further ado) 1217 * 2. Start, SA, read, data, restart, SA, read, ... 1218 * (slave read in fragmented mode) 1219 * 3. Start, SA, write, data, restart, SA, read, .. 1220 * (regular write-read mode) 1221 */ 1222 if ((bus->state == I2C_OPER_STARTED && 1223 bus->operation == I2C_READ_OPER && 1224 bus->stop_ind == I2C_SLAVE_XMIT_IND) || 1225 bus->stop_ind == I2C_SLAVE_RCV_IND) { 1226 /* slave tx after slave rx w/o STOP */ 1227 bus->stop_ind = I2C_SLAVE_RESTART_IND; 1228 } 1229 } 1230 1231 if (NPCM_I2CST_XMIT & i2cst) 1232 bus->stop_ind = I2C_SLAVE_XMIT_IND; 1233 else 1234 bus->stop_ind = I2C_SLAVE_RCV_IND; 1235 bus->state = I2C_SLAVE_MATCH; 1236 npcm_i2c_slave_rd_wr(bus); 1237 iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST); 1238 ret = IRQ_HANDLED; 1239 } 1240 1241 /* Slave SDA status is set - tx or rx */ 1242 if ((NPCM_I2CST_SDAST & i2cst) || 1243 (bus->fifo_use && 1244 (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) { 1245 npcm_i2c_slave_rd_wr(bus); 1246 iowrite8(NPCM_I2CST_SDAST, bus->reg + NPCM_I2CST); 1247 ret = IRQ_HANDLED; 1248 } /* SDAST */ 1249 1250 /* 1251 * If irq is not one of the above, make sure EOB is disabled and all 1252 * status bits are cleared. 1253 */ 1254 if (ret == IRQ_NONE) { 1255 npcm_i2c_eob_int(bus, false); 1256 npcm_i2c_clear_master_status(bus); 1257 } 1258 1259 return IRQ_HANDLED; 1260 } 1261 1262 static int npcm_i2c_reg_slave(struct i2c_client *client) 1263 { 1264 unsigned long lock_flags; 1265 struct npcm_i2c *bus = i2c_get_adapdata(client->adapter); 1266 1267 bus->slave = client; 1268 1269 if (client->flags & I2C_CLIENT_TEN) 1270 return -EAFNOSUPPORT; 1271 1272 spin_lock_irqsave(&bus->lock, lock_flags); 1273 1274 npcm_i2c_init_params(bus); 1275 bus->slv_rd_size = 0; 1276 bus->slv_wr_size = 0; 1277 bus->slv_rd_ind = 0; 1278 bus->slv_wr_ind = 0; 1279 if (client->flags & I2C_CLIENT_PEC) 1280 bus->PEC_use = true; 1281 1282 dev_info(bus->dev, "i2c%d register slave SA=0x%x, PEC=%d\n", bus->num, 1283 client->addr, bus->PEC_use); 1284 1285 npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, client->addr, true); 1286 npcm_i2c_clear_fifo_int(bus); 1287 npcm_i2c_clear_rx_fifo(bus); 1288 npcm_i2c_clear_tx_fifo(bus); 1289 npcm_i2c_slave_int_enable(bus, true); 1290 1291 spin_unlock_irqrestore(&bus->lock, lock_flags); 1292 return 0; 1293 } 1294 1295 static int npcm_i2c_unreg_slave(struct i2c_client *client) 1296 { 1297 struct npcm_i2c *bus = client->adapter->algo_data; 1298 unsigned long lock_flags; 1299 1300 spin_lock_irqsave(&bus->lock, lock_flags); 1301 if (!bus->slave) { 1302 spin_unlock_irqrestore(&bus->lock, lock_flags); 1303 return -EINVAL; 1304 } 1305 npcm_i2c_slave_int_enable(bus, false); 1306 npcm_i2c_remove_slave_addr(bus, client->addr); 1307 bus->slave = NULL; 1308 spin_unlock_irqrestore(&bus->lock, lock_flags); 1309 return 0; 1310 } 1311 #endif /* CONFIG_I2C_SLAVE */ 1312 1313 static void npcm_i2c_master_fifo_read(struct npcm_i2c *bus) 1314 { 1315 int rcount; 1316 int fifo_bytes; 1317 enum i2c_state_ind ind = I2C_MASTER_DONE_IND; 1318 1319 fifo_bytes = npcm_i2c_fifo_usage(bus); 1320 rcount = bus->rd_size - bus->rd_ind; 1321 1322 /* 1323 * In order not to change the RX_TRH during transaction (we found that 1324 * this might be problematic if it takes too much time to read the FIFO) 1325 * we read the data in the following way. If the number of bytes to 1326 * read == FIFO Size + C (where C < FIFO Size)then first read C bytes 1327 * and in the next int we read rest of the data. 1328 */ 1329 if (rcount < (2 * bus->data->fifo_size) && rcount > bus->data->fifo_size) 1330 fifo_bytes = rcount - bus->data->fifo_size; 1331 1332 if (rcount <= fifo_bytes) { 1333 /* last bytes are about to be read - end of tx */ 1334 bus->state = I2C_STOP_PENDING; 1335 bus->stop_ind = ind; 1336 npcm_i2c_eob_int(bus, true); 1337 /* Stop should be set before reading last byte. */ 1338 npcm_i2c_master_stop(bus); 1339 npcm_i2c_read_fifo(bus, fifo_bytes); 1340 } else { 1341 npcm_i2c_read_fifo(bus, fifo_bytes); 1342 rcount = bus->rd_size - bus->rd_ind; 1343 npcm_i2c_set_fifo(bus, rcount, -1); 1344 } 1345 } 1346 1347 static void npcm_i2c_irq_master_handler_write(struct npcm_i2c *bus) 1348 { 1349 u16 wcount; 1350 1351 if (bus->fifo_use) 1352 npcm_i2c_clear_tx_fifo(bus); /* clear the TX fifo status bit */ 1353 1354 /* Master write operation - last byte handling */ 1355 if (bus->wr_ind == bus->wr_size) { 1356 if (bus->fifo_use && npcm_i2c_fifo_usage(bus) > 0) 1357 /* 1358 * No more bytes to send (to add to the FIFO), 1359 * however the FIFO is not empty yet. It is 1360 * still in the middle of tx. Currently there's nothing 1361 * to do except for waiting to the end of the tx 1362 * We will get an int when the FIFO will get empty. 1363 */ 1364 return; 1365 1366 if (bus->rd_size == 0) { 1367 /* all bytes have been written, in wr only operation */ 1368 npcm_i2c_eob_int(bus, true); 1369 bus->state = I2C_STOP_PENDING; 1370 bus->stop_ind = I2C_MASTER_DONE_IND; 1371 npcm_i2c_master_stop(bus); 1372 /* Clear SDA Status bit (by writing dummy byte) */ 1373 npcm_i2c_wr_byte(bus, 0xFF); 1374 1375 } else { 1376 /* last write-byte written on previous int - restart */ 1377 npcm_i2c_set_fifo(bus, bus->rd_size, -1); 1378 /* Generate repeated start upon next write to SDA */ 1379 npcm_i2c_master_start(bus); 1380 1381 /* 1382 * Receiving one byte only - stall after successful 1383 * completion of send address byte. If we NACK here, and 1384 * slave doesn't ACK the address, we might 1385 * unintentionally NACK the next multi-byte read. 1386 */ 1387 if (bus->rd_size == 1) 1388 npcm_i2c_stall_after_start(bus, true); 1389 1390 /* Next int will occur on read */ 1391 bus->operation = I2C_READ_OPER; 1392 /* send the slave address in read direction */ 1393 npcm_i2c_wr_byte(bus, bus->dest_addr | 0x1); 1394 } 1395 } else { 1396 /* write next byte not last byte and not slave address */ 1397 if (!bus->fifo_use || bus->wr_size == 1) { 1398 npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]); 1399 } else { 1400 wcount = bus->wr_size - bus->wr_ind; 1401 npcm_i2c_set_fifo(bus, -1, wcount); 1402 if (wcount) 1403 npcm_i2c_write_to_fifo_master(bus, wcount); 1404 } 1405 } 1406 } 1407 1408 static void npcm_i2c_irq_master_handler_read(struct npcm_i2c *bus) 1409 { 1410 u16 block_extra_bytes_size; 1411 u8 data; 1412 1413 /* added bytes to the packet: */ 1414 block_extra_bytes_size = bus->read_block_use + bus->PEC_use; 1415 1416 /* 1417 * Perform master read, distinguishing between last byte and the rest of 1418 * the bytes. The last byte should be read when the clock is stopped 1419 */ 1420 if (bus->rd_ind == 0) { /* first byte handling: */ 1421 if (bus->read_block_use) { 1422 /* first byte in block protocol is the size: */ 1423 data = npcm_i2c_rd_byte(bus); 1424 data = clamp_val(data, 1, I2C_SMBUS_BLOCK_MAX); 1425 bus->rd_size = data + block_extra_bytes_size; 1426 bus->rd_buf[bus->rd_ind++] = data; 1427 1428 /* clear RX FIFO interrupt status: */ 1429 if (bus->fifo_use) { 1430 data = ioread8(bus->reg + NPCM_I2CFIF_CTS); 1431 data = data | NPCM_I2CFIF_CTS_RXF_TXE; 1432 iowrite8(data, bus->reg + NPCM_I2CFIF_CTS); 1433 } 1434 1435 npcm_i2c_set_fifo(bus, bus->rd_size - 1, -1); 1436 npcm_i2c_stall_after_start(bus, false); 1437 } else { 1438 npcm_i2c_clear_tx_fifo(bus); 1439 npcm_i2c_master_fifo_read(bus); 1440 } 1441 } else { 1442 if (bus->rd_size == block_extra_bytes_size && 1443 bus->read_block_use) { 1444 bus->state = I2C_STOP_PENDING; 1445 bus->stop_ind = I2C_BLOCK_BYTES_ERR_IND; 1446 bus->cmd_err = -EIO; 1447 npcm_i2c_eob_int(bus, true); 1448 npcm_i2c_master_stop(bus); 1449 npcm_i2c_read_fifo(bus, npcm_i2c_fifo_usage(bus)); 1450 } else { 1451 npcm_i2c_master_fifo_read(bus); 1452 } 1453 } 1454 } 1455 1456 static void npcm_i2c_irq_handle_nmatch(struct npcm_i2c *bus) 1457 { 1458 iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST); 1459 npcm_i2c_nack(bus); 1460 bus->stop_ind = I2C_BUS_ERR_IND; 1461 npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus)); 1462 } 1463 1464 /* A NACK has occurred */ 1465 static void npcm_i2c_irq_handle_nack(struct npcm_i2c *bus) 1466 { 1467 u8 val; 1468 1469 if (bus->nack_cnt < ULLONG_MAX) 1470 bus->nack_cnt++; 1471 1472 if (bus->fifo_use) { 1473 /* 1474 * if there are still untransmitted bytes in TX FIFO 1475 * reduce them from wr_ind 1476 */ 1477 if (bus->operation == I2C_WRITE_OPER) 1478 bus->wr_ind -= npcm_i2c_fifo_usage(bus); 1479 1480 /* clear the FIFO */ 1481 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS); 1482 } 1483 1484 /* In master write operation, got unexpected NACK */ 1485 bus->stop_ind = I2C_NACK_IND; 1486 /* Only current master is allowed to issue Stop Condition */ 1487 if (npcm_i2c_is_master(bus)) { 1488 /* stopping in the middle */ 1489 npcm_i2c_eob_int(bus, false); 1490 npcm_i2c_master_stop(bus); 1491 1492 /* Clear SDA Status bit (by reading dummy byte) */ 1493 npcm_i2c_rd_byte(bus); 1494 1495 /* 1496 * The bus is released from stall only after the SW clears 1497 * NEGACK bit. Then a Stop condition is sent. 1498 */ 1499 npcm_i2c_clear_master_status(bus); 1500 readx_poll_timeout_atomic(ioread8, bus->reg + NPCM_I2CCST, val, 1501 !(val & NPCM_I2CCST_BUSY), 10, 200); 1502 /* Verify no status bits are still set after bus is released */ 1503 npcm_i2c_clear_master_status(bus); 1504 } 1505 bus->state = I2C_IDLE; 1506 1507 /* 1508 * In Master mode, NACK should be cleared only after STOP. 1509 * In such case, the bus is released from stall only after the 1510 * software clears NACK bit. Then a Stop condition is sent. 1511 */ 1512 npcm_i2c_callback(bus, bus->stop_ind, bus->wr_ind); 1513 } 1514 1515 /* Master mode: a Bus Error has been identified */ 1516 static void npcm_i2c_irq_handle_ber(struct npcm_i2c *bus) 1517 { 1518 if (bus->ber_cnt < ULLONG_MAX) 1519 bus->ber_cnt++; 1520 bus->stop_ind = I2C_BUS_ERR_IND; 1521 if (npcm_i2c_is_master(bus)) { 1522 npcm_i2c_master_abort(bus); 1523 } else { 1524 npcm_i2c_clear_master_status(bus); 1525 1526 /* Clear BB (BUS BUSY) bit */ 1527 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST); 1528 1529 bus->cmd_err = -EAGAIN; 1530 npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus)); 1531 } 1532 bus->state = I2C_IDLE; 1533 } 1534 1535 /* EOB: a master End Of Busy (meaning STOP completed) */ 1536 static void npcm_i2c_irq_handle_eob(struct npcm_i2c *bus) 1537 { 1538 npcm_i2c_eob_int(bus, false); 1539 bus->state = I2C_IDLE; 1540 npcm_i2c_callback(bus, bus->stop_ind, bus->rd_ind); 1541 } 1542 1543 /* Address sent and requested stall occurred (Master mode) */ 1544 static void npcm_i2c_irq_handle_stall_after_start(struct npcm_i2c *bus) 1545 { 1546 if (npcm_i2c_is_quick(bus)) { 1547 bus->state = I2C_STOP_PENDING; 1548 bus->stop_ind = I2C_MASTER_DONE_IND; 1549 npcm_i2c_eob_int(bus, true); 1550 npcm_i2c_master_stop(bus); 1551 } else if ((bus->rd_size == 1) && !bus->read_block_use) { 1552 /* 1553 * Receiving one byte only - set NACK after ensuring 1554 * slave ACKed the address byte. 1555 */ 1556 npcm_i2c_nack(bus); 1557 } 1558 1559 /* Reset stall-after-address-byte */ 1560 npcm_i2c_stall_after_start(bus, false); 1561 1562 /* Clear stall only after setting STOP */ 1563 iowrite8(NPCM_I2CST_STASTR, bus->reg + NPCM_I2CST); 1564 } 1565 1566 /* SDA status is set - TX or RX, master */ 1567 static void npcm_i2c_irq_handle_sda(struct npcm_i2c *bus, u8 i2cst) 1568 { 1569 u8 fif_cts; 1570 1571 if (!npcm_i2c_is_master(bus)) 1572 return; 1573 1574 if (bus->state == I2C_IDLE) { 1575 bus->stop_ind = I2C_WAKE_UP_IND; 1576 1577 if (npcm_i2c_is_quick(bus) || bus->read_block_use) 1578 /* 1579 * Need to stall after successful 1580 * completion of sending address byte 1581 */ 1582 npcm_i2c_stall_after_start(bus, true); 1583 else 1584 npcm_i2c_stall_after_start(bus, false); 1585 1586 /* 1587 * Receiving one byte only - stall after successful completion 1588 * of sending address byte If we NACK here, and slave doesn't 1589 * ACK the address, we might unintentionally NACK the next 1590 * multi-byte read 1591 */ 1592 if (bus->wr_size == 0 && bus->rd_size == 1) 1593 npcm_i2c_stall_after_start(bus, true); 1594 1595 /* Initiate I2C master tx */ 1596 1597 /* select bank 1 for FIFO regs */ 1598 npcm_i2c_select_bank(bus, I2C_BANK_1); 1599 1600 fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS); 1601 fif_cts = fif_cts & ~NPCM_I2CFIF_CTS_SLVRSTR; 1602 1603 /* clear FIFO and relevant status bits. */ 1604 fif_cts = fif_cts | NPCM_I2CFIF_CTS_CLR_FIFO; 1605 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS); 1606 1607 /* re-enable */ 1608 fif_cts = fif_cts | NPCM_I2CFIF_CTS_RXF_TXE; 1609 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS); 1610 1611 /* 1612 * Configure the FIFO threshold: 1613 * according to the needed # of bytes to read. 1614 * Note: due to HW limitation can't config the rx fifo before it 1615 * got and ACK on the restart. LAST bit will not be reset unless 1616 * RX completed. It will stay set on the next tx. 1617 */ 1618 if (bus->wr_size) 1619 npcm_i2c_set_fifo(bus, -1, bus->wr_size); 1620 else 1621 npcm_i2c_set_fifo(bus, bus->rd_size, -1); 1622 1623 bus->state = I2C_OPER_STARTED; 1624 1625 if (npcm_i2c_is_quick(bus) || bus->wr_size) 1626 npcm_i2c_wr_byte(bus, bus->dest_addr); 1627 else 1628 npcm_i2c_wr_byte(bus, bus->dest_addr | BIT(0)); 1629 /* SDA interrupt, after start\restart */ 1630 } else { 1631 if (NPCM_I2CST_XMIT & i2cst) { 1632 bus->operation = I2C_WRITE_OPER; 1633 npcm_i2c_irq_master_handler_write(bus); 1634 } else { 1635 bus->operation = I2C_READ_OPER; 1636 npcm_i2c_irq_master_handler_read(bus); 1637 } 1638 } 1639 } 1640 1641 static int npcm_i2c_int_master_handler(struct npcm_i2c *bus) 1642 { 1643 u8 i2cst; 1644 int ret = -EIO; 1645 1646 i2cst = ioread8(bus->reg + NPCM_I2CST); 1647 1648 if (FIELD_GET(NPCM_I2CST_NMATCH, i2cst)) { 1649 npcm_i2c_irq_handle_nmatch(bus); 1650 return 0; 1651 } 1652 /* A NACK has occurred */ 1653 if (FIELD_GET(NPCM_I2CST_NEGACK, i2cst)) { 1654 npcm_i2c_irq_handle_nack(bus); 1655 return 0; 1656 } 1657 1658 /* Master mode: a Bus Error has been identified */ 1659 if (FIELD_GET(NPCM_I2CST_BER, i2cst)) { 1660 npcm_i2c_irq_handle_ber(bus); 1661 return 0; 1662 } 1663 1664 /* EOB: a master End Of Busy (meaning STOP completed) */ 1665 if ((FIELD_GET(NPCM_I2CCTL1_EOBINTE, 1666 ioread8(bus->reg + NPCM_I2CCTL1)) == 1) && 1667 (FIELD_GET(NPCM_I2CCST3_EO_BUSY, 1668 ioread8(bus->reg + NPCM_I2CCST3)))) { 1669 npcm_i2c_irq_handle_eob(bus); 1670 return 0; 1671 } 1672 1673 /* Address sent and requested stall occurred (Master mode) */ 1674 if (FIELD_GET(NPCM_I2CST_STASTR, i2cst)) { 1675 npcm_i2c_irq_handle_stall_after_start(bus); 1676 ret = 0; 1677 } 1678 1679 /* SDA status is set - TX or RX, master */ 1680 if (FIELD_GET(NPCM_I2CST_SDAST, i2cst) || 1681 (bus->fifo_use && 1682 (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) { 1683 npcm_i2c_irq_handle_sda(bus, i2cst); 1684 ret = 0; 1685 } 1686 1687 return ret; 1688 } 1689 1690 /* recovery using TGCLK functionality of the module */ 1691 static int npcm_i2c_recovery_tgclk(struct i2c_adapter *_adap) 1692 { 1693 u8 val; 1694 u8 fif_cts; 1695 bool done = false; 1696 int status = -ENOTRECOVERABLE; 1697 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap); 1698 /* Allow 3 bytes (27 toggles) to be read from the slave: */ 1699 int iter = 27; 1700 1701 if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1)) { 1702 dev_dbg(bus->dev, "bus%d-0x%x recovery skipped, bus not stuck", 1703 bus->num, bus->dest_addr); 1704 npcm_i2c_reset(bus); 1705 return 0; 1706 } 1707 1708 npcm_i2c_int_enable(bus, false); 1709 npcm_i2c_disable(bus); 1710 npcm_i2c_enable(bus); 1711 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST); 1712 npcm_i2c_clear_tx_fifo(bus); 1713 npcm_i2c_clear_rx_fifo(bus); 1714 iowrite8(0, bus->reg + NPCM_I2CRXF_CTL); 1715 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); 1716 npcm_i2c_stall_after_start(bus, false); 1717 1718 /* select bank 1 for FIFO regs */ 1719 npcm_i2c_select_bank(bus, I2C_BANK_1); 1720 1721 /* clear FIFO and relevant status bits. */ 1722 fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS); 1723 fif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR; 1724 fif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO; 1725 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS); 1726 npcm_i2c_set_fifo(bus, -1, 0); 1727 1728 /* Repeat the following sequence until SDA is released */ 1729 do { 1730 /* Issue a single SCL toggle */ 1731 iowrite8(NPCM_I2CCST_TGSCL, bus->reg + NPCM_I2CCST); 1732 usleep_range(20, 30); 1733 /* If SDA line is inactive (high), stop */ 1734 if (npcm_i2c_get_SDA(_adap)) { 1735 done = true; 1736 status = 0; 1737 } 1738 } while (!done && iter--); 1739 1740 /* If SDA line is released: send start-addr-stop, to re-sync. */ 1741 if (npcm_i2c_get_SDA(_adap)) { 1742 /* Send an address byte in write direction: */ 1743 npcm_i2c_wr_byte(bus, bus->dest_addr); 1744 npcm_i2c_master_start(bus); 1745 /* Wait until START condition is sent */ 1746 status = readx_poll_timeout(npcm_i2c_get_SCL, _adap, val, !val, 1747 20, 200); 1748 /* If START condition was sent */ 1749 if (npcm_i2c_is_master(bus) > 0) { 1750 usleep_range(20, 30); 1751 npcm_i2c_master_stop(bus); 1752 usleep_range(200, 500); 1753 } 1754 } 1755 npcm_i2c_reset(bus); 1756 npcm_i2c_int_enable(bus, true); 1757 1758 if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1)) 1759 status = 0; 1760 else 1761 status = -ENOTRECOVERABLE; 1762 if (status) { 1763 if (bus->rec_fail_cnt < ULLONG_MAX) 1764 bus->rec_fail_cnt++; 1765 } else { 1766 if (bus->rec_succ_cnt < ULLONG_MAX) 1767 bus->rec_succ_cnt++; 1768 } 1769 return status; 1770 } 1771 1772 /* recovery using bit banging functionality of the module */ 1773 static void npcm_i2c_recovery_init(struct i2c_adapter *_adap) 1774 { 1775 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap); 1776 struct i2c_bus_recovery_info *rinfo = &bus->rinfo; 1777 1778 rinfo->recover_bus = npcm_i2c_recovery_tgclk; 1779 1780 /* 1781 * npcm i2c HW allows direct reading of SCL and SDA. 1782 * However, it does not support setting SCL and SDA directly. 1783 * The recovery function can toggle SCL when SDA is low (but not set) 1784 * Getter functions used internally, and can be used externally. 1785 */ 1786 rinfo->get_scl = npcm_i2c_get_SCL; 1787 rinfo->get_sda = npcm_i2c_get_SDA; 1788 _adap->bus_recovery_info = rinfo; 1789 } 1790 1791 /* SCLFRQ min/max field values */ 1792 #define SCLFRQ_MIN 10 1793 #define SCLFRQ_MAX 511 1794 #define clk_coef(freq, mul) DIV_ROUND_UP((freq) * (mul), 1000000) 1795 1796 /* 1797 * npcm_i2c_init_clk: init HW timing parameters. 1798 * NPCM7XX i2c module timing parameters are dependent on module core clk (APB) 1799 * and bus frequency. 1800 * 100kHz bus requires tSCL = 4 * SCLFRQ * tCLK. LT and HT are symmetric. 1801 * 400kHz bus requires asymmetric HT and LT. A different equation is recommended 1802 * by the HW designer, given core clock range (equations in comments below). 1803 * 1804 */ 1805 static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz) 1806 { 1807 u32 k1 = 0; 1808 u32 k2 = 0; 1809 u8 dbnct = 0; 1810 u32 sclfrq = 0; 1811 u8 hldt = 7; 1812 u8 fast_mode = 0; 1813 u32 src_clk_khz; 1814 u32 bus_freq_khz; 1815 1816 src_clk_khz = bus->apb_clk / 1000; 1817 bus_freq_khz = bus_freq_hz / 1000; 1818 bus->bus_freq = bus_freq_hz; 1819 1820 /* 100KHz and below: */ 1821 if (bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) { 1822 sclfrq = src_clk_khz / (bus_freq_khz * 4); 1823 1824 if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX) 1825 return -EDOM; 1826 1827 if (src_clk_khz >= 40000) 1828 hldt = 17; 1829 else if (src_clk_khz >= 12500) 1830 hldt = 15; 1831 else 1832 hldt = 7; 1833 } 1834 1835 /* 400KHz: */ 1836 else if (bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) { 1837 sclfrq = 0; 1838 fast_mode = I2CCTL3_400K_MODE; 1839 1840 if (src_clk_khz < 7500) 1841 /* 400KHZ cannot be supported for core clock < 7.5MHz */ 1842 return -EDOM; 1843 1844 else if (src_clk_khz >= 50000) { 1845 k1 = 80; 1846 k2 = 48; 1847 hldt = 12; 1848 dbnct = 7; 1849 } 1850 1851 /* Master or Slave with frequency > 25MHz */ 1852 else if (src_clk_khz > 25000) { 1853 hldt = clk_coef(src_clk_khz, 300) + 7; 1854 k1 = clk_coef(src_clk_khz, 1600); 1855 k2 = clk_coef(src_clk_khz, 900); 1856 } 1857 } 1858 1859 /* 1MHz: */ 1860 else if (bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) { 1861 sclfrq = 0; 1862 fast_mode = I2CCTL3_400K_MODE; 1863 1864 /* 1MHZ cannot be supported for core clock < 24 MHz */ 1865 if (src_clk_khz < 24000) 1866 return -EDOM; 1867 1868 k1 = clk_coef(src_clk_khz, 620); 1869 k2 = clk_coef(src_clk_khz, 380); 1870 1871 /* Core clk > 40 MHz */ 1872 if (src_clk_khz > 40000) { 1873 /* 1874 * Set HLDT: 1875 * SDA hold time: (HLDT-7) * T(CLK) >= 120 1876 * HLDT = 120/T(CLK) + 7 = 120 * FREQ(CLK) + 7 1877 */ 1878 hldt = clk_coef(src_clk_khz, 120) + 7; 1879 } else { 1880 hldt = 7; 1881 dbnct = 2; 1882 } 1883 } 1884 1885 /* Frequency larger than 1 MHz is not supported */ 1886 else 1887 return -EINVAL; 1888 1889 if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) { 1890 k1 = round_up(k1, 2); 1891 k2 = round_up(k2 + 1, 2); 1892 if (k1 < SCLFRQ_MIN || k1 > SCLFRQ_MAX || 1893 k2 < SCLFRQ_MIN || k2 > SCLFRQ_MAX) 1894 return -EDOM; 1895 } 1896 1897 /* write sclfrq value. bits [6:0] are in I2CCTL2 reg */ 1898 iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, sclfrq & 0x7F), 1899 bus->reg + NPCM_I2CCTL2); 1900 1901 /* bits [8:7] are in I2CCTL3 reg */ 1902 iowrite8(fast_mode | FIELD_PREP(I2CCTL3_SCLFRQ8_7, (sclfrq >> 7) & 0x3), 1903 bus->reg + NPCM_I2CCTL3); 1904 1905 /* Select Bank 0 to access NPCM_I2CCTL4/NPCM_I2CCTL5 */ 1906 npcm_i2c_select_bank(bus, I2C_BANK_0); 1907 1908 if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) { 1909 /* 1910 * Set SCL Low/High Time: 1911 * k1 = 2 * SCLLT7-0 -> Low Time = k1 / 2 1912 * k2 = 2 * SCLLT7-0 -> High Time = k2 / 2 1913 */ 1914 iowrite8(k1 / 2, bus->reg + NPCM_I2CSCLLT); 1915 iowrite8(k2 / 2, bus->reg + NPCM_I2CSCLHT); 1916 1917 iowrite8(dbnct, bus->reg + NPCM_I2CCTL5); 1918 } 1919 1920 iowrite8(hldt, bus->reg + NPCM_I2CCTL4); 1921 1922 /* Return to Bank 1, and stay there by default: */ 1923 npcm_i2c_select_bank(bus, I2C_BANK_1); 1924 1925 return 0; 1926 } 1927 1928 static int npcm_i2c_init_module(struct npcm_i2c *bus, enum i2c_mode mode, 1929 u32 bus_freq_hz) 1930 { 1931 u8 val; 1932 int ret; 1933 1934 /* Check whether module already enabled or frequency is out of bounds */ 1935 if ((bus->state != I2C_DISABLE && bus->state != I2C_IDLE) || 1936 bus_freq_hz < I2C_FREQ_MIN_HZ || bus_freq_hz > I2C_FREQ_MAX_HZ) 1937 return -EINVAL; 1938 1939 npcm_i2c_int_enable(bus, false); 1940 npcm_i2c_disable(bus); 1941 1942 /* Configure FIFO mode : */ 1943 if (FIELD_GET(I2C_VER_FIFO_EN, ioread8(bus->reg + I2C_VER))) { 1944 bus->fifo_use = true; 1945 npcm_i2c_select_bank(bus, I2C_BANK_0); 1946 val = ioread8(bus->reg + NPCM_I2CFIF_CTL); 1947 val |= NPCM_I2CFIF_CTL_FIFO_EN; 1948 iowrite8(val, bus->reg + NPCM_I2CFIF_CTL); 1949 npcm_i2c_select_bank(bus, I2C_BANK_1); 1950 } else { 1951 bus->fifo_use = false; 1952 } 1953 1954 /* Configure I2C module clock frequency */ 1955 ret = npcm_i2c_init_clk(bus, bus_freq_hz); 1956 if (ret) { 1957 dev_err(bus->dev, "npcm_i2c_init_clk failed\n"); 1958 return ret; 1959 } 1960 1961 /* Enable module (before configuring CTL1) */ 1962 npcm_i2c_enable(bus); 1963 bus->state = I2C_IDLE; 1964 val = ioread8(bus->reg + NPCM_I2CCTL1); 1965 val = (val | NPCM_I2CCTL1_NMINTE) & ~NPCM_I2CCTL1_RWS; 1966 iowrite8(val, bus->reg + NPCM_I2CCTL1); 1967 1968 npcm_i2c_reset(bus); 1969 1970 /* Check HW is OK: SDA and SCL should be high at this point. */ 1971 if ((npcm_i2c_get_SDA(&bus->adap) == 0) || (npcm_i2c_get_SCL(&bus->adap) == 0)) { 1972 dev_err(bus->dev, "I2C%d init fail: lines are low\n", bus->num); 1973 dev_err(bus->dev, "SDA=%d SCL=%d\n", npcm_i2c_get_SDA(&bus->adap), 1974 npcm_i2c_get_SCL(&bus->adap)); 1975 return -ENXIO; 1976 } 1977 1978 npcm_i2c_int_enable(bus, true); 1979 return 0; 1980 } 1981 1982 static int __npcm_i2c_init(struct npcm_i2c *bus, struct platform_device *pdev) 1983 { 1984 u32 clk_freq_hz; 1985 int ret; 1986 1987 /* Initialize the internal data structures */ 1988 bus->state = I2C_DISABLE; 1989 bus->master_or_slave = I2C_SLAVE; 1990 bus->int_time_stamp = 0; 1991 #if IS_ENABLED(CONFIG_I2C_SLAVE) 1992 bus->slave = NULL; 1993 #endif 1994 1995 ret = device_property_read_u32(&pdev->dev, "clock-frequency", 1996 &clk_freq_hz); 1997 if (ret) { 1998 dev_info(&pdev->dev, "Could not read clock-frequency property"); 1999 clk_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; 2000 } 2001 2002 ret = npcm_i2c_init_module(bus, I2C_MASTER, clk_freq_hz); 2003 if (ret) { 2004 dev_err(&pdev->dev, "npcm_i2c_init_module failed\n"); 2005 return ret; 2006 } 2007 2008 return 0; 2009 } 2010 2011 static irqreturn_t npcm_i2c_bus_irq(int irq, void *dev_id) 2012 { 2013 struct npcm_i2c *bus = dev_id; 2014 2015 if (npcm_i2c_is_master(bus)) 2016 bus->master_or_slave = I2C_MASTER; 2017 2018 if (bus->master_or_slave == I2C_MASTER) { 2019 bus->int_time_stamp = jiffies; 2020 if (!npcm_i2c_int_master_handler(bus)) 2021 return IRQ_HANDLED; 2022 } 2023 #if IS_ENABLED(CONFIG_I2C_SLAVE) 2024 if (bus->slave) { 2025 bus->master_or_slave = I2C_SLAVE; 2026 if (npcm_i2c_int_slave_handler(bus)) 2027 return IRQ_HANDLED; 2028 } 2029 #endif 2030 /* Clear status bits for spurious interrupts */ 2031 npcm_i2c_clear_master_status(bus); 2032 2033 return IRQ_HANDLED; 2034 } 2035 2036 static bool npcm_i2c_master_start_xmit(struct npcm_i2c *bus, 2037 u8 slave_addr, u16 nwrite, u16 nread, 2038 u8 *write_data, u8 *read_data, 2039 bool use_PEC, bool use_read_block) 2040 { 2041 if (bus->state != I2C_IDLE) { 2042 bus->cmd_err = -EBUSY; 2043 return false; 2044 } 2045 bus->dest_addr = slave_addr << 1; 2046 bus->wr_buf = write_data; 2047 bus->wr_size = nwrite; 2048 bus->wr_ind = 0; 2049 bus->rd_buf = read_data; 2050 bus->rd_size = nread; 2051 bus->rd_ind = 0; 2052 bus->PEC_use = 0; 2053 2054 /* for tx PEC is appended to buffer from i2c IF. PEC flag is ignored */ 2055 if (nread) 2056 bus->PEC_use = use_PEC; 2057 2058 bus->read_block_use = use_read_block; 2059 if (nread && !nwrite) 2060 bus->operation = I2C_READ_OPER; 2061 else 2062 bus->operation = I2C_WRITE_OPER; 2063 if (bus->fifo_use) { 2064 u8 i2cfif_cts; 2065 2066 npcm_i2c_select_bank(bus, I2C_BANK_1); 2067 /* clear FIFO and relevant status bits. */ 2068 i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS); 2069 i2cfif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR; 2070 i2cfif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO; 2071 iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS); 2072 } 2073 2074 bus->state = I2C_IDLE; 2075 npcm_i2c_stall_after_start(bus, true); 2076 npcm_i2c_master_start(bus); 2077 return true; 2078 } 2079 2080 static int npcm_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 2081 int num) 2082 { 2083 struct npcm_i2c *bus = container_of(adap, struct npcm_i2c, adap); 2084 struct i2c_msg *msg0, *msg1; 2085 unsigned long time_left, flags; 2086 u16 nwrite, nread; 2087 u8 *write_data, *read_data; 2088 u8 slave_addr; 2089 unsigned long timeout; 2090 bool read_block = false; 2091 bool read_PEC = false; 2092 u8 bus_busy; 2093 unsigned long timeout_usec; 2094 2095 if (bus->state == I2C_DISABLE) { 2096 dev_err(bus->dev, "I2C%d module is disabled", bus->num); 2097 return -EINVAL; 2098 } 2099 2100 msg0 = &msgs[0]; 2101 slave_addr = msg0->addr; 2102 if (msg0->flags & I2C_M_RD) { /* read */ 2103 nwrite = 0; 2104 write_data = NULL; 2105 read_data = msg0->buf; 2106 if (msg0->flags & I2C_M_RECV_LEN) { 2107 nread = 1; 2108 read_block = true; 2109 if (msg0->flags & I2C_CLIENT_PEC) 2110 read_PEC = true; 2111 } else { 2112 nread = msg0->len; 2113 } 2114 } else { /* write */ 2115 nwrite = msg0->len; 2116 write_data = msg0->buf; 2117 nread = 0; 2118 read_data = NULL; 2119 if (num == 2) { 2120 msg1 = &msgs[1]; 2121 read_data = msg1->buf; 2122 if (msg1->flags & I2C_M_RECV_LEN) { 2123 nread = 1; 2124 read_block = true; 2125 if (msg1->flags & I2C_CLIENT_PEC) 2126 read_PEC = true; 2127 } else { 2128 nread = msg1->len; 2129 read_block = false; 2130 } 2131 } 2132 } 2133 2134 /* 2135 * Adaptive TimeOut: estimated time in usec + 100% margin: 2136 * 2: double the timeout for clock stretching case 2137 * 9: bits per transaction (including the ack/nack) 2138 */ 2139 timeout_usec = (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + nwrite); 2140 timeout = max_t(unsigned long, bus->adap.timeout, usecs_to_jiffies(timeout_usec)); 2141 if (nwrite >= 32 * 1024 || nread >= 32 * 1024) { 2142 dev_err(bus->dev, "i2c%d buffer too big\n", bus->num); 2143 return -EINVAL; 2144 } 2145 2146 time_left = jiffies + timeout + 1; 2147 do { 2148 /* 2149 * we must clear slave address immediately when the bus is not 2150 * busy, so we spinlock it, but we don't keep the lock for the 2151 * entire while since it is too long. 2152 */ 2153 spin_lock_irqsave(&bus->lock, flags); 2154 bus_busy = ioread8(bus->reg + NPCM_I2CCST) & NPCM_I2CCST_BB; 2155 #if IS_ENABLED(CONFIG_I2C_SLAVE) 2156 if (!bus_busy && bus->slave) 2157 iowrite8((bus->slave->addr & 0x7F), 2158 bus->reg + NPCM_I2CADDR1); 2159 #endif 2160 spin_unlock_irqrestore(&bus->lock, flags); 2161 2162 } while (time_is_after_jiffies(time_left) && bus_busy); 2163 2164 if (bus_busy) { 2165 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST); 2166 npcm_i2c_reset(bus); 2167 i2c_recover_bus(adap); 2168 return -EAGAIN; 2169 } 2170 2171 npcm_i2c_init_params(bus); 2172 bus->dest_addr = slave_addr; 2173 bus->msgs = msgs; 2174 bus->msgs_num = num; 2175 bus->cmd_err = 0; 2176 bus->read_block_use = read_block; 2177 2178 reinit_completion(&bus->cmd_complete); 2179 2180 npcm_i2c_int_enable(bus, true); 2181 2182 if (npcm_i2c_master_start_xmit(bus, slave_addr, nwrite, nread, 2183 write_data, read_data, read_PEC, 2184 read_block)) { 2185 time_left = wait_for_completion_timeout(&bus->cmd_complete, 2186 timeout); 2187 2188 if (time_left == 0) { 2189 if (bus->timeout_cnt < ULLONG_MAX) 2190 bus->timeout_cnt++; 2191 if (bus->master_or_slave == I2C_MASTER) { 2192 i2c_recover_bus(adap); 2193 bus->cmd_err = -EIO; 2194 bus->state = I2C_IDLE; 2195 } 2196 } 2197 } 2198 2199 /* if there was BER, check if need to recover the bus: */ 2200 if (bus->cmd_err == -EAGAIN) 2201 bus->cmd_err = i2c_recover_bus(adap); 2202 2203 /* 2204 * After any type of error, check if LAST bit is still set, 2205 * due to a HW issue. 2206 * It cannot be cleared without resetting the module. 2207 */ 2208 else if (bus->cmd_err && 2209 (bus->data->rxf_ctl_last_pec & ioread8(bus->reg + NPCM_I2CRXF_CTL))) 2210 npcm_i2c_reset(bus); 2211 2212 /* After any xfer, successful or not, stall and EOB must be disabled */ 2213 npcm_i2c_stall_after_start(bus, false); 2214 npcm_i2c_eob_int(bus, false); 2215 2216 #if IS_ENABLED(CONFIG_I2C_SLAVE) 2217 /* reenable slave if it was enabled */ 2218 if (bus->slave) 2219 iowrite8((bus->slave->addr & 0x7F) | NPCM_I2CADDR_SAEN, 2220 bus->reg + NPCM_I2CADDR1); 2221 #else 2222 npcm_i2c_int_enable(bus, false); 2223 #endif 2224 return bus->cmd_err; 2225 } 2226 2227 static u32 npcm_i2c_functionality(struct i2c_adapter *adap) 2228 { 2229 return I2C_FUNC_I2C | 2230 I2C_FUNC_SMBUS_EMUL | 2231 I2C_FUNC_SMBUS_BLOCK_DATA | 2232 I2C_FUNC_SMBUS_PEC | 2233 I2C_FUNC_SLAVE; 2234 } 2235 2236 static const struct i2c_adapter_quirks npcm_i2c_quirks = { 2237 .max_read_len = 32768, 2238 .max_write_len = 32768, 2239 .flags = I2C_AQ_COMB_WRITE_THEN_READ, 2240 }; 2241 2242 static const struct i2c_algorithm npcm_i2c_algo = { 2243 .master_xfer = npcm_i2c_master_xfer, 2244 .functionality = npcm_i2c_functionality, 2245 #if IS_ENABLED(CONFIG_I2C_SLAVE) 2246 .reg_slave = npcm_i2c_reg_slave, 2247 .unreg_slave = npcm_i2c_unreg_slave, 2248 #endif 2249 }; 2250 2251 static void npcm_i2c_init_debugfs(struct platform_device *pdev, 2252 struct npcm_i2c *bus) 2253 { 2254 debugfs_create_u64("ber_cnt", 0444, bus->adap.debugfs, &bus->ber_cnt); 2255 debugfs_create_u64("nack_cnt", 0444, bus->adap.debugfs, &bus->nack_cnt); 2256 debugfs_create_u64("rec_succ_cnt", 0444, bus->adap.debugfs, &bus->rec_succ_cnt); 2257 debugfs_create_u64("rec_fail_cnt", 0444, bus->adap.debugfs, &bus->rec_fail_cnt); 2258 debugfs_create_u64("timeout_cnt", 0444, bus->adap.debugfs, &bus->timeout_cnt); 2259 debugfs_create_u64("tx_complete_cnt", 0444, bus->adap.debugfs, &bus->tx_complete_cnt); 2260 } 2261 2262 static int npcm_i2c_probe_bus(struct platform_device *pdev) 2263 { 2264 struct device_node *np = pdev->dev.of_node; 2265 static struct regmap *gcr_regmap; 2266 struct device *dev = &pdev->dev; 2267 struct i2c_adapter *adap; 2268 struct npcm_i2c *bus; 2269 struct clk *i2c_clk; 2270 int irq; 2271 int ret; 2272 2273 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL); 2274 if (!bus) 2275 return -ENOMEM; 2276 2277 bus->dev = &pdev->dev; 2278 2279 bus->data = of_device_get_match_data(dev); 2280 if (!bus->data) { 2281 dev_err(dev, "OF data missing\n"); 2282 return -EINVAL; 2283 } 2284 2285 bus->num = of_alias_get_id(pdev->dev.of_node, "i2c"); 2286 /* core clk must be acquired to calculate module timing settings */ 2287 i2c_clk = devm_clk_get(&pdev->dev, NULL); 2288 if (IS_ERR(i2c_clk)) 2289 return PTR_ERR(i2c_clk); 2290 bus->apb_clk = clk_get_rate(i2c_clk); 2291 2292 gcr_regmap = syscon_regmap_lookup_by_phandle(np, "nuvoton,sys-mgr"); 2293 if (IS_ERR(gcr_regmap)) 2294 gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr"); 2295 2296 if (IS_ERR(gcr_regmap)) 2297 return PTR_ERR(gcr_regmap); 2298 regmap_write(gcr_regmap, NPCM_I2CSEGCTL, bus->data->segctl_init_val); 2299 2300 bus->reg = devm_platform_ioremap_resource(pdev, 0); 2301 if (IS_ERR(bus->reg)) 2302 return PTR_ERR(bus->reg); 2303 2304 spin_lock_init(&bus->lock); 2305 init_completion(&bus->cmd_complete); 2306 2307 adap = &bus->adap; 2308 adap->owner = THIS_MODULE; 2309 adap->retries = 3; 2310 adap->timeout = msecs_to_jiffies(35); 2311 adap->algo = &npcm_i2c_algo; 2312 adap->quirks = &npcm_i2c_quirks; 2313 adap->algo_data = bus; 2314 adap->dev.parent = &pdev->dev; 2315 adap->dev.of_node = pdev->dev.of_node; 2316 adap->nr = pdev->id; 2317 2318 irq = platform_get_irq(pdev, 0); 2319 if (irq < 0) 2320 return irq; 2321 2322 ret = devm_request_irq(bus->dev, irq, npcm_i2c_bus_irq, 0, 2323 dev_name(bus->dev), bus); 2324 if (ret) 2325 return ret; 2326 2327 ret = __npcm_i2c_init(bus, pdev); 2328 if (ret) 2329 return ret; 2330 2331 npcm_i2c_recovery_init(adap); 2332 2333 i2c_set_adapdata(adap, bus); 2334 2335 snprintf(bus->adap.name, sizeof(bus->adap.name), "npcm_i2c_%d", 2336 bus->num); 2337 ret = i2c_add_numbered_adapter(&bus->adap); 2338 if (ret) 2339 return ret; 2340 2341 platform_set_drvdata(pdev, bus); 2342 npcm_i2c_init_debugfs(pdev, bus); 2343 return 0; 2344 } 2345 2346 static void npcm_i2c_remove_bus(struct platform_device *pdev) 2347 { 2348 unsigned long lock_flags; 2349 struct npcm_i2c *bus = platform_get_drvdata(pdev); 2350 2351 spin_lock_irqsave(&bus->lock, lock_flags); 2352 npcm_i2c_disable(bus); 2353 spin_unlock_irqrestore(&bus->lock, lock_flags); 2354 i2c_del_adapter(&bus->adap); 2355 } 2356 2357 static const struct of_device_id npcm_i2c_bus_of_table[] = { 2358 { .compatible = "nuvoton,npcm750-i2c", .data = &npxm7xx_i2c_data }, 2359 { .compatible = "nuvoton,npcm845-i2c", .data = &npxm8xx_i2c_data }, 2360 {} 2361 }; 2362 MODULE_DEVICE_TABLE(of, npcm_i2c_bus_of_table); 2363 2364 static struct platform_driver npcm_i2c_bus_driver = { 2365 .probe = npcm_i2c_probe_bus, 2366 .remove_new = npcm_i2c_remove_bus, 2367 .driver = { 2368 .name = "nuvoton-i2c", 2369 .of_match_table = npcm_i2c_bus_of_table, 2370 } 2371 }; 2372 2373 module_platform_driver(npcm_i2c_bus_driver); 2374 2375 MODULE_AUTHOR("Avi Fishman <avi.fishman@gmail.com>"); 2376 MODULE_AUTHOR("Tali Perry <tali.perry@nuvoton.com>"); 2377 MODULE_AUTHOR("Tyrone Ting <kfting@nuvoton.com>"); 2378 MODULE_DESCRIPTION("Nuvoton I2C Bus Driver"); 2379 MODULE_LICENSE("GPL v2"); 2380