1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Nuvoton NPCM7xx I2C Controller driver 4 * 5 * Copyright (C) 2020 Nuvoton Technologies tali.perry@nuvoton.com 6 */ 7 #include <linux/bitfield.h> 8 #include <linux/clk.h> 9 #include <linux/debugfs.h> 10 #include <linux/errno.h> 11 #include <linux/i2c.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/irq.h> 15 #include <linux/jiffies.h> 16 #include <linux/kernel.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/platform_device.h> 22 #include <linux/regmap.h> 23 24 enum i2c_mode { 25 I2C_MASTER, 26 I2C_SLAVE, 27 }; 28 29 /* 30 * External I2C Interface driver xfer indication values, which indicate status 31 * of the bus. 32 */ 33 enum i2c_state_ind { 34 I2C_NO_STATUS_IND = 0, 35 I2C_SLAVE_RCV_IND, 36 I2C_SLAVE_XMIT_IND, 37 I2C_SLAVE_XMIT_MISSING_DATA_IND, 38 I2C_SLAVE_RESTART_IND, 39 I2C_SLAVE_DONE_IND, 40 I2C_MASTER_DONE_IND, 41 I2C_NACK_IND, 42 I2C_BUS_ERR_IND, 43 I2C_WAKE_UP_IND, 44 I2C_BLOCK_BYTES_ERR_IND, 45 I2C_SLAVE_RCV_MISSING_DATA_IND, 46 }; 47 48 /* 49 * Operation type values (used to define the operation currently running) 50 * module is interrupt driven, on each interrupt the current operation is 51 * checked to see if the module is currently reading or writing. 52 */ 53 enum i2c_oper { 54 I2C_NO_OPER = 0, 55 I2C_WRITE_OPER, 56 I2C_READ_OPER, 57 }; 58 59 /* I2C Bank (module had 2 banks of registers) */ 60 enum i2c_bank { 61 I2C_BANK_0 = 0, 62 I2C_BANK_1, 63 }; 64 65 /* Internal I2C states values (for the I2C module state machine). */ 66 enum i2c_state { 67 I2C_DISABLE = 0, 68 I2C_IDLE, 69 I2C_MASTER_START, 70 I2C_SLAVE_MATCH, 71 I2C_OPER_STARTED, 72 I2C_STOP_PENDING, 73 }; 74 75 #if IS_ENABLED(CONFIG_I2C_SLAVE) 76 /* Module supports setting multiple own slave addresses */ 77 enum i2c_addr { 78 I2C_SLAVE_ADDR1 = 0, 79 I2C_SLAVE_ADDR2, 80 I2C_SLAVE_ADDR3, 81 I2C_SLAVE_ADDR4, 82 I2C_SLAVE_ADDR5, 83 I2C_SLAVE_ADDR6, 84 I2C_SLAVE_ADDR7, 85 I2C_SLAVE_ADDR8, 86 I2C_SLAVE_ADDR9, 87 I2C_SLAVE_ADDR10, 88 I2C_GC_ADDR, 89 I2C_ARP_ADDR, 90 }; 91 #endif 92 93 /* init register and default value required to enable module */ 94 #define NPCM_I2CSEGCTL 0xE4 95 96 /* Common regs */ 97 #define NPCM_I2CSDA 0x00 98 #define NPCM_I2CST 0x02 99 #define NPCM_I2CCST 0x04 100 #define NPCM_I2CCTL1 0x06 101 #define NPCM_I2CADDR1 0x08 102 #define NPCM_I2CCTL2 0x0A 103 #define NPCM_I2CADDR2 0x0C 104 #define NPCM_I2CCTL3 0x0E 105 #define NPCM_I2CCST2 0x18 106 #define NPCM_I2CCST3 0x19 107 #define I2C_VER 0x1F 108 109 /* BANK 0 regs */ 110 #define NPCM_I2CADDR3 0x10 111 #define NPCM_I2CADDR7 0x11 112 #define NPCM_I2CADDR4 0x12 113 #define NPCM_I2CADDR8 0x13 114 #define NPCM_I2CADDR5 0x14 115 #define NPCM_I2CADDR9 0x15 116 #define NPCM_I2CADDR6 0x16 117 #define NPCM_I2CADDR10 0x17 118 #define NPCM_I2CCTL4 0x1A 119 #define NPCM_I2CCTL5 0x1B 120 #define NPCM_I2CSCLLT 0x1C /* SCL Low Time */ 121 #define NPCM_I2CFIF_CTL 0x1D /* FIFO Control */ 122 #define NPCM_I2CSCLHT 0x1E /* SCL High Time */ 123 124 /* BANK 1 regs */ 125 #define NPCM_I2CFIF_CTS 0x10 /* Both FIFOs Control and Status */ 126 #define NPCM_I2CTXF_CTL 0x12 /* Tx-FIFO Control */ 127 #define NPCM_I2CT_OUT 0x14 /* Bus T.O. */ 128 #define NPCM_I2CPEC 0x16 /* PEC Data */ 129 #define NPCM_I2CTXF_STS 0x1A /* Tx-FIFO Status */ 130 #define NPCM_I2CRXF_STS 0x1C /* Rx-FIFO Status */ 131 #define NPCM_I2CRXF_CTL 0x1E /* Rx-FIFO Control */ 132 133 #if IS_ENABLED(CONFIG_I2C_SLAVE) 134 /* 135 * npcm_i2caddr array: 136 * The module supports having multiple own slave addresses. 137 * Since the addr regs are sprinkled all over the address space, 138 * use this array to get the address or each register. 139 */ 140 #define I2C_NUM_OWN_ADDR 2 141 #define I2C_NUM_OWN_ADDR_SUPPORTED 2 142 143 static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = { 144 NPCM_I2CADDR1, NPCM_I2CADDR2, 145 }; 146 #endif 147 148 /* NPCM_I2CST reg fields */ 149 #define NPCM_I2CST_XMIT BIT(0) /* Transmit mode */ 150 #define NPCM_I2CST_MASTER BIT(1) /* Master mode */ 151 #define NPCM_I2CST_NMATCH BIT(2) /* New match */ 152 #define NPCM_I2CST_STASTR BIT(3) /* Stall after start */ 153 #define NPCM_I2CST_NEGACK BIT(4) /* Negative ACK */ 154 #define NPCM_I2CST_BER BIT(5) /* Bus error */ 155 #define NPCM_I2CST_SDAST BIT(6) /* SDA status */ 156 #define NPCM_I2CST_SLVSTP BIT(7) /* Slave stop */ 157 158 /* NPCM_I2CCST reg fields */ 159 #define NPCM_I2CCST_BUSY BIT(0) /* Busy */ 160 #define NPCM_I2CCST_BB BIT(1) /* Bus busy */ 161 #define NPCM_I2CCST_MATCH BIT(2) /* Address match */ 162 #define NPCM_I2CCST_GCMATCH BIT(3) /* Global call match */ 163 #define NPCM_I2CCST_TSDA BIT(4) /* Test SDA line */ 164 #define NPCM_I2CCST_TGSCL BIT(5) /* Toggle SCL line */ 165 #define NPCM_I2CCST_MATCHAF BIT(6) /* Match address field */ 166 #define NPCM_I2CCST_ARPMATCH BIT(7) /* ARP address match */ 167 168 /* NPCM_I2CCTL1 reg fields */ 169 #define NPCM_I2CCTL1_START BIT(0) /* Generate start condition */ 170 #define NPCM_I2CCTL1_STOP BIT(1) /* Generate stop condition */ 171 #define NPCM_I2CCTL1_INTEN BIT(2) /* Interrupt enable */ 172 #define NPCM_I2CCTL1_EOBINTE BIT(3) 173 #define NPCM_I2CCTL1_ACK BIT(4) 174 #define NPCM_I2CCTL1_GCMEN BIT(5) /* Global call match enable */ 175 #define NPCM_I2CCTL1_NMINTE BIT(6) /* New match interrupt enable */ 176 #define NPCM_I2CCTL1_STASTRE BIT(7) /* Stall after start enable */ 177 178 /* RW1S fields (inside a RW reg): */ 179 #define NPCM_I2CCTL1_RWS \ 180 (NPCM_I2CCTL1_START | NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK) 181 182 /* npcm_i2caddr reg fields */ 183 #define NPCM_I2CADDR_A GENMASK(6, 0) /* Address */ 184 #define NPCM_I2CADDR_SAEN BIT(7) /* Slave address enable */ 185 186 /* NPCM_I2CCTL2 reg fields */ 187 #define I2CCTL2_ENABLE BIT(0) /* Module enable */ 188 #define I2CCTL2_SCLFRQ6_0 GENMASK(7, 1) /* Bits 0:6 of frequency divisor */ 189 190 /* NPCM_I2CCTL3 reg fields */ 191 #define I2CCTL3_SCLFRQ8_7 GENMASK(1, 0) /* Bits 7:8 of frequency divisor */ 192 #define I2CCTL3_ARPMEN BIT(2) /* ARP match enable */ 193 #define I2CCTL3_IDL_START BIT(3) 194 #define I2CCTL3_400K_MODE BIT(4) 195 #define I2CCTL3_BNK_SEL BIT(5) 196 #define I2CCTL3_SDA_LVL BIT(6) 197 #define I2CCTL3_SCL_LVL BIT(7) 198 199 /* NPCM_I2CCST2 reg fields */ 200 #define NPCM_I2CCST2_MATCHA1F BIT(0) 201 #define NPCM_I2CCST2_MATCHA2F BIT(1) 202 #define NPCM_I2CCST2_MATCHA3F BIT(2) 203 #define NPCM_I2CCST2_MATCHA4F BIT(3) 204 #define NPCM_I2CCST2_MATCHA5F BIT(4) 205 #define NPCM_I2CCST2_MATCHA6F BIT(5) 206 #define NPCM_I2CCST2_MATCHA7F BIT(5) 207 #define NPCM_I2CCST2_INTSTS BIT(7) 208 209 /* NPCM_I2CCST3 reg fields */ 210 #define NPCM_I2CCST3_MATCHA8F BIT(0) 211 #define NPCM_I2CCST3_MATCHA9F BIT(1) 212 #define NPCM_I2CCST3_MATCHA10F BIT(2) 213 #define NPCM_I2CCST3_EO_BUSY BIT(7) 214 215 /* NPCM_I2CCTL4 reg fields */ 216 #define I2CCTL4_HLDT GENMASK(5, 0) 217 #define I2CCTL4_LVL_WE BIT(7) 218 219 /* NPCM_I2CCTL5 reg fields */ 220 #define I2CCTL5_DBNCT GENMASK(3, 0) 221 222 /* NPCM_I2CFIF_CTS reg fields */ 223 #define NPCM_I2CFIF_CTS_RXF_TXE BIT(1) 224 #define NPCM_I2CFIF_CTS_RFTE_IE BIT(3) 225 #define NPCM_I2CFIF_CTS_CLR_FIFO BIT(6) 226 #define NPCM_I2CFIF_CTS_SLVRSTR BIT(7) 227 228 /* NPCM_I2CTXF_CTL reg field */ 229 #define NPCM_I2CTXF_CTL_THR_TXIE BIT(6) 230 231 /* NPCM_I2CT_OUT reg fields */ 232 #define NPCM_I2CT_OUT_TO_CKDIV GENMASK(5, 0) 233 #define NPCM_I2CT_OUT_T_OUTIE BIT(6) 234 #define NPCM_I2CT_OUT_T_OUTST BIT(7) 235 236 /* NPCM_I2CTXF_STS reg fields */ 237 #define NPCM_I2CTXF_STS_TX_THST BIT(6) 238 239 /* NPCM_I2CRXF_STS reg fields */ 240 #define NPCM_I2CRXF_STS_RX_THST BIT(6) 241 242 /* NPCM_I2CFIF_CTL reg fields */ 243 #define NPCM_I2CFIF_CTL_FIFO_EN BIT(4) 244 245 /* NPCM_I2CRXF_CTL reg fields */ 246 #define NPCM_I2CRXF_CTL_THR_RXIE BIT(6) 247 248 #define MAX_I2C_HW_FIFO_SIZE 32 249 250 /* I2C_VER reg fields */ 251 #define I2C_VER_VERSION GENMASK(6, 0) 252 #define I2C_VER_FIFO_EN BIT(7) 253 254 /* stall/stuck timeout in us */ 255 #define DEFAULT_STALL_COUNT 25 256 257 /* SCLFRQ field position */ 258 #define SCLFRQ_0_TO_6 GENMASK(6, 0) 259 #define SCLFRQ_7_TO_8 GENMASK(8, 7) 260 261 /* supported clk settings. values in Hz. */ 262 #define I2C_FREQ_MIN_HZ 10000 263 #define I2C_FREQ_MAX_HZ I2C_MAX_FAST_MODE_PLUS_FREQ 264 265 struct npcm_i2c_data { 266 u8 fifo_size; 267 u32 segctl_init_val; 268 u8 txf_sts_tx_bytes; 269 u8 rxf_sts_rx_bytes; 270 u8 rxf_ctl_last_pec; 271 }; 272 273 static const struct npcm_i2c_data npxm7xx_i2c_data = { 274 .fifo_size = 16, 275 .segctl_init_val = 0x0333F000, 276 .txf_sts_tx_bytes = GENMASK(4, 0), 277 .rxf_sts_rx_bytes = GENMASK(4, 0), 278 .rxf_ctl_last_pec = BIT(5), 279 }; 280 281 static const struct npcm_i2c_data npxm8xx_i2c_data = { 282 .fifo_size = 32, 283 .segctl_init_val = 0x9333F000, 284 .txf_sts_tx_bytes = GENMASK(5, 0), 285 .rxf_sts_rx_bytes = GENMASK(5, 0), 286 .rxf_ctl_last_pec = BIT(7), 287 }; 288 289 /* Status of one I2C module */ 290 struct npcm_i2c { 291 struct i2c_adapter adap; 292 struct device *dev; 293 unsigned char __iomem *reg; 294 const struct npcm_i2c_data *data; 295 spinlock_t lock; /* IRQ synchronization */ 296 struct completion cmd_complete; 297 int cmd_err; 298 struct i2c_msg *msgs; 299 int msgs_num; 300 int num; 301 u32 apb_clk; 302 struct i2c_bus_recovery_info rinfo; 303 enum i2c_state state; 304 enum i2c_oper operation; 305 enum i2c_mode master_or_slave; 306 enum i2c_state_ind stop_ind; 307 u8 dest_addr; 308 u8 *rd_buf; 309 u16 rd_size; 310 u16 rd_ind; 311 u8 *wr_buf; 312 u16 wr_size; 313 u16 wr_ind; 314 bool fifo_use; 315 u16 PEC_mask; /* PEC bit mask per slave address */ 316 bool PEC_use; 317 bool read_block_use; 318 unsigned long int_time_stamp; 319 unsigned long bus_freq; /* in Hz */ 320 #if IS_ENABLED(CONFIG_I2C_SLAVE) 321 u8 own_slave_addr; 322 struct i2c_client *slave; 323 int slv_rd_size; 324 int slv_rd_ind; 325 int slv_wr_size; 326 int slv_wr_ind; 327 u8 slv_rd_buf[MAX_I2C_HW_FIFO_SIZE]; 328 u8 slv_wr_buf[MAX_I2C_HW_FIFO_SIZE]; 329 #endif 330 struct dentry *debugfs; /* debugfs device directory */ 331 u64 ber_cnt; 332 u64 rec_succ_cnt; 333 u64 rec_fail_cnt; 334 u64 nack_cnt; 335 u64 timeout_cnt; 336 u64 tx_complete_cnt; 337 }; 338 339 static inline void npcm_i2c_select_bank(struct npcm_i2c *bus, 340 enum i2c_bank bank) 341 { 342 u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3); 343 344 if (bank == I2C_BANK_0) 345 i2cctl3 = i2cctl3 & ~I2CCTL3_BNK_SEL; 346 else 347 i2cctl3 = i2cctl3 | I2CCTL3_BNK_SEL; 348 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3); 349 } 350 351 static void npcm_i2c_init_params(struct npcm_i2c *bus) 352 { 353 bus->stop_ind = I2C_NO_STATUS_IND; 354 bus->rd_size = 0; 355 bus->wr_size = 0; 356 bus->rd_ind = 0; 357 bus->wr_ind = 0; 358 bus->read_block_use = false; 359 bus->int_time_stamp = 0; 360 bus->PEC_use = false; 361 bus->PEC_mask = 0; 362 #if IS_ENABLED(CONFIG_I2C_SLAVE) 363 if (bus->slave) 364 bus->master_or_slave = I2C_SLAVE; 365 #endif 366 } 367 368 static inline void npcm_i2c_wr_byte(struct npcm_i2c *bus, u8 data) 369 { 370 iowrite8(data, bus->reg + NPCM_I2CSDA); 371 } 372 373 static inline u8 npcm_i2c_rd_byte(struct npcm_i2c *bus) 374 { 375 return ioread8(bus->reg + NPCM_I2CSDA); 376 } 377 378 static int npcm_i2c_get_SCL(struct i2c_adapter *_adap) 379 { 380 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap); 381 382 return !!(I2CCTL3_SCL_LVL & ioread8(bus->reg + NPCM_I2CCTL3)); 383 } 384 385 static int npcm_i2c_get_SDA(struct i2c_adapter *_adap) 386 { 387 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap); 388 389 return !!(I2CCTL3_SDA_LVL & ioread8(bus->reg + NPCM_I2CCTL3)); 390 } 391 392 static inline u16 npcm_i2c_get_index(struct npcm_i2c *bus) 393 { 394 if (bus->operation == I2C_READ_OPER) 395 return bus->rd_ind; 396 if (bus->operation == I2C_WRITE_OPER) 397 return bus->wr_ind; 398 return 0; 399 } 400 401 /* quick protocol (just address) */ 402 static inline bool npcm_i2c_is_quick(struct npcm_i2c *bus) 403 { 404 return bus->wr_size == 0 && bus->rd_size == 0; 405 } 406 407 static void npcm_i2c_disable(struct npcm_i2c *bus) 408 { 409 u8 i2cctl2; 410 411 #if IS_ENABLED(CONFIG_I2C_SLAVE) 412 int i; 413 414 /* Slave addresses removal */ 415 for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++) 416 iowrite8(0, bus->reg + npcm_i2caddr[i]); 417 418 #endif 419 /* Disable module */ 420 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2); 421 i2cctl2 = i2cctl2 & ~I2CCTL2_ENABLE; 422 iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2); 423 424 bus->state = I2C_DISABLE; 425 } 426 427 static void npcm_i2c_enable(struct npcm_i2c *bus) 428 { 429 u8 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2); 430 431 i2cctl2 = i2cctl2 | I2CCTL2_ENABLE; 432 iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2); 433 bus->state = I2C_IDLE; 434 } 435 436 /* enable\disable end of busy (EOB) interrupts */ 437 static inline void npcm_i2c_eob_int(struct npcm_i2c *bus, bool enable) 438 { 439 u8 val; 440 441 /* Clear EO_BUSY pending bit: */ 442 val = ioread8(bus->reg + NPCM_I2CCST3); 443 val = val | NPCM_I2CCST3_EO_BUSY; 444 iowrite8(val, bus->reg + NPCM_I2CCST3); 445 446 val = ioread8(bus->reg + NPCM_I2CCTL1); 447 val &= ~NPCM_I2CCTL1_RWS; 448 if (enable) 449 val |= NPCM_I2CCTL1_EOBINTE; 450 else 451 val &= ~NPCM_I2CCTL1_EOBINTE; 452 iowrite8(val, bus->reg + NPCM_I2CCTL1); 453 } 454 455 static inline bool npcm_i2c_tx_fifo_empty(struct npcm_i2c *bus) 456 { 457 u8 tx_fifo_sts; 458 459 tx_fifo_sts = ioread8(bus->reg + NPCM_I2CTXF_STS); 460 /* check if TX FIFO is not empty */ 461 if ((tx_fifo_sts & bus->data->txf_sts_tx_bytes) == 0) 462 return false; 463 464 /* check if TX FIFO status bit is set: */ 465 return !!FIELD_GET(NPCM_I2CTXF_STS_TX_THST, tx_fifo_sts); 466 } 467 468 static inline bool npcm_i2c_rx_fifo_full(struct npcm_i2c *bus) 469 { 470 u8 rx_fifo_sts; 471 472 rx_fifo_sts = ioread8(bus->reg + NPCM_I2CRXF_STS); 473 /* check if RX FIFO is not empty: */ 474 if ((rx_fifo_sts & bus->data->rxf_sts_rx_bytes) == 0) 475 return false; 476 477 /* check if rx fifo full status is set: */ 478 return !!FIELD_GET(NPCM_I2CRXF_STS_RX_THST, rx_fifo_sts); 479 } 480 481 static inline void npcm_i2c_clear_fifo_int(struct npcm_i2c *bus) 482 { 483 u8 val; 484 485 val = ioread8(bus->reg + NPCM_I2CFIF_CTS); 486 val = (val & NPCM_I2CFIF_CTS_SLVRSTR) | NPCM_I2CFIF_CTS_RXF_TXE; 487 iowrite8(val, bus->reg + NPCM_I2CFIF_CTS); 488 } 489 490 static inline void npcm_i2c_clear_tx_fifo(struct npcm_i2c *bus) 491 { 492 u8 val; 493 494 val = ioread8(bus->reg + NPCM_I2CTXF_STS); 495 val = val | NPCM_I2CTXF_STS_TX_THST; 496 iowrite8(val, bus->reg + NPCM_I2CTXF_STS); 497 } 498 499 static inline void npcm_i2c_clear_rx_fifo(struct npcm_i2c *bus) 500 { 501 u8 val; 502 503 val = ioread8(bus->reg + NPCM_I2CRXF_STS); 504 val = val | NPCM_I2CRXF_STS_RX_THST; 505 iowrite8(val, bus->reg + NPCM_I2CRXF_STS); 506 } 507 508 static void npcm_i2c_int_enable(struct npcm_i2c *bus, bool enable) 509 { 510 u8 val; 511 512 val = ioread8(bus->reg + NPCM_I2CCTL1); 513 val &= ~NPCM_I2CCTL1_RWS; 514 if (enable) 515 val |= NPCM_I2CCTL1_INTEN; 516 else 517 val &= ~NPCM_I2CCTL1_INTEN; 518 iowrite8(val, bus->reg + NPCM_I2CCTL1); 519 } 520 521 static inline void npcm_i2c_master_start(struct npcm_i2c *bus) 522 { 523 u8 val; 524 525 val = ioread8(bus->reg + NPCM_I2CCTL1); 526 val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK); 527 val |= NPCM_I2CCTL1_START; 528 iowrite8(val, bus->reg + NPCM_I2CCTL1); 529 } 530 531 static inline void npcm_i2c_master_stop(struct npcm_i2c *bus) 532 { 533 u8 val; 534 535 /* 536 * override HW issue: I2C may fail to supply stop condition in Master 537 * Write operation. 538 * Need to delay at least 5 us from the last int, before issueing a stop 539 */ 540 udelay(10); /* function called from interrupt, can't sleep */ 541 val = ioread8(bus->reg + NPCM_I2CCTL1); 542 val &= ~(NPCM_I2CCTL1_START | NPCM_I2CCTL1_ACK); 543 val |= NPCM_I2CCTL1_STOP; 544 iowrite8(val, bus->reg + NPCM_I2CCTL1); 545 546 if (!bus->fifo_use) 547 return; 548 549 npcm_i2c_select_bank(bus, I2C_BANK_1); 550 551 if (bus->operation == I2C_READ_OPER) 552 npcm_i2c_clear_rx_fifo(bus); 553 else 554 npcm_i2c_clear_tx_fifo(bus); 555 npcm_i2c_clear_fifo_int(bus); 556 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); 557 } 558 559 static inline void npcm_i2c_stall_after_start(struct npcm_i2c *bus, bool stall) 560 { 561 u8 val; 562 563 val = ioread8(bus->reg + NPCM_I2CCTL1); 564 val &= ~NPCM_I2CCTL1_RWS; 565 if (stall) 566 val |= NPCM_I2CCTL1_STASTRE; 567 else 568 val &= ~NPCM_I2CCTL1_STASTRE; 569 iowrite8(val, bus->reg + NPCM_I2CCTL1); 570 } 571 572 static inline void npcm_i2c_nack(struct npcm_i2c *bus) 573 { 574 u8 val; 575 576 val = ioread8(bus->reg + NPCM_I2CCTL1); 577 val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_START); 578 val |= NPCM_I2CCTL1_ACK; 579 iowrite8(val, bus->reg + NPCM_I2CCTL1); 580 } 581 582 static inline void npcm_i2c_clear_master_status(struct npcm_i2c *bus) 583 { 584 u8 val; 585 586 /* Clear NEGACK, STASTR and BER bits */ 587 val = NPCM_I2CST_BER | NPCM_I2CST_NEGACK | NPCM_I2CST_STASTR; 588 iowrite8(val, bus->reg + NPCM_I2CST); 589 } 590 591 #if IS_ENABLED(CONFIG_I2C_SLAVE) 592 static void npcm_i2c_slave_int_enable(struct npcm_i2c *bus, bool enable) 593 { 594 u8 i2cctl1; 595 596 /* enable interrupt on slave match: */ 597 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1); 598 i2cctl1 &= ~NPCM_I2CCTL1_RWS; 599 if (enable) 600 i2cctl1 |= NPCM_I2CCTL1_NMINTE; 601 else 602 i2cctl1 &= ~NPCM_I2CCTL1_NMINTE; 603 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1); 604 } 605 606 static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type, 607 u8 addr, bool enable) 608 { 609 u8 i2cctl1; 610 u8 i2cctl3; 611 u8 sa_reg; 612 613 sa_reg = (addr & 0x7F) | FIELD_PREP(NPCM_I2CADDR_SAEN, enable); 614 if (addr_type == I2C_GC_ADDR) { 615 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1); 616 if (enable) 617 i2cctl1 |= NPCM_I2CCTL1_GCMEN; 618 else 619 i2cctl1 &= ~NPCM_I2CCTL1_GCMEN; 620 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1); 621 return 0; 622 } else if (addr_type == I2C_ARP_ADDR) { 623 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3); 624 if (enable) 625 i2cctl3 |= I2CCTL3_ARPMEN; 626 else 627 i2cctl3 &= ~I2CCTL3_ARPMEN; 628 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3); 629 return 0; 630 } 631 if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10) 632 dev_err(bus->dev, "try to enable more than 2 SA not supported\n"); 633 634 if (addr_type >= I2C_ARP_ADDR) 635 return -EFAULT; 636 637 /* Set and enable the address */ 638 iowrite8(sa_reg, bus->reg + npcm_i2caddr[addr_type]); 639 npcm_i2c_slave_int_enable(bus, enable); 640 641 return 0; 642 } 643 #endif 644 645 static void npcm_i2c_reset(struct npcm_i2c *bus) 646 { 647 /* 648 * Save I2CCTL1 relevant bits. It is being cleared when the module 649 * is disabled. 650 */ 651 u8 i2cctl1; 652 #if IS_ENABLED(CONFIG_I2C_SLAVE) 653 u8 addr; 654 #endif 655 656 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1); 657 658 npcm_i2c_disable(bus); 659 npcm_i2c_enable(bus); 660 661 /* Restore NPCM_I2CCTL1 Status */ 662 i2cctl1 &= ~NPCM_I2CCTL1_RWS; 663 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1); 664 665 /* Clear BB (BUS BUSY) bit */ 666 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST); 667 iowrite8(0xFF, bus->reg + NPCM_I2CST); 668 669 /* Clear and disable EOB */ 670 npcm_i2c_eob_int(bus, false); 671 672 /* Clear all fifo bits: */ 673 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS); 674 675 #if IS_ENABLED(CONFIG_I2C_SLAVE) 676 if (bus->slave) { 677 addr = bus->slave->addr; 678 npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, addr, true); 679 } 680 #endif 681 682 /* Clear status bits for spurious interrupts */ 683 npcm_i2c_clear_master_status(bus); 684 685 bus->state = I2C_IDLE; 686 } 687 688 static inline bool npcm_i2c_is_master(struct npcm_i2c *bus) 689 { 690 return !!FIELD_GET(NPCM_I2CST_MASTER, ioread8(bus->reg + NPCM_I2CST)); 691 } 692 693 static void npcm_i2c_callback(struct npcm_i2c *bus, 694 enum i2c_state_ind op_status, u16 info) 695 { 696 struct i2c_msg *msgs; 697 int msgs_num; 698 699 msgs = bus->msgs; 700 msgs_num = bus->msgs_num; 701 /* 702 * check that transaction was not timed-out, and msgs still 703 * holds a valid value. 704 */ 705 if (!msgs) 706 return; 707 708 if (completion_done(&bus->cmd_complete)) 709 return; 710 711 switch (op_status) { 712 case I2C_MASTER_DONE_IND: 713 bus->cmd_err = bus->msgs_num; 714 if (bus->tx_complete_cnt < ULLONG_MAX) 715 bus->tx_complete_cnt++; 716 fallthrough; 717 case I2C_BLOCK_BYTES_ERR_IND: 718 /* Master tx finished and all transmit bytes were sent */ 719 if (bus->msgs) { 720 if (msgs[0].flags & I2C_M_RD) 721 msgs[0].len = info; 722 else if (msgs_num == 2 && 723 msgs[1].flags & I2C_M_RD) 724 msgs[1].len = info; 725 } 726 if (completion_done(&bus->cmd_complete) == false) 727 complete(&bus->cmd_complete); 728 break; 729 730 case I2C_NACK_IND: 731 /* MASTER transmit got a NACK before tx all bytes */ 732 bus->cmd_err = -ENXIO; 733 if (bus->master_or_slave == I2C_MASTER) 734 complete(&bus->cmd_complete); 735 736 break; 737 case I2C_BUS_ERR_IND: 738 /* Bus error */ 739 bus->cmd_err = -EAGAIN; 740 if (bus->master_or_slave == I2C_MASTER) 741 complete(&bus->cmd_complete); 742 743 break; 744 case I2C_WAKE_UP_IND: 745 /* I2C wake up */ 746 break; 747 default: 748 break; 749 } 750 751 bus->operation = I2C_NO_OPER; 752 #if IS_ENABLED(CONFIG_I2C_SLAVE) 753 if (bus->slave) 754 bus->master_or_slave = I2C_SLAVE; 755 #endif 756 } 757 758 static u8 npcm_i2c_fifo_usage(struct npcm_i2c *bus) 759 { 760 if (bus->operation == I2C_WRITE_OPER) 761 return (bus->data->txf_sts_tx_bytes & 762 ioread8(bus->reg + NPCM_I2CTXF_STS)); 763 if (bus->operation == I2C_READ_OPER) 764 return (bus->data->rxf_sts_rx_bytes & 765 ioread8(bus->reg + NPCM_I2CRXF_STS)); 766 return 0; 767 } 768 769 static void npcm_i2c_write_to_fifo_master(struct npcm_i2c *bus, u16 max_bytes) 770 { 771 u8 size_free_fifo; 772 773 /* 774 * Fill the FIFO, while the FIFO is not full and there are more bytes 775 * to write 776 */ 777 size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus); 778 while (max_bytes-- && size_free_fifo) { 779 if (bus->wr_ind < bus->wr_size) 780 npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]); 781 else 782 npcm_i2c_wr_byte(bus, 0xFF); 783 size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus); 784 } 785 } 786 787 /* 788 * npcm_i2c_set_fifo: 789 * configure the FIFO before using it. If nread is -1 RX FIFO will not be 790 * configured. same for nwrite 791 */ 792 static void npcm_i2c_set_fifo(struct npcm_i2c *bus, int nread, int nwrite) 793 { 794 u8 rxf_ctl = 0; 795 796 if (!bus->fifo_use) 797 return; 798 npcm_i2c_select_bank(bus, I2C_BANK_1); 799 npcm_i2c_clear_tx_fifo(bus); 800 npcm_i2c_clear_rx_fifo(bus); 801 802 /* configure RX FIFO */ 803 if (nread > 0) { 804 rxf_ctl = min_t(int, nread, bus->data->fifo_size); 805 806 /* set LAST bit. if LAST is set next FIFO packet is nacked */ 807 if (nread <= bus->data->fifo_size) 808 rxf_ctl |= bus->data->rxf_ctl_last_pec; 809 810 /* 811 * if we are about to read the first byte in blk rd mode, 812 * don't NACK it. If slave returns zero size HW can't NACK 813 * it immediately, it will read extra byte and then NACK. 814 */ 815 if (bus->rd_ind == 0 && bus->read_block_use) { 816 /* set fifo to read one byte, no last: */ 817 rxf_ctl = 1; 818 } 819 820 /* set fifo size: */ 821 iowrite8(rxf_ctl, bus->reg + NPCM_I2CRXF_CTL); 822 } 823 824 /* configure TX FIFO */ 825 if (nwrite > 0) { 826 if (nwrite > bus->data->fifo_size) 827 /* data to send is more then FIFO size. */ 828 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CTXF_CTL); 829 else 830 iowrite8(nwrite, bus->reg + NPCM_I2CTXF_CTL); 831 832 npcm_i2c_clear_tx_fifo(bus); 833 } 834 } 835 836 static void npcm_i2c_read_fifo(struct npcm_i2c *bus, u8 bytes_in_fifo) 837 { 838 u8 data; 839 840 while (bytes_in_fifo--) { 841 data = npcm_i2c_rd_byte(bus); 842 if (bus->rd_ind < bus->rd_size) 843 bus->rd_buf[bus->rd_ind++] = data; 844 } 845 } 846 847 static void npcm_i2c_master_abort(struct npcm_i2c *bus) 848 { 849 /* Only current master is allowed to issue a stop condition */ 850 if (!npcm_i2c_is_master(bus)) 851 return; 852 853 npcm_i2c_eob_int(bus, true); 854 npcm_i2c_master_stop(bus); 855 npcm_i2c_clear_master_status(bus); 856 } 857 858 #if IS_ENABLED(CONFIG_I2C_SLAVE) 859 static u8 npcm_i2c_get_slave_addr(struct npcm_i2c *bus, enum i2c_addr addr_type) 860 { 861 u8 slave_add; 862 863 if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10) 864 dev_err(bus->dev, "get slave: try to use more than 2 SA not supported\n"); 865 866 slave_add = ioread8(bus->reg + npcm_i2caddr[(int)addr_type]); 867 868 return slave_add; 869 } 870 871 static int npcm_i2c_remove_slave_addr(struct npcm_i2c *bus, u8 slave_add) 872 { 873 int i; 874 875 /* Set the enable bit */ 876 slave_add |= 0x80; 877 878 for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++) { 879 if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add) 880 iowrite8(0, bus->reg + npcm_i2caddr[i]); 881 } 882 883 return 0; 884 } 885 886 static void npcm_i2c_write_fifo_slave(struct npcm_i2c *bus, u16 max_bytes) 887 { 888 /* 889 * Fill the FIFO, while the FIFO is not full and there are more bytes 890 * to write 891 */ 892 npcm_i2c_clear_fifo_int(bus); 893 npcm_i2c_clear_tx_fifo(bus); 894 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); 895 while (max_bytes-- && bus->data->fifo_size != npcm_i2c_fifo_usage(bus)) { 896 if (bus->slv_wr_size <= 0) 897 break; 898 bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1); 899 npcm_i2c_wr_byte(bus, bus->slv_wr_buf[bus->slv_wr_ind]); 900 bus->slv_wr_ind++; 901 bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1); 902 bus->slv_wr_size--; 903 } 904 } 905 906 static void npcm_i2c_read_fifo_slave(struct npcm_i2c *bus, u8 bytes_in_fifo) 907 { 908 u8 data; 909 910 if (!bus->slave) 911 return; 912 913 while (bytes_in_fifo--) { 914 data = npcm_i2c_rd_byte(bus); 915 916 bus->slv_rd_ind = bus->slv_rd_ind & (bus->data->fifo_size - 1); 917 bus->slv_rd_buf[bus->slv_rd_ind] = data; 918 bus->slv_rd_ind++; 919 920 /* 1st byte is length in block protocol: */ 921 if (bus->slv_rd_ind == 1 && bus->read_block_use) 922 bus->slv_rd_size = data + bus->PEC_use + 1; 923 } 924 } 925 926 static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus) 927 { 928 int i; 929 u8 value; 930 int ind; 931 int ret = bus->slv_wr_ind; 932 933 /* fill a cyclic buffer */ 934 for (i = 0; i < bus->data->fifo_size; i++) { 935 if (bus->slv_wr_size >= bus->data->fifo_size) 936 break; 937 if (bus->state == I2C_SLAVE_MATCH) { 938 i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value); 939 bus->state = I2C_OPER_STARTED; 940 } else { 941 i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value); 942 } 943 ind = (bus->slv_wr_ind + bus->slv_wr_size) & (bus->data->fifo_size - 1); 944 bus->slv_wr_buf[ind] = value; 945 bus->slv_wr_size++; 946 } 947 return bus->data->fifo_size - ret; 948 } 949 950 static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus) 951 { 952 int i; 953 954 for (i = 0; i < bus->slv_rd_ind; i++) 955 i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED, 956 &bus->slv_rd_buf[i]); 957 /* 958 * once we send bytes up, need to reset the counter of the wr buf 959 * got data from master (new offset in device), ignore wr fifo: 960 */ 961 if (bus->slv_rd_ind) { 962 bus->slv_wr_size = 0; 963 bus->slv_wr_ind = 0; 964 } 965 966 bus->slv_rd_ind = 0; 967 bus->slv_rd_size = bus->adap.quirks->max_read_len; 968 969 npcm_i2c_clear_fifo_int(bus); 970 npcm_i2c_clear_rx_fifo(bus); 971 } 972 973 static void npcm_i2c_slave_receive(struct npcm_i2c *bus, u16 nread, 974 u8 *read_data) 975 { 976 bus->state = I2C_OPER_STARTED; 977 bus->operation = I2C_READ_OPER; 978 bus->slv_rd_size = nread; 979 bus->slv_rd_ind = 0; 980 981 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); 982 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL); 983 npcm_i2c_clear_tx_fifo(bus); 984 npcm_i2c_clear_rx_fifo(bus); 985 } 986 987 static void npcm_i2c_slave_xmit(struct npcm_i2c *bus, u16 nwrite, 988 u8 *write_data) 989 { 990 if (nwrite == 0) 991 return; 992 993 bus->operation = I2C_WRITE_OPER; 994 995 /* get the next buffer */ 996 npcm_i2c_slave_get_wr_buf(bus); 997 npcm_i2c_write_fifo_slave(bus, nwrite); 998 } 999 1000 /* 1001 * npcm_i2c_slave_wr_buf_sync: 1002 * currently slave IF only supports single byte operations. 1003 * in order to utilize the npcm HW FIFO, the driver will ask for 16 bytes 1004 * at a time, pack them in buffer, and then transmit them all together 1005 * to the FIFO and onward to the bus. 1006 * NACK on read will be once reached to bus->adap->quirks->max_read_len. 1007 * sending a NACK wherever the backend requests for it is not supported. 1008 * the next two functions allow reading to local buffer before writing it all 1009 * to the HW FIFO. 1010 */ 1011 static void npcm_i2c_slave_wr_buf_sync(struct npcm_i2c *bus) 1012 { 1013 int left_in_fifo; 1014 1015 left_in_fifo = bus->data->txf_sts_tx_bytes & 1016 ioread8(bus->reg + NPCM_I2CTXF_STS); 1017 1018 /* fifo already full: */ 1019 if (left_in_fifo >= bus->data->fifo_size || 1020 bus->slv_wr_size >= bus->data->fifo_size) 1021 return; 1022 1023 /* update the wr fifo index back to the untransmitted bytes: */ 1024 bus->slv_wr_ind = bus->slv_wr_ind - left_in_fifo; 1025 bus->slv_wr_size = bus->slv_wr_size + left_in_fifo; 1026 1027 if (bus->slv_wr_ind < 0) 1028 bus->slv_wr_ind += bus->data->fifo_size; 1029 } 1030 1031 static void npcm_i2c_slave_rd_wr(struct npcm_i2c *bus) 1032 { 1033 if (NPCM_I2CST_XMIT & ioread8(bus->reg + NPCM_I2CST)) { 1034 /* 1035 * Slave got an address match with direction bit 1 so it should 1036 * transmit data. Write till the master will NACK 1037 */ 1038 bus->operation = I2C_WRITE_OPER; 1039 npcm_i2c_slave_xmit(bus, bus->adap.quirks->max_write_len, 1040 bus->slv_wr_buf); 1041 } else { 1042 /* 1043 * Slave got an address match with direction bit 0 so it should 1044 * receive data. 1045 * this module does not support saying no to bytes. 1046 * it will always ACK. 1047 */ 1048 bus->operation = I2C_READ_OPER; 1049 npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus)); 1050 bus->stop_ind = I2C_SLAVE_RCV_IND; 1051 npcm_i2c_slave_send_rd_buf(bus); 1052 npcm_i2c_slave_receive(bus, bus->adap.quirks->max_read_len, 1053 bus->slv_rd_buf); 1054 } 1055 } 1056 1057 static irqreturn_t npcm_i2c_int_slave_handler(struct npcm_i2c *bus) 1058 { 1059 u8 val; 1060 irqreturn_t ret = IRQ_NONE; 1061 u8 i2cst = ioread8(bus->reg + NPCM_I2CST); 1062 1063 /* Slave: A NACK has occurred */ 1064 if (NPCM_I2CST_NEGACK & i2cst) { 1065 bus->stop_ind = I2C_NACK_IND; 1066 npcm_i2c_slave_wr_buf_sync(bus); 1067 if (bus->fifo_use) 1068 /* clear the FIFO */ 1069 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, 1070 bus->reg + NPCM_I2CFIF_CTS); 1071 1072 /* In slave write, NACK is OK, otherwise it is a problem */ 1073 bus->stop_ind = I2C_NO_STATUS_IND; 1074 bus->operation = I2C_NO_OPER; 1075 bus->own_slave_addr = 0xFF; 1076 1077 /* 1078 * Slave has to wait for STOP to decide this is the end 1079 * of the transaction. tx is not yet considered as done 1080 */ 1081 iowrite8(NPCM_I2CST_NEGACK, bus->reg + NPCM_I2CST); 1082 1083 ret = IRQ_HANDLED; 1084 } 1085 1086 /* Slave mode: a Bus Error (BER) has been identified */ 1087 if (NPCM_I2CST_BER & i2cst) { 1088 /* 1089 * Check whether bus arbitration or Start or Stop during data 1090 * xfer bus arbitration problem should not result in recovery 1091 */ 1092 bus->stop_ind = I2C_BUS_ERR_IND; 1093 1094 /* wait for bus busy before clear fifo */ 1095 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS); 1096 1097 bus->state = I2C_IDLE; 1098 1099 /* 1100 * in BER case we might get 2 interrupts: one for slave one for 1101 * master ( for a channel which is master\slave switching) 1102 */ 1103 if (completion_done(&bus->cmd_complete) == false) { 1104 bus->cmd_err = -EIO; 1105 complete(&bus->cmd_complete); 1106 } 1107 bus->own_slave_addr = 0xFF; 1108 iowrite8(NPCM_I2CST_BER, bus->reg + NPCM_I2CST); 1109 ret = IRQ_HANDLED; 1110 } 1111 1112 /* A Slave Stop Condition has been identified */ 1113 if (NPCM_I2CST_SLVSTP & i2cst) { 1114 u8 bytes_in_fifo = npcm_i2c_fifo_usage(bus); 1115 1116 bus->stop_ind = I2C_SLAVE_DONE_IND; 1117 1118 if (bus->operation == I2C_READ_OPER) 1119 npcm_i2c_read_fifo_slave(bus, bytes_in_fifo); 1120 1121 /* if the buffer is empty nothing will be sent */ 1122 npcm_i2c_slave_send_rd_buf(bus); 1123 1124 /* Slave done transmitting or receiving */ 1125 bus->stop_ind = I2C_NO_STATUS_IND; 1126 1127 /* 1128 * Note, just because we got here, it doesn't mean we through 1129 * away the wr buffer. 1130 * we keep it until the next received offset. 1131 */ 1132 bus->operation = I2C_NO_OPER; 1133 bus->own_slave_addr = 0xFF; 1134 i2c_slave_event(bus->slave, I2C_SLAVE_STOP, 0); 1135 iowrite8(NPCM_I2CST_SLVSTP, bus->reg + NPCM_I2CST); 1136 if (bus->fifo_use) { 1137 npcm_i2c_clear_fifo_int(bus); 1138 npcm_i2c_clear_rx_fifo(bus); 1139 npcm_i2c_clear_tx_fifo(bus); 1140 1141 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, 1142 bus->reg + NPCM_I2CFIF_CTS); 1143 } 1144 bus->state = I2C_IDLE; 1145 ret = IRQ_HANDLED; 1146 } 1147 1148 /* restart condition occurred and Rx-FIFO was not empty */ 1149 if (bus->fifo_use && FIELD_GET(NPCM_I2CFIF_CTS_SLVRSTR, 1150 ioread8(bus->reg + NPCM_I2CFIF_CTS))) { 1151 bus->stop_ind = I2C_SLAVE_RESTART_IND; 1152 bus->master_or_slave = I2C_SLAVE; 1153 if (bus->operation == I2C_READ_OPER) 1154 npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus)); 1155 bus->operation = I2C_WRITE_OPER; 1156 iowrite8(0, bus->reg + NPCM_I2CRXF_CTL); 1157 val = NPCM_I2CFIF_CTS_CLR_FIFO | NPCM_I2CFIF_CTS_SLVRSTR | 1158 NPCM_I2CFIF_CTS_RXF_TXE; 1159 iowrite8(val, bus->reg + NPCM_I2CFIF_CTS); 1160 npcm_i2c_slave_rd_wr(bus); 1161 ret = IRQ_HANDLED; 1162 } 1163 1164 /* A Slave Address Match has been identified */ 1165 if (NPCM_I2CST_NMATCH & i2cst) { 1166 u8 info = 0; 1167 1168 /* Address match automatically implies slave mode */ 1169 bus->master_or_slave = I2C_SLAVE; 1170 npcm_i2c_clear_fifo_int(bus); 1171 npcm_i2c_clear_rx_fifo(bus); 1172 npcm_i2c_clear_tx_fifo(bus); 1173 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); 1174 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL); 1175 if (NPCM_I2CST_XMIT & i2cst) { 1176 bus->operation = I2C_WRITE_OPER; 1177 } else { 1178 i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_REQUESTED, 1179 &info); 1180 bus->operation = I2C_READ_OPER; 1181 } 1182 if (bus->own_slave_addr == 0xFF) { 1183 /* Check which type of address match */ 1184 val = ioread8(bus->reg + NPCM_I2CCST); 1185 if (NPCM_I2CCST_MATCH & val) { 1186 u16 addr; 1187 enum i2c_addr eaddr; 1188 u8 i2ccst2; 1189 u8 i2ccst3; 1190 1191 i2ccst3 = ioread8(bus->reg + NPCM_I2CCST3); 1192 i2ccst2 = ioread8(bus->reg + NPCM_I2CCST2); 1193 1194 /* 1195 * the i2c module can response to 10 own SA. 1196 * check which one was addressed by the master. 1197 * respond to the first one. 1198 */ 1199 addr = ((i2ccst3 & 0x07) << 7) | 1200 (i2ccst2 & 0x7F); 1201 info = ffs(addr); 1202 eaddr = (enum i2c_addr)info; 1203 addr = npcm_i2c_get_slave_addr(bus, eaddr); 1204 addr &= 0x7F; 1205 bus->own_slave_addr = addr; 1206 if (bus->PEC_mask & BIT(info)) 1207 bus->PEC_use = true; 1208 else 1209 bus->PEC_use = false; 1210 } else { 1211 if (NPCM_I2CCST_GCMATCH & val) 1212 bus->own_slave_addr = 0; 1213 if (NPCM_I2CCST_ARPMATCH & val) 1214 bus->own_slave_addr = 0x61; 1215 } 1216 } else { 1217 /* 1218 * Slave match can happen in two options: 1219 * 1. Start, SA, read (slave read without further ado) 1220 * 2. Start, SA, read, data, restart, SA, read, ... 1221 * (slave read in fragmented mode) 1222 * 3. Start, SA, write, data, restart, SA, read, .. 1223 * (regular write-read mode) 1224 */ 1225 if ((bus->state == I2C_OPER_STARTED && 1226 bus->operation == I2C_READ_OPER && 1227 bus->stop_ind == I2C_SLAVE_XMIT_IND) || 1228 bus->stop_ind == I2C_SLAVE_RCV_IND) { 1229 /* slave tx after slave rx w/o STOP */ 1230 bus->stop_ind = I2C_SLAVE_RESTART_IND; 1231 } 1232 } 1233 1234 if (NPCM_I2CST_XMIT & i2cst) 1235 bus->stop_ind = I2C_SLAVE_XMIT_IND; 1236 else 1237 bus->stop_ind = I2C_SLAVE_RCV_IND; 1238 bus->state = I2C_SLAVE_MATCH; 1239 npcm_i2c_slave_rd_wr(bus); 1240 iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST); 1241 ret = IRQ_HANDLED; 1242 } 1243 1244 /* Slave SDA status is set - tx or rx */ 1245 if ((NPCM_I2CST_SDAST & i2cst) || 1246 (bus->fifo_use && 1247 (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) { 1248 npcm_i2c_slave_rd_wr(bus); 1249 iowrite8(NPCM_I2CST_SDAST, bus->reg + NPCM_I2CST); 1250 ret = IRQ_HANDLED; 1251 } /* SDAST */ 1252 1253 /* 1254 * If irq is not one of the above, make sure EOB is disabled and all 1255 * status bits are cleared. 1256 */ 1257 if (ret == IRQ_NONE) { 1258 npcm_i2c_eob_int(bus, false); 1259 npcm_i2c_clear_master_status(bus); 1260 } 1261 1262 return IRQ_HANDLED; 1263 } 1264 1265 static int npcm_i2c_reg_slave(struct i2c_client *client) 1266 { 1267 unsigned long lock_flags; 1268 struct npcm_i2c *bus = i2c_get_adapdata(client->adapter); 1269 1270 bus->slave = client; 1271 1272 if (!bus->slave) 1273 return -EINVAL; 1274 1275 if (client->flags & I2C_CLIENT_TEN) 1276 return -EAFNOSUPPORT; 1277 1278 spin_lock_irqsave(&bus->lock, lock_flags); 1279 1280 npcm_i2c_init_params(bus); 1281 bus->slv_rd_size = 0; 1282 bus->slv_wr_size = 0; 1283 bus->slv_rd_ind = 0; 1284 bus->slv_wr_ind = 0; 1285 if (client->flags & I2C_CLIENT_PEC) 1286 bus->PEC_use = true; 1287 1288 dev_info(bus->dev, "i2c%d register slave SA=0x%x, PEC=%d\n", bus->num, 1289 client->addr, bus->PEC_use); 1290 1291 npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, client->addr, true); 1292 npcm_i2c_clear_fifo_int(bus); 1293 npcm_i2c_clear_rx_fifo(bus); 1294 npcm_i2c_clear_tx_fifo(bus); 1295 npcm_i2c_slave_int_enable(bus, true); 1296 1297 spin_unlock_irqrestore(&bus->lock, lock_flags); 1298 return 0; 1299 } 1300 1301 static int npcm_i2c_unreg_slave(struct i2c_client *client) 1302 { 1303 struct npcm_i2c *bus = client->adapter->algo_data; 1304 unsigned long lock_flags; 1305 1306 spin_lock_irqsave(&bus->lock, lock_flags); 1307 if (!bus->slave) { 1308 spin_unlock_irqrestore(&bus->lock, lock_flags); 1309 return -EINVAL; 1310 } 1311 npcm_i2c_slave_int_enable(bus, false); 1312 npcm_i2c_remove_slave_addr(bus, client->addr); 1313 bus->slave = NULL; 1314 spin_unlock_irqrestore(&bus->lock, lock_flags); 1315 return 0; 1316 } 1317 #endif /* CONFIG_I2C_SLAVE */ 1318 1319 static void npcm_i2c_master_fifo_read(struct npcm_i2c *bus) 1320 { 1321 int rcount; 1322 int fifo_bytes; 1323 enum i2c_state_ind ind = I2C_MASTER_DONE_IND; 1324 1325 fifo_bytes = npcm_i2c_fifo_usage(bus); 1326 rcount = bus->rd_size - bus->rd_ind; 1327 1328 /* 1329 * In order not to change the RX_TRH during transaction (we found that 1330 * this might be problematic if it takes too much time to read the FIFO) 1331 * we read the data in the following way. If the number of bytes to 1332 * read == FIFO Size + C (where C < FIFO Size)then first read C bytes 1333 * and in the next int we read rest of the data. 1334 */ 1335 if (rcount < (2 * bus->data->fifo_size) && rcount > bus->data->fifo_size) 1336 fifo_bytes = rcount - bus->data->fifo_size; 1337 1338 if (rcount <= fifo_bytes) { 1339 /* last bytes are about to be read - end of tx */ 1340 bus->state = I2C_STOP_PENDING; 1341 bus->stop_ind = ind; 1342 npcm_i2c_eob_int(bus, true); 1343 /* Stop should be set before reading last byte. */ 1344 npcm_i2c_master_stop(bus); 1345 npcm_i2c_read_fifo(bus, fifo_bytes); 1346 } else { 1347 npcm_i2c_read_fifo(bus, fifo_bytes); 1348 rcount = bus->rd_size - bus->rd_ind; 1349 npcm_i2c_set_fifo(bus, rcount, -1); 1350 } 1351 } 1352 1353 static void npcm_i2c_irq_master_handler_write(struct npcm_i2c *bus) 1354 { 1355 u16 wcount; 1356 1357 if (bus->fifo_use) 1358 npcm_i2c_clear_tx_fifo(bus); /* clear the TX fifo status bit */ 1359 1360 /* Master write operation - last byte handling */ 1361 if (bus->wr_ind == bus->wr_size) { 1362 if (bus->fifo_use && npcm_i2c_fifo_usage(bus) > 0) 1363 /* 1364 * No more bytes to send (to add to the FIFO), 1365 * however the FIFO is not empty yet. It is 1366 * still in the middle of tx. Currently there's nothing 1367 * to do except for waiting to the end of the tx 1368 * We will get an int when the FIFO will get empty. 1369 */ 1370 return; 1371 1372 if (bus->rd_size == 0) { 1373 /* all bytes have been written, in wr only operation */ 1374 npcm_i2c_eob_int(bus, true); 1375 bus->state = I2C_STOP_PENDING; 1376 bus->stop_ind = I2C_MASTER_DONE_IND; 1377 npcm_i2c_master_stop(bus); 1378 /* Clear SDA Status bit (by writing dummy byte) */ 1379 npcm_i2c_wr_byte(bus, 0xFF); 1380 1381 } else { 1382 /* last write-byte written on previous int - restart */ 1383 npcm_i2c_set_fifo(bus, bus->rd_size, -1); 1384 /* Generate repeated start upon next write to SDA */ 1385 npcm_i2c_master_start(bus); 1386 1387 /* 1388 * Receiving one byte only - stall after successful 1389 * completion of send address byte. If we NACK here, and 1390 * slave doesn't ACK the address, we might 1391 * unintentionally NACK the next multi-byte read. 1392 */ 1393 if (bus->rd_size == 1) 1394 npcm_i2c_stall_after_start(bus, true); 1395 1396 /* Next int will occur on read */ 1397 bus->operation = I2C_READ_OPER; 1398 /* send the slave address in read direction */ 1399 npcm_i2c_wr_byte(bus, bus->dest_addr | 0x1); 1400 } 1401 } else { 1402 /* write next byte not last byte and not slave address */ 1403 if (!bus->fifo_use || bus->wr_size == 1) { 1404 npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]); 1405 } else { 1406 wcount = bus->wr_size - bus->wr_ind; 1407 npcm_i2c_set_fifo(bus, -1, wcount); 1408 if (wcount) 1409 npcm_i2c_write_to_fifo_master(bus, wcount); 1410 } 1411 } 1412 } 1413 1414 static void npcm_i2c_irq_master_handler_read(struct npcm_i2c *bus) 1415 { 1416 u16 block_extra_bytes_size; 1417 u8 data; 1418 1419 /* added bytes to the packet: */ 1420 block_extra_bytes_size = bus->read_block_use + bus->PEC_use; 1421 1422 /* 1423 * Perform master read, distinguishing between last byte and the rest of 1424 * the bytes. The last byte should be read when the clock is stopped 1425 */ 1426 if (bus->rd_ind == 0) { /* first byte handling: */ 1427 if (bus->read_block_use) { 1428 /* first byte in block protocol is the size: */ 1429 data = npcm_i2c_rd_byte(bus); 1430 data = clamp_val(data, 1, I2C_SMBUS_BLOCK_MAX); 1431 bus->rd_size = data + block_extra_bytes_size; 1432 bus->rd_buf[bus->rd_ind++] = data; 1433 1434 /* clear RX FIFO interrupt status: */ 1435 if (bus->fifo_use) { 1436 data = ioread8(bus->reg + NPCM_I2CFIF_CTS); 1437 data = data | NPCM_I2CFIF_CTS_RXF_TXE; 1438 iowrite8(data, bus->reg + NPCM_I2CFIF_CTS); 1439 } 1440 1441 npcm_i2c_set_fifo(bus, bus->rd_size - 1, -1); 1442 npcm_i2c_stall_after_start(bus, false); 1443 } else { 1444 npcm_i2c_clear_tx_fifo(bus); 1445 npcm_i2c_master_fifo_read(bus); 1446 } 1447 } else { 1448 if (bus->rd_size == block_extra_bytes_size && 1449 bus->read_block_use) { 1450 bus->state = I2C_STOP_PENDING; 1451 bus->stop_ind = I2C_BLOCK_BYTES_ERR_IND; 1452 bus->cmd_err = -EIO; 1453 npcm_i2c_eob_int(bus, true); 1454 npcm_i2c_master_stop(bus); 1455 npcm_i2c_read_fifo(bus, npcm_i2c_fifo_usage(bus)); 1456 } else { 1457 npcm_i2c_master_fifo_read(bus); 1458 } 1459 } 1460 } 1461 1462 static void npcm_i2c_irq_handle_nmatch(struct npcm_i2c *bus) 1463 { 1464 iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST); 1465 npcm_i2c_nack(bus); 1466 bus->stop_ind = I2C_BUS_ERR_IND; 1467 npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus)); 1468 } 1469 1470 /* A NACK has occurred */ 1471 static void npcm_i2c_irq_handle_nack(struct npcm_i2c *bus) 1472 { 1473 u8 val; 1474 1475 if (bus->nack_cnt < ULLONG_MAX) 1476 bus->nack_cnt++; 1477 1478 if (bus->fifo_use) { 1479 /* 1480 * if there are still untransmitted bytes in TX FIFO 1481 * reduce them from wr_ind 1482 */ 1483 if (bus->operation == I2C_WRITE_OPER) 1484 bus->wr_ind -= npcm_i2c_fifo_usage(bus); 1485 1486 /* clear the FIFO */ 1487 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS); 1488 } 1489 1490 /* In master write operation, got unexpected NACK */ 1491 bus->stop_ind = I2C_NACK_IND; 1492 /* Only current master is allowed to issue Stop Condition */ 1493 if (npcm_i2c_is_master(bus)) { 1494 /* stopping in the middle */ 1495 npcm_i2c_eob_int(bus, false); 1496 npcm_i2c_master_stop(bus); 1497 1498 /* Clear SDA Status bit (by reading dummy byte) */ 1499 npcm_i2c_rd_byte(bus); 1500 1501 /* 1502 * The bus is released from stall only after the SW clears 1503 * NEGACK bit. Then a Stop condition is sent. 1504 */ 1505 npcm_i2c_clear_master_status(bus); 1506 readx_poll_timeout_atomic(ioread8, bus->reg + NPCM_I2CCST, val, 1507 !(val & NPCM_I2CCST_BUSY), 10, 200); 1508 /* Verify no status bits are still set after bus is released */ 1509 npcm_i2c_clear_master_status(bus); 1510 } 1511 bus->state = I2C_IDLE; 1512 1513 /* 1514 * In Master mode, NACK should be cleared only after STOP. 1515 * In such case, the bus is released from stall only after the 1516 * software clears NACK bit. Then a Stop condition is sent. 1517 */ 1518 npcm_i2c_callback(bus, bus->stop_ind, bus->wr_ind); 1519 } 1520 1521 /* Master mode: a Bus Error has been identified */ 1522 static void npcm_i2c_irq_handle_ber(struct npcm_i2c *bus) 1523 { 1524 if (bus->ber_cnt < ULLONG_MAX) 1525 bus->ber_cnt++; 1526 bus->stop_ind = I2C_BUS_ERR_IND; 1527 if (npcm_i2c_is_master(bus)) { 1528 npcm_i2c_master_abort(bus); 1529 } else { 1530 npcm_i2c_clear_master_status(bus); 1531 1532 /* Clear BB (BUS BUSY) bit */ 1533 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST); 1534 1535 bus->cmd_err = -EAGAIN; 1536 npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus)); 1537 } 1538 bus->state = I2C_IDLE; 1539 } 1540 1541 /* EOB: a master End Of Busy (meaning STOP completed) */ 1542 static void npcm_i2c_irq_handle_eob(struct npcm_i2c *bus) 1543 { 1544 npcm_i2c_eob_int(bus, false); 1545 bus->state = I2C_IDLE; 1546 npcm_i2c_callback(bus, bus->stop_ind, bus->rd_ind); 1547 } 1548 1549 /* Address sent and requested stall occurred (Master mode) */ 1550 static void npcm_i2c_irq_handle_stall_after_start(struct npcm_i2c *bus) 1551 { 1552 if (npcm_i2c_is_quick(bus)) { 1553 bus->state = I2C_STOP_PENDING; 1554 bus->stop_ind = I2C_MASTER_DONE_IND; 1555 npcm_i2c_eob_int(bus, true); 1556 npcm_i2c_master_stop(bus); 1557 } else if ((bus->rd_size == 1) && !bus->read_block_use) { 1558 /* 1559 * Receiving one byte only - set NACK after ensuring 1560 * slave ACKed the address byte. 1561 */ 1562 npcm_i2c_nack(bus); 1563 } 1564 1565 /* Reset stall-after-address-byte */ 1566 npcm_i2c_stall_after_start(bus, false); 1567 1568 /* Clear stall only after setting STOP */ 1569 iowrite8(NPCM_I2CST_STASTR, bus->reg + NPCM_I2CST); 1570 } 1571 1572 /* SDA status is set - TX or RX, master */ 1573 static void npcm_i2c_irq_handle_sda(struct npcm_i2c *bus, u8 i2cst) 1574 { 1575 u8 fif_cts; 1576 1577 if (!npcm_i2c_is_master(bus)) 1578 return; 1579 1580 if (bus->state == I2C_IDLE) { 1581 bus->stop_ind = I2C_WAKE_UP_IND; 1582 1583 if (npcm_i2c_is_quick(bus) || bus->read_block_use) 1584 /* 1585 * Need to stall after successful 1586 * completion of sending address byte 1587 */ 1588 npcm_i2c_stall_after_start(bus, true); 1589 else 1590 npcm_i2c_stall_after_start(bus, false); 1591 1592 /* 1593 * Receiving one byte only - stall after successful completion 1594 * of sending address byte If we NACK here, and slave doesn't 1595 * ACK the address, we might unintentionally NACK the next 1596 * multi-byte read 1597 */ 1598 if (bus->wr_size == 0 && bus->rd_size == 1) 1599 npcm_i2c_stall_after_start(bus, true); 1600 1601 /* Initiate I2C master tx */ 1602 1603 /* select bank 1 for FIFO regs */ 1604 npcm_i2c_select_bank(bus, I2C_BANK_1); 1605 1606 fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS); 1607 fif_cts = fif_cts & ~NPCM_I2CFIF_CTS_SLVRSTR; 1608 1609 /* clear FIFO and relevant status bits. */ 1610 fif_cts = fif_cts | NPCM_I2CFIF_CTS_CLR_FIFO; 1611 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS); 1612 1613 /* re-enable */ 1614 fif_cts = fif_cts | NPCM_I2CFIF_CTS_RXF_TXE; 1615 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS); 1616 1617 /* 1618 * Configure the FIFO threshold: 1619 * according to the needed # of bytes to read. 1620 * Note: due to HW limitation can't config the rx fifo before it 1621 * got and ACK on the restart. LAST bit will not be reset unless 1622 * RX completed. It will stay set on the next tx. 1623 */ 1624 if (bus->wr_size) 1625 npcm_i2c_set_fifo(bus, -1, bus->wr_size); 1626 else 1627 npcm_i2c_set_fifo(bus, bus->rd_size, -1); 1628 1629 bus->state = I2C_OPER_STARTED; 1630 1631 if (npcm_i2c_is_quick(bus) || bus->wr_size) 1632 npcm_i2c_wr_byte(bus, bus->dest_addr); 1633 else 1634 npcm_i2c_wr_byte(bus, bus->dest_addr | BIT(0)); 1635 /* SDA interrupt, after start\restart */ 1636 } else { 1637 if (NPCM_I2CST_XMIT & i2cst) { 1638 bus->operation = I2C_WRITE_OPER; 1639 npcm_i2c_irq_master_handler_write(bus); 1640 } else { 1641 bus->operation = I2C_READ_OPER; 1642 npcm_i2c_irq_master_handler_read(bus); 1643 } 1644 } 1645 } 1646 1647 static int npcm_i2c_int_master_handler(struct npcm_i2c *bus) 1648 { 1649 u8 i2cst; 1650 int ret = -EIO; 1651 1652 i2cst = ioread8(bus->reg + NPCM_I2CST); 1653 1654 if (FIELD_GET(NPCM_I2CST_NMATCH, i2cst)) { 1655 npcm_i2c_irq_handle_nmatch(bus); 1656 return 0; 1657 } 1658 /* A NACK has occurred */ 1659 if (FIELD_GET(NPCM_I2CST_NEGACK, i2cst)) { 1660 npcm_i2c_irq_handle_nack(bus); 1661 return 0; 1662 } 1663 1664 /* Master mode: a Bus Error has been identified */ 1665 if (FIELD_GET(NPCM_I2CST_BER, i2cst)) { 1666 npcm_i2c_irq_handle_ber(bus); 1667 return 0; 1668 } 1669 1670 /* EOB: a master End Of Busy (meaning STOP completed) */ 1671 if ((FIELD_GET(NPCM_I2CCTL1_EOBINTE, 1672 ioread8(bus->reg + NPCM_I2CCTL1)) == 1) && 1673 (FIELD_GET(NPCM_I2CCST3_EO_BUSY, 1674 ioread8(bus->reg + NPCM_I2CCST3)))) { 1675 npcm_i2c_irq_handle_eob(bus); 1676 return 0; 1677 } 1678 1679 /* Address sent and requested stall occurred (Master mode) */ 1680 if (FIELD_GET(NPCM_I2CST_STASTR, i2cst)) { 1681 npcm_i2c_irq_handle_stall_after_start(bus); 1682 ret = 0; 1683 } 1684 1685 /* SDA status is set - TX or RX, master */ 1686 if (FIELD_GET(NPCM_I2CST_SDAST, i2cst) || 1687 (bus->fifo_use && 1688 (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) { 1689 npcm_i2c_irq_handle_sda(bus, i2cst); 1690 ret = 0; 1691 } 1692 1693 return ret; 1694 } 1695 1696 /* recovery using TGCLK functionality of the module */ 1697 static int npcm_i2c_recovery_tgclk(struct i2c_adapter *_adap) 1698 { 1699 u8 val; 1700 u8 fif_cts; 1701 bool done = false; 1702 int status = -ENOTRECOVERABLE; 1703 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap); 1704 /* Allow 3 bytes (27 toggles) to be read from the slave: */ 1705 int iter = 27; 1706 1707 if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1)) { 1708 dev_dbg(bus->dev, "bus%d-0x%x recovery skipped, bus not stuck", 1709 bus->num, bus->dest_addr); 1710 npcm_i2c_reset(bus); 1711 return 0; 1712 } 1713 1714 npcm_i2c_int_enable(bus, false); 1715 npcm_i2c_disable(bus); 1716 npcm_i2c_enable(bus); 1717 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST); 1718 npcm_i2c_clear_tx_fifo(bus); 1719 npcm_i2c_clear_rx_fifo(bus); 1720 iowrite8(0, bus->reg + NPCM_I2CRXF_CTL); 1721 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); 1722 npcm_i2c_stall_after_start(bus, false); 1723 1724 /* select bank 1 for FIFO regs */ 1725 npcm_i2c_select_bank(bus, I2C_BANK_1); 1726 1727 /* clear FIFO and relevant status bits. */ 1728 fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS); 1729 fif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR; 1730 fif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO; 1731 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS); 1732 npcm_i2c_set_fifo(bus, -1, 0); 1733 1734 /* Repeat the following sequence until SDA is released */ 1735 do { 1736 /* Issue a single SCL toggle */ 1737 iowrite8(NPCM_I2CCST_TGSCL, bus->reg + NPCM_I2CCST); 1738 usleep_range(20, 30); 1739 /* If SDA line is inactive (high), stop */ 1740 if (npcm_i2c_get_SDA(_adap)) { 1741 done = true; 1742 status = 0; 1743 } 1744 } while (!done && iter--); 1745 1746 /* If SDA line is released: send start-addr-stop, to re-sync. */ 1747 if (npcm_i2c_get_SDA(_adap)) { 1748 /* Send an address byte in write direction: */ 1749 npcm_i2c_wr_byte(bus, bus->dest_addr); 1750 npcm_i2c_master_start(bus); 1751 /* Wait until START condition is sent */ 1752 status = readx_poll_timeout(npcm_i2c_get_SCL, _adap, val, !val, 1753 20, 200); 1754 /* If START condition was sent */ 1755 if (npcm_i2c_is_master(bus) > 0) { 1756 usleep_range(20, 30); 1757 npcm_i2c_master_stop(bus); 1758 usleep_range(200, 500); 1759 } 1760 } 1761 npcm_i2c_reset(bus); 1762 npcm_i2c_int_enable(bus, true); 1763 1764 if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1)) 1765 status = 0; 1766 else 1767 status = -ENOTRECOVERABLE; 1768 if (status) { 1769 if (bus->rec_fail_cnt < ULLONG_MAX) 1770 bus->rec_fail_cnt++; 1771 } else { 1772 if (bus->rec_succ_cnt < ULLONG_MAX) 1773 bus->rec_succ_cnt++; 1774 } 1775 return status; 1776 } 1777 1778 /* recovery using bit banging functionality of the module */ 1779 static void npcm_i2c_recovery_init(struct i2c_adapter *_adap) 1780 { 1781 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap); 1782 struct i2c_bus_recovery_info *rinfo = &bus->rinfo; 1783 1784 rinfo->recover_bus = npcm_i2c_recovery_tgclk; 1785 1786 /* 1787 * npcm i2c HW allows direct reading of SCL and SDA. 1788 * However, it does not support setting SCL and SDA directly. 1789 * The recovery function can toggle SCL when SDA is low (but not set) 1790 * Getter functions used internally, and can be used externally. 1791 */ 1792 rinfo->get_scl = npcm_i2c_get_SCL; 1793 rinfo->get_sda = npcm_i2c_get_SDA; 1794 _adap->bus_recovery_info = rinfo; 1795 } 1796 1797 /* SCLFRQ min/max field values */ 1798 #define SCLFRQ_MIN 10 1799 #define SCLFRQ_MAX 511 1800 #define clk_coef(freq, mul) DIV_ROUND_UP((freq) * (mul), 1000000) 1801 1802 /* 1803 * npcm_i2c_init_clk: init HW timing parameters. 1804 * NPCM7XX i2c module timing parameters are dependent on module core clk (APB) 1805 * and bus frequency. 1806 * 100kHz bus requires tSCL = 4 * SCLFRQ * tCLK. LT and HT are symmetric. 1807 * 400kHz bus requires asymmetric HT and LT. A different equation is recommended 1808 * by the HW designer, given core clock range (equations in comments below). 1809 * 1810 */ 1811 static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz) 1812 { 1813 u32 k1 = 0; 1814 u32 k2 = 0; 1815 u8 dbnct = 0; 1816 u32 sclfrq = 0; 1817 u8 hldt = 7; 1818 u8 fast_mode = 0; 1819 u32 src_clk_khz; 1820 u32 bus_freq_khz; 1821 1822 src_clk_khz = bus->apb_clk / 1000; 1823 bus_freq_khz = bus_freq_hz / 1000; 1824 bus->bus_freq = bus_freq_hz; 1825 1826 /* 100KHz and below: */ 1827 if (bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) { 1828 sclfrq = src_clk_khz / (bus_freq_khz * 4); 1829 1830 if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX) 1831 return -EDOM; 1832 1833 if (src_clk_khz >= 40000) 1834 hldt = 17; 1835 else if (src_clk_khz >= 12500) 1836 hldt = 15; 1837 else 1838 hldt = 7; 1839 } 1840 1841 /* 400KHz: */ 1842 else if (bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) { 1843 sclfrq = 0; 1844 fast_mode = I2CCTL3_400K_MODE; 1845 1846 if (src_clk_khz < 7500) 1847 /* 400KHZ cannot be supported for core clock < 7.5MHz */ 1848 return -EDOM; 1849 1850 else if (src_clk_khz >= 50000) { 1851 k1 = 80; 1852 k2 = 48; 1853 hldt = 12; 1854 dbnct = 7; 1855 } 1856 1857 /* Master or Slave with frequency > 25MHz */ 1858 else if (src_clk_khz > 25000) { 1859 hldt = clk_coef(src_clk_khz, 300) + 7; 1860 k1 = clk_coef(src_clk_khz, 1600); 1861 k2 = clk_coef(src_clk_khz, 900); 1862 } 1863 } 1864 1865 /* 1MHz: */ 1866 else if (bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) { 1867 sclfrq = 0; 1868 fast_mode = I2CCTL3_400K_MODE; 1869 1870 /* 1MHZ cannot be supported for core clock < 24 MHz */ 1871 if (src_clk_khz < 24000) 1872 return -EDOM; 1873 1874 k1 = clk_coef(src_clk_khz, 620); 1875 k2 = clk_coef(src_clk_khz, 380); 1876 1877 /* Core clk > 40 MHz */ 1878 if (src_clk_khz > 40000) { 1879 /* 1880 * Set HLDT: 1881 * SDA hold time: (HLDT-7) * T(CLK) >= 120 1882 * HLDT = 120/T(CLK) + 7 = 120 * FREQ(CLK) + 7 1883 */ 1884 hldt = clk_coef(src_clk_khz, 120) + 7; 1885 } else { 1886 hldt = 7; 1887 dbnct = 2; 1888 } 1889 } 1890 1891 /* Frequency larger than 1 MHz is not supported */ 1892 else 1893 return -EINVAL; 1894 1895 if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) { 1896 k1 = round_up(k1, 2); 1897 k2 = round_up(k2 + 1, 2); 1898 if (k1 < SCLFRQ_MIN || k1 > SCLFRQ_MAX || 1899 k2 < SCLFRQ_MIN || k2 > SCLFRQ_MAX) 1900 return -EDOM; 1901 } 1902 1903 /* write sclfrq value. bits [6:0] are in I2CCTL2 reg */ 1904 iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, sclfrq & 0x7F), 1905 bus->reg + NPCM_I2CCTL2); 1906 1907 /* bits [8:7] are in I2CCTL3 reg */ 1908 iowrite8(fast_mode | FIELD_PREP(I2CCTL3_SCLFRQ8_7, (sclfrq >> 7) & 0x3), 1909 bus->reg + NPCM_I2CCTL3); 1910 1911 /* Select Bank 0 to access NPCM_I2CCTL4/NPCM_I2CCTL5 */ 1912 npcm_i2c_select_bank(bus, I2C_BANK_0); 1913 1914 if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) { 1915 /* 1916 * Set SCL Low/High Time: 1917 * k1 = 2 * SCLLT7-0 -> Low Time = k1 / 2 1918 * k2 = 2 * SCLLT7-0 -> High Time = k2 / 2 1919 */ 1920 iowrite8(k1 / 2, bus->reg + NPCM_I2CSCLLT); 1921 iowrite8(k2 / 2, bus->reg + NPCM_I2CSCLHT); 1922 1923 iowrite8(dbnct, bus->reg + NPCM_I2CCTL5); 1924 } 1925 1926 iowrite8(hldt, bus->reg + NPCM_I2CCTL4); 1927 1928 /* Return to Bank 1, and stay there by default: */ 1929 npcm_i2c_select_bank(bus, I2C_BANK_1); 1930 1931 return 0; 1932 } 1933 1934 static int npcm_i2c_init_module(struct npcm_i2c *bus, enum i2c_mode mode, 1935 u32 bus_freq_hz) 1936 { 1937 u8 val; 1938 int ret; 1939 1940 /* Check whether module already enabled or frequency is out of bounds */ 1941 if ((bus->state != I2C_DISABLE && bus->state != I2C_IDLE) || 1942 bus_freq_hz < I2C_FREQ_MIN_HZ || bus_freq_hz > I2C_FREQ_MAX_HZ) 1943 return -EINVAL; 1944 1945 npcm_i2c_int_enable(bus, false); 1946 npcm_i2c_disable(bus); 1947 1948 /* Configure FIFO mode : */ 1949 if (FIELD_GET(I2C_VER_FIFO_EN, ioread8(bus->reg + I2C_VER))) { 1950 bus->fifo_use = true; 1951 npcm_i2c_select_bank(bus, I2C_BANK_0); 1952 val = ioread8(bus->reg + NPCM_I2CFIF_CTL); 1953 val |= NPCM_I2CFIF_CTL_FIFO_EN; 1954 iowrite8(val, bus->reg + NPCM_I2CFIF_CTL); 1955 npcm_i2c_select_bank(bus, I2C_BANK_1); 1956 } else { 1957 bus->fifo_use = false; 1958 } 1959 1960 /* Configure I2C module clock frequency */ 1961 ret = npcm_i2c_init_clk(bus, bus_freq_hz); 1962 if (ret) { 1963 dev_err(bus->dev, "npcm_i2c_init_clk failed\n"); 1964 return ret; 1965 } 1966 1967 /* Enable module (before configuring CTL1) */ 1968 npcm_i2c_enable(bus); 1969 bus->state = I2C_IDLE; 1970 val = ioread8(bus->reg + NPCM_I2CCTL1); 1971 val = (val | NPCM_I2CCTL1_NMINTE) & ~NPCM_I2CCTL1_RWS; 1972 iowrite8(val, bus->reg + NPCM_I2CCTL1); 1973 1974 npcm_i2c_reset(bus); 1975 1976 /* Check HW is OK: SDA and SCL should be high at this point. */ 1977 if ((npcm_i2c_get_SDA(&bus->adap) == 0) || (npcm_i2c_get_SCL(&bus->adap) == 0)) { 1978 dev_err(bus->dev, "I2C%d init fail: lines are low\n", bus->num); 1979 dev_err(bus->dev, "SDA=%d SCL=%d\n", npcm_i2c_get_SDA(&bus->adap), 1980 npcm_i2c_get_SCL(&bus->adap)); 1981 return -ENXIO; 1982 } 1983 1984 npcm_i2c_int_enable(bus, true); 1985 return 0; 1986 } 1987 1988 static int __npcm_i2c_init(struct npcm_i2c *bus, struct platform_device *pdev) 1989 { 1990 u32 clk_freq_hz; 1991 int ret; 1992 1993 /* Initialize the internal data structures */ 1994 bus->state = I2C_DISABLE; 1995 bus->master_or_slave = I2C_SLAVE; 1996 bus->int_time_stamp = 0; 1997 #if IS_ENABLED(CONFIG_I2C_SLAVE) 1998 bus->slave = NULL; 1999 #endif 2000 2001 ret = device_property_read_u32(&pdev->dev, "clock-frequency", 2002 &clk_freq_hz); 2003 if (ret) { 2004 dev_info(&pdev->dev, "Could not read clock-frequency property"); 2005 clk_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; 2006 } 2007 2008 ret = npcm_i2c_init_module(bus, I2C_MASTER, clk_freq_hz); 2009 if (ret) { 2010 dev_err(&pdev->dev, "npcm_i2c_init_module failed\n"); 2011 return ret; 2012 } 2013 2014 return 0; 2015 } 2016 2017 static irqreturn_t npcm_i2c_bus_irq(int irq, void *dev_id) 2018 { 2019 struct npcm_i2c *bus = dev_id; 2020 2021 if (npcm_i2c_is_master(bus)) 2022 bus->master_or_slave = I2C_MASTER; 2023 2024 if (bus->master_or_slave == I2C_MASTER) { 2025 bus->int_time_stamp = jiffies; 2026 if (!npcm_i2c_int_master_handler(bus)) 2027 return IRQ_HANDLED; 2028 } 2029 #if IS_ENABLED(CONFIG_I2C_SLAVE) 2030 if (bus->slave) { 2031 bus->master_or_slave = I2C_SLAVE; 2032 if (npcm_i2c_int_slave_handler(bus)) 2033 return IRQ_HANDLED; 2034 } 2035 #endif 2036 /* Clear status bits for spurious interrupts */ 2037 npcm_i2c_clear_master_status(bus); 2038 2039 return IRQ_HANDLED; 2040 } 2041 2042 static bool npcm_i2c_master_start_xmit(struct npcm_i2c *bus, 2043 u8 slave_addr, u16 nwrite, u16 nread, 2044 u8 *write_data, u8 *read_data, 2045 bool use_PEC, bool use_read_block) 2046 { 2047 if (bus->state != I2C_IDLE) { 2048 bus->cmd_err = -EBUSY; 2049 return false; 2050 } 2051 bus->dest_addr = slave_addr << 1; 2052 bus->wr_buf = write_data; 2053 bus->wr_size = nwrite; 2054 bus->wr_ind = 0; 2055 bus->rd_buf = read_data; 2056 bus->rd_size = nread; 2057 bus->rd_ind = 0; 2058 bus->PEC_use = 0; 2059 2060 /* for tx PEC is appended to buffer from i2c IF. PEC flag is ignored */ 2061 if (nread) 2062 bus->PEC_use = use_PEC; 2063 2064 bus->read_block_use = use_read_block; 2065 if (nread && !nwrite) 2066 bus->operation = I2C_READ_OPER; 2067 else 2068 bus->operation = I2C_WRITE_OPER; 2069 if (bus->fifo_use) { 2070 u8 i2cfif_cts; 2071 2072 npcm_i2c_select_bank(bus, I2C_BANK_1); 2073 /* clear FIFO and relevant status bits. */ 2074 i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS); 2075 i2cfif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR; 2076 i2cfif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO; 2077 iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS); 2078 } 2079 2080 bus->state = I2C_IDLE; 2081 npcm_i2c_stall_after_start(bus, true); 2082 npcm_i2c_master_start(bus); 2083 return true; 2084 } 2085 2086 static int npcm_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 2087 int num) 2088 { 2089 struct npcm_i2c *bus = container_of(adap, struct npcm_i2c, adap); 2090 struct i2c_msg *msg0, *msg1; 2091 unsigned long time_left, flags; 2092 u16 nwrite, nread; 2093 u8 *write_data, *read_data; 2094 u8 slave_addr; 2095 unsigned long timeout; 2096 bool read_block = false; 2097 bool read_PEC = false; 2098 u8 bus_busy; 2099 unsigned long timeout_usec; 2100 2101 if (bus->state == I2C_DISABLE) { 2102 dev_err(bus->dev, "I2C%d module is disabled", bus->num); 2103 return -EINVAL; 2104 } 2105 2106 msg0 = &msgs[0]; 2107 slave_addr = msg0->addr; 2108 if (msg0->flags & I2C_M_RD) { /* read */ 2109 nwrite = 0; 2110 write_data = NULL; 2111 read_data = msg0->buf; 2112 if (msg0->flags & I2C_M_RECV_LEN) { 2113 nread = 1; 2114 read_block = true; 2115 if (msg0->flags & I2C_CLIENT_PEC) 2116 read_PEC = true; 2117 } else { 2118 nread = msg0->len; 2119 } 2120 } else { /* write */ 2121 nwrite = msg0->len; 2122 write_data = msg0->buf; 2123 nread = 0; 2124 read_data = NULL; 2125 if (num == 2) { 2126 msg1 = &msgs[1]; 2127 read_data = msg1->buf; 2128 if (msg1->flags & I2C_M_RECV_LEN) { 2129 nread = 1; 2130 read_block = true; 2131 if (msg1->flags & I2C_CLIENT_PEC) 2132 read_PEC = true; 2133 } else { 2134 nread = msg1->len; 2135 read_block = false; 2136 } 2137 } 2138 } 2139 2140 /* 2141 * Adaptive TimeOut: estimated time in usec + 100% margin: 2142 * 2: double the timeout for clock stretching case 2143 * 9: bits per transaction (including the ack/nack) 2144 */ 2145 timeout_usec = (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + nwrite); 2146 timeout = max_t(unsigned long, bus->adap.timeout, usecs_to_jiffies(timeout_usec)); 2147 if (nwrite >= 32 * 1024 || nread >= 32 * 1024) { 2148 dev_err(bus->dev, "i2c%d buffer too big\n", bus->num); 2149 return -EINVAL; 2150 } 2151 2152 time_left = jiffies + timeout + 1; 2153 do { 2154 /* 2155 * we must clear slave address immediately when the bus is not 2156 * busy, so we spinlock it, but we don't keep the lock for the 2157 * entire while since it is too long. 2158 */ 2159 spin_lock_irqsave(&bus->lock, flags); 2160 bus_busy = ioread8(bus->reg + NPCM_I2CCST) & NPCM_I2CCST_BB; 2161 #if IS_ENABLED(CONFIG_I2C_SLAVE) 2162 if (!bus_busy && bus->slave) 2163 iowrite8((bus->slave->addr & 0x7F), 2164 bus->reg + NPCM_I2CADDR1); 2165 #endif 2166 spin_unlock_irqrestore(&bus->lock, flags); 2167 2168 } while (time_is_after_jiffies(time_left) && bus_busy); 2169 2170 if (bus_busy) { 2171 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST); 2172 npcm_i2c_reset(bus); 2173 i2c_recover_bus(adap); 2174 return -EAGAIN; 2175 } 2176 2177 npcm_i2c_init_params(bus); 2178 bus->dest_addr = slave_addr; 2179 bus->msgs = msgs; 2180 bus->msgs_num = num; 2181 bus->cmd_err = 0; 2182 bus->read_block_use = read_block; 2183 2184 reinit_completion(&bus->cmd_complete); 2185 2186 npcm_i2c_int_enable(bus, true); 2187 2188 if (npcm_i2c_master_start_xmit(bus, slave_addr, nwrite, nread, 2189 write_data, read_data, read_PEC, 2190 read_block)) { 2191 time_left = wait_for_completion_timeout(&bus->cmd_complete, 2192 timeout); 2193 2194 if (time_left == 0) { 2195 if (bus->timeout_cnt < ULLONG_MAX) 2196 bus->timeout_cnt++; 2197 if (bus->master_or_slave == I2C_MASTER) { 2198 i2c_recover_bus(adap); 2199 bus->cmd_err = -EIO; 2200 bus->state = I2C_IDLE; 2201 } 2202 } 2203 } 2204 2205 /* if there was BER, check if need to recover the bus: */ 2206 if (bus->cmd_err == -EAGAIN) 2207 bus->cmd_err = i2c_recover_bus(adap); 2208 2209 /* 2210 * After any type of error, check if LAST bit is still set, 2211 * due to a HW issue. 2212 * It cannot be cleared without resetting the module. 2213 */ 2214 else if (bus->cmd_err && 2215 (bus->data->rxf_ctl_last_pec & ioread8(bus->reg + NPCM_I2CRXF_CTL))) 2216 npcm_i2c_reset(bus); 2217 2218 /* After any xfer, successful or not, stall and EOB must be disabled */ 2219 npcm_i2c_stall_after_start(bus, false); 2220 npcm_i2c_eob_int(bus, false); 2221 2222 #if IS_ENABLED(CONFIG_I2C_SLAVE) 2223 /* reenable slave if it was enabled */ 2224 if (bus->slave) 2225 iowrite8((bus->slave->addr & 0x7F) | NPCM_I2CADDR_SAEN, 2226 bus->reg + NPCM_I2CADDR1); 2227 #else 2228 npcm_i2c_int_enable(bus, false); 2229 #endif 2230 return bus->cmd_err; 2231 } 2232 2233 static u32 npcm_i2c_functionality(struct i2c_adapter *adap) 2234 { 2235 return I2C_FUNC_I2C | 2236 I2C_FUNC_SMBUS_EMUL | 2237 I2C_FUNC_SMBUS_BLOCK_DATA | 2238 I2C_FUNC_SMBUS_PEC | 2239 I2C_FUNC_SLAVE; 2240 } 2241 2242 static const struct i2c_adapter_quirks npcm_i2c_quirks = { 2243 .max_read_len = 32768, 2244 .max_write_len = 32768, 2245 .flags = I2C_AQ_COMB_WRITE_THEN_READ, 2246 }; 2247 2248 static const struct i2c_algorithm npcm_i2c_algo = { 2249 .master_xfer = npcm_i2c_master_xfer, 2250 .functionality = npcm_i2c_functionality, 2251 #if IS_ENABLED(CONFIG_I2C_SLAVE) 2252 .reg_slave = npcm_i2c_reg_slave, 2253 .unreg_slave = npcm_i2c_unreg_slave, 2254 #endif 2255 }; 2256 2257 /* i2c debugfs directory: used to keep health monitor of i2c devices */ 2258 static struct dentry *npcm_i2c_debugfs_dir; 2259 2260 static void npcm_i2c_init_debugfs(struct platform_device *pdev, 2261 struct npcm_i2c *bus) 2262 { 2263 struct dentry *d; 2264 2265 if (!npcm_i2c_debugfs_dir) 2266 return; 2267 d = debugfs_create_dir(dev_name(&pdev->dev), npcm_i2c_debugfs_dir); 2268 if (IS_ERR_OR_NULL(d)) 2269 return; 2270 debugfs_create_u64("ber_cnt", 0444, d, &bus->ber_cnt); 2271 debugfs_create_u64("nack_cnt", 0444, d, &bus->nack_cnt); 2272 debugfs_create_u64("rec_succ_cnt", 0444, d, &bus->rec_succ_cnt); 2273 debugfs_create_u64("rec_fail_cnt", 0444, d, &bus->rec_fail_cnt); 2274 debugfs_create_u64("timeout_cnt", 0444, d, &bus->timeout_cnt); 2275 debugfs_create_u64("tx_complete_cnt", 0444, d, &bus->tx_complete_cnt); 2276 2277 bus->debugfs = d; 2278 } 2279 2280 static int npcm_i2c_probe_bus(struct platform_device *pdev) 2281 { 2282 struct device_node *np = pdev->dev.of_node; 2283 static struct regmap *gcr_regmap; 2284 struct device *dev = &pdev->dev; 2285 struct i2c_adapter *adap; 2286 struct npcm_i2c *bus; 2287 struct clk *i2c_clk; 2288 int irq; 2289 int ret; 2290 2291 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL); 2292 if (!bus) 2293 return -ENOMEM; 2294 2295 bus->dev = &pdev->dev; 2296 2297 bus->data = of_device_get_match_data(dev); 2298 if (!bus->data) { 2299 dev_err(dev, "OF data missing\n"); 2300 return -EINVAL; 2301 } 2302 2303 bus->num = of_alias_get_id(pdev->dev.of_node, "i2c"); 2304 /* core clk must be acquired to calculate module timing settings */ 2305 i2c_clk = devm_clk_get(&pdev->dev, NULL); 2306 if (IS_ERR(i2c_clk)) 2307 return PTR_ERR(i2c_clk); 2308 bus->apb_clk = clk_get_rate(i2c_clk); 2309 2310 gcr_regmap = syscon_regmap_lookup_by_phandle(np, "nuvoton,sys-mgr"); 2311 if (IS_ERR(gcr_regmap)) 2312 gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr"); 2313 2314 if (IS_ERR(gcr_regmap)) 2315 return PTR_ERR(gcr_regmap); 2316 regmap_write(gcr_regmap, NPCM_I2CSEGCTL, bus->data->segctl_init_val); 2317 2318 bus->reg = devm_platform_ioremap_resource(pdev, 0); 2319 if (IS_ERR(bus->reg)) 2320 return PTR_ERR(bus->reg); 2321 2322 spin_lock_init(&bus->lock); 2323 init_completion(&bus->cmd_complete); 2324 2325 adap = &bus->adap; 2326 adap->owner = THIS_MODULE; 2327 adap->retries = 3; 2328 adap->timeout = msecs_to_jiffies(35); 2329 adap->algo = &npcm_i2c_algo; 2330 adap->quirks = &npcm_i2c_quirks; 2331 adap->algo_data = bus; 2332 adap->dev.parent = &pdev->dev; 2333 adap->dev.of_node = pdev->dev.of_node; 2334 adap->nr = pdev->id; 2335 2336 irq = platform_get_irq(pdev, 0); 2337 if (irq < 0) 2338 return irq; 2339 2340 ret = devm_request_irq(bus->dev, irq, npcm_i2c_bus_irq, 0, 2341 dev_name(bus->dev), bus); 2342 if (ret) 2343 return ret; 2344 2345 ret = __npcm_i2c_init(bus, pdev); 2346 if (ret) 2347 return ret; 2348 2349 npcm_i2c_recovery_init(adap); 2350 2351 i2c_set_adapdata(adap, bus); 2352 2353 snprintf(bus->adap.name, sizeof(bus->adap.name), "npcm_i2c_%d", 2354 bus->num); 2355 ret = i2c_add_numbered_adapter(&bus->adap); 2356 if (ret) 2357 return ret; 2358 2359 platform_set_drvdata(pdev, bus); 2360 npcm_i2c_init_debugfs(pdev, bus); 2361 return 0; 2362 } 2363 2364 static int npcm_i2c_remove_bus(struct platform_device *pdev) 2365 { 2366 unsigned long lock_flags; 2367 struct npcm_i2c *bus = platform_get_drvdata(pdev); 2368 2369 debugfs_remove_recursive(bus->debugfs); 2370 spin_lock_irqsave(&bus->lock, lock_flags); 2371 npcm_i2c_disable(bus); 2372 spin_unlock_irqrestore(&bus->lock, lock_flags); 2373 i2c_del_adapter(&bus->adap); 2374 return 0; 2375 } 2376 2377 static const struct of_device_id npcm_i2c_bus_of_table[] = { 2378 { .compatible = "nuvoton,npcm750-i2c", .data = &npxm7xx_i2c_data }, 2379 { .compatible = "nuvoton,npcm845-i2c", .data = &npxm8xx_i2c_data }, 2380 {} 2381 }; 2382 MODULE_DEVICE_TABLE(of, npcm_i2c_bus_of_table); 2383 2384 static struct platform_driver npcm_i2c_bus_driver = { 2385 .probe = npcm_i2c_probe_bus, 2386 .remove = npcm_i2c_remove_bus, 2387 .driver = { 2388 .name = "nuvoton-i2c", 2389 .of_match_table = npcm_i2c_bus_of_table, 2390 } 2391 }; 2392 2393 static int __init npcm_i2c_init(void) 2394 { 2395 int ret; 2396 2397 npcm_i2c_debugfs_dir = debugfs_create_dir("npcm_i2c", NULL); 2398 2399 ret = platform_driver_register(&npcm_i2c_bus_driver); 2400 if (ret) { 2401 debugfs_remove_recursive(npcm_i2c_debugfs_dir); 2402 return ret; 2403 } 2404 2405 return 0; 2406 } 2407 module_init(npcm_i2c_init); 2408 2409 static void __exit npcm_i2c_exit(void) 2410 { 2411 platform_driver_unregister(&npcm_i2c_bus_driver); 2412 debugfs_remove_recursive(npcm_i2c_debugfs_dir); 2413 } 2414 module_exit(npcm_i2c_exit); 2415 2416 MODULE_AUTHOR("Avi Fishman <avi.fishman@gmail.com>"); 2417 MODULE_AUTHOR("Tali Perry <tali.perry@nuvoton.com>"); 2418 MODULE_AUTHOR("Tyrone Ting <kfting@nuvoton.com>"); 2419 MODULE_DESCRIPTION("Nuvoton I2C Bus Driver"); 2420 MODULE_LICENSE("GPL v2"); 2421