1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2009 ST-Ericsson SA 4 * Copyright (C) 2009 STMicroelectronics 5 * 6 * I2C master mode controller driver, used in Nomadik 8815 7 * and Ux500 platforms. 8 * 9 * The Mobileye EyeQ5 and EyeQ6H platforms are also supported; they use 10 * the same Ux500/DB8500 IP block with two quirks: 11 * - The memory bus only supports 32-bit accesses. 12 * - (only EyeQ5) A register must be configured for the I2C speed mode; 13 * it is located in a shared register region called OLB. 14 * 15 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> 16 * Author: Sachin Verma <sachin.verma@st.com> 17 */ 18 #include <linux/amba/bus.h> 19 #include <linux/bitfield.h> 20 #include <linux/clk.h> 21 #include <linux/err.h> 22 #include <linux/i2c.h> 23 #include <linux/init.h> 24 #include <linux/interrupt.h> 25 #include <linux/io.h> 26 #include <linux/mfd/syscon.h> 27 #include <linux/module.h> 28 #include <linux/of.h> 29 #include <linux/of_device.h> 30 #include <linux/pinctrl/consumer.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regmap.h> 33 #include <linux/slab.h> 34 #include <linux/units.h> 35 36 #define DRIVER_NAME "nmk-i2c" 37 38 /* I2C Controller register offsets */ 39 #define I2C_CR (0x000) 40 #define I2C_SCR (0x004) 41 #define I2C_HSMCR (0x008) 42 #define I2C_MCR (0x00C) 43 #define I2C_TFR (0x010) 44 #define I2C_SR (0x014) 45 #define I2C_RFR (0x018) 46 #define I2C_TFTR (0x01C) 47 #define I2C_RFTR (0x020) 48 #define I2C_DMAR (0x024) 49 #define I2C_BRCR (0x028) 50 #define I2C_IMSCR (0x02C) 51 #define I2C_RISR (0x030) 52 #define I2C_MISR (0x034) 53 #define I2C_ICR (0x038) 54 55 /* Control registers */ 56 #define I2C_CR_PE BIT(0) /* Peripheral Enable */ 57 #define I2C_CR_OM GENMASK(2, 1) /* Operating mode */ 58 #define I2C_CR_SAM BIT(3) /* Slave addressing mode */ 59 #define I2C_CR_SM GENMASK(5, 4) /* Speed mode */ 60 #define I2C_CR_SGCM BIT(6) /* Slave general call mode */ 61 #define I2C_CR_FTX BIT(7) /* Flush Transmit */ 62 #define I2C_CR_FRX BIT(8) /* Flush Receive */ 63 #define I2C_CR_DMA_TX_EN BIT(9) /* DMA Tx enable */ 64 #define I2C_CR_DMA_RX_EN BIT(10) /* DMA Rx Enable */ 65 #define I2C_CR_DMA_SLE BIT(11) /* DMA sync. logic enable */ 66 #define I2C_CR_LM BIT(12) /* Loopback mode */ 67 #define I2C_CR_FON GENMASK(14, 13) /* Filtering on */ 68 #define I2C_CR_FS GENMASK(16, 15) /* Force stop enable */ 69 70 /* Slave control register (SCR) */ 71 #define I2C_SCR_SLSU GENMASK(31, 16) /* Slave data setup time */ 72 73 /* Master controller (MCR) register */ 74 #define I2C_MCR_OP BIT(0) /* Operation */ 75 #define I2C_MCR_A7 GENMASK(7, 1) /* 7-bit address */ 76 #define I2C_MCR_EA10 GENMASK(10, 8) /* 10-bit Extended address */ 77 #define I2C_MCR_SB BIT(11) /* Extended address */ 78 #define I2C_MCR_AM GENMASK(13, 12) /* Address type */ 79 #define I2C_MCR_STOP BIT(14) /* Stop condition */ 80 #define I2C_MCR_LENGTH GENMASK(25, 15) /* Transaction length */ 81 82 /* Status register (SR) */ 83 #define I2C_SR_OP GENMASK(1, 0) /* Operation */ 84 #define I2C_SR_STATUS GENMASK(3, 2) /* controller status */ 85 #define I2C_SR_CAUSE GENMASK(6, 4) /* Abort cause */ 86 #define I2C_SR_TYPE GENMASK(8, 7) /* Receive type */ 87 #define I2C_SR_LENGTH GENMASK(19, 9) /* Transfer length */ 88 89 /* Baud-rate counter register (BRCR) */ 90 #define I2C_BRCR_BRCNT1 GENMASK(31, 16) /* Baud-rate counter 1 */ 91 #define I2C_BRCR_BRCNT2 GENMASK(15, 0) /* Baud-rate counter 2 */ 92 93 /* Interrupt mask set/clear (IMSCR) bits */ 94 #define I2C_IT_TXFE BIT(0) 95 #define I2C_IT_TXFNE BIT(1) 96 #define I2C_IT_TXFF BIT(2) 97 #define I2C_IT_TXFOVR BIT(3) 98 #define I2C_IT_RXFE BIT(4) 99 #define I2C_IT_RXFNF BIT(5) 100 #define I2C_IT_RXFF BIT(6) 101 #define I2C_IT_RFSR BIT(16) 102 #define I2C_IT_RFSE BIT(17) 103 #define I2C_IT_WTSR BIT(18) 104 #define I2C_IT_MTD BIT(19) 105 #define I2C_IT_STD BIT(20) 106 #define I2C_IT_MAL BIT(24) 107 #define I2C_IT_BERR BIT(25) 108 #define I2C_IT_MTDWS BIT(28) 109 110 /* some bits in ICR are reserved */ 111 #define I2C_CLEAR_ALL_INTS 0x131f007f 112 113 /* maximum threshold value */ 114 #define MAX_I2C_FIFO_THRESHOLD 15 115 116 enum i2c_freq_mode { 117 I2C_FREQ_MODE_STANDARD, /* up to 100 Kb/s */ 118 I2C_FREQ_MODE_FAST, /* up to 400 Kb/s */ 119 I2C_FREQ_MODE_HIGH_SPEED, /* up to 3.4 Mb/s */ 120 I2C_FREQ_MODE_FAST_PLUS, /* up to 1 Mb/s */ 121 }; 122 123 /* Mobileye EyeQ5 offset into a shared register region (called OLB) */ 124 #define NMK_I2C_EYEQ5_OLB_IOCR2 0x0B8 125 126 enum i2c_eyeq5_speed { 127 I2C_EYEQ5_SPEED_FAST, 128 I2C_EYEQ5_SPEED_FAST_PLUS, 129 I2C_EYEQ5_SPEED_HIGH_SPEED, 130 }; 131 132 /** 133 * struct i2c_vendor_data - per-vendor variations 134 * @has_mtdws: variant has the MTDWS bit 135 * @fifodepth: variant FIFO depth 136 */ 137 struct i2c_vendor_data { 138 bool has_mtdws; 139 u32 fifodepth; 140 }; 141 142 enum i2c_status { 143 I2C_NOP, 144 I2C_ON_GOING, 145 I2C_OK, 146 I2C_ABORT 147 }; 148 149 /* operation */ 150 enum i2c_operation { 151 I2C_NO_OPERATION = 0xff, 152 I2C_WRITE = 0x00, 153 I2C_READ = 0x01 154 }; 155 156 enum i2c_operating_mode { 157 I2C_OM_SLAVE, 158 I2C_OM_MASTER, 159 I2C_OM_MASTER_OR_SLAVE, 160 }; 161 162 /** 163 * struct i2c_nmk_client - client specific data 164 * @slave_adr: 7-bit slave address 165 * @count: no. bytes to be transferred 166 * @buffer: client data buffer 167 * @xfer_bytes: bytes transferred till now 168 * @operation: current I2C operation 169 */ 170 struct i2c_nmk_client { 171 unsigned short slave_adr; 172 unsigned long count; 173 unsigned char *buffer; 174 unsigned long xfer_bytes; 175 enum i2c_operation operation; 176 }; 177 178 /** 179 * struct nmk_i2c_dev - private data structure of the controller. 180 * @vendor: vendor data for this variant. 181 * @adev: parent amba device. 182 * @adap: corresponding I2C adapter. 183 * @irq: interrupt line for the controller. 184 * @virtbase: virtual io memory area. 185 * @clk: hardware i2c block clock. 186 * @cli: holder of client specific data. 187 * @clk_freq: clock frequency for the operation mode 188 * @tft: Tx FIFO Threshold in bytes 189 * @rft: Rx FIFO Threshold in bytes 190 * @timeout_usecs: Slave response timeout 191 * @sm: speed mode 192 * @stop: stop condition. 193 * @xfer_wq: xfer done wait queue. 194 * @xfer_done: xfer done boolean. 195 * @result: controller propogated result. 196 * @has_32b_bus: controller is on a bus that only supports 32-bit accesses. 197 */ 198 struct nmk_i2c_dev { 199 struct i2c_vendor_data *vendor; 200 struct amba_device *adev; 201 struct i2c_adapter adap; 202 int irq; 203 void __iomem *virtbase; 204 struct clk *clk; 205 struct i2c_nmk_client cli; 206 u32 clk_freq; 207 unsigned char tft; 208 unsigned char rft; 209 u32 timeout_usecs; 210 enum i2c_freq_mode sm; 211 int stop; 212 struct wait_queue_head xfer_wq; 213 bool xfer_done; 214 int result; 215 bool has_32b_bus; 216 }; 217 218 /* controller's abort causes */ 219 static const char *abort_causes[] = { 220 "no ack received after address transmission", 221 "no ack received during data phase", 222 "ack received after xmission of master code", 223 "master lost arbitration", 224 "slave restarts", 225 "slave reset", 226 "overflow, maxsize is 2047 bytes", 227 }; 228 229 static inline void i2c_set_bit(void __iomem *reg, u32 mask) 230 { 231 writel(readl(reg) | mask, reg); 232 } 233 234 static inline void i2c_clr_bit(void __iomem *reg, u32 mask) 235 { 236 writel(readl(reg) & ~mask, reg); 237 } 238 239 static inline u8 nmk_i2c_readb(const struct nmk_i2c_dev *priv, 240 unsigned long reg) 241 { 242 if (priv->has_32b_bus) 243 return readl(priv->virtbase + reg); 244 else 245 return readb(priv->virtbase + reg); 246 } 247 248 static inline void nmk_i2c_writeb(const struct nmk_i2c_dev *priv, u32 val, 249 unsigned long reg) 250 { 251 if (priv->has_32b_bus) 252 writel(val, priv->virtbase + reg); 253 else 254 writeb(val, priv->virtbase + reg); 255 } 256 257 /** 258 * flush_i2c_fifo() - This function flushes the I2C FIFO 259 * @priv: private data of I2C Driver 260 * 261 * This function flushes the I2C Tx and Rx FIFOs. It returns 262 * 0 on successful flushing of FIFO 263 */ 264 static int flush_i2c_fifo(struct nmk_i2c_dev *priv) 265 { 266 #define LOOP_ATTEMPTS 10 267 ktime_t timeout; 268 int i; 269 270 /* 271 * flush the transmit and receive FIFO. The flushing 272 * operation takes several cycles before to be completed. 273 * On the completion, the I2C internal logic clears these 274 * bits, until then no one must access Tx, Rx FIFO and 275 * should poll on these bits waiting for the completion. 276 */ 277 writel((I2C_CR_FTX | I2C_CR_FRX), priv->virtbase + I2C_CR); 278 279 for (i = 0; i < LOOP_ATTEMPTS; i++) { 280 timeout = ktime_add_us(ktime_get(), priv->timeout_usecs); 281 282 while (ktime_after(timeout, ktime_get())) { 283 if ((readl(priv->virtbase + I2C_CR) & 284 (I2C_CR_FTX | I2C_CR_FRX)) == 0) 285 return 0; 286 } 287 } 288 289 dev_err(&priv->adev->dev, 290 "flushing operation timed out giving up after %d attempts", 291 LOOP_ATTEMPTS); 292 293 return -ETIMEDOUT; 294 } 295 296 /** 297 * disable_all_interrupts() - Disable all interrupts of this I2c Bus 298 * @priv: private data of I2C Driver 299 */ 300 static void disable_all_interrupts(struct nmk_i2c_dev *priv) 301 { 302 writel(0, priv->virtbase + I2C_IMSCR); 303 } 304 305 /** 306 * clear_all_interrupts() - Clear all interrupts of I2C Controller 307 * @priv: private data of I2C Driver 308 */ 309 static void clear_all_interrupts(struct nmk_i2c_dev *priv) 310 { 311 writel(I2C_CLEAR_ALL_INTS, priv->virtbase + I2C_ICR); 312 } 313 314 /** 315 * init_hw() - initialize the I2C hardware 316 * @priv: private data of I2C Driver 317 */ 318 static int init_hw(struct nmk_i2c_dev *priv) 319 { 320 int stat; 321 322 stat = flush_i2c_fifo(priv); 323 if (stat) 324 goto exit; 325 326 /* disable the controller */ 327 i2c_clr_bit(priv->virtbase + I2C_CR, I2C_CR_PE); 328 329 disable_all_interrupts(priv); 330 331 clear_all_interrupts(priv); 332 333 priv->cli.operation = I2C_NO_OPERATION; 334 335 exit: 336 return stat; 337 } 338 339 /* enable peripheral, master mode operation */ 340 #define DEFAULT_I2C_REG_CR (FIELD_PREP(I2C_CR_OM, I2C_OM_MASTER) | I2C_CR_PE) 341 342 /* grab top three bits from extended I2C addresses */ 343 #define ADR_3MSB_BITS GENMASK(9, 7) 344 345 /** 346 * load_i2c_mcr_reg() - load the MCR register 347 * @priv: private data of controller 348 * @flags: message flags 349 */ 350 static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *priv, u16 flags) 351 { 352 u32 mcr = 0; 353 unsigned short slave_adr_3msb_bits; 354 355 mcr |= FIELD_PREP(I2C_MCR_A7, priv->cli.slave_adr); 356 357 if (unlikely(flags & I2C_M_TEN)) { 358 /* 10-bit address transaction */ 359 mcr |= FIELD_PREP(I2C_MCR_AM, 2); 360 /* 361 * Get the top 3 bits. 362 * EA10 represents extended address in MCR. This includes 363 * the extension (MSB bits) of the 7 bit address loaded 364 * in A7 365 */ 366 slave_adr_3msb_bits = FIELD_GET(ADR_3MSB_BITS, 367 priv->cli.slave_adr); 368 369 mcr |= FIELD_PREP(I2C_MCR_EA10, slave_adr_3msb_bits); 370 } else { 371 /* 7-bit address transaction */ 372 mcr |= FIELD_PREP(I2C_MCR_AM, 1); 373 } 374 375 /* start byte procedure not applied */ 376 mcr |= FIELD_PREP(I2C_MCR_SB, 0); 377 378 /* check the operation, master read/write? */ 379 if (priv->cli.operation == I2C_WRITE) 380 mcr |= FIELD_PREP(I2C_MCR_OP, I2C_WRITE); 381 else 382 mcr |= FIELD_PREP(I2C_MCR_OP, I2C_READ); 383 384 /* stop or repeated start? */ 385 if (priv->stop) 386 mcr |= FIELD_PREP(I2C_MCR_STOP, 1); 387 else 388 mcr &= ~FIELD_PREP(I2C_MCR_STOP, 1); 389 390 mcr |= FIELD_PREP(I2C_MCR_LENGTH, priv->cli.count); 391 392 return mcr; 393 } 394 395 /** 396 * setup_i2c_controller() - setup the controller 397 * @priv: private data of controller 398 */ 399 static void setup_i2c_controller(struct nmk_i2c_dev *priv) 400 { 401 u32 brcr; 402 u32 i2c_clk, div; 403 u32 ns; 404 u16 slsu; 405 406 writel(0x0, priv->virtbase + I2C_CR); 407 writel(0x0, priv->virtbase + I2C_HSMCR); 408 writel(0x0, priv->virtbase + I2C_TFTR); 409 writel(0x0, priv->virtbase + I2C_RFTR); 410 writel(0x0, priv->virtbase + I2C_DMAR); 411 412 i2c_clk = clk_get_rate(priv->clk); 413 414 /* 415 * set the slsu: 416 * 417 * slsu defines the data setup time after SCL clock 418 * stretching in terms of i2c clk cycles + 1 (zero means 419 * "wait one cycle"), the needed setup time for the three 420 * modes are 250ns, 100ns, 10ns respectively. 421 * 422 * As the time for one cycle T in nanoseconds is 423 * T = (1/f) * HZ_PER_GHZ => 424 * slsu = cycles / (HZ_PER_GHZ / f) + 1 425 */ 426 ns = DIV_ROUND_UP(HZ_PER_GHZ, i2c_clk); 427 switch (priv->sm) { 428 case I2C_FREQ_MODE_FAST: 429 case I2C_FREQ_MODE_FAST_PLUS: 430 slsu = DIV_ROUND_UP(100, ns); /* Fast */ 431 break; 432 case I2C_FREQ_MODE_HIGH_SPEED: 433 slsu = DIV_ROUND_UP(10, ns); /* High */ 434 break; 435 case I2C_FREQ_MODE_STANDARD: 436 default: 437 slsu = DIV_ROUND_UP(250, ns); /* Standard */ 438 break; 439 } 440 slsu += 1; 441 442 dev_dbg(&priv->adev->dev, "calculated SLSU = %04x\n", slsu); 443 writel(FIELD_PREP(I2C_SCR_SLSU, slsu), priv->virtbase + I2C_SCR); 444 445 /* 446 * The spec says, in case of std. mode the divider is 447 * 2 whereas it is 3 for fast and fastplus mode of 448 * operation. 449 */ 450 div = (priv->clk_freq > I2C_MAX_STANDARD_MODE_FREQ) ? 3 : 2; 451 452 /* 453 * generate the mask for baud rate counters. The controller 454 * has two baud rate counters. One is used for High speed 455 * operation, and the other is for std, fast mode, fast mode 456 * plus operation. 457 * 458 * BRCR is a clock divider amount. Pick highest value that 459 * leads to rate strictly below target. Eg when asking for 460 * 400kHz you want a bus rate <=400kHz (and not >=400kHz). 461 */ 462 brcr = DIV_ROUND_UP(i2c_clk, priv->clk_freq * div); 463 464 if (priv->sm == I2C_FREQ_MODE_HIGH_SPEED) 465 brcr = FIELD_PREP(I2C_BRCR_BRCNT1, brcr); 466 else 467 brcr = FIELD_PREP(I2C_BRCR_BRCNT2, brcr); 468 469 /* set the baud rate counter register */ 470 writel(brcr, priv->virtbase + I2C_BRCR); 471 472 /* set the speed mode */ 473 writel(FIELD_PREP(I2C_CR_SM, priv->sm), priv->virtbase + I2C_CR); 474 475 /* set the Tx and Rx FIFO threshold */ 476 writel(priv->tft, priv->virtbase + I2C_TFTR); 477 writel(priv->rft, priv->virtbase + I2C_RFTR); 478 } 479 480 static bool nmk_i2c_wait_xfer_done(struct nmk_i2c_dev *priv) 481 { 482 if (priv->timeout_usecs < jiffies_to_usecs(1)) { 483 unsigned long timeout_usecs = priv->timeout_usecs; 484 ktime_t timeout = ktime_set(0, timeout_usecs * NSEC_PER_USEC); 485 486 wait_event_hrtimeout(priv->xfer_wq, priv->xfer_done, timeout); 487 } else { 488 unsigned long timeout = usecs_to_jiffies(priv->timeout_usecs); 489 490 wait_event_timeout(priv->xfer_wq, priv->xfer_done, timeout); 491 } 492 493 return priv->xfer_done; 494 } 495 496 /** 497 * read_i2c() - Read from I2C client device 498 * @priv: private data of I2C Driver 499 * @flags: message flags 500 * 501 * This function reads from i2c client device when controller is in 502 * master mode. There is a completion timeout. If there is no transfer 503 * before timeout error is returned. 504 */ 505 static int read_i2c(struct nmk_i2c_dev *priv, u16 flags) 506 { 507 u32 mcr, irq_mask; 508 int status = 0; 509 bool xfer_done; 510 511 mcr = load_i2c_mcr_reg(priv, flags); 512 writel(mcr, priv->virtbase + I2C_MCR); 513 514 /* load the current CR value */ 515 writel(readl(priv->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, 516 priv->virtbase + I2C_CR); 517 518 /* enable the controller */ 519 i2c_set_bit(priv->virtbase + I2C_CR, I2C_CR_PE); 520 521 init_waitqueue_head(&priv->xfer_wq); 522 priv->xfer_done = false; 523 524 /* enable interrupts by setting the mask */ 525 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF | 526 I2C_IT_MAL | I2C_IT_BERR); 527 528 if (priv->stop || !priv->vendor->has_mtdws) 529 irq_mask |= I2C_IT_MTD; 530 else 531 irq_mask |= I2C_IT_MTDWS; 532 533 irq_mask &= I2C_CLEAR_ALL_INTS; 534 535 writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask, 536 priv->virtbase + I2C_IMSCR); 537 538 xfer_done = nmk_i2c_wait_xfer_done(priv); 539 540 if (!xfer_done) 541 status = -ETIMEDOUT; 542 543 return status; 544 } 545 546 static void fill_tx_fifo(struct nmk_i2c_dev *priv, int no_bytes) 547 { 548 int count; 549 550 for (count = (no_bytes - 2); 551 (count > 0) && 552 (priv->cli.count != 0); 553 count--) { 554 /* write to the Tx FIFO */ 555 nmk_i2c_writeb(priv, *priv->cli.buffer, I2C_TFR); 556 priv->cli.buffer++; 557 priv->cli.count--; 558 priv->cli.xfer_bytes++; 559 } 560 561 } 562 563 /** 564 * write_i2c() - Write data to I2C client. 565 * @priv: private data of I2C Driver 566 * @flags: message flags 567 * 568 * This function writes data to I2C client 569 */ 570 static int write_i2c(struct nmk_i2c_dev *priv, u16 flags) 571 { 572 u32 mcr, irq_mask; 573 u32 status = 0; 574 bool xfer_done; 575 576 mcr = load_i2c_mcr_reg(priv, flags); 577 578 writel(mcr, priv->virtbase + I2C_MCR); 579 580 /* load the current CR value */ 581 writel(readl(priv->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, 582 priv->virtbase + I2C_CR); 583 584 /* enable the controller */ 585 i2c_set_bit(priv->virtbase + I2C_CR, I2C_CR_PE); 586 587 init_waitqueue_head(&priv->xfer_wq); 588 priv->xfer_done = false; 589 590 /* enable interrupts by settings the masks */ 591 irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR); 592 593 /* Fill the TX FIFO with transmit data */ 594 fill_tx_fifo(priv, MAX_I2C_FIFO_THRESHOLD); 595 596 if (priv->cli.count != 0) 597 irq_mask |= I2C_IT_TXFNE; 598 599 /* 600 * check if we want to transfer a single or multiple bytes, if so 601 * set the MTDWS bit (Master Transaction Done Without Stop) 602 * to start repeated start operation 603 */ 604 if (priv->stop || !priv->vendor->has_mtdws) 605 irq_mask |= I2C_IT_MTD; 606 else 607 irq_mask |= I2C_IT_MTDWS; 608 609 irq_mask &= I2C_CLEAR_ALL_INTS; 610 611 writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask, 612 priv->virtbase + I2C_IMSCR); 613 614 xfer_done = nmk_i2c_wait_xfer_done(priv); 615 616 if (!xfer_done) { 617 /* Controller timed out */ 618 dev_err(&priv->adev->dev, "write to slave 0x%x timed out\n", 619 priv->cli.slave_adr); 620 status = -ETIMEDOUT; 621 } 622 623 return status; 624 } 625 626 /** 627 * nmk_i2c_xfer_one() - transmit a single I2C message 628 * @priv: device with a message encoded into it 629 * @flags: message flags 630 */ 631 static int nmk_i2c_xfer_one(struct nmk_i2c_dev *priv, u16 flags) 632 { 633 int status; 634 635 if (flags & I2C_M_RD) { 636 /* read operation */ 637 priv->cli.operation = I2C_READ; 638 status = read_i2c(priv, flags); 639 } else { 640 /* write operation */ 641 priv->cli.operation = I2C_WRITE; 642 status = write_i2c(priv, flags); 643 } 644 645 if (status || priv->result) { 646 u32 i2c_sr; 647 u32 cause; 648 649 i2c_sr = readl(priv->virtbase + I2C_SR); 650 if (FIELD_GET(I2C_SR_STATUS, i2c_sr) == I2C_ABORT) { 651 cause = FIELD_GET(I2C_SR_CAUSE, i2c_sr); 652 dev_err(&priv->adev->dev, "%s\n", 653 cause >= ARRAY_SIZE(abort_causes) ? 654 "unknown reason" : 655 abort_causes[cause]); 656 } 657 658 init_hw(priv); 659 660 status = status ? status : priv->result; 661 } 662 663 return status; 664 } 665 666 /** 667 * nmk_i2c_xfer() - I2C transfer function used by kernel framework 668 * @i2c_adap: Adapter pointer to the controller 669 * @msgs: Pointer to data to be written. 670 * @num_msgs: Number of messages to be executed 671 * 672 * This is the function called by the generic kernel i2c_transfer() 673 * or i2c_smbus...() API calls. Note that this code is protected by the 674 * semaphore set in the kernel i2c_transfer() function. 675 * 676 * NOTE: 677 * READ TRANSFER : We impose a restriction of the first message to be the 678 * index message for any read transaction. 679 * - a no index is coded as '0', 680 * - 2byte big endian index is coded as '3' 681 * !!! msg[0].buf holds the actual index. 682 * This is compatible with generic messages of smbus emulator 683 * that send a one byte index. 684 * eg. a I2C transation to read 2 bytes from index 0 685 * idx = 0; 686 * msg[0].addr = client->addr; 687 * msg[0].flags = 0x0; 688 * msg[0].len = 1; 689 * msg[0].buf = &idx; 690 * 691 * msg[1].addr = client->addr; 692 * msg[1].flags = I2C_M_RD; 693 * msg[1].len = 2; 694 * msg[1].buf = rd_buff 695 * i2c_transfer(adap, msg, 2); 696 * 697 * WRITE TRANSFER : The I2C standard interface interprets all data as payload. 698 * If you want to emulate an SMBUS write transaction put the 699 * index as first byte(or first and second) in the payload. 700 * eg. a I2C transation to write 2 bytes from index 1 701 * wr_buff[0] = 0x1; 702 * wr_buff[1] = 0x23; 703 * wr_buff[2] = 0x46; 704 * msg[0].flags = 0x0; 705 * msg[0].len = 3; 706 * msg[0].buf = wr_buff; 707 * i2c_transfer(adap, msg, 1); 708 * 709 * To read or write a block of data (multiple bytes) using SMBUS emulation 710 * please use the i2c_smbus_read_i2c_block_data() 711 * or i2c_smbus_write_i2c_block_data() API 712 */ 713 static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap, 714 struct i2c_msg msgs[], int num_msgs) 715 { 716 int status = 0; 717 int i; 718 struct nmk_i2c_dev *priv = i2c_get_adapdata(i2c_adap); 719 int j; 720 721 pm_runtime_get_sync(&priv->adev->dev); 722 723 /* Attempt three times to send the message queue */ 724 for (j = 0; j < 3; j++) { 725 /* setup the i2c controller */ 726 setup_i2c_controller(priv); 727 728 for (i = 0; i < num_msgs; i++) { 729 priv->cli.slave_adr = msgs[i].addr; 730 priv->cli.buffer = msgs[i].buf; 731 priv->cli.count = msgs[i].len; 732 priv->stop = (i < (num_msgs - 1)) ? 0 : 1; 733 priv->result = 0; 734 735 status = nmk_i2c_xfer_one(priv, msgs[i].flags); 736 if (status != 0) 737 break; 738 } 739 if (status == 0) 740 break; 741 } 742 743 pm_runtime_put_sync(&priv->adev->dev); 744 745 /* return the no. messages processed */ 746 if (status) 747 return status; 748 else 749 return num_msgs; 750 } 751 752 /** 753 * disable_interrupts() - disable the interrupts 754 * @priv: private data of controller 755 * @irq: interrupt number 756 */ 757 static int disable_interrupts(struct nmk_i2c_dev *priv, u32 irq) 758 { 759 irq &= I2C_CLEAR_ALL_INTS; 760 writel(readl(priv->virtbase + I2C_IMSCR) & ~irq, 761 priv->virtbase + I2C_IMSCR); 762 return 0; 763 } 764 765 /** 766 * i2c_irq_handler() - interrupt routine 767 * @irq: interrupt number 768 * @arg: data passed to the handler 769 * 770 * This is the interrupt handler for the i2c driver. Currently 771 * it handles the major interrupts like Rx & Tx FIFO management 772 * interrupts, master transaction interrupts, arbitration and 773 * bus error interrupts. The rest of the interrupts are treated as 774 * unhandled. 775 */ 776 static irqreturn_t i2c_irq_handler(int irq, void *arg) 777 { 778 struct nmk_i2c_dev *priv = arg; 779 struct device *dev = &priv->adev->dev; 780 u32 tft, rft; 781 u32 count; 782 u32 misr, src; 783 784 /* load Tx FIFO and Rx FIFO threshold values */ 785 tft = readl(priv->virtbase + I2C_TFTR); 786 rft = readl(priv->virtbase + I2C_RFTR); 787 788 /* read interrupt status register */ 789 misr = readl(priv->virtbase + I2C_MISR); 790 791 src = __ffs(misr); 792 switch (BIT(src)) { 793 794 /* Transmit FIFO nearly empty interrupt */ 795 case I2C_IT_TXFNE: 796 { 797 if (priv->cli.operation == I2C_READ) { 798 /* 799 * in read operation why do we care for writing? 800 * so disable the Transmit FIFO interrupt 801 */ 802 disable_interrupts(priv, I2C_IT_TXFNE); 803 } else { 804 fill_tx_fifo(priv, (MAX_I2C_FIFO_THRESHOLD - tft)); 805 /* 806 * if done, close the transfer by disabling the 807 * corresponding TXFNE interrupt 808 */ 809 if (priv->cli.count == 0) 810 disable_interrupts(priv, I2C_IT_TXFNE); 811 } 812 } 813 break; 814 815 /* 816 * Rx FIFO nearly full interrupt. 817 * This is set when the numer of entries in Rx FIFO is 818 * greater or equal than the threshold value programmed 819 * in RFT 820 */ 821 case I2C_IT_RXFNF: 822 for (count = rft; count > 0; count--) { 823 /* Read the Rx FIFO */ 824 *priv->cli.buffer = nmk_i2c_readb(priv, I2C_RFR); 825 priv->cli.buffer++; 826 } 827 priv->cli.count -= rft; 828 priv->cli.xfer_bytes += rft; 829 break; 830 831 /* Rx FIFO full */ 832 case I2C_IT_RXFF: 833 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) { 834 *priv->cli.buffer = nmk_i2c_readb(priv, I2C_RFR); 835 priv->cli.buffer++; 836 } 837 priv->cli.count -= MAX_I2C_FIFO_THRESHOLD; 838 priv->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD; 839 break; 840 841 /* Master Transaction Done with/without stop */ 842 case I2C_IT_MTD: 843 case I2C_IT_MTDWS: 844 if (priv->cli.operation == I2C_READ) { 845 while (!(readl(priv->virtbase + I2C_RISR) 846 & I2C_IT_RXFE)) { 847 if (priv->cli.count == 0) 848 break; 849 *priv->cli.buffer = 850 nmk_i2c_readb(priv, I2C_RFR); 851 priv->cli.buffer++; 852 priv->cli.count--; 853 priv->cli.xfer_bytes++; 854 } 855 } 856 857 disable_all_interrupts(priv); 858 clear_all_interrupts(priv); 859 860 if (priv->cli.count) { 861 priv->result = -EIO; 862 dev_err(dev, "%lu bytes still remain to be xfered\n", 863 priv->cli.count); 864 init_hw(priv); 865 } 866 priv->xfer_done = true; 867 wake_up(&priv->xfer_wq); 868 869 870 break; 871 872 /* Master Arbitration lost interrupt */ 873 case I2C_IT_MAL: 874 priv->result = -EIO; 875 init_hw(priv); 876 877 i2c_set_bit(priv->virtbase + I2C_ICR, I2C_IT_MAL); 878 priv->xfer_done = true; 879 wake_up(&priv->xfer_wq); 880 881 882 break; 883 884 /* 885 * Bus Error interrupt. 886 * This happens when an unexpected start/stop condition occurs 887 * during the transaction. 888 */ 889 case I2C_IT_BERR: 890 { 891 u32 sr; 892 893 sr = readl(priv->virtbase + I2C_SR); 894 priv->result = -EIO; 895 if (FIELD_GET(I2C_SR_STATUS, sr) == I2C_ABORT) 896 init_hw(priv); 897 898 i2c_set_bit(priv->virtbase + I2C_ICR, I2C_IT_BERR); 899 priv->xfer_done = true; 900 wake_up(&priv->xfer_wq); 901 902 } 903 break; 904 905 /* 906 * Tx FIFO overrun interrupt. 907 * This is set when a write operation in Tx FIFO is performed and 908 * the Tx FIFO is full. 909 */ 910 case I2C_IT_TXFOVR: 911 priv->result = -EIO; 912 init_hw(priv); 913 914 dev_err(dev, "Tx Fifo Over run\n"); 915 priv->xfer_done = true; 916 wake_up(&priv->xfer_wq); 917 918 919 break; 920 921 /* unhandled interrupts by this driver - TODO*/ 922 case I2C_IT_TXFE: 923 case I2C_IT_TXFF: 924 case I2C_IT_RXFE: 925 case I2C_IT_RFSR: 926 case I2C_IT_RFSE: 927 case I2C_IT_WTSR: 928 case I2C_IT_STD: 929 dev_err(dev, "unhandled Interrupt\n"); 930 break; 931 default: 932 dev_err(dev, "spurious Interrupt..\n"); 933 break; 934 } 935 936 return IRQ_HANDLED; 937 } 938 939 static int nmk_i2c_suspend_late(struct device *dev) 940 { 941 int ret; 942 943 ret = pm_runtime_force_suspend(dev); 944 if (ret) 945 return ret; 946 947 pinctrl_pm_select_sleep_state(dev); 948 return 0; 949 } 950 951 static int nmk_i2c_resume_early(struct device *dev) 952 { 953 return pm_runtime_force_resume(dev); 954 } 955 956 static int nmk_i2c_runtime_suspend(struct device *dev) 957 { 958 struct amba_device *adev = to_amba_device(dev); 959 struct nmk_i2c_dev *priv = amba_get_drvdata(adev); 960 961 clk_disable_unprepare(priv->clk); 962 pinctrl_pm_select_idle_state(dev); 963 return 0; 964 } 965 966 static int nmk_i2c_runtime_resume(struct device *dev) 967 { 968 struct amba_device *adev = to_amba_device(dev); 969 struct nmk_i2c_dev *priv = amba_get_drvdata(adev); 970 int ret; 971 972 ret = clk_prepare_enable(priv->clk); 973 if (ret) { 974 dev_err(dev, "can't prepare_enable clock\n"); 975 return ret; 976 } 977 978 pinctrl_pm_select_default_state(dev); 979 980 ret = init_hw(priv); 981 if (ret) { 982 clk_disable_unprepare(priv->clk); 983 pinctrl_pm_select_idle_state(dev); 984 } 985 986 return ret; 987 } 988 989 static const struct dev_pm_ops nmk_i2c_pm = { 990 LATE_SYSTEM_SLEEP_PM_OPS(nmk_i2c_suspend_late, nmk_i2c_resume_early) 991 RUNTIME_PM_OPS(nmk_i2c_runtime_suspend, nmk_i2c_runtime_resume, NULL) 992 }; 993 994 static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap) 995 { 996 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR; 997 } 998 999 static const struct i2c_algorithm nmk_i2c_algo = { 1000 .xfer = nmk_i2c_xfer, 1001 .functionality = nmk_i2c_functionality 1002 }; 1003 1004 static void nmk_i2c_of_probe(struct device_node *np, 1005 struct nmk_i2c_dev *priv) 1006 { 1007 u32 timeout_usecs; 1008 1009 /* Default to 100 kHz if no frequency is given in the node */ 1010 if (of_property_read_u32(np, "clock-frequency", &priv->clk_freq)) 1011 priv->clk_freq = I2C_MAX_STANDARD_MODE_FREQ; 1012 1013 if (priv->clk_freq <= I2C_MAX_STANDARD_MODE_FREQ) 1014 priv->sm = I2C_FREQ_MODE_STANDARD; 1015 else if (priv->clk_freq <= I2C_MAX_FAST_MODE_FREQ) 1016 priv->sm = I2C_FREQ_MODE_FAST; 1017 else if (priv->clk_freq <= I2C_MAX_FAST_MODE_PLUS_FREQ) 1018 priv->sm = I2C_FREQ_MODE_FAST_PLUS; 1019 else 1020 priv->sm = I2C_FREQ_MODE_HIGH_SPEED; 1021 priv->tft = 1; /* Tx FIFO threshold */ 1022 priv->rft = 8; /* Rx FIFO threshold */ 1023 1024 /* Slave response timeout */ 1025 if (!of_property_read_u32(np, "i2c-transfer-timeout-us", &timeout_usecs)) 1026 priv->timeout_usecs = timeout_usecs; 1027 else 1028 priv->timeout_usecs = 200 * USEC_PER_MSEC; 1029 } 1030 1031 static const unsigned int nmk_i2c_eyeq5_masks[] = { 1032 GENMASK(5, 4), 1033 GENMASK(7, 6), 1034 GENMASK(9, 8), 1035 GENMASK(11, 10), 1036 GENMASK(13, 12), 1037 }; 1038 1039 static int nmk_i2c_eyeq5_probe(struct nmk_i2c_dev *priv) 1040 { 1041 struct device *dev = &priv->adev->dev; 1042 struct device_node *np = dev->of_node; 1043 unsigned int mask, speed_mode; 1044 struct regmap *olb; 1045 unsigned int id; 1046 1047 olb = syscon_regmap_lookup_by_phandle_args(np, "mobileye,olb", 1, &id); 1048 if (IS_ERR(olb)) 1049 return PTR_ERR(olb); 1050 if (id >= ARRAY_SIZE(nmk_i2c_eyeq5_masks)) 1051 return -ENOENT; 1052 1053 if (priv->clk_freq <= 400000) 1054 speed_mode = I2C_EYEQ5_SPEED_FAST; 1055 else if (priv->clk_freq <= 1000000) 1056 speed_mode = I2C_EYEQ5_SPEED_FAST_PLUS; 1057 else 1058 speed_mode = I2C_EYEQ5_SPEED_HIGH_SPEED; 1059 1060 mask = nmk_i2c_eyeq5_masks[id]; 1061 regmap_update_bits(olb, NMK_I2C_EYEQ5_OLB_IOCR2, 1062 mask, speed_mode << __fls(mask)); 1063 1064 return 0; 1065 } 1066 1067 #define NMK_I2C_EYEQ_FLAG_32B_BUS BIT(0) 1068 #define NMK_I2C_EYEQ_FLAG_IS_EYEQ5 BIT(1) 1069 1070 static const struct of_device_id nmk_i2c_eyeq_match_table[] = { 1071 { 1072 .compatible = "mobileye,eyeq5-i2c", 1073 .data = (void *)(NMK_I2C_EYEQ_FLAG_32B_BUS | NMK_I2C_EYEQ_FLAG_IS_EYEQ5), 1074 }, 1075 { 1076 .compatible = "mobileye,eyeq6h-i2c", 1077 .data = (void *)NMK_I2C_EYEQ_FLAG_32B_BUS, 1078 }, 1079 { /* sentinel */ } 1080 }; 1081 1082 static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id) 1083 { 1084 struct i2c_vendor_data *vendor = id->data; 1085 u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1; 1086 struct device_node *np = adev->dev.of_node; 1087 const struct of_device_id *match; 1088 struct device *dev = &adev->dev; 1089 unsigned long match_flags = 0; 1090 struct nmk_i2c_dev *priv; 1091 struct i2c_adapter *adap; 1092 int ret = 0; 1093 1094 /* 1095 * We do not want to attach a .of_match_table to our amba driver. 1096 * Do not convert to device_get_match_data(). 1097 */ 1098 match = of_match_device(nmk_i2c_eyeq_match_table, dev); 1099 if (match) 1100 match_flags = (unsigned long)match->data; 1101 1102 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1103 if (!priv) 1104 return -ENOMEM; 1105 1106 priv->vendor = vendor; 1107 priv->adev = adev; 1108 priv->has_32b_bus = match_flags & NMK_I2C_EYEQ_FLAG_32B_BUS; 1109 nmk_i2c_of_probe(np, priv); 1110 1111 if (match_flags & NMK_I2C_EYEQ_FLAG_IS_EYEQ5) { 1112 ret = nmk_i2c_eyeq5_probe(priv); 1113 if (ret) 1114 return dev_err_probe(dev, ret, "failed OLB lookup\n"); 1115 } 1116 1117 if (priv->tft > max_fifo_threshold) { 1118 dev_warn(dev, "requested TX FIFO threshold %u, adjusted down to %u\n", 1119 priv->tft, max_fifo_threshold); 1120 priv->tft = max_fifo_threshold; 1121 } 1122 1123 if (priv->rft > max_fifo_threshold) { 1124 dev_warn(dev, "requested RX FIFO threshold %u, adjusted down to %u\n", 1125 priv->rft, max_fifo_threshold); 1126 priv->rft = max_fifo_threshold; 1127 } 1128 1129 amba_set_drvdata(adev, priv); 1130 1131 priv->virtbase = devm_ioremap(dev, adev->res.start, 1132 resource_size(&adev->res)); 1133 if (!priv->virtbase) 1134 return -ENOMEM; 1135 1136 priv->irq = adev->irq[0]; 1137 ret = devm_request_irq(dev, priv->irq, i2c_irq_handler, 0, 1138 DRIVER_NAME, priv); 1139 if (ret) 1140 return dev_err_probe(dev, ret, 1141 "cannot claim the irq %d\n", priv->irq); 1142 1143 priv->clk = devm_clk_get_enabled(dev, NULL); 1144 if (IS_ERR(priv->clk)) 1145 return dev_err_probe(dev, PTR_ERR(priv->clk), 1146 "could enable i2c clock\n"); 1147 1148 init_hw(priv); 1149 1150 adap = &priv->adap; 1151 adap->dev.of_node = np; 1152 adap->dev.parent = dev; 1153 adap->owner = THIS_MODULE; 1154 adap->class = I2C_CLASS_DEPRECATED; 1155 adap->algo = &nmk_i2c_algo; 1156 adap->timeout = usecs_to_jiffies(priv->timeout_usecs); 1157 snprintf(adap->name, sizeof(adap->name), 1158 "Nomadik I2C at %pR", &adev->res); 1159 1160 i2c_set_adapdata(adap, priv); 1161 1162 dev_info(dev, 1163 "initialize %s on virtual base %p\n", 1164 adap->name, priv->virtbase); 1165 1166 ret = i2c_add_adapter(adap); 1167 if (ret) 1168 return ret; 1169 1170 pm_runtime_put(dev); 1171 1172 return 0; 1173 } 1174 1175 static void nmk_i2c_remove(struct amba_device *adev) 1176 { 1177 struct nmk_i2c_dev *priv = amba_get_drvdata(adev); 1178 1179 i2c_del_adapter(&priv->adap); 1180 flush_i2c_fifo(priv); 1181 disable_all_interrupts(priv); 1182 clear_all_interrupts(priv); 1183 /* disable the controller */ 1184 i2c_clr_bit(priv->virtbase + I2C_CR, I2C_CR_PE); 1185 } 1186 1187 static struct i2c_vendor_data vendor_stn8815 = { 1188 .has_mtdws = false, 1189 .fifodepth = 16, /* Guessed from TFTR/RFTR = 7 */ 1190 }; 1191 1192 static struct i2c_vendor_data vendor_db8500 = { 1193 .has_mtdws = true, 1194 .fifodepth = 32, /* Guessed from TFTR/RFTR = 15 */ 1195 }; 1196 1197 static const struct amba_id nmk_i2c_ids[] = { 1198 { 1199 .id = 0x00180024, 1200 .mask = 0x00ffffff, 1201 .data = &vendor_stn8815, 1202 }, 1203 { 1204 .id = 0x00380024, 1205 .mask = 0x00ffffff, 1206 .data = &vendor_db8500, 1207 }, 1208 {}, 1209 }; 1210 1211 MODULE_DEVICE_TABLE(amba, nmk_i2c_ids); 1212 1213 static struct amba_driver nmk_i2c_driver = { 1214 .drv = { 1215 .name = DRIVER_NAME, 1216 .pm = pm_ptr(&nmk_i2c_pm), 1217 }, 1218 .id_table = nmk_i2c_ids, 1219 .probe = nmk_i2c_probe, 1220 .remove = nmk_i2c_remove, 1221 }; 1222 1223 static int __init nmk_i2c_init(void) 1224 { 1225 return amba_driver_register(&nmk_i2c_driver); 1226 } 1227 1228 static void __exit nmk_i2c_exit(void) 1229 { 1230 amba_driver_unregister(&nmk_i2c_driver); 1231 } 1232 1233 subsys_initcall(nmk_i2c_init); 1234 module_exit(nmk_i2c_exit); 1235 1236 MODULE_AUTHOR("Sachin Verma"); 1237 MODULE_AUTHOR("Srinidhi KASAGAR"); 1238 MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver"); 1239 MODULE_LICENSE("GPL"); 1240