1 /* 2 * Copyright (C) 2009 ST-Ericsson SA 3 * Copyright (C) 2009 STMicroelectronics 4 * 5 * I2C master mode controller driver, used in Nomadik 8815 6 * and Ux500 platforms. 7 * 8 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> 9 * Author: Sachin Verma <sachin.verma@st.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2, as 13 * published by the Free Software Foundation. 14 */ 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/amba/bus.h> 18 #include <linux/atomic.h> 19 #include <linux/slab.h> 20 #include <linux/interrupt.h> 21 #include <linux/i2c.h> 22 #include <linux/err.h> 23 #include <linux/clk.h> 24 #include <linux/io.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/platform_data/i2c-nomadik.h> 28 29 #define DRIVER_NAME "nmk-i2c" 30 31 /* I2C Controller register offsets */ 32 #define I2C_CR (0x000) 33 #define I2C_SCR (0x004) 34 #define I2C_HSMCR (0x008) 35 #define I2C_MCR (0x00C) 36 #define I2C_TFR (0x010) 37 #define I2C_SR (0x014) 38 #define I2C_RFR (0x018) 39 #define I2C_TFTR (0x01C) 40 #define I2C_RFTR (0x020) 41 #define I2C_DMAR (0x024) 42 #define I2C_BRCR (0x028) 43 #define I2C_IMSCR (0x02C) 44 #define I2C_RISR (0x030) 45 #define I2C_MISR (0x034) 46 #define I2C_ICR (0x038) 47 48 /* Control registers */ 49 #define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */ 50 #define I2C_CR_OM (0x3 << 1) /* Operating mode */ 51 #define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */ 52 #define I2C_CR_SM (0x3 << 4) /* Speed mode */ 53 #define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */ 54 #define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */ 55 #define I2C_CR_FRX (0x1 << 8) /* Flush Receive */ 56 #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */ 57 #define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */ 58 #define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */ 59 #define I2C_CR_LM (0x1 << 12) /* Loopback mode */ 60 #define I2C_CR_FON (0x3 << 13) /* Filtering on */ 61 #define I2C_CR_FS (0x3 << 15) /* Force stop enable */ 62 63 /* Master controller (MCR) register */ 64 #define I2C_MCR_OP (0x1 << 0) /* Operation */ 65 #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */ 66 #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */ 67 #define I2C_MCR_SB (0x1 << 11) /* Extended address */ 68 #define I2C_MCR_AM (0x3 << 12) /* Address type */ 69 #define I2C_MCR_STOP (0x1 << 14) /* Stop condition */ 70 #define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */ 71 72 /* Status register (SR) */ 73 #define I2C_SR_OP (0x3 << 0) /* Operation */ 74 #define I2C_SR_STATUS (0x3 << 2) /* controller status */ 75 #define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */ 76 #define I2C_SR_TYPE (0x3 << 7) /* Receive type */ 77 #define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */ 78 79 /* Interrupt mask set/clear (IMSCR) bits */ 80 #define I2C_IT_TXFE (0x1 << 0) 81 #define I2C_IT_TXFNE (0x1 << 1) 82 #define I2C_IT_TXFF (0x1 << 2) 83 #define I2C_IT_TXFOVR (0x1 << 3) 84 #define I2C_IT_RXFE (0x1 << 4) 85 #define I2C_IT_RXFNF (0x1 << 5) 86 #define I2C_IT_RXFF (0x1 << 6) 87 #define I2C_IT_RFSR (0x1 << 16) 88 #define I2C_IT_RFSE (0x1 << 17) 89 #define I2C_IT_WTSR (0x1 << 18) 90 #define I2C_IT_MTD (0x1 << 19) 91 #define I2C_IT_STD (0x1 << 20) 92 #define I2C_IT_MAL (0x1 << 24) 93 #define I2C_IT_BERR (0x1 << 25) 94 #define I2C_IT_MTDWS (0x1 << 28) 95 96 #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask)) 97 98 /* some bits in ICR are reserved */ 99 #define I2C_CLEAR_ALL_INTS 0x131f007f 100 101 /* first three msb bits are reserved */ 102 #define IRQ_MASK(mask) (mask & 0x1fffffff) 103 104 /* maximum threshold value */ 105 #define MAX_I2C_FIFO_THRESHOLD 15 106 107 enum i2c_status { 108 I2C_NOP, 109 I2C_ON_GOING, 110 I2C_OK, 111 I2C_ABORT 112 }; 113 114 /* operation */ 115 enum i2c_operation { 116 I2C_NO_OPERATION = 0xff, 117 I2C_WRITE = 0x00, 118 I2C_READ = 0x01 119 }; 120 121 /** 122 * struct i2c_nmk_client - client specific data 123 * @slave_adr: 7-bit slave address 124 * @count: no. bytes to be transferred 125 * @buffer: client data buffer 126 * @xfer_bytes: bytes transferred till now 127 * @operation: current I2C operation 128 */ 129 struct i2c_nmk_client { 130 unsigned short slave_adr; 131 unsigned long count; 132 unsigned char *buffer; 133 unsigned long xfer_bytes; 134 enum i2c_operation operation; 135 }; 136 137 /** 138 * struct nmk_i2c_dev - private data structure of the controller. 139 * @adev: parent amba device. 140 * @adap: corresponding I2C adapter. 141 * @irq: interrupt line for the controller. 142 * @virtbase: virtual io memory area. 143 * @clk: hardware i2c block clock. 144 * @cfg: machine provided controller configuration. 145 * @cli: holder of client specific data. 146 * @stop: stop condition. 147 * @xfer_complete: acknowledge completion for a I2C message. 148 * @result: controller propogated result. 149 * @regulator: pointer to i2c regulator. 150 * @busy: Busy doing transfer. 151 */ 152 struct nmk_i2c_dev { 153 struct amba_device *adev; 154 struct i2c_adapter adap; 155 int irq; 156 void __iomem *virtbase; 157 struct clk *clk; 158 struct nmk_i2c_controller cfg; 159 struct i2c_nmk_client cli; 160 int stop; 161 struct completion xfer_complete; 162 int result; 163 struct regulator *regulator; 164 bool busy; 165 }; 166 167 /* controller's abort causes */ 168 static const char *abort_causes[] = { 169 "no ack received after address transmission", 170 "no ack received during data phase", 171 "ack received after xmission of master code", 172 "master lost arbitration", 173 "slave restarts", 174 "slave reset", 175 "overflow, maxsize is 2047 bytes", 176 }; 177 178 static inline void i2c_set_bit(void __iomem *reg, u32 mask) 179 { 180 writel(readl(reg) | mask, reg); 181 } 182 183 static inline void i2c_clr_bit(void __iomem *reg, u32 mask) 184 { 185 writel(readl(reg) & ~mask, reg); 186 } 187 188 /** 189 * flush_i2c_fifo() - This function flushes the I2C FIFO 190 * @dev: private data of I2C Driver 191 * 192 * This function flushes the I2C Tx and Rx FIFOs. It returns 193 * 0 on successful flushing of FIFO 194 */ 195 static int flush_i2c_fifo(struct nmk_i2c_dev *dev) 196 { 197 #define LOOP_ATTEMPTS 10 198 int i; 199 unsigned long timeout; 200 201 /* 202 * flush the transmit and receive FIFO. The flushing 203 * operation takes several cycles before to be completed. 204 * On the completion, the I2C internal logic clears these 205 * bits, until then no one must access Tx, Rx FIFO and 206 * should poll on these bits waiting for the completion. 207 */ 208 writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR); 209 210 for (i = 0; i < LOOP_ATTEMPTS; i++) { 211 timeout = jiffies + dev->adap.timeout; 212 213 while (!time_after(jiffies, timeout)) { 214 if ((readl(dev->virtbase + I2C_CR) & 215 (I2C_CR_FTX | I2C_CR_FRX)) == 0) 216 return 0; 217 } 218 } 219 220 dev_err(&dev->adev->dev, 221 "flushing operation timed out giving up after %d attempts", 222 LOOP_ATTEMPTS); 223 224 return -ETIMEDOUT; 225 } 226 227 /** 228 * disable_all_interrupts() - Disable all interrupts of this I2c Bus 229 * @dev: private data of I2C Driver 230 */ 231 static void disable_all_interrupts(struct nmk_i2c_dev *dev) 232 { 233 u32 mask = IRQ_MASK(0); 234 writel(mask, dev->virtbase + I2C_IMSCR); 235 } 236 237 /** 238 * clear_all_interrupts() - Clear all interrupts of I2C Controller 239 * @dev: private data of I2C Driver 240 */ 241 static void clear_all_interrupts(struct nmk_i2c_dev *dev) 242 { 243 u32 mask; 244 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS); 245 writel(mask, dev->virtbase + I2C_ICR); 246 } 247 248 /** 249 * init_hw() - initialize the I2C hardware 250 * @dev: private data of I2C Driver 251 */ 252 static int init_hw(struct nmk_i2c_dev *dev) 253 { 254 int stat; 255 256 stat = flush_i2c_fifo(dev); 257 if (stat) 258 goto exit; 259 260 /* disable the controller */ 261 i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE); 262 263 disable_all_interrupts(dev); 264 265 clear_all_interrupts(dev); 266 267 dev->cli.operation = I2C_NO_OPERATION; 268 269 exit: 270 return stat; 271 } 272 273 /* enable peripheral, master mode operation */ 274 #define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE) 275 276 /** 277 * load_i2c_mcr_reg() - load the MCR register 278 * @dev: private data of controller 279 * @flags: message flags 280 */ 281 static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags) 282 { 283 u32 mcr = 0; 284 unsigned short slave_adr_3msb_bits; 285 286 mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1); 287 288 if (unlikely(flags & I2C_M_TEN)) { 289 /* 10-bit address transaction */ 290 mcr |= GEN_MASK(2, I2C_MCR_AM, 12); 291 /* 292 * Get the top 3 bits. 293 * EA10 represents extended address in MCR. This includes 294 * the extension (MSB bits) of the 7 bit address loaded 295 * in A7 296 */ 297 slave_adr_3msb_bits = (dev->cli.slave_adr >> 7) & 0x7; 298 299 mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8); 300 } else { 301 /* 7-bit address transaction */ 302 mcr |= GEN_MASK(1, I2C_MCR_AM, 12); 303 } 304 305 /* start byte procedure not applied */ 306 mcr |= GEN_MASK(0, I2C_MCR_SB, 11); 307 308 /* check the operation, master read/write? */ 309 if (dev->cli.operation == I2C_WRITE) 310 mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0); 311 else 312 mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0); 313 314 /* stop or repeated start? */ 315 if (dev->stop) 316 mcr |= GEN_MASK(1, I2C_MCR_STOP, 14); 317 else 318 mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14)); 319 320 mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15); 321 322 return mcr; 323 } 324 325 /** 326 * setup_i2c_controller() - setup the controller 327 * @dev: private data of controller 328 */ 329 static void setup_i2c_controller(struct nmk_i2c_dev *dev) 330 { 331 u32 brcr1, brcr2; 332 u32 i2c_clk, div; 333 334 writel(0x0, dev->virtbase + I2C_CR); 335 writel(0x0, dev->virtbase + I2C_HSMCR); 336 writel(0x0, dev->virtbase + I2C_TFTR); 337 writel(0x0, dev->virtbase + I2C_RFTR); 338 writel(0x0, dev->virtbase + I2C_DMAR); 339 340 /* 341 * set the slsu: 342 * 343 * slsu defines the data setup time after SCL clock 344 * stretching in terms of i2c clk cycles. The 345 * needed setup time for the three modes are 250ns, 346 * 100ns, 10ns respectively thus leading to the values 347 * of 14, 6, 2 for a 48 MHz i2c clk. 348 */ 349 writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR); 350 351 i2c_clk = clk_get_rate(dev->clk); 352 353 /* fallback to std. mode if machine has not provided it */ 354 if (dev->cfg.clk_freq == 0) 355 dev->cfg.clk_freq = 100000; 356 357 /* 358 * The spec says, in case of std. mode the divider is 359 * 2 whereas it is 3 for fast and fastplus mode of 360 * operation. TODO - high speed support. 361 */ 362 div = (dev->cfg.clk_freq > 100000) ? 3 : 2; 363 364 /* 365 * generate the mask for baud rate counters. The controller 366 * has two baud rate counters. One is used for High speed 367 * operation, and the other is for std, fast mode, fast mode 368 * plus operation. Currently we do not supprt high speed mode 369 * so set brcr1 to 0. 370 */ 371 brcr1 = 0 << 16; 372 brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff; 373 374 /* set the baud rate counter register */ 375 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); 376 377 /* 378 * set the speed mode. Currently we support 379 * only standard and fast mode of operation 380 * TODO - support for fast mode plus (up to 1Mb/s) 381 * and high speed (up to 3.4 Mb/s) 382 */ 383 if (dev->cfg.sm > I2C_FREQ_MODE_FAST) { 384 dev_err(&dev->adev->dev, 385 "do not support this mode defaulting to std. mode\n"); 386 brcr2 = i2c_clk/(100000 * 2) & 0xffff; 387 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); 388 writel(I2C_FREQ_MODE_STANDARD << 4, 389 dev->virtbase + I2C_CR); 390 } 391 writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR); 392 393 /* set the Tx and Rx FIFO threshold */ 394 writel(dev->cfg.tft, dev->virtbase + I2C_TFTR); 395 writel(dev->cfg.rft, dev->virtbase + I2C_RFTR); 396 } 397 398 /** 399 * read_i2c() - Read from I2C client device 400 * @dev: private data of I2C Driver 401 * @flags: message flags 402 * 403 * This function reads from i2c client device when controller is in 404 * master mode. There is a completion timeout. If there is no transfer 405 * before timeout error is returned. 406 */ 407 static int read_i2c(struct nmk_i2c_dev *dev, u16 flags) 408 { 409 u32 status = 0; 410 u32 mcr; 411 u32 irq_mask = 0; 412 int timeout; 413 414 mcr = load_i2c_mcr_reg(dev, flags); 415 writel(mcr, dev->virtbase + I2C_MCR); 416 417 /* load the current CR value */ 418 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, 419 dev->virtbase + I2C_CR); 420 421 /* enable the controller */ 422 i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE); 423 424 init_completion(&dev->xfer_complete); 425 426 /* enable interrupts by setting the mask */ 427 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF | 428 I2C_IT_MAL | I2C_IT_BERR); 429 430 if (dev->stop) 431 irq_mask |= I2C_IT_MTD; 432 else 433 irq_mask |= I2C_IT_MTDWS; 434 435 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); 436 437 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, 438 dev->virtbase + I2C_IMSCR); 439 440 timeout = wait_for_completion_timeout( 441 &dev->xfer_complete, dev->adap.timeout); 442 443 if (timeout < 0) { 444 dev_err(&dev->adev->dev, 445 "wait_for_completion_timeout " 446 "returned %d waiting for event\n", timeout); 447 status = timeout; 448 } 449 450 if (timeout == 0) { 451 /* Controller timed out */ 452 dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n", 453 dev->cli.slave_adr); 454 status = -ETIMEDOUT; 455 } 456 return status; 457 } 458 459 static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes) 460 { 461 int count; 462 463 for (count = (no_bytes - 2); 464 (count > 0) && 465 (dev->cli.count != 0); 466 count--) { 467 /* write to the Tx FIFO */ 468 writeb(*dev->cli.buffer, 469 dev->virtbase + I2C_TFR); 470 dev->cli.buffer++; 471 dev->cli.count--; 472 dev->cli.xfer_bytes++; 473 } 474 475 } 476 477 /** 478 * write_i2c() - Write data to I2C client. 479 * @dev: private data of I2C Driver 480 * @flags: message flags 481 * 482 * This function writes data to I2C client 483 */ 484 static int write_i2c(struct nmk_i2c_dev *dev, u16 flags) 485 { 486 u32 status = 0; 487 u32 mcr; 488 u32 irq_mask = 0; 489 int timeout; 490 491 mcr = load_i2c_mcr_reg(dev, flags); 492 493 writel(mcr, dev->virtbase + I2C_MCR); 494 495 /* load the current CR value */ 496 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, 497 dev->virtbase + I2C_CR); 498 499 /* enable the controller */ 500 i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE); 501 502 init_completion(&dev->xfer_complete); 503 504 /* enable interrupts by settings the masks */ 505 irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR); 506 507 /* Fill the TX FIFO with transmit data */ 508 fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD); 509 510 if (dev->cli.count != 0) 511 irq_mask |= I2C_IT_TXFNE; 512 513 /* 514 * check if we want to transfer a single or multiple bytes, if so 515 * set the MTDWS bit (Master Transaction Done Without Stop) 516 * to start repeated start operation 517 */ 518 if (dev->stop) 519 irq_mask |= I2C_IT_MTD; 520 else 521 irq_mask |= I2C_IT_MTDWS; 522 523 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); 524 525 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, 526 dev->virtbase + I2C_IMSCR); 527 528 timeout = wait_for_completion_timeout( 529 &dev->xfer_complete, dev->adap.timeout); 530 531 if (timeout < 0) { 532 dev_err(&dev->adev->dev, 533 "wait_for_completion_timeout " 534 "returned %d waiting for event\n", timeout); 535 status = timeout; 536 } 537 538 if (timeout == 0) { 539 /* Controller timed out */ 540 dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n", 541 dev->cli.slave_adr); 542 status = -ETIMEDOUT; 543 } 544 545 return status; 546 } 547 548 /** 549 * nmk_i2c_xfer_one() - transmit a single I2C message 550 * @dev: device with a message encoded into it 551 * @flags: message flags 552 */ 553 static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags) 554 { 555 int status; 556 557 if (flags & I2C_M_RD) { 558 /* read operation */ 559 dev->cli.operation = I2C_READ; 560 status = read_i2c(dev, flags); 561 } else { 562 /* write operation */ 563 dev->cli.operation = I2C_WRITE; 564 status = write_i2c(dev, flags); 565 } 566 567 if (status || (dev->result)) { 568 u32 i2c_sr; 569 u32 cause; 570 571 i2c_sr = readl(dev->virtbase + I2C_SR); 572 /* 573 * Check if the controller I2C operation status 574 * is set to ABORT(11b). 575 */ 576 if (((i2c_sr >> 2) & 0x3) == 0x3) { 577 /* get the abort cause */ 578 cause = (i2c_sr >> 4) & 0x7; 579 dev_err(&dev->adev->dev, "%s\n", 580 cause >= ARRAY_SIZE(abort_causes) ? 581 "unknown reason" : 582 abort_causes[cause]); 583 } 584 585 (void) init_hw(dev); 586 587 status = status ? status : dev->result; 588 } 589 590 return status; 591 } 592 593 /** 594 * nmk_i2c_xfer() - I2C transfer function used by kernel framework 595 * @i2c_adap: Adapter pointer to the controller 596 * @msgs: Pointer to data to be written. 597 * @num_msgs: Number of messages to be executed 598 * 599 * This is the function called by the generic kernel i2c_transfer() 600 * or i2c_smbus...() API calls. Note that this code is protected by the 601 * semaphore set in the kernel i2c_transfer() function. 602 * 603 * NOTE: 604 * READ TRANSFER : We impose a restriction of the first message to be the 605 * index message for any read transaction. 606 * - a no index is coded as '0', 607 * - 2byte big endian index is coded as '3' 608 * !!! msg[0].buf holds the actual index. 609 * This is compatible with generic messages of smbus emulator 610 * that send a one byte index. 611 * eg. a I2C transation to read 2 bytes from index 0 612 * idx = 0; 613 * msg[0].addr = client->addr; 614 * msg[0].flags = 0x0; 615 * msg[0].len = 1; 616 * msg[0].buf = &idx; 617 * 618 * msg[1].addr = client->addr; 619 * msg[1].flags = I2C_M_RD; 620 * msg[1].len = 2; 621 * msg[1].buf = rd_buff 622 * i2c_transfer(adap, msg, 2); 623 * 624 * WRITE TRANSFER : The I2C standard interface interprets all data as payload. 625 * If you want to emulate an SMBUS write transaction put the 626 * index as first byte(or first and second) in the payload. 627 * eg. a I2C transation to write 2 bytes from index 1 628 * wr_buff[0] = 0x1; 629 * wr_buff[1] = 0x23; 630 * wr_buff[2] = 0x46; 631 * msg[0].flags = 0x0; 632 * msg[0].len = 3; 633 * msg[0].buf = wr_buff; 634 * i2c_transfer(adap, msg, 1); 635 * 636 * To read or write a block of data (multiple bytes) using SMBUS emulation 637 * please use the i2c_smbus_read_i2c_block_data() 638 * or i2c_smbus_write_i2c_block_data() API 639 */ 640 static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap, 641 struct i2c_msg msgs[], int num_msgs) 642 { 643 int status; 644 int i; 645 struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap); 646 int j; 647 648 dev->busy = true; 649 650 if (dev->regulator) 651 regulator_enable(dev->regulator); 652 pm_runtime_get_sync(&dev->adev->dev); 653 654 clk_enable(dev->clk); 655 656 status = init_hw(dev); 657 if (status) 658 goto out; 659 660 /* Attempt three times to send the message queue */ 661 for (j = 0; j < 3; j++) { 662 /* setup the i2c controller */ 663 setup_i2c_controller(dev); 664 665 for (i = 0; i < num_msgs; i++) { 666 dev->cli.slave_adr = msgs[i].addr; 667 dev->cli.buffer = msgs[i].buf; 668 dev->cli.count = msgs[i].len; 669 dev->stop = (i < (num_msgs - 1)) ? 0 : 1; 670 dev->result = 0; 671 672 status = nmk_i2c_xfer_one(dev, msgs[i].flags); 673 if (status != 0) 674 break; 675 } 676 if (status == 0) 677 break; 678 } 679 680 out: 681 clk_disable(dev->clk); 682 pm_runtime_put_sync(&dev->adev->dev); 683 if (dev->regulator) 684 regulator_disable(dev->regulator); 685 686 dev->busy = false; 687 688 /* return the no. messages processed */ 689 if (status) 690 return status; 691 else 692 return num_msgs; 693 } 694 695 /** 696 * disable_interrupts() - disable the interrupts 697 * @dev: private data of controller 698 * @irq: interrupt number 699 */ 700 static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq) 701 { 702 irq = IRQ_MASK(irq); 703 writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq), 704 dev->virtbase + I2C_IMSCR); 705 return 0; 706 } 707 708 /** 709 * i2c_irq_handler() - interrupt routine 710 * @irq: interrupt number 711 * @arg: data passed to the handler 712 * 713 * This is the interrupt handler for the i2c driver. Currently 714 * it handles the major interrupts like Rx & Tx FIFO management 715 * interrupts, master transaction interrupts, arbitration and 716 * bus error interrupts. The rest of the interrupts are treated as 717 * unhandled. 718 */ 719 static irqreturn_t i2c_irq_handler(int irq, void *arg) 720 { 721 struct nmk_i2c_dev *dev = arg; 722 u32 tft, rft; 723 u32 count; 724 u32 misr; 725 u32 src = 0; 726 727 /* load Tx FIFO and Rx FIFO threshold values */ 728 tft = readl(dev->virtbase + I2C_TFTR); 729 rft = readl(dev->virtbase + I2C_RFTR); 730 731 /* read interrupt status register */ 732 misr = readl(dev->virtbase + I2C_MISR); 733 734 src = __ffs(misr); 735 switch ((1 << src)) { 736 737 /* Transmit FIFO nearly empty interrupt */ 738 case I2C_IT_TXFNE: 739 { 740 if (dev->cli.operation == I2C_READ) { 741 /* 742 * in read operation why do we care for writing? 743 * so disable the Transmit FIFO interrupt 744 */ 745 disable_interrupts(dev, I2C_IT_TXFNE); 746 } else { 747 fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft)); 748 /* 749 * if done, close the transfer by disabling the 750 * corresponding TXFNE interrupt 751 */ 752 if (dev->cli.count == 0) 753 disable_interrupts(dev, I2C_IT_TXFNE); 754 } 755 } 756 break; 757 758 /* 759 * Rx FIFO nearly full interrupt. 760 * This is set when the numer of entries in Rx FIFO is 761 * greater or equal than the threshold value programmed 762 * in RFT 763 */ 764 case I2C_IT_RXFNF: 765 for (count = rft; count > 0; count--) { 766 /* Read the Rx FIFO */ 767 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); 768 dev->cli.buffer++; 769 } 770 dev->cli.count -= rft; 771 dev->cli.xfer_bytes += rft; 772 break; 773 774 /* Rx FIFO full */ 775 case I2C_IT_RXFF: 776 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) { 777 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); 778 dev->cli.buffer++; 779 } 780 dev->cli.count -= MAX_I2C_FIFO_THRESHOLD; 781 dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD; 782 break; 783 784 /* Master Transaction Done with/without stop */ 785 case I2C_IT_MTD: 786 case I2C_IT_MTDWS: 787 if (dev->cli.operation == I2C_READ) { 788 while (!(readl(dev->virtbase + I2C_RISR) 789 & I2C_IT_RXFE)) { 790 if (dev->cli.count == 0) 791 break; 792 *dev->cli.buffer = 793 readb(dev->virtbase + I2C_RFR); 794 dev->cli.buffer++; 795 dev->cli.count--; 796 dev->cli.xfer_bytes++; 797 } 798 } 799 800 disable_all_interrupts(dev); 801 clear_all_interrupts(dev); 802 803 if (dev->cli.count) { 804 dev->result = -EIO; 805 dev_err(&dev->adev->dev, 806 "%lu bytes still remain to be xfered\n", 807 dev->cli.count); 808 (void) init_hw(dev); 809 } 810 complete(&dev->xfer_complete); 811 812 break; 813 814 /* Master Arbitration lost interrupt */ 815 case I2C_IT_MAL: 816 dev->result = -EIO; 817 (void) init_hw(dev); 818 819 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL); 820 complete(&dev->xfer_complete); 821 822 break; 823 824 /* 825 * Bus Error interrupt. 826 * This happens when an unexpected start/stop condition occurs 827 * during the transaction. 828 */ 829 case I2C_IT_BERR: 830 dev->result = -EIO; 831 /* get the status */ 832 if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT) 833 (void) init_hw(dev); 834 835 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR); 836 complete(&dev->xfer_complete); 837 838 break; 839 840 /* 841 * Tx FIFO overrun interrupt. 842 * This is set when a write operation in Tx FIFO is performed and 843 * the Tx FIFO is full. 844 */ 845 case I2C_IT_TXFOVR: 846 dev->result = -EIO; 847 (void) init_hw(dev); 848 849 dev_err(&dev->adev->dev, "Tx Fifo Over run\n"); 850 complete(&dev->xfer_complete); 851 852 break; 853 854 /* unhandled interrupts by this driver - TODO*/ 855 case I2C_IT_TXFE: 856 case I2C_IT_TXFF: 857 case I2C_IT_RXFE: 858 case I2C_IT_RFSR: 859 case I2C_IT_RFSE: 860 case I2C_IT_WTSR: 861 case I2C_IT_STD: 862 dev_err(&dev->adev->dev, "unhandled Interrupt\n"); 863 break; 864 default: 865 dev_err(&dev->adev->dev, "spurious Interrupt..\n"); 866 break; 867 } 868 869 return IRQ_HANDLED; 870 } 871 872 873 #ifdef CONFIG_PM 874 static int nmk_i2c_suspend(struct device *dev) 875 { 876 struct amba_device *adev = to_amba_device(dev); 877 struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev); 878 879 if (nmk_i2c->busy) 880 return -EBUSY; 881 882 return 0; 883 } 884 885 static int nmk_i2c_resume(struct device *dev) 886 { 887 return 0; 888 } 889 #else 890 #define nmk_i2c_suspend NULL 891 #define nmk_i2c_resume NULL 892 #endif 893 894 /* 895 * We use noirq so that we suspend late and resume before the wakeup interrupt 896 * to ensure that we do the !pm_runtime_suspended() check in resume before 897 * there has been a regular pm runtime resume (via pm_runtime_get_sync()). 898 */ 899 static const struct dev_pm_ops nmk_i2c_pm = { 900 .suspend_noirq = nmk_i2c_suspend, 901 .resume_noirq = nmk_i2c_resume, 902 }; 903 904 static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap) 905 { 906 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR; 907 } 908 909 static const struct i2c_algorithm nmk_i2c_algo = { 910 .master_xfer = nmk_i2c_xfer, 911 .functionality = nmk_i2c_functionality 912 }; 913 914 static atomic_t adapter_id = ATOMIC_INIT(0); 915 916 static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id) 917 { 918 int ret = 0; 919 struct nmk_i2c_controller *pdata = 920 adev->dev.platform_data; 921 struct nmk_i2c_dev *dev; 922 struct i2c_adapter *adap; 923 924 if (!pdata) { 925 dev_warn(&adev->dev, "no platform data\n"); 926 return -ENODEV; 927 } 928 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL); 929 if (!dev) { 930 dev_err(&adev->dev, "cannot allocate memory\n"); 931 ret = -ENOMEM; 932 goto err_no_mem; 933 } 934 dev->busy = false; 935 dev->adev = adev; 936 amba_set_drvdata(adev, dev); 937 938 dev->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); 939 if (!dev->virtbase) { 940 ret = -ENOMEM; 941 goto err_no_ioremap; 942 } 943 944 dev->irq = adev->irq[0]; 945 ret = request_irq(dev->irq, i2c_irq_handler, 0, 946 DRIVER_NAME, dev); 947 if (ret) { 948 dev_err(&adev->dev, "cannot claim the irq %d\n", dev->irq); 949 goto err_irq; 950 } 951 952 dev->regulator = regulator_get(&adev->dev, "v-i2c"); 953 if (IS_ERR(dev->regulator)) { 954 dev_warn(&adev->dev, "could not get i2c regulator\n"); 955 dev->regulator = NULL; 956 } 957 958 pm_suspend_ignore_children(&adev->dev, true); 959 960 dev->clk = clk_get(&adev->dev, NULL); 961 if (IS_ERR(dev->clk)) { 962 dev_err(&adev->dev, "could not get i2c clock\n"); 963 ret = PTR_ERR(dev->clk); 964 goto err_no_clk; 965 } 966 967 adap = &dev->adap; 968 adap->dev.parent = &adev->dev; 969 adap->owner = THIS_MODULE; 970 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 971 adap->algo = &nmk_i2c_algo; 972 adap->timeout = msecs_to_jiffies(pdata->timeout); 973 adap->nr = atomic_read(&adapter_id); 974 snprintf(adap->name, sizeof(adap->name), 975 "Nomadik I2C%d at %pR", adap->nr, &adev->res); 976 atomic_inc(&adapter_id); 977 978 /* fetch the controller configuration from machine */ 979 dev->cfg.clk_freq = pdata->clk_freq; 980 dev->cfg.slsu = pdata->slsu; 981 dev->cfg.tft = pdata->tft; 982 dev->cfg.rft = pdata->rft; 983 dev->cfg.sm = pdata->sm; 984 985 i2c_set_adapdata(adap, dev); 986 987 dev_info(&adev->dev, 988 "initialize %s on virtual base %p\n", 989 adap->name, dev->virtbase); 990 991 ret = i2c_add_numbered_adapter(adap); 992 if (ret) { 993 dev_err(&adev->dev, "failed to add adapter\n"); 994 goto err_add_adap; 995 } 996 997 pm_runtime_put(&adev->dev); 998 999 return 0; 1000 1001 err_add_adap: 1002 clk_put(dev->clk); 1003 err_no_clk: 1004 if (dev->regulator) 1005 regulator_put(dev->regulator); 1006 free_irq(dev->irq, dev); 1007 err_irq: 1008 iounmap(dev->virtbase); 1009 err_no_ioremap: 1010 amba_set_drvdata(adev, NULL); 1011 kfree(dev); 1012 err_no_mem: 1013 1014 return ret; 1015 } 1016 1017 static int nmk_i2c_remove(struct amba_device *adev) 1018 { 1019 struct resource *res = &adev->res; 1020 struct nmk_i2c_dev *dev = amba_get_drvdata(adev); 1021 1022 i2c_del_adapter(&dev->adap); 1023 flush_i2c_fifo(dev); 1024 disable_all_interrupts(dev); 1025 clear_all_interrupts(dev); 1026 /* disable the controller */ 1027 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE); 1028 free_irq(dev->irq, dev); 1029 iounmap(dev->virtbase); 1030 if (res) 1031 release_mem_region(res->start, resource_size(res)); 1032 clk_put(dev->clk); 1033 if (dev->regulator) 1034 regulator_put(dev->regulator); 1035 pm_runtime_disable(&adev->dev); 1036 amba_set_drvdata(adev, NULL); 1037 kfree(dev); 1038 1039 return 0; 1040 } 1041 1042 static struct amba_id nmk_i2c_ids[] = { 1043 { 1044 .id = 0x00180024, 1045 .mask = 0x00ffffff, 1046 }, 1047 { 1048 .id = 0x00380024, 1049 .mask = 0x00ffffff, 1050 }, 1051 {}, 1052 }; 1053 1054 MODULE_DEVICE_TABLE(amba, nmk_i2c_ids); 1055 1056 static struct amba_driver nmk_i2c_driver = { 1057 .drv = { 1058 .owner = THIS_MODULE, 1059 .name = DRIVER_NAME, 1060 .pm = &nmk_i2c_pm, 1061 }, 1062 .id_table = nmk_i2c_ids, 1063 .probe = nmk_i2c_probe, 1064 .remove = nmk_i2c_remove, 1065 }; 1066 1067 static int __init nmk_i2c_init(void) 1068 { 1069 return amba_driver_register(&nmk_i2c_driver); 1070 } 1071 1072 static void __exit nmk_i2c_exit(void) 1073 { 1074 amba_driver_unregister(&nmk_i2c_driver); 1075 } 1076 1077 subsys_initcall(nmk_i2c_init); 1078 module_exit(nmk_i2c_exit); 1079 1080 MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR"); 1081 MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver"); 1082 MODULE_LICENSE("GPL"); 1083