1 /* 2 * Copyright (C) 2009 ST-Ericsson SA 3 * Copyright (C) 2009 STMicroelectronics 4 * 5 * I2C master mode controller driver, used in Nomadik 8815 6 * and Ux500 platforms. 7 * 8 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> 9 * Author: Sachin Verma <sachin.verma@st.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2, as 13 * published by the Free Software Foundation. 14 */ 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/amba/bus.h> 18 #include <linux/atomic.h> 19 #include <linux/slab.h> 20 #include <linux/interrupt.h> 21 #include <linux/i2c.h> 22 #include <linux/err.h> 23 #include <linux/clk.h> 24 #include <linux/io.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/platform_data/i2c-nomadik.h> 27 #include <linux/of.h> 28 #include <linux/of_i2c.h> 29 30 #define DRIVER_NAME "nmk-i2c" 31 32 /* I2C Controller register offsets */ 33 #define I2C_CR (0x000) 34 #define I2C_SCR (0x004) 35 #define I2C_HSMCR (0x008) 36 #define I2C_MCR (0x00C) 37 #define I2C_TFR (0x010) 38 #define I2C_SR (0x014) 39 #define I2C_RFR (0x018) 40 #define I2C_TFTR (0x01C) 41 #define I2C_RFTR (0x020) 42 #define I2C_DMAR (0x024) 43 #define I2C_BRCR (0x028) 44 #define I2C_IMSCR (0x02C) 45 #define I2C_RISR (0x030) 46 #define I2C_MISR (0x034) 47 #define I2C_ICR (0x038) 48 49 /* Control registers */ 50 #define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */ 51 #define I2C_CR_OM (0x3 << 1) /* Operating mode */ 52 #define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */ 53 #define I2C_CR_SM (0x3 << 4) /* Speed mode */ 54 #define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */ 55 #define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */ 56 #define I2C_CR_FRX (0x1 << 8) /* Flush Receive */ 57 #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */ 58 #define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */ 59 #define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */ 60 #define I2C_CR_LM (0x1 << 12) /* Loopback mode */ 61 #define I2C_CR_FON (0x3 << 13) /* Filtering on */ 62 #define I2C_CR_FS (0x3 << 15) /* Force stop enable */ 63 64 /* Master controller (MCR) register */ 65 #define I2C_MCR_OP (0x1 << 0) /* Operation */ 66 #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */ 67 #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */ 68 #define I2C_MCR_SB (0x1 << 11) /* Extended address */ 69 #define I2C_MCR_AM (0x3 << 12) /* Address type */ 70 #define I2C_MCR_STOP (0x1 << 14) /* Stop condition */ 71 #define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */ 72 73 /* Status register (SR) */ 74 #define I2C_SR_OP (0x3 << 0) /* Operation */ 75 #define I2C_SR_STATUS (0x3 << 2) /* controller status */ 76 #define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */ 77 #define I2C_SR_TYPE (0x3 << 7) /* Receive type */ 78 #define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */ 79 80 /* Interrupt mask set/clear (IMSCR) bits */ 81 #define I2C_IT_TXFE (0x1 << 0) 82 #define I2C_IT_TXFNE (0x1 << 1) 83 #define I2C_IT_TXFF (0x1 << 2) 84 #define I2C_IT_TXFOVR (0x1 << 3) 85 #define I2C_IT_RXFE (0x1 << 4) 86 #define I2C_IT_RXFNF (0x1 << 5) 87 #define I2C_IT_RXFF (0x1 << 6) 88 #define I2C_IT_RFSR (0x1 << 16) 89 #define I2C_IT_RFSE (0x1 << 17) 90 #define I2C_IT_WTSR (0x1 << 18) 91 #define I2C_IT_MTD (0x1 << 19) 92 #define I2C_IT_STD (0x1 << 20) 93 #define I2C_IT_MAL (0x1 << 24) 94 #define I2C_IT_BERR (0x1 << 25) 95 #define I2C_IT_MTDWS (0x1 << 28) 96 97 #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask)) 98 99 /* some bits in ICR are reserved */ 100 #define I2C_CLEAR_ALL_INTS 0x131f007f 101 102 /* first three msb bits are reserved */ 103 #define IRQ_MASK(mask) (mask & 0x1fffffff) 104 105 /* maximum threshold value */ 106 #define MAX_I2C_FIFO_THRESHOLD 15 107 108 enum i2c_status { 109 I2C_NOP, 110 I2C_ON_GOING, 111 I2C_OK, 112 I2C_ABORT 113 }; 114 115 /* operation */ 116 enum i2c_operation { 117 I2C_NO_OPERATION = 0xff, 118 I2C_WRITE = 0x00, 119 I2C_READ = 0x01 120 }; 121 122 /** 123 * struct i2c_nmk_client - client specific data 124 * @slave_adr: 7-bit slave address 125 * @count: no. bytes to be transferred 126 * @buffer: client data buffer 127 * @xfer_bytes: bytes transferred till now 128 * @operation: current I2C operation 129 */ 130 struct i2c_nmk_client { 131 unsigned short slave_adr; 132 unsigned long count; 133 unsigned char *buffer; 134 unsigned long xfer_bytes; 135 enum i2c_operation operation; 136 }; 137 138 /** 139 * struct nmk_i2c_dev - private data structure of the controller. 140 * @adev: parent amba device. 141 * @adap: corresponding I2C adapter. 142 * @irq: interrupt line for the controller. 143 * @virtbase: virtual io memory area. 144 * @clk: hardware i2c block clock. 145 * @cfg: machine provided controller configuration. 146 * @cli: holder of client specific data. 147 * @stop: stop condition. 148 * @xfer_complete: acknowledge completion for a I2C message. 149 * @result: controller propogated result. 150 * @busy: Busy doing transfer. 151 */ 152 struct nmk_i2c_dev { 153 struct amba_device *adev; 154 struct i2c_adapter adap; 155 int irq; 156 void __iomem *virtbase; 157 struct clk *clk; 158 struct nmk_i2c_controller cfg; 159 struct i2c_nmk_client cli; 160 int stop; 161 struct completion xfer_complete; 162 int result; 163 bool busy; 164 }; 165 166 /* controller's abort causes */ 167 static const char *abort_causes[] = { 168 "no ack received after address transmission", 169 "no ack received during data phase", 170 "ack received after xmission of master code", 171 "master lost arbitration", 172 "slave restarts", 173 "slave reset", 174 "overflow, maxsize is 2047 bytes", 175 }; 176 177 static inline void i2c_set_bit(void __iomem *reg, u32 mask) 178 { 179 writel(readl(reg) | mask, reg); 180 } 181 182 static inline void i2c_clr_bit(void __iomem *reg, u32 mask) 183 { 184 writel(readl(reg) & ~mask, reg); 185 } 186 187 /** 188 * flush_i2c_fifo() - This function flushes the I2C FIFO 189 * @dev: private data of I2C Driver 190 * 191 * This function flushes the I2C Tx and Rx FIFOs. It returns 192 * 0 on successful flushing of FIFO 193 */ 194 static int flush_i2c_fifo(struct nmk_i2c_dev *dev) 195 { 196 #define LOOP_ATTEMPTS 10 197 int i; 198 unsigned long timeout; 199 200 /* 201 * flush the transmit and receive FIFO. The flushing 202 * operation takes several cycles before to be completed. 203 * On the completion, the I2C internal logic clears these 204 * bits, until then no one must access Tx, Rx FIFO and 205 * should poll on these bits waiting for the completion. 206 */ 207 writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR); 208 209 for (i = 0; i < LOOP_ATTEMPTS; i++) { 210 timeout = jiffies + dev->adap.timeout; 211 212 while (!time_after(jiffies, timeout)) { 213 if ((readl(dev->virtbase + I2C_CR) & 214 (I2C_CR_FTX | I2C_CR_FRX)) == 0) 215 return 0; 216 } 217 } 218 219 dev_err(&dev->adev->dev, 220 "flushing operation timed out giving up after %d attempts", 221 LOOP_ATTEMPTS); 222 223 return -ETIMEDOUT; 224 } 225 226 /** 227 * disable_all_interrupts() - Disable all interrupts of this I2c Bus 228 * @dev: private data of I2C Driver 229 */ 230 static void disable_all_interrupts(struct nmk_i2c_dev *dev) 231 { 232 u32 mask = IRQ_MASK(0); 233 writel(mask, dev->virtbase + I2C_IMSCR); 234 } 235 236 /** 237 * clear_all_interrupts() - Clear all interrupts of I2C Controller 238 * @dev: private data of I2C Driver 239 */ 240 static void clear_all_interrupts(struct nmk_i2c_dev *dev) 241 { 242 u32 mask; 243 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS); 244 writel(mask, dev->virtbase + I2C_ICR); 245 } 246 247 /** 248 * init_hw() - initialize the I2C hardware 249 * @dev: private data of I2C Driver 250 */ 251 static int init_hw(struct nmk_i2c_dev *dev) 252 { 253 int stat; 254 255 stat = flush_i2c_fifo(dev); 256 if (stat) 257 goto exit; 258 259 /* disable the controller */ 260 i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE); 261 262 disable_all_interrupts(dev); 263 264 clear_all_interrupts(dev); 265 266 dev->cli.operation = I2C_NO_OPERATION; 267 268 exit: 269 return stat; 270 } 271 272 /* enable peripheral, master mode operation */ 273 #define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE) 274 275 /** 276 * load_i2c_mcr_reg() - load the MCR register 277 * @dev: private data of controller 278 * @flags: message flags 279 */ 280 static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags) 281 { 282 u32 mcr = 0; 283 unsigned short slave_adr_3msb_bits; 284 285 mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1); 286 287 if (unlikely(flags & I2C_M_TEN)) { 288 /* 10-bit address transaction */ 289 mcr |= GEN_MASK(2, I2C_MCR_AM, 12); 290 /* 291 * Get the top 3 bits. 292 * EA10 represents extended address in MCR. This includes 293 * the extension (MSB bits) of the 7 bit address loaded 294 * in A7 295 */ 296 slave_adr_3msb_bits = (dev->cli.slave_adr >> 7) & 0x7; 297 298 mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8); 299 } else { 300 /* 7-bit address transaction */ 301 mcr |= GEN_MASK(1, I2C_MCR_AM, 12); 302 } 303 304 /* start byte procedure not applied */ 305 mcr |= GEN_MASK(0, I2C_MCR_SB, 11); 306 307 /* check the operation, master read/write? */ 308 if (dev->cli.operation == I2C_WRITE) 309 mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0); 310 else 311 mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0); 312 313 /* stop or repeated start? */ 314 if (dev->stop) 315 mcr |= GEN_MASK(1, I2C_MCR_STOP, 14); 316 else 317 mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14)); 318 319 mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15); 320 321 return mcr; 322 } 323 324 /** 325 * setup_i2c_controller() - setup the controller 326 * @dev: private data of controller 327 */ 328 static void setup_i2c_controller(struct nmk_i2c_dev *dev) 329 { 330 u32 brcr1, brcr2; 331 u32 i2c_clk, div; 332 333 writel(0x0, dev->virtbase + I2C_CR); 334 writel(0x0, dev->virtbase + I2C_HSMCR); 335 writel(0x0, dev->virtbase + I2C_TFTR); 336 writel(0x0, dev->virtbase + I2C_RFTR); 337 writel(0x0, dev->virtbase + I2C_DMAR); 338 339 /* 340 * set the slsu: 341 * 342 * slsu defines the data setup time after SCL clock 343 * stretching in terms of i2c clk cycles. The 344 * needed setup time for the three modes are 250ns, 345 * 100ns, 10ns respectively thus leading to the values 346 * of 14, 6, 2 for a 48 MHz i2c clk. 347 */ 348 writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR); 349 350 i2c_clk = clk_get_rate(dev->clk); 351 352 /* 353 * The spec says, in case of std. mode the divider is 354 * 2 whereas it is 3 for fast and fastplus mode of 355 * operation. TODO - high speed support. 356 */ 357 div = (dev->cfg.clk_freq > 100000) ? 3 : 2; 358 359 /* 360 * generate the mask for baud rate counters. The controller 361 * has two baud rate counters. One is used for High speed 362 * operation, and the other is for std, fast mode, fast mode 363 * plus operation. Currently we do not supprt high speed mode 364 * so set brcr1 to 0. 365 */ 366 brcr1 = 0 << 16; 367 brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff; 368 369 /* set the baud rate counter register */ 370 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); 371 372 /* 373 * set the speed mode. Currently we support 374 * only standard and fast mode of operation 375 * TODO - support for fast mode plus (up to 1Mb/s) 376 * and high speed (up to 3.4 Mb/s) 377 */ 378 if (dev->cfg.sm > I2C_FREQ_MODE_FAST) { 379 dev_err(&dev->adev->dev, 380 "do not support this mode defaulting to std. mode\n"); 381 brcr2 = i2c_clk/(100000 * 2) & 0xffff; 382 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR); 383 writel(I2C_FREQ_MODE_STANDARD << 4, 384 dev->virtbase + I2C_CR); 385 } 386 writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR); 387 388 /* set the Tx and Rx FIFO threshold */ 389 writel(dev->cfg.tft, dev->virtbase + I2C_TFTR); 390 writel(dev->cfg.rft, dev->virtbase + I2C_RFTR); 391 } 392 393 /** 394 * read_i2c() - Read from I2C client device 395 * @dev: private data of I2C Driver 396 * @flags: message flags 397 * 398 * This function reads from i2c client device when controller is in 399 * master mode. There is a completion timeout. If there is no transfer 400 * before timeout error is returned. 401 */ 402 static int read_i2c(struct nmk_i2c_dev *dev, u16 flags) 403 { 404 u32 status = 0; 405 u32 mcr; 406 u32 irq_mask = 0; 407 int timeout; 408 409 mcr = load_i2c_mcr_reg(dev, flags); 410 writel(mcr, dev->virtbase + I2C_MCR); 411 412 /* load the current CR value */ 413 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, 414 dev->virtbase + I2C_CR); 415 416 /* enable the controller */ 417 i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE); 418 419 init_completion(&dev->xfer_complete); 420 421 /* enable interrupts by setting the mask */ 422 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF | 423 I2C_IT_MAL | I2C_IT_BERR); 424 425 if (dev->stop) 426 irq_mask |= I2C_IT_MTD; 427 else 428 irq_mask |= I2C_IT_MTDWS; 429 430 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); 431 432 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, 433 dev->virtbase + I2C_IMSCR); 434 435 timeout = wait_for_completion_timeout( 436 &dev->xfer_complete, dev->adap.timeout); 437 438 if (timeout < 0) { 439 dev_err(&dev->adev->dev, 440 "wait_for_completion_timeout " 441 "returned %d waiting for event\n", timeout); 442 status = timeout; 443 } 444 445 if (timeout == 0) { 446 /* Controller timed out */ 447 dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n", 448 dev->cli.slave_adr); 449 status = -ETIMEDOUT; 450 } 451 return status; 452 } 453 454 static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes) 455 { 456 int count; 457 458 for (count = (no_bytes - 2); 459 (count > 0) && 460 (dev->cli.count != 0); 461 count--) { 462 /* write to the Tx FIFO */ 463 writeb(*dev->cli.buffer, 464 dev->virtbase + I2C_TFR); 465 dev->cli.buffer++; 466 dev->cli.count--; 467 dev->cli.xfer_bytes++; 468 } 469 470 } 471 472 /** 473 * write_i2c() - Write data to I2C client. 474 * @dev: private data of I2C Driver 475 * @flags: message flags 476 * 477 * This function writes data to I2C client 478 */ 479 static int write_i2c(struct nmk_i2c_dev *dev, u16 flags) 480 { 481 u32 status = 0; 482 u32 mcr; 483 u32 irq_mask = 0; 484 int timeout; 485 486 mcr = load_i2c_mcr_reg(dev, flags); 487 488 writel(mcr, dev->virtbase + I2C_MCR); 489 490 /* load the current CR value */ 491 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, 492 dev->virtbase + I2C_CR); 493 494 /* enable the controller */ 495 i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE); 496 497 init_completion(&dev->xfer_complete); 498 499 /* enable interrupts by settings the masks */ 500 irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR); 501 502 /* Fill the TX FIFO with transmit data */ 503 fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD); 504 505 if (dev->cli.count != 0) 506 irq_mask |= I2C_IT_TXFNE; 507 508 /* 509 * check if we want to transfer a single or multiple bytes, if so 510 * set the MTDWS bit (Master Transaction Done Without Stop) 511 * to start repeated start operation 512 */ 513 if (dev->stop) 514 irq_mask |= I2C_IT_MTD; 515 else 516 irq_mask |= I2C_IT_MTDWS; 517 518 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); 519 520 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, 521 dev->virtbase + I2C_IMSCR); 522 523 timeout = wait_for_completion_timeout( 524 &dev->xfer_complete, dev->adap.timeout); 525 526 if (timeout < 0) { 527 dev_err(&dev->adev->dev, 528 "wait_for_completion_timeout " 529 "returned %d waiting for event\n", timeout); 530 status = timeout; 531 } 532 533 if (timeout == 0) { 534 /* Controller timed out */ 535 dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n", 536 dev->cli.slave_adr); 537 status = -ETIMEDOUT; 538 } 539 540 return status; 541 } 542 543 /** 544 * nmk_i2c_xfer_one() - transmit a single I2C message 545 * @dev: device with a message encoded into it 546 * @flags: message flags 547 */ 548 static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags) 549 { 550 int status; 551 552 if (flags & I2C_M_RD) { 553 /* read operation */ 554 dev->cli.operation = I2C_READ; 555 status = read_i2c(dev, flags); 556 } else { 557 /* write operation */ 558 dev->cli.operation = I2C_WRITE; 559 status = write_i2c(dev, flags); 560 } 561 562 if (status || (dev->result)) { 563 u32 i2c_sr; 564 u32 cause; 565 566 i2c_sr = readl(dev->virtbase + I2C_SR); 567 /* 568 * Check if the controller I2C operation status 569 * is set to ABORT(11b). 570 */ 571 if (((i2c_sr >> 2) & 0x3) == 0x3) { 572 /* get the abort cause */ 573 cause = (i2c_sr >> 4) & 0x7; 574 dev_err(&dev->adev->dev, "%s\n", 575 cause >= ARRAY_SIZE(abort_causes) ? 576 "unknown reason" : 577 abort_causes[cause]); 578 } 579 580 (void) init_hw(dev); 581 582 status = status ? status : dev->result; 583 } 584 585 return status; 586 } 587 588 /** 589 * nmk_i2c_xfer() - I2C transfer function used by kernel framework 590 * @i2c_adap: Adapter pointer to the controller 591 * @msgs: Pointer to data to be written. 592 * @num_msgs: Number of messages to be executed 593 * 594 * This is the function called by the generic kernel i2c_transfer() 595 * or i2c_smbus...() API calls. Note that this code is protected by the 596 * semaphore set in the kernel i2c_transfer() function. 597 * 598 * NOTE: 599 * READ TRANSFER : We impose a restriction of the first message to be the 600 * index message for any read transaction. 601 * - a no index is coded as '0', 602 * - 2byte big endian index is coded as '3' 603 * !!! msg[0].buf holds the actual index. 604 * This is compatible with generic messages of smbus emulator 605 * that send a one byte index. 606 * eg. a I2C transation to read 2 bytes from index 0 607 * idx = 0; 608 * msg[0].addr = client->addr; 609 * msg[0].flags = 0x0; 610 * msg[0].len = 1; 611 * msg[0].buf = &idx; 612 * 613 * msg[1].addr = client->addr; 614 * msg[1].flags = I2C_M_RD; 615 * msg[1].len = 2; 616 * msg[1].buf = rd_buff 617 * i2c_transfer(adap, msg, 2); 618 * 619 * WRITE TRANSFER : The I2C standard interface interprets all data as payload. 620 * If you want to emulate an SMBUS write transaction put the 621 * index as first byte(or first and second) in the payload. 622 * eg. a I2C transation to write 2 bytes from index 1 623 * wr_buff[0] = 0x1; 624 * wr_buff[1] = 0x23; 625 * wr_buff[2] = 0x46; 626 * msg[0].flags = 0x0; 627 * msg[0].len = 3; 628 * msg[0].buf = wr_buff; 629 * i2c_transfer(adap, msg, 1); 630 * 631 * To read or write a block of data (multiple bytes) using SMBUS emulation 632 * please use the i2c_smbus_read_i2c_block_data() 633 * or i2c_smbus_write_i2c_block_data() API 634 */ 635 static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap, 636 struct i2c_msg msgs[], int num_msgs) 637 { 638 int status; 639 int i; 640 struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap); 641 int j; 642 643 dev->busy = true; 644 645 pm_runtime_get_sync(&dev->adev->dev); 646 647 clk_enable(dev->clk); 648 649 status = init_hw(dev); 650 if (status) 651 goto out; 652 653 /* Attempt three times to send the message queue */ 654 for (j = 0; j < 3; j++) { 655 /* setup the i2c controller */ 656 setup_i2c_controller(dev); 657 658 for (i = 0; i < num_msgs; i++) { 659 dev->cli.slave_adr = msgs[i].addr; 660 dev->cli.buffer = msgs[i].buf; 661 dev->cli.count = msgs[i].len; 662 dev->stop = (i < (num_msgs - 1)) ? 0 : 1; 663 dev->result = 0; 664 665 status = nmk_i2c_xfer_one(dev, msgs[i].flags); 666 if (status != 0) 667 break; 668 } 669 if (status == 0) 670 break; 671 } 672 673 out: 674 clk_disable(dev->clk); 675 pm_runtime_put_sync(&dev->adev->dev); 676 677 dev->busy = false; 678 679 /* return the no. messages processed */ 680 if (status) 681 return status; 682 else 683 return num_msgs; 684 } 685 686 /** 687 * disable_interrupts() - disable the interrupts 688 * @dev: private data of controller 689 * @irq: interrupt number 690 */ 691 static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq) 692 { 693 irq = IRQ_MASK(irq); 694 writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq), 695 dev->virtbase + I2C_IMSCR); 696 return 0; 697 } 698 699 /** 700 * i2c_irq_handler() - interrupt routine 701 * @irq: interrupt number 702 * @arg: data passed to the handler 703 * 704 * This is the interrupt handler for the i2c driver. Currently 705 * it handles the major interrupts like Rx & Tx FIFO management 706 * interrupts, master transaction interrupts, arbitration and 707 * bus error interrupts. The rest of the interrupts are treated as 708 * unhandled. 709 */ 710 static irqreturn_t i2c_irq_handler(int irq, void *arg) 711 { 712 struct nmk_i2c_dev *dev = arg; 713 u32 tft, rft; 714 u32 count; 715 u32 misr; 716 u32 src = 0; 717 718 /* load Tx FIFO and Rx FIFO threshold values */ 719 tft = readl(dev->virtbase + I2C_TFTR); 720 rft = readl(dev->virtbase + I2C_RFTR); 721 722 /* read interrupt status register */ 723 misr = readl(dev->virtbase + I2C_MISR); 724 725 src = __ffs(misr); 726 switch ((1 << src)) { 727 728 /* Transmit FIFO nearly empty interrupt */ 729 case I2C_IT_TXFNE: 730 { 731 if (dev->cli.operation == I2C_READ) { 732 /* 733 * in read operation why do we care for writing? 734 * so disable the Transmit FIFO interrupt 735 */ 736 disable_interrupts(dev, I2C_IT_TXFNE); 737 } else { 738 fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft)); 739 /* 740 * if done, close the transfer by disabling the 741 * corresponding TXFNE interrupt 742 */ 743 if (dev->cli.count == 0) 744 disable_interrupts(dev, I2C_IT_TXFNE); 745 } 746 } 747 break; 748 749 /* 750 * Rx FIFO nearly full interrupt. 751 * This is set when the numer of entries in Rx FIFO is 752 * greater or equal than the threshold value programmed 753 * in RFT 754 */ 755 case I2C_IT_RXFNF: 756 for (count = rft; count > 0; count--) { 757 /* Read the Rx FIFO */ 758 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); 759 dev->cli.buffer++; 760 } 761 dev->cli.count -= rft; 762 dev->cli.xfer_bytes += rft; 763 break; 764 765 /* Rx FIFO full */ 766 case I2C_IT_RXFF: 767 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) { 768 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR); 769 dev->cli.buffer++; 770 } 771 dev->cli.count -= MAX_I2C_FIFO_THRESHOLD; 772 dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD; 773 break; 774 775 /* Master Transaction Done with/without stop */ 776 case I2C_IT_MTD: 777 case I2C_IT_MTDWS: 778 if (dev->cli.operation == I2C_READ) { 779 while (!(readl(dev->virtbase + I2C_RISR) 780 & I2C_IT_RXFE)) { 781 if (dev->cli.count == 0) 782 break; 783 *dev->cli.buffer = 784 readb(dev->virtbase + I2C_RFR); 785 dev->cli.buffer++; 786 dev->cli.count--; 787 dev->cli.xfer_bytes++; 788 } 789 } 790 791 disable_all_interrupts(dev); 792 clear_all_interrupts(dev); 793 794 if (dev->cli.count) { 795 dev->result = -EIO; 796 dev_err(&dev->adev->dev, 797 "%lu bytes still remain to be xfered\n", 798 dev->cli.count); 799 (void) init_hw(dev); 800 } 801 complete(&dev->xfer_complete); 802 803 break; 804 805 /* Master Arbitration lost interrupt */ 806 case I2C_IT_MAL: 807 dev->result = -EIO; 808 (void) init_hw(dev); 809 810 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL); 811 complete(&dev->xfer_complete); 812 813 break; 814 815 /* 816 * Bus Error interrupt. 817 * This happens when an unexpected start/stop condition occurs 818 * during the transaction. 819 */ 820 case I2C_IT_BERR: 821 dev->result = -EIO; 822 /* get the status */ 823 if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT) 824 (void) init_hw(dev); 825 826 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR); 827 complete(&dev->xfer_complete); 828 829 break; 830 831 /* 832 * Tx FIFO overrun interrupt. 833 * This is set when a write operation in Tx FIFO is performed and 834 * the Tx FIFO is full. 835 */ 836 case I2C_IT_TXFOVR: 837 dev->result = -EIO; 838 (void) init_hw(dev); 839 840 dev_err(&dev->adev->dev, "Tx Fifo Over run\n"); 841 complete(&dev->xfer_complete); 842 843 break; 844 845 /* unhandled interrupts by this driver - TODO*/ 846 case I2C_IT_TXFE: 847 case I2C_IT_TXFF: 848 case I2C_IT_RXFE: 849 case I2C_IT_RFSR: 850 case I2C_IT_RFSE: 851 case I2C_IT_WTSR: 852 case I2C_IT_STD: 853 dev_err(&dev->adev->dev, "unhandled Interrupt\n"); 854 break; 855 default: 856 dev_err(&dev->adev->dev, "spurious Interrupt..\n"); 857 break; 858 } 859 860 return IRQ_HANDLED; 861 } 862 863 864 #ifdef CONFIG_PM 865 static int nmk_i2c_suspend(struct device *dev) 866 { 867 struct amba_device *adev = to_amba_device(dev); 868 struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev); 869 870 if (nmk_i2c->busy) 871 return -EBUSY; 872 873 return 0; 874 } 875 876 static int nmk_i2c_resume(struct device *dev) 877 { 878 return 0; 879 } 880 #else 881 #define nmk_i2c_suspend NULL 882 #define nmk_i2c_resume NULL 883 #endif 884 885 /* 886 * We use noirq so that we suspend late and resume before the wakeup interrupt 887 * to ensure that we do the !pm_runtime_suspended() check in resume before 888 * there has been a regular pm runtime resume (via pm_runtime_get_sync()). 889 */ 890 static const struct dev_pm_ops nmk_i2c_pm = { 891 .suspend_noirq = nmk_i2c_suspend, 892 .resume_noirq = nmk_i2c_resume, 893 }; 894 895 static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap) 896 { 897 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR; 898 } 899 900 static const struct i2c_algorithm nmk_i2c_algo = { 901 .master_xfer = nmk_i2c_xfer, 902 .functionality = nmk_i2c_functionality 903 }; 904 905 static struct nmk_i2c_controller u8500_i2c = { 906 /* 907 * Slave data setup time; 250ns, 100ns, and 10ns, which 908 * is 14, 6 and 2 respectively for a 48Mhz i2c clock. 909 */ 910 .slsu = 0xe, 911 .tft = 1, /* Tx FIFO threshold */ 912 .rft = 8, /* Rx FIFO threshold */ 913 .clk_freq = 400000, /* fast mode operation */ 914 .timeout = 200, /* Slave response timeout(ms) */ 915 .sm = I2C_FREQ_MODE_FAST, 916 }; 917 918 static void nmk_i2c_of_probe(struct device_node *np, 919 struct nmk_i2c_controller *pdata) 920 { 921 of_property_read_u32(np, "clock-frequency", &pdata->clk_freq); 922 923 /* This driver only supports 'standard' and 'fast' modes of operation. */ 924 if (pdata->clk_freq <= 100000) 925 pdata->sm = I2C_FREQ_MODE_STANDARD; 926 else 927 pdata->sm = I2C_FREQ_MODE_FAST; 928 } 929 930 static atomic_t adapter_id = ATOMIC_INIT(0); 931 932 static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id) 933 { 934 int ret = 0; 935 struct nmk_i2c_controller *pdata = adev->dev.platform_data; 936 struct device_node *np = adev->dev.of_node; 937 struct nmk_i2c_dev *dev; 938 struct i2c_adapter *adap; 939 940 if (!pdata) { 941 if (np) { 942 pdata = devm_kzalloc(&adev->dev, sizeof(*pdata), GFP_KERNEL); 943 if (!pdata) { 944 ret = -ENOMEM; 945 goto err_no_mem; 946 } 947 /* Provide the default configuration as a base. */ 948 memcpy(pdata, &u8500_i2c, sizeof(struct nmk_i2c_controller)); 949 nmk_i2c_of_probe(np, pdata); 950 } else 951 /* No i2c configuration found, using the default. */ 952 pdata = &u8500_i2c; 953 } 954 955 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL); 956 if (!dev) { 957 dev_err(&adev->dev, "cannot allocate memory\n"); 958 ret = -ENOMEM; 959 goto err_no_mem; 960 } 961 dev->busy = false; 962 dev->adev = adev; 963 amba_set_drvdata(adev, dev); 964 965 dev->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); 966 if (!dev->virtbase) { 967 ret = -ENOMEM; 968 goto err_no_ioremap; 969 } 970 971 dev->irq = adev->irq[0]; 972 ret = request_irq(dev->irq, i2c_irq_handler, 0, 973 DRIVER_NAME, dev); 974 if (ret) { 975 dev_err(&adev->dev, "cannot claim the irq %d\n", dev->irq); 976 goto err_irq; 977 } 978 979 pm_suspend_ignore_children(&adev->dev, true); 980 981 dev->clk = clk_get(&adev->dev, NULL); 982 if (IS_ERR(dev->clk)) { 983 dev_err(&adev->dev, "could not get i2c clock\n"); 984 ret = PTR_ERR(dev->clk); 985 goto err_no_clk; 986 } 987 988 adap = &dev->adap; 989 adap->dev.of_node = np; 990 adap->dev.parent = &adev->dev; 991 adap->owner = THIS_MODULE; 992 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 993 adap->algo = &nmk_i2c_algo; 994 adap->timeout = msecs_to_jiffies(pdata->timeout); 995 adap->nr = atomic_read(&adapter_id); 996 snprintf(adap->name, sizeof(adap->name), 997 "Nomadik I2C%d at %pR", adap->nr, &adev->res); 998 atomic_inc(&adapter_id); 999 1000 /* fetch the controller configuration from machine */ 1001 dev->cfg.clk_freq = pdata->clk_freq; 1002 dev->cfg.slsu = pdata->slsu; 1003 dev->cfg.tft = pdata->tft; 1004 dev->cfg.rft = pdata->rft; 1005 dev->cfg.sm = pdata->sm; 1006 1007 i2c_set_adapdata(adap, dev); 1008 1009 dev_info(&adev->dev, 1010 "initialize %s on virtual base %p\n", 1011 adap->name, dev->virtbase); 1012 1013 ret = i2c_add_numbered_adapter(adap); 1014 if (ret) { 1015 dev_err(&adev->dev, "failed to add adapter\n"); 1016 goto err_add_adap; 1017 } 1018 1019 of_i2c_register_devices(adap); 1020 1021 pm_runtime_put(&adev->dev); 1022 1023 return 0; 1024 1025 err_add_adap: 1026 clk_put(dev->clk); 1027 err_no_clk: 1028 free_irq(dev->irq, dev); 1029 err_irq: 1030 iounmap(dev->virtbase); 1031 err_no_ioremap: 1032 amba_set_drvdata(adev, NULL); 1033 kfree(dev); 1034 err_no_mem: 1035 1036 return ret; 1037 } 1038 1039 static int nmk_i2c_remove(struct amba_device *adev) 1040 { 1041 struct resource *res = &adev->res; 1042 struct nmk_i2c_dev *dev = amba_get_drvdata(adev); 1043 1044 i2c_del_adapter(&dev->adap); 1045 flush_i2c_fifo(dev); 1046 disable_all_interrupts(dev); 1047 clear_all_interrupts(dev); 1048 /* disable the controller */ 1049 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE); 1050 free_irq(dev->irq, dev); 1051 iounmap(dev->virtbase); 1052 if (res) 1053 release_mem_region(res->start, resource_size(res)); 1054 clk_put(dev->clk); 1055 pm_runtime_disable(&adev->dev); 1056 amba_set_drvdata(adev, NULL); 1057 kfree(dev); 1058 1059 return 0; 1060 } 1061 1062 static struct amba_id nmk_i2c_ids[] = { 1063 { 1064 .id = 0x00180024, 1065 .mask = 0x00ffffff, 1066 }, 1067 { 1068 .id = 0x00380024, 1069 .mask = 0x00ffffff, 1070 }, 1071 {}, 1072 }; 1073 1074 MODULE_DEVICE_TABLE(amba, nmk_i2c_ids); 1075 1076 static struct amba_driver nmk_i2c_driver = { 1077 .drv = { 1078 .owner = THIS_MODULE, 1079 .name = DRIVER_NAME, 1080 .pm = &nmk_i2c_pm, 1081 }, 1082 .id_table = nmk_i2c_ids, 1083 .probe = nmk_i2c_probe, 1084 .remove = nmk_i2c_remove, 1085 }; 1086 1087 static int __init nmk_i2c_init(void) 1088 { 1089 return amba_driver_register(&nmk_i2c_driver); 1090 } 1091 1092 static void __exit nmk_i2c_exit(void) 1093 { 1094 amba_driver_unregister(&nmk_i2c_driver); 1095 } 1096 1097 subsys_initcall(nmk_i2c_init); 1098 module_exit(nmk_i2c_exit); 1099 1100 MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR"); 1101 MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver"); 1102 MODULE_LICENSE("GPL"); 1103