1 /* 2 SMBus driver for nVidia nForce2 MCP 3 4 Added nForce3 Pro 150 Thomas Leibold <thomas@plx.com>, 5 Ported to 2.5 Patrick Dreker <patrick@dreker.de>, 6 Copyright (c) 2003 Hans-Frieder Vogt <hfvogt@arcor.de>, 7 Based on 8 SMBus 2.0 driver for AMD-8111 IO-Hub 9 Copyright (c) 2002 Vojtech Pavlik 10 11 This program is free software; you can redistribute it and/or modify 12 it under the terms of the GNU General Public License as published by 13 the Free Software Foundation; either version 2 of the License, or 14 (at your option) any later version. 15 16 This program is distributed in the hope that it will be useful, 17 but WITHOUT ANY WARRANTY; without even the implied warranty of 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 GNU General Public License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with this program; if not, write to the Free Software 23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 24 */ 25 26 /* 27 SUPPORTED DEVICES PCI ID 28 nForce2 MCP 0064 29 nForce2 Ultra 400 MCP 0084 30 nForce3 Pro150 MCP 00D4 31 nForce3 250Gb MCP 00E4 32 nForce4 MCP 0052 33 nForce4 MCP-04 0034 34 nForce MCP51 0264 35 nForce MCP55 0368 36 nForce MCP61 03EB 37 nForce MCP65 0446 38 nForce MCP67 0542 39 nForce MCP73 07D8 40 nForce MCP78S 0752 41 nForce MCP79 0AA2 42 43 This driver supports the 2 SMBuses that are included in the MCP of the 44 nForce2/3/4/5xx chipsets. 45 */ 46 47 /* Note: we assume there can only be one nForce2, with two SMBus interfaces */ 48 49 #include <linux/module.h> 50 #include <linux/pci.h> 51 #include <linux/kernel.h> 52 #include <linux/stddef.h> 53 #include <linux/ioport.h> 54 #include <linux/init.h> 55 #include <linux/i2c.h> 56 #include <linux/delay.h> 57 #include <linux/dmi.h> 58 #include <linux/acpi.h> 59 #include <linux/slab.h> 60 #include <linux/io.h> 61 62 MODULE_LICENSE("GPL"); 63 MODULE_AUTHOR ("Hans-Frieder Vogt <hfvogt@gmx.net>"); 64 MODULE_DESCRIPTION("nForce2/3/4/5xx SMBus driver"); 65 66 67 struct nforce2_smbus { 68 struct i2c_adapter adapter; 69 int base; 70 int size; 71 int blockops; 72 int can_abort; 73 }; 74 75 76 /* 77 * nVidia nForce2 SMBus control register definitions 78 * (Newer incarnations use standard BARs 4 and 5 instead) 79 */ 80 #define NFORCE_PCI_SMB1 0x50 81 #define NFORCE_PCI_SMB2 0x54 82 83 84 /* 85 * ACPI 2.0 chapter 13 SMBus 2.0 EC register model 86 */ 87 #define NVIDIA_SMB_PRTCL (smbus->base + 0x00) /* protocol, PEC */ 88 #define NVIDIA_SMB_STS (smbus->base + 0x01) /* status */ 89 #define NVIDIA_SMB_ADDR (smbus->base + 0x02) /* address */ 90 #define NVIDIA_SMB_CMD (smbus->base + 0x03) /* command */ 91 #define NVIDIA_SMB_DATA (smbus->base + 0x04) /* 32 data registers */ 92 #define NVIDIA_SMB_BCNT (smbus->base + 0x24) /* number of data 93 bytes */ 94 #define NVIDIA_SMB_STATUS_ABRT (smbus->base + 0x3c) /* register used to 95 check the status of 96 the abort command */ 97 #define NVIDIA_SMB_CTRL (smbus->base + 0x3e) /* control register */ 98 99 #define NVIDIA_SMB_STATUS_ABRT_STS 0x01 /* Bit to notify that 100 abort succeeded */ 101 #define NVIDIA_SMB_CTRL_ABORT 0x20 102 #define NVIDIA_SMB_STS_DONE 0x80 103 #define NVIDIA_SMB_STS_ALRM 0x40 104 #define NVIDIA_SMB_STS_RES 0x20 105 #define NVIDIA_SMB_STS_STATUS 0x1f 106 107 #define NVIDIA_SMB_PRTCL_WRITE 0x00 108 #define NVIDIA_SMB_PRTCL_READ 0x01 109 #define NVIDIA_SMB_PRTCL_QUICK 0x02 110 #define NVIDIA_SMB_PRTCL_BYTE 0x04 111 #define NVIDIA_SMB_PRTCL_BYTE_DATA 0x06 112 #define NVIDIA_SMB_PRTCL_WORD_DATA 0x08 113 #define NVIDIA_SMB_PRTCL_BLOCK_DATA 0x0a 114 #define NVIDIA_SMB_PRTCL_PEC 0x80 115 116 /* Misc definitions */ 117 #define MAX_TIMEOUT 100 118 119 /* We disable the second SMBus channel on these boards */ 120 static struct dmi_system_id __devinitdata nforce2_dmi_blacklist2[] = { 121 { 122 .ident = "DFI Lanparty NF4 Expert", 123 .matches = { 124 DMI_MATCH(DMI_BOARD_VENDOR, "DFI Corp,LTD"), 125 DMI_MATCH(DMI_BOARD_NAME, "LP UT NF4 Expert"), 126 }, 127 }, 128 { } 129 }; 130 131 static struct pci_driver nforce2_driver; 132 133 /* For multiplexing support, we need a global reference to the 1st 134 SMBus channel */ 135 #if defined CONFIG_I2C_NFORCE2_S4985 || defined CONFIG_I2C_NFORCE2_S4985_MODULE 136 struct i2c_adapter *nforce2_smbus; 137 EXPORT_SYMBOL_GPL(nforce2_smbus); 138 139 static void nforce2_set_reference(struct i2c_adapter *adap) 140 { 141 nforce2_smbus = adap; 142 } 143 #else 144 static inline void nforce2_set_reference(struct i2c_adapter *adap) { } 145 #endif 146 147 static void nforce2_abort(struct i2c_adapter *adap) 148 { 149 struct nforce2_smbus *smbus = adap->algo_data; 150 int timeout = 0; 151 unsigned char temp; 152 153 dev_dbg(&adap->dev, "Aborting current transaction\n"); 154 155 outb_p(NVIDIA_SMB_CTRL_ABORT, NVIDIA_SMB_CTRL); 156 do { 157 msleep(1); 158 temp = inb_p(NVIDIA_SMB_STATUS_ABRT); 159 } while (!(temp & NVIDIA_SMB_STATUS_ABRT_STS) && 160 (timeout++ < MAX_TIMEOUT)); 161 if (!(temp & NVIDIA_SMB_STATUS_ABRT_STS)) 162 dev_err(&adap->dev, "Can't reset the smbus\n"); 163 outb_p(NVIDIA_SMB_STATUS_ABRT_STS, NVIDIA_SMB_STATUS_ABRT); 164 } 165 166 static int nforce2_check_status(struct i2c_adapter *adap) 167 { 168 struct nforce2_smbus *smbus = adap->algo_data; 169 int timeout = 0; 170 unsigned char temp; 171 172 do { 173 msleep(1); 174 temp = inb_p(NVIDIA_SMB_STS); 175 } while ((!temp) && (timeout++ < MAX_TIMEOUT)); 176 177 if (timeout > MAX_TIMEOUT) { 178 dev_dbg(&adap->dev, "SMBus Timeout!\n"); 179 if (smbus->can_abort) 180 nforce2_abort(adap); 181 return -ETIMEDOUT; 182 } 183 if (!(temp & NVIDIA_SMB_STS_DONE) || (temp & NVIDIA_SMB_STS_STATUS)) { 184 dev_dbg(&adap->dev, "Transaction failed (0x%02x)!\n", temp); 185 return -EIO; 186 } 187 return 0; 188 } 189 190 /* Return negative errno on error */ 191 static s32 nforce2_access(struct i2c_adapter * adap, u16 addr, 192 unsigned short flags, char read_write, 193 u8 command, int size, union i2c_smbus_data * data) 194 { 195 struct nforce2_smbus *smbus = adap->algo_data; 196 unsigned char protocol, pec; 197 u8 len; 198 int i, status; 199 200 protocol = (read_write == I2C_SMBUS_READ) ? NVIDIA_SMB_PRTCL_READ : 201 NVIDIA_SMB_PRTCL_WRITE; 202 pec = (flags & I2C_CLIENT_PEC) ? NVIDIA_SMB_PRTCL_PEC : 0; 203 204 switch (size) { 205 206 case I2C_SMBUS_QUICK: 207 protocol |= NVIDIA_SMB_PRTCL_QUICK; 208 read_write = I2C_SMBUS_WRITE; 209 break; 210 211 case I2C_SMBUS_BYTE: 212 if (read_write == I2C_SMBUS_WRITE) 213 outb_p(command, NVIDIA_SMB_CMD); 214 protocol |= NVIDIA_SMB_PRTCL_BYTE; 215 break; 216 217 case I2C_SMBUS_BYTE_DATA: 218 outb_p(command, NVIDIA_SMB_CMD); 219 if (read_write == I2C_SMBUS_WRITE) 220 outb_p(data->byte, NVIDIA_SMB_DATA); 221 protocol |= NVIDIA_SMB_PRTCL_BYTE_DATA; 222 break; 223 224 case I2C_SMBUS_WORD_DATA: 225 outb_p(command, NVIDIA_SMB_CMD); 226 if (read_write == I2C_SMBUS_WRITE) { 227 outb_p(data->word, NVIDIA_SMB_DATA); 228 outb_p(data->word >> 8, NVIDIA_SMB_DATA+1); 229 } 230 protocol |= NVIDIA_SMB_PRTCL_WORD_DATA | pec; 231 break; 232 233 case I2C_SMBUS_BLOCK_DATA: 234 outb_p(command, NVIDIA_SMB_CMD); 235 if (read_write == I2C_SMBUS_WRITE) { 236 len = data->block[0]; 237 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) { 238 dev_err(&adap->dev, 239 "Transaction failed " 240 "(requested block size: %d)\n", 241 len); 242 return -EINVAL; 243 } 244 outb_p(len, NVIDIA_SMB_BCNT); 245 for (i = 0; i < I2C_SMBUS_BLOCK_MAX; i++) 246 outb_p(data->block[i + 1], 247 NVIDIA_SMB_DATA+i); 248 } 249 protocol |= NVIDIA_SMB_PRTCL_BLOCK_DATA | pec; 250 break; 251 252 default: 253 dev_err(&adap->dev, "Unsupported transaction %d\n", size); 254 return -EOPNOTSUPP; 255 } 256 257 outb_p((addr & 0x7f) << 1, NVIDIA_SMB_ADDR); 258 outb_p(protocol, NVIDIA_SMB_PRTCL); 259 260 status = nforce2_check_status(adap); 261 if (status) 262 return status; 263 264 if (read_write == I2C_SMBUS_WRITE) 265 return 0; 266 267 switch (size) { 268 269 case I2C_SMBUS_BYTE: 270 case I2C_SMBUS_BYTE_DATA: 271 data->byte = inb_p(NVIDIA_SMB_DATA); 272 break; 273 274 case I2C_SMBUS_WORD_DATA: 275 data->word = inb_p(NVIDIA_SMB_DATA) | (inb_p(NVIDIA_SMB_DATA+1) << 8); 276 break; 277 278 case I2C_SMBUS_BLOCK_DATA: 279 len = inb_p(NVIDIA_SMB_BCNT); 280 if ((len <= 0) || (len > I2C_SMBUS_BLOCK_MAX)) { 281 dev_err(&adap->dev, "Transaction failed " 282 "(received block size: 0x%02x)\n", 283 len); 284 return -EPROTO; 285 } 286 for (i = 0; i < len; i++) 287 data->block[i+1] = inb_p(NVIDIA_SMB_DATA + i); 288 data->block[0] = len; 289 break; 290 } 291 292 return 0; 293 } 294 295 296 static u32 nforce2_func(struct i2c_adapter *adapter) 297 { 298 /* other functionality might be possible, but is not tested */ 299 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 300 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 301 I2C_FUNC_SMBUS_PEC | 302 (((struct nforce2_smbus*)adapter->algo_data)->blockops ? 303 I2C_FUNC_SMBUS_BLOCK_DATA : 0); 304 } 305 306 static struct i2c_algorithm smbus_algorithm = { 307 .smbus_xfer = nforce2_access, 308 .functionality = nforce2_func, 309 }; 310 311 312 static const struct pci_device_id nforce2_ids[] = { 313 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS) }, 314 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS) }, 315 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS) }, 316 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS) }, 317 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE4_SMBUS) }, 318 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SMBUS) }, 319 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS) }, 320 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS) }, 321 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SMBUS) }, 322 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_SMBUS) }, 323 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_SMBUS) }, 324 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_SMBUS) }, 325 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP78S_SMBUS) }, 326 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP79_SMBUS) }, 327 { 0 } 328 }; 329 330 MODULE_DEVICE_TABLE (pci, nforce2_ids); 331 332 333 static int __devinit nforce2_probe_smb (struct pci_dev *dev, int bar, 334 int alt_reg, struct nforce2_smbus *smbus, const char *name) 335 { 336 int error; 337 338 smbus->base = pci_resource_start(dev, bar); 339 if (smbus->base) { 340 smbus->size = pci_resource_len(dev, bar); 341 } else { 342 /* Older incarnations of the device used non-standard BARs */ 343 u16 iobase; 344 345 if (pci_read_config_word(dev, alt_reg, &iobase) 346 != PCIBIOS_SUCCESSFUL) { 347 dev_err(&dev->dev, "Error reading PCI config for %s\n", 348 name); 349 return -EIO; 350 } 351 352 smbus->base = iobase & PCI_BASE_ADDRESS_IO_MASK; 353 smbus->size = 64; 354 } 355 356 error = acpi_check_region(smbus->base, smbus->size, 357 nforce2_driver.name); 358 if (error) 359 return -1; 360 361 if (!request_region(smbus->base, smbus->size, nforce2_driver.name)) { 362 dev_err(&smbus->adapter.dev, "Error requesting region %02x .. %02X for %s\n", 363 smbus->base, smbus->base+smbus->size-1, name); 364 return -EBUSY; 365 } 366 smbus->adapter.owner = THIS_MODULE; 367 smbus->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 368 smbus->adapter.algo = &smbus_algorithm; 369 smbus->adapter.algo_data = smbus; 370 smbus->adapter.dev.parent = &dev->dev; 371 snprintf(smbus->adapter.name, sizeof(smbus->adapter.name), 372 "SMBus nForce2 adapter at %04x", smbus->base); 373 374 error = i2c_add_adapter(&smbus->adapter); 375 if (error) { 376 dev_err(&smbus->adapter.dev, "Failed to register adapter.\n"); 377 release_region(smbus->base, smbus->size); 378 return error; 379 } 380 dev_info(&smbus->adapter.dev, "nForce2 SMBus adapter at %#x\n", smbus->base); 381 return 0; 382 } 383 384 385 static int __devinit nforce2_probe(struct pci_dev *dev, const struct pci_device_id *id) 386 { 387 struct nforce2_smbus *smbuses; 388 int res1, res2; 389 390 /* we support 2 SMBus adapters */ 391 if (!(smbuses = kzalloc(2*sizeof(struct nforce2_smbus), GFP_KERNEL))) 392 return -ENOMEM; 393 pci_set_drvdata(dev, smbuses); 394 395 switch(dev->device) { 396 case PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS: 397 case PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS: 398 case PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS: 399 smbuses[0].blockops = 1; 400 smbuses[1].blockops = 1; 401 smbuses[0].can_abort = 1; 402 smbuses[1].can_abort = 1; 403 } 404 405 /* SMBus adapter 1 */ 406 res1 = nforce2_probe_smb(dev, 4, NFORCE_PCI_SMB1, &smbuses[0], "SMB1"); 407 if (res1 < 0) 408 smbuses[0].base = 0; /* to have a check value */ 409 410 /* SMBus adapter 2 */ 411 if (dmi_check_system(nforce2_dmi_blacklist2)) { 412 dev_err(&dev->dev, "Disabling SMB2 for safety reasons.\n"); 413 res2 = -EPERM; 414 smbuses[1].base = 0; 415 } else { 416 res2 = nforce2_probe_smb(dev, 5, NFORCE_PCI_SMB2, &smbuses[1], 417 "SMB2"); 418 if (res2 < 0) 419 smbuses[1].base = 0; /* to have a check value */ 420 } 421 422 if ((res1 < 0) && (res2 < 0)) { 423 /* we did not find even one of the SMBuses, so we give up */ 424 kfree(smbuses); 425 return -ENODEV; 426 } 427 428 nforce2_set_reference(&smbuses[0].adapter); 429 return 0; 430 } 431 432 433 static void __devexit nforce2_remove(struct pci_dev *dev) 434 { 435 struct nforce2_smbus *smbuses = (void*) pci_get_drvdata(dev); 436 437 nforce2_set_reference(NULL); 438 if (smbuses[0].base) { 439 i2c_del_adapter(&smbuses[0].adapter); 440 release_region(smbuses[0].base, smbuses[0].size); 441 } 442 if (smbuses[1].base) { 443 i2c_del_adapter(&smbuses[1].adapter); 444 release_region(smbuses[1].base, smbuses[1].size); 445 } 446 kfree(smbuses); 447 } 448 449 static struct pci_driver nforce2_driver = { 450 .name = "nForce2_smbus", 451 .id_table = nforce2_ids, 452 .probe = nforce2_probe, 453 .remove = __devexit_p(nforce2_remove), 454 }; 455 456 static int __init nforce2_init(void) 457 { 458 return pci_register_driver(&nforce2_driver); 459 } 460 461 static void __exit nforce2_exit(void) 462 { 463 pci_unregister_driver(&nforce2_driver); 464 } 465 466 module_init(nforce2_init); 467 module_exit(nforce2_exit); 468 469