1 /* 2 * Freescale MXS I2C bus driver 3 * 4 * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K. 5 * 6 * based on a (non-working) driver which was: 7 * 8 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 */ 16 17 #include <linux/slab.h> 18 #include <linux/device.h> 19 #include <linux/module.h> 20 #include <linux/i2c.h> 21 #include <linux/err.h> 22 #include <linux/interrupt.h> 23 #include <linux/completion.h> 24 #include <linux/platform_device.h> 25 #include <linux/jiffies.h> 26 #include <linux/io.h> 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/stmp_device.h> 29 #include <linux/of.h> 30 #include <linux/of_device.h> 31 #include <linux/of_i2c.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/dmaengine.h> 34 #include <linux/fsl/mxs-dma.h> 35 36 #define DRIVER_NAME "mxs-i2c" 37 38 static bool use_pioqueue; 39 module_param(use_pioqueue, bool, 0); 40 MODULE_PARM_DESC(use_pioqueue, "Use PIOQUEUE mode for transfer instead of DMA"); 41 42 #define MXS_I2C_CTRL0 (0x00) 43 #define MXS_I2C_CTRL0_SET (0x04) 44 45 #define MXS_I2C_CTRL0_SFTRST 0x80000000 46 #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000 47 #define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000 48 #define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000 49 #define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000 50 #define MXS_I2C_CTRL0_MASTER_MODE 0x00020000 51 #define MXS_I2C_CTRL0_DIRECTION 0x00010000 52 #define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF) 53 54 #define MXS_I2C_TIMING0 (0x10) 55 #define MXS_I2C_TIMING1 (0x20) 56 #define MXS_I2C_TIMING2 (0x30) 57 58 #define MXS_I2C_CTRL1 (0x40) 59 #define MXS_I2C_CTRL1_SET (0x44) 60 #define MXS_I2C_CTRL1_CLR (0x48) 61 62 #define MXS_I2C_CTRL1_BUS_FREE_IRQ 0x80 63 #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40 64 #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20 65 #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10 66 #define MXS_I2C_CTRL1_EARLY_TERM_IRQ 0x08 67 #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ 0x04 68 #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ 0x02 69 #define MXS_I2C_CTRL1_SLAVE_IRQ 0x01 70 71 #define MXS_I2C_IRQ_MASK (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \ 72 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \ 73 MXS_I2C_CTRL1_EARLY_TERM_IRQ | \ 74 MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \ 75 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \ 76 MXS_I2C_CTRL1_SLAVE_IRQ) 77 78 #define MXS_I2C_QUEUECTRL (0x60) 79 #define MXS_I2C_QUEUECTRL_SET (0x64) 80 #define MXS_I2C_QUEUECTRL_CLR (0x68) 81 82 #define MXS_I2C_QUEUECTRL_QUEUE_RUN 0x20 83 #define MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE 0x04 84 85 #define MXS_I2C_QUEUESTAT (0x70) 86 #define MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY 0x00002000 87 #define MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK 0x0000001F 88 89 #define MXS_I2C_QUEUECMD (0x80) 90 91 #define MXS_I2C_QUEUEDATA (0x90) 92 93 #define MXS_I2C_DATA (0xa0) 94 95 96 #define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \ 97 MXS_I2C_CTRL0_PRE_SEND_START | \ 98 MXS_I2C_CTRL0_MASTER_MODE | \ 99 MXS_I2C_CTRL0_DIRECTION | \ 100 MXS_I2C_CTRL0_XFER_COUNT(1)) 101 102 #define MXS_CMD_I2C_WRITE (MXS_I2C_CTRL0_PRE_SEND_START | \ 103 MXS_I2C_CTRL0_MASTER_MODE | \ 104 MXS_I2C_CTRL0_DIRECTION) 105 106 #define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \ 107 MXS_I2C_CTRL0_MASTER_MODE) 108 109 struct mxs_i2c_speed_config { 110 uint32_t timing0; 111 uint32_t timing1; 112 uint32_t timing2; 113 }; 114 115 /* 116 * Timing values for the default 24MHz clock supplied into the i2c block. 117 * 118 * The bus can operate at 95kHz or at 400kHz with the following timing 119 * register configurations. The 100kHz mode isn't present because it's 120 * values are not stated in the i.MX233/i.MX28 datasheet. The 95kHz mode 121 * shall be close enough replacement. Therefore when the bus is configured 122 * for 100kHz operation, 95kHz timing settings are actually loaded. 123 * 124 * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4]. 125 */ 126 static const struct mxs_i2c_speed_config mxs_i2c_95kHz_config = { 127 .timing0 = 0x00780030, 128 .timing1 = 0x00800030, 129 .timing2 = 0x00300030, 130 }; 131 132 static const struct mxs_i2c_speed_config mxs_i2c_400kHz_config = { 133 .timing0 = 0x000f0007, 134 .timing1 = 0x001f000f, 135 .timing2 = 0x00300030, 136 }; 137 138 /** 139 * struct mxs_i2c_dev - per device, private MXS-I2C data 140 * 141 * @dev: driver model device node 142 * @regs: IO registers pointer 143 * @cmd_complete: completion object for transaction wait 144 * @cmd_err: error code for last transaction 145 * @adapter: i2c subsystem adapter node 146 */ 147 struct mxs_i2c_dev { 148 struct device *dev; 149 void __iomem *regs; 150 struct completion cmd_complete; 151 u32 cmd_err; 152 struct i2c_adapter adapter; 153 const struct mxs_i2c_speed_config *speed; 154 155 /* DMA support components */ 156 bool dma_mode; 157 int dma_channel; 158 struct dma_chan *dmach; 159 struct mxs_dma_data dma_data; 160 uint32_t pio_data[2]; 161 uint32_t addr_data; 162 struct scatterlist sg_io[2]; 163 bool dma_read; 164 }; 165 166 static void mxs_i2c_reset(struct mxs_i2c_dev *i2c) 167 { 168 stmp_reset_block(i2c->regs); 169 170 writel(i2c->speed->timing0, i2c->regs + MXS_I2C_TIMING0); 171 writel(i2c->speed->timing1, i2c->regs + MXS_I2C_TIMING1); 172 writel(i2c->speed->timing2, i2c->regs + MXS_I2C_TIMING2); 173 174 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET); 175 if (i2c->dma_mode) 176 writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE, 177 i2c->regs + MXS_I2C_QUEUECTRL_CLR); 178 else 179 writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE, 180 i2c->regs + MXS_I2C_QUEUECTRL_SET); 181 } 182 183 static void mxs_i2c_pioq_setup_read(struct mxs_i2c_dev *i2c, u8 addr, int len, 184 int flags) 185 { 186 u32 data; 187 188 writel(MXS_CMD_I2C_SELECT, i2c->regs + MXS_I2C_QUEUECMD); 189 190 data = (addr << 1) | I2C_SMBUS_READ; 191 writel(data, i2c->regs + MXS_I2C_DATA); 192 193 data = MXS_CMD_I2C_READ | MXS_I2C_CTRL0_XFER_COUNT(len) | flags; 194 writel(data, i2c->regs + MXS_I2C_QUEUECMD); 195 } 196 197 static void mxs_i2c_pioq_setup_write(struct mxs_i2c_dev *i2c, 198 u8 addr, u8 *buf, int len, int flags) 199 { 200 u32 data; 201 int i, shifts_left; 202 203 data = MXS_CMD_I2C_WRITE | MXS_I2C_CTRL0_XFER_COUNT(len + 1) | flags; 204 writel(data, i2c->regs + MXS_I2C_QUEUECMD); 205 206 /* 207 * We have to copy the slave address (u8) and buffer (arbitrary number 208 * of u8) into the data register (u32). To achieve that, the u8 are put 209 * into the MSBs of 'data' which is then shifted for the next u8. When 210 * appropriate, 'data' is written to MXS_I2C_DATA. So, the first u32 211 * looks like this: 212 * 213 * 3 2 1 0 214 * 10987654|32109876|54321098|76543210 215 * --------+--------+--------+-------- 216 * buffer+2|buffer+1|buffer+0|slave_addr 217 */ 218 219 data = ((addr << 1) | I2C_SMBUS_WRITE) << 24; 220 221 for (i = 0; i < len; i++) { 222 data >>= 8; 223 data |= buf[i] << 24; 224 if ((i & 3) == 2) 225 writel(data, i2c->regs + MXS_I2C_DATA); 226 } 227 228 /* Write out the remaining bytes if any */ 229 shifts_left = 24 - (i & 3) * 8; 230 if (shifts_left) 231 writel(data >> shifts_left, i2c->regs + MXS_I2C_DATA); 232 } 233 234 /* 235 * TODO: should be replaceable with a waitqueue and RD_QUEUE_IRQ (setting the 236 * rd_threshold to 1). Couldn't get this to work, though. 237 */ 238 static int mxs_i2c_wait_for_data(struct mxs_i2c_dev *i2c) 239 { 240 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 241 242 while (readl(i2c->regs + MXS_I2C_QUEUESTAT) 243 & MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY) { 244 if (time_after(jiffies, timeout)) 245 return -ETIMEDOUT; 246 cond_resched(); 247 } 248 249 return 0; 250 } 251 252 static int mxs_i2c_finish_read(struct mxs_i2c_dev *i2c, u8 *buf, int len) 253 { 254 u32 uninitialized_var(data); 255 int i; 256 257 for (i = 0; i < len; i++) { 258 if ((i & 3) == 0) { 259 if (mxs_i2c_wait_for_data(i2c)) 260 return -ETIMEDOUT; 261 data = readl(i2c->regs + MXS_I2C_QUEUEDATA); 262 } 263 buf[i] = data & 0xff; 264 data >>= 8; 265 } 266 267 return 0; 268 } 269 270 static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c) 271 { 272 if (i2c->dma_read) { 273 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE); 274 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE); 275 } else { 276 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE); 277 } 278 } 279 280 static void mxs_i2c_dma_irq_callback(void *param) 281 { 282 struct mxs_i2c_dev *i2c = param; 283 284 complete(&i2c->cmd_complete); 285 mxs_i2c_dma_finish(i2c); 286 } 287 288 static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap, 289 struct i2c_msg *msg, uint32_t flags) 290 { 291 struct dma_async_tx_descriptor *desc; 292 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap); 293 294 if (msg->flags & I2C_M_RD) { 295 i2c->dma_read = 1; 296 i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_READ; 297 298 /* 299 * SELECT command. 300 */ 301 302 /* Queue the PIO register write transfer. */ 303 i2c->pio_data[0] = MXS_CMD_I2C_SELECT; 304 desc = dmaengine_prep_slave_sg(i2c->dmach, 305 (struct scatterlist *)&i2c->pio_data[0], 306 1, DMA_TRANS_NONE, 0); 307 if (!desc) { 308 dev_err(i2c->dev, 309 "Failed to get PIO reg. write descriptor.\n"); 310 goto select_init_pio_fail; 311 } 312 313 /* Queue the DMA data transfer. */ 314 sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1); 315 dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE); 316 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1, 317 DMA_MEM_TO_DEV, 318 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 319 if (!desc) { 320 dev_err(i2c->dev, 321 "Failed to get DMA data write descriptor.\n"); 322 goto select_init_dma_fail; 323 } 324 325 /* 326 * READ command. 327 */ 328 329 /* Queue the PIO register write transfer. */ 330 i2c->pio_data[1] = flags | MXS_CMD_I2C_READ | 331 MXS_I2C_CTRL0_XFER_COUNT(msg->len); 332 desc = dmaengine_prep_slave_sg(i2c->dmach, 333 (struct scatterlist *)&i2c->pio_data[1], 334 1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT); 335 if (!desc) { 336 dev_err(i2c->dev, 337 "Failed to get PIO reg. write descriptor.\n"); 338 goto select_init_dma_fail; 339 } 340 341 /* Queue the DMA data transfer. */ 342 sg_init_one(&i2c->sg_io[1], msg->buf, msg->len); 343 dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE); 344 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1, 345 DMA_DEV_TO_MEM, 346 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 347 if (!desc) { 348 dev_err(i2c->dev, 349 "Failed to get DMA data write descriptor.\n"); 350 goto read_init_dma_fail; 351 } 352 } else { 353 i2c->dma_read = 0; 354 i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_WRITE; 355 356 /* 357 * WRITE command. 358 */ 359 360 /* Queue the PIO register write transfer. */ 361 i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE | 362 MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1); 363 desc = dmaengine_prep_slave_sg(i2c->dmach, 364 (struct scatterlist *)&i2c->pio_data[0], 365 1, DMA_TRANS_NONE, 0); 366 if (!desc) { 367 dev_err(i2c->dev, 368 "Failed to get PIO reg. write descriptor.\n"); 369 goto write_init_pio_fail; 370 } 371 372 /* Queue the DMA data transfer. */ 373 sg_init_table(i2c->sg_io, 2); 374 sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1); 375 sg_set_buf(&i2c->sg_io[1], msg->buf, msg->len); 376 dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE); 377 desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2, 378 DMA_MEM_TO_DEV, 379 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 380 if (!desc) { 381 dev_err(i2c->dev, 382 "Failed to get DMA data write descriptor.\n"); 383 goto write_init_dma_fail; 384 } 385 } 386 387 /* 388 * The last descriptor must have this callback, 389 * to finish the DMA transaction. 390 */ 391 desc->callback = mxs_i2c_dma_irq_callback; 392 desc->callback_param = i2c; 393 394 /* Start the transfer. */ 395 dmaengine_submit(desc); 396 dma_async_issue_pending(i2c->dmach); 397 return 0; 398 399 /* Read failpath. */ 400 read_init_dma_fail: 401 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE); 402 select_init_dma_fail: 403 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE); 404 select_init_pio_fail: 405 return -EINVAL; 406 407 /* Write failpath. */ 408 write_init_dma_fail: 409 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE); 410 write_init_pio_fail: 411 return -EINVAL; 412 } 413 414 /* 415 * Low level master read/write transaction. 416 */ 417 static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, 418 int stop) 419 { 420 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap); 421 int ret; 422 int flags; 423 424 flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0; 425 426 dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", 427 msg->addr, msg->len, msg->flags, stop); 428 429 if (msg->len == 0) 430 return -EINVAL; 431 432 init_completion(&i2c->cmd_complete); 433 i2c->cmd_err = 0; 434 435 if (i2c->dma_mode) { 436 ret = mxs_i2c_dma_setup_xfer(adap, msg, flags); 437 if (ret) 438 return ret; 439 } else { 440 if (msg->flags & I2C_M_RD) { 441 mxs_i2c_pioq_setup_read(i2c, msg->addr, 442 msg->len, flags); 443 } else { 444 mxs_i2c_pioq_setup_write(i2c, msg->addr, msg->buf, 445 msg->len, flags); 446 } 447 448 writel(MXS_I2C_QUEUECTRL_QUEUE_RUN, 449 i2c->regs + MXS_I2C_QUEUECTRL_SET); 450 } 451 452 ret = wait_for_completion_timeout(&i2c->cmd_complete, 453 msecs_to_jiffies(1000)); 454 if (ret == 0) 455 goto timeout; 456 457 if (!i2c->dma_mode && !i2c->cmd_err && (msg->flags & I2C_M_RD)) { 458 ret = mxs_i2c_finish_read(i2c, msg->buf, msg->len); 459 if (ret) 460 goto timeout; 461 } 462 463 if (i2c->cmd_err == -ENXIO) 464 mxs_i2c_reset(i2c); 465 else 466 writel(MXS_I2C_QUEUECTRL_QUEUE_RUN, 467 i2c->regs + MXS_I2C_QUEUECTRL_CLR); 468 469 dev_dbg(i2c->dev, "Done with err=%d\n", i2c->cmd_err); 470 471 return i2c->cmd_err; 472 473 timeout: 474 dev_dbg(i2c->dev, "Timeout!\n"); 475 if (i2c->dma_mode) 476 mxs_i2c_dma_finish(i2c); 477 mxs_i2c_reset(i2c); 478 return -ETIMEDOUT; 479 } 480 481 static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 482 int num) 483 { 484 int i; 485 int err; 486 487 for (i = 0; i < num; i++) { 488 err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1)); 489 if (err) 490 return err; 491 } 492 493 return num; 494 } 495 496 static u32 mxs_i2c_func(struct i2c_adapter *adap) 497 { 498 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 499 } 500 501 static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id) 502 { 503 struct mxs_i2c_dev *i2c = dev_id; 504 u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK; 505 bool is_last_cmd; 506 507 if (!stat) 508 return IRQ_NONE; 509 510 if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ) 511 i2c->cmd_err = -ENXIO; 512 else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ | 513 MXS_I2C_CTRL1_MASTER_LOSS_IRQ | 514 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ)) 515 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */ 516 i2c->cmd_err = -EIO; 517 518 if (!i2c->dma_mode) { 519 is_last_cmd = (readl(i2c->regs + MXS_I2C_QUEUESTAT) & 520 MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK) == 0; 521 522 if (is_last_cmd || i2c->cmd_err) 523 complete(&i2c->cmd_complete); 524 } 525 526 writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR); 527 528 return IRQ_HANDLED; 529 } 530 531 static const struct i2c_algorithm mxs_i2c_algo = { 532 .master_xfer = mxs_i2c_xfer, 533 .functionality = mxs_i2c_func, 534 }; 535 536 static bool mxs_i2c_dma_filter(struct dma_chan *chan, void *param) 537 { 538 struct mxs_i2c_dev *i2c = param; 539 540 if (!mxs_dma_is_apbx(chan)) 541 return false; 542 543 if (chan->chan_id != i2c->dma_channel) 544 return false; 545 546 chan->private = &i2c->dma_data; 547 548 return true; 549 } 550 551 static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c) 552 { 553 uint32_t speed; 554 struct device *dev = i2c->dev; 555 struct device_node *node = dev->of_node; 556 int ret; 557 558 /* 559 * The MXS I2C DMA mode is prefered and enabled by default. 560 * The PIO mode is still supported, but should be used only 561 * for debuging purposes etc. 562 */ 563 i2c->dma_mode = !use_pioqueue; 564 if (!i2c->dma_mode) 565 dev_info(dev, "Using PIOQUEUE mode for I2C transfers!\n"); 566 567 /* 568 * TODO: This is a temporary solution and should be changed 569 * to use generic DMA binding later when the helpers get in. 570 */ 571 ret = of_property_read_u32(node, "fsl,i2c-dma-channel", 572 &i2c->dma_channel); 573 if (ret) { 574 dev_warn(dev, "Failed to get DMA channel, using PIOQUEUE!\n"); 575 i2c->dma_mode = 0; 576 } 577 578 ret = of_property_read_u32(node, "clock-frequency", &speed); 579 if (ret) 580 dev_warn(dev, "No I2C speed selected, using 100kHz\n"); 581 else if (speed == 400000) 582 i2c->speed = &mxs_i2c_400kHz_config; 583 else if (speed != 100000) 584 dev_warn(dev, "Unsupported I2C speed selected, using 100kHz\n"); 585 586 return 0; 587 } 588 589 static int __devinit mxs_i2c_probe(struct platform_device *pdev) 590 { 591 struct device *dev = &pdev->dev; 592 struct mxs_i2c_dev *i2c; 593 struct i2c_adapter *adap; 594 struct pinctrl *pinctrl; 595 struct resource *res; 596 resource_size_t res_size; 597 int err, irq, dmairq; 598 dma_cap_mask_t mask; 599 600 pinctrl = devm_pinctrl_get_select_default(dev); 601 if (IS_ERR(pinctrl)) 602 return PTR_ERR(pinctrl); 603 604 i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL); 605 if (!i2c) 606 return -ENOMEM; 607 608 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 609 irq = platform_get_irq(pdev, 0); 610 dmairq = platform_get_irq(pdev, 1); 611 612 if (!res || irq < 0 || dmairq < 0) 613 return -ENOENT; 614 615 res_size = resource_size(res); 616 if (!devm_request_mem_region(dev, res->start, res_size, res->name)) 617 return -EBUSY; 618 619 i2c->regs = devm_ioremap_nocache(dev, res->start, res_size); 620 if (!i2c->regs) 621 return -EBUSY; 622 623 err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c); 624 if (err) 625 return err; 626 627 i2c->dev = dev; 628 i2c->speed = &mxs_i2c_95kHz_config; 629 630 if (dev->of_node) { 631 err = mxs_i2c_get_ofdata(i2c); 632 if (err) 633 return err; 634 } 635 636 /* Setup the DMA */ 637 if (i2c->dma_mode) { 638 dma_cap_zero(mask); 639 dma_cap_set(DMA_SLAVE, mask); 640 i2c->dma_data.chan_irq = dmairq; 641 i2c->dmach = dma_request_channel(mask, mxs_i2c_dma_filter, i2c); 642 if (!i2c->dmach) { 643 dev_err(dev, "Failed to request dma\n"); 644 return -ENODEV; 645 } 646 } 647 648 platform_set_drvdata(pdev, i2c); 649 650 /* Do reset to enforce correct startup after pinmuxing */ 651 mxs_i2c_reset(i2c); 652 653 adap = &i2c->adapter; 654 strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name)); 655 adap->owner = THIS_MODULE; 656 adap->algo = &mxs_i2c_algo; 657 adap->dev.parent = dev; 658 adap->nr = pdev->id; 659 adap->dev.of_node = pdev->dev.of_node; 660 i2c_set_adapdata(adap, i2c); 661 err = i2c_add_numbered_adapter(adap); 662 if (err) { 663 dev_err(dev, "Failed to add adapter (%d)\n", err); 664 writel(MXS_I2C_CTRL0_SFTRST, 665 i2c->regs + MXS_I2C_CTRL0_SET); 666 return err; 667 } 668 669 of_i2c_register_devices(adap); 670 671 return 0; 672 } 673 674 static int __devexit mxs_i2c_remove(struct platform_device *pdev) 675 { 676 struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev); 677 int ret; 678 679 ret = i2c_del_adapter(&i2c->adapter); 680 if (ret) 681 return -EBUSY; 682 683 if (i2c->dmach) 684 dma_release_channel(i2c->dmach); 685 686 writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET); 687 688 platform_set_drvdata(pdev, NULL); 689 690 return 0; 691 } 692 693 static const struct of_device_id mxs_i2c_dt_ids[] = { 694 { .compatible = "fsl,imx28-i2c", }, 695 { /* sentinel */ } 696 }; 697 MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids); 698 699 static struct platform_driver mxs_i2c_driver = { 700 .driver = { 701 .name = DRIVER_NAME, 702 .owner = THIS_MODULE, 703 .of_match_table = mxs_i2c_dt_ids, 704 }, 705 .remove = __devexit_p(mxs_i2c_remove), 706 }; 707 708 static int __init mxs_i2c_init(void) 709 { 710 return platform_driver_probe(&mxs_i2c_driver, mxs_i2c_probe); 711 } 712 subsys_initcall(mxs_i2c_init); 713 714 static void __exit mxs_i2c_exit(void) 715 { 716 platform_driver_unregister(&mxs_i2c_driver); 717 } 718 module_exit(mxs_i2c_exit); 719 720 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); 721 MODULE_DESCRIPTION("MXS I2C Bus Driver"); 722 MODULE_LICENSE("GPL"); 723 MODULE_ALIAS("platform:" DRIVER_NAME); 724