1 /* 2 * Driver for the i2c controller on the Marvell line of host bridges for MIPS 3 * and PPC (e.g, gt642[46]0, mv643[46]0, mv644[46]0). 4 * 5 * Author: Mark A. Greer <mgreer@mvista.com> 6 * 7 * 2005 (c) MontaVista, Software, Inc. This file is licensed under 8 * the terms of the GNU General Public License version 2. This program 9 * is licensed "as is" without any warranty of any kind, whether express 10 * or implied. 11 */ 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/spinlock.h> 15 #include <linux/i2c.h> 16 #include <linux/interrupt.h> 17 #include <linux/mv643xx.h> 18 #include <linux/platform_device.h> 19 20 #include <asm/io.h> 21 22 /* Register defines */ 23 #define MV64XXX_I2C_REG_SLAVE_ADDR 0x00 24 #define MV64XXX_I2C_REG_DATA 0x04 25 #define MV64XXX_I2C_REG_CONTROL 0x08 26 #define MV64XXX_I2C_REG_STATUS 0x0c 27 #define MV64XXX_I2C_REG_BAUD 0x0c 28 #define MV64XXX_I2C_REG_EXT_SLAVE_ADDR 0x10 29 #define MV64XXX_I2C_REG_SOFT_RESET 0x1c 30 31 #define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004 32 #define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008 33 #define MV64XXX_I2C_REG_CONTROL_STOP 0x00000010 34 #define MV64XXX_I2C_REG_CONTROL_START 0x00000020 35 #define MV64XXX_I2C_REG_CONTROL_TWSIEN 0x00000040 36 #define MV64XXX_I2C_REG_CONTROL_INTEN 0x00000080 37 38 /* Ctlr status values */ 39 #define MV64XXX_I2C_STATUS_BUS_ERR 0x00 40 #define MV64XXX_I2C_STATUS_MAST_START 0x08 41 #define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10 42 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18 43 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20 44 #define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28 45 #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30 46 #define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38 47 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40 48 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48 49 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50 50 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58 51 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0 52 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8 53 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0 54 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8 55 #define MV64XXX_I2C_STATUS_NO_STATUS 0xf8 56 57 /* Driver states */ 58 enum { 59 MV64XXX_I2C_STATE_INVALID, 60 MV64XXX_I2C_STATE_IDLE, 61 MV64XXX_I2C_STATE_WAITING_FOR_START_COND, 62 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK, 63 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK, 64 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK, 65 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA, 66 }; 67 68 /* Driver actions */ 69 enum { 70 MV64XXX_I2C_ACTION_INVALID, 71 MV64XXX_I2C_ACTION_CONTINUE, 72 MV64XXX_I2C_ACTION_SEND_START, 73 MV64XXX_I2C_ACTION_SEND_ADDR_1, 74 MV64XXX_I2C_ACTION_SEND_ADDR_2, 75 MV64XXX_I2C_ACTION_SEND_DATA, 76 MV64XXX_I2C_ACTION_RCV_DATA, 77 MV64XXX_I2C_ACTION_RCV_DATA_STOP, 78 MV64XXX_I2C_ACTION_SEND_STOP, 79 }; 80 81 struct mv64xxx_i2c_data { 82 int irq; 83 u32 state; 84 u32 action; 85 u32 aborting; 86 u32 cntl_bits; 87 void __iomem *reg_base; 88 u32 reg_base_p; 89 u32 addr1; 90 u32 addr2; 91 u32 bytes_left; 92 u32 byte_posn; 93 u32 block; 94 int rc; 95 u32 freq_m; 96 u32 freq_n; 97 wait_queue_head_t waitq; 98 spinlock_t lock; 99 struct i2c_msg *msg; 100 struct i2c_adapter adapter; 101 }; 102 103 /* 104 ***************************************************************************** 105 * 106 * Finite State Machine & Interrupt Routines 107 * 108 ***************************************************************************** 109 */ 110 static void 111 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status) 112 { 113 /* 114 * If state is idle, then this is likely the remnants of an old 115 * operation that driver has given up on or the user has killed. 116 * If so, issue the stop condition and go to idle. 117 */ 118 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) { 119 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 120 return; 121 } 122 123 /* The status from the ctlr [mostly] tells us what to do next */ 124 switch (status) { 125 /* Start condition interrupt */ 126 case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */ 127 case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */ 128 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1; 129 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK; 130 break; 131 132 /* Performing a write */ 133 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */ 134 if (drv_data->msg->flags & I2C_M_TEN) { 135 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2; 136 drv_data->state = 137 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK; 138 break; 139 } 140 /* FALLTHRU */ 141 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */ 142 case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */ 143 if ((drv_data->bytes_left == 0) 144 || (drv_data->aborting 145 && (drv_data->byte_posn != 0))) { 146 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 147 drv_data->state = MV64XXX_I2C_STATE_IDLE; 148 } else { 149 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA; 150 drv_data->state = 151 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK; 152 drv_data->bytes_left--; 153 } 154 break; 155 156 /* Performing a read */ 157 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */ 158 if (drv_data->msg->flags & I2C_M_TEN) { 159 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2; 160 drv_data->state = 161 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK; 162 break; 163 } 164 /* FALLTHRU */ 165 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */ 166 if (drv_data->bytes_left == 0) { 167 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 168 drv_data->state = MV64XXX_I2C_STATE_IDLE; 169 break; 170 } 171 /* FALLTHRU */ 172 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */ 173 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK) 174 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE; 175 else { 176 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA; 177 drv_data->bytes_left--; 178 } 179 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA; 180 181 if ((drv_data->bytes_left == 1) || drv_data->aborting) 182 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK; 183 break; 184 185 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */ 186 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP; 187 drv_data->state = MV64XXX_I2C_STATE_IDLE; 188 break; 189 190 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */ 191 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */ 192 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */ 193 /* Doesn't seem to be a device at other end */ 194 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 195 drv_data->state = MV64XXX_I2C_STATE_IDLE; 196 drv_data->rc = -ENODEV; 197 break; 198 199 default: 200 dev_err(&drv_data->adapter.dev, 201 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, " 202 "status: 0x%x, addr: 0x%x, flags: 0x%x\n", 203 drv_data->state, status, drv_data->msg->addr, 204 drv_data->msg->flags); 205 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 206 drv_data->state = MV64XXX_I2C_STATE_IDLE; 207 drv_data->rc = -EIO; 208 } 209 } 210 211 static void 212 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data) 213 { 214 switch(drv_data->action) { 215 case MV64XXX_I2C_ACTION_CONTINUE: 216 writel(drv_data->cntl_bits, 217 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 218 break; 219 220 case MV64XXX_I2C_ACTION_SEND_START: 221 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START, 222 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 223 break; 224 225 case MV64XXX_I2C_ACTION_SEND_ADDR_1: 226 writel(drv_data->addr1, 227 drv_data->reg_base + MV64XXX_I2C_REG_DATA); 228 writel(drv_data->cntl_bits, 229 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 230 break; 231 232 case MV64XXX_I2C_ACTION_SEND_ADDR_2: 233 writel(drv_data->addr2, 234 drv_data->reg_base + MV64XXX_I2C_REG_DATA); 235 writel(drv_data->cntl_bits, 236 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 237 break; 238 239 case MV64XXX_I2C_ACTION_SEND_DATA: 240 writel(drv_data->msg->buf[drv_data->byte_posn++], 241 drv_data->reg_base + MV64XXX_I2C_REG_DATA); 242 writel(drv_data->cntl_bits, 243 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 244 break; 245 246 case MV64XXX_I2C_ACTION_RCV_DATA: 247 drv_data->msg->buf[drv_data->byte_posn++] = 248 readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA); 249 writel(drv_data->cntl_bits, 250 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 251 break; 252 253 case MV64XXX_I2C_ACTION_RCV_DATA_STOP: 254 drv_data->msg->buf[drv_data->byte_posn++] = 255 readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA); 256 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; 257 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, 258 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 259 drv_data->block = 0; 260 wake_up_interruptible(&drv_data->waitq); 261 break; 262 263 case MV64XXX_I2C_ACTION_INVALID: 264 default: 265 dev_err(&drv_data->adapter.dev, 266 "mv64xxx_i2c_do_action: Invalid action: %d\n", 267 drv_data->action); 268 drv_data->rc = -EIO; 269 /* FALLTHRU */ 270 case MV64XXX_I2C_ACTION_SEND_STOP: 271 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; 272 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, 273 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 274 drv_data->block = 0; 275 wake_up_interruptible(&drv_data->waitq); 276 break; 277 } 278 } 279 280 static int 281 mv64xxx_i2c_intr(int irq, void *dev_id, struct pt_regs *regs) 282 { 283 struct mv64xxx_i2c_data *drv_data = dev_id; 284 unsigned long flags; 285 u32 status; 286 int rc = IRQ_NONE; 287 288 spin_lock_irqsave(&drv_data->lock, flags); 289 while (readl(drv_data->reg_base + MV64XXX_I2C_REG_CONTROL) & 290 MV64XXX_I2C_REG_CONTROL_IFLG) { 291 status = readl(drv_data->reg_base + MV64XXX_I2C_REG_STATUS); 292 mv64xxx_i2c_fsm(drv_data, status); 293 mv64xxx_i2c_do_action(drv_data); 294 rc = IRQ_HANDLED; 295 } 296 spin_unlock_irqrestore(&drv_data->lock, flags); 297 298 return rc; 299 } 300 301 /* 302 ***************************************************************************** 303 * 304 * I2C Msg Execution Routines 305 * 306 ***************************************************************************** 307 */ 308 static void 309 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data, 310 struct i2c_msg *msg) 311 { 312 u32 dir = 0; 313 314 drv_data->msg = msg; 315 drv_data->byte_posn = 0; 316 drv_data->bytes_left = msg->len; 317 drv_data->aborting = 0; 318 drv_data->rc = 0; 319 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK | 320 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN; 321 322 if (msg->flags & I2C_M_RD) 323 dir = 1; 324 325 if (msg->flags & I2C_M_REV_DIR_ADDR) 326 dir ^= 1; 327 328 if (msg->flags & I2C_M_TEN) { 329 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir; 330 drv_data->addr2 = (u32)msg->addr & 0xff; 331 } else { 332 drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir; 333 drv_data->addr2 = 0; 334 } 335 } 336 337 static void 338 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data) 339 { 340 long time_left; 341 unsigned long flags; 342 char abort = 0; 343 344 time_left = wait_event_interruptible_timeout(drv_data->waitq, 345 !drv_data->block, msecs_to_jiffies(drv_data->adapter.timeout)); 346 347 spin_lock_irqsave(&drv_data->lock, flags); 348 if (!time_left) { /* Timed out */ 349 drv_data->rc = -ETIMEDOUT; 350 abort = 1; 351 } else if (time_left < 0) { /* Interrupted/Error */ 352 drv_data->rc = time_left; /* errno value */ 353 abort = 1; 354 } 355 356 if (abort && drv_data->block) { 357 drv_data->aborting = 1; 358 spin_unlock_irqrestore(&drv_data->lock, flags); 359 360 time_left = wait_event_timeout(drv_data->waitq, 361 !drv_data->block, 362 msecs_to_jiffies(drv_data->adapter.timeout)); 363 364 if ((time_left <= 0) && drv_data->block) { 365 drv_data->state = MV64XXX_I2C_STATE_IDLE; 366 dev_err(&drv_data->adapter.dev, 367 "mv64xxx: I2C bus locked, block: %d, " 368 "time_left: %d\n", drv_data->block, 369 (int)time_left); 370 } 371 } else 372 spin_unlock_irqrestore(&drv_data->lock, flags); 373 } 374 375 static int 376 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg) 377 { 378 unsigned long flags; 379 380 spin_lock_irqsave(&drv_data->lock, flags); 381 mv64xxx_i2c_prepare_for_io(drv_data, msg); 382 383 if (unlikely(msg->flags & I2C_M_NOSTART)) { /* Skip start/addr phases */ 384 if (drv_data->msg->flags & I2C_M_RD) { 385 /* No action to do, wait for slave to send a byte */ 386 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE; 387 drv_data->state = 388 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA; 389 } else { 390 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA; 391 drv_data->state = 392 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK; 393 drv_data->bytes_left--; 394 } 395 } else { 396 drv_data->action = MV64XXX_I2C_ACTION_SEND_START; 397 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND; 398 } 399 400 drv_data->block = 1; 401 mv64xxx_i2c_do_action(drv_data); 402 spin_unlock_irqrestore(&drv_data->lock, flags); 403 404 mv64xxx_i2c_wait_for_completion(drv_data); 405 return drv_data->rc; 406 } 407 408 /* 409 ***************************************************************************** 410 * 411 * I2C Core Support Routines (Interface to higher level I2C code) 412 * 413 ***************************************************************************** 414 */ 415 static u32 416 mv64xxx_i2c_functionality(struct i2c_adapter *adap) 417 { 418 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL; 419 } 420 421 static int 422 mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 423 { 424 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap); 425 int i, rc; 426 427 for (i=0; i<num; i++) 428 if ((rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i])) < 0) 429 return rc; 430 431 return num; 432 } 433 434 static struct i2c_algorithm mv64xxx_i2c_algo = { 435 .master_xfer = mv64xxx_i2c_xfer, 436 .functionality = mv64xxx_i2c_functionality, 437 }; 438 439 /* 440 ***************************************************************************** 441 * 442 * Driver Interface & Early Init Routines 443 * 444 ***************************************************************************** 445 */ 446 static void __devinit 447 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data) 448 { 449 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET); 450 writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)), 451 drv_data->reg_base + MV64XXX_I2C_REG_BAUD); 452 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR); 453 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR); 454 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP, 455 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 456 drv_data->state = MV64XXX_I2C_STATE_IDLE; 457 } 458 459 static int __devinit 460 mv64xxx_i2c_map_regs(struct platform_device *pd, 461 struct mv64xxx_i2c_data *drv_data) 462 { 463 struct resource *r; 464 465 if ((r = platform_get_resource(pd, IORESOURCE_MEM, 0)) && 466 request_mem_region(r->start, MV64XXX_I2C_REG_BLOCK_SIZE, 467 drv_data->adapter.name)) { 468 469 drv_data->reg_base = ioremap(r->start, 470 MV64XXX_I2C_REG_BLOCK_SIZE); 471 drv_data->reg_base_p = r->start; 472 } else 473 return -ENOMEM; 474 475 return 0; 476 } 477 478 static void __devexit 479 mv64xxx_i2c_unmap_regs(struct mv64xxx_i2c_data *drv_data) 480 { 481 if (drv_data->reg_base) { 482 iounmap(drv_data->reg_base); 483 release_mem_region(drv_data->reg_base_p, 484 MV64XXX_I2C_REG_BLOCK_SIZE); 485 } 486 487 drv_data->reg_base = NULL; 488 drv_data->reg_base_p = 0; 489 } 490 491 static int __devinit 492 mv64xxx_i2c_probe(struct platform_device *pd) 493 { 494 struct mv64xxx_i2c_data *drv_data; 495 struct mv64xxx_i2c_pdata *pdata = pd->dev.platform_data; 496 int rc; 497 498 if ((pd->id != 0) || !pdata) 499 return -ENODEV; 500 501 drv_data = kzalloc(sizeof(struct mv64xxx_i2c_data), GFP_KERNEL); 502 if (!drv_data) 503 return -ENOMEM; 504 505 if (mv64xxx_i2c_map_regs(pd, drv_data)) { 506 rc = -ENODEV; 507 goto exit_kfree; 508 } 509 510 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter", 511 I2C_NAME_SIZE); 512 513 init_waitqueue_head(&drv_data->waitq); 514 spin_lock_init(&drv_data->lock); 515 516 drv_data->freq_m = pdata->freq_m; 517 drv_data->freq_n = pdata->freq_n; 518 drv_data->irq = platform_get_irq(pd, 0); 519 if (drv_data->irq < 0) { 520 rc = -ENXIO; 521 goto exit_unmap_regs; 522 } 523 drv_data->adapter.id = I2C_HW_MV64XXX; 524 drv_data->adapter.algo = &mv64xxx_i2c_algo; 525 drv_data->adapter.owner = THIS_MODULE; 526 drv_data->adapter.class = I2C_CLASS_HWMON; 527 drv_data->adapter.timeout = pdata->timeout; 528 drv_data->adapter.retries = pdata->retries; 529 platform_set_drvdata(pd, drv_data); 530 i2c_set_adapdata(&drv_data->adapter, drv_data); 531 532 if (request_irq(drv_data->irq, mv64xxx_i2c_intr, 0, 533 MV64XXX_I2C_CTLR_NAME, drv_data)) { 534 dev_err(&drv_data->adapter.dev, 535 "mv64xxx: Can't register intr handler irq: %d\n", 536 drv_data->irq); 537 rc = -EINVAL; 538 goto exit_unmap_regs; 539 } else if ((rc = i2c_add_adapter(&drv_data->adapter)) != 0) { 540 dev_err(&drv_data->adapter.dev, 541 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc); 542 goto exit_free_irq; 543 } 544 545 mv64xxx_i2c_hw_init(drv_data); 546 547 return 0; 548 549 exit_free_irq: 550 free_irq(drv_data->irq, drv_data); 551 exit_unmap_regs: 552 mv64xxx_i2c_unmap_regs(drv_data); 553 exit_kfree: 554 kfree(drv_data); 555 return rc; 556 } 557 558 static int __devexit 559 mv64xxx_i2c_remove(struct platform_device *dev) 560 { 561 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev); 562 int rc; 563 564 rc = i2c_del_adapter(&drv_data->adapter); 565 free_irq(drv_data->irq, drv_data); 566 mv64xxx_i2c_unmap_regs(drv_data); 567 kfree(drv_data); 568 569 return rc; 570 } 571 572 static struct platform_driver mv64xxx_i2c_driver = { 573 .probe = mv64xxx_i2c_probe, 574 .remove = mv64xxx_i2c_remove, 575 .driver = { 576 .owner = THIS_MODULE, 577 .name = MV64XXX_I2C_CTLR_NAME, 578 }, 579 }; 580 581 static int __init 582 mv64xxx_i2c_init(void) 583 { 584 return platform_driver_register(&mv64xxx_i2c_driver); 585 } 586 587 static void __exit 588 mv64xxx_i2c_exit(void) 589 { 590 platform_driver_unregister(&mv64xxx_i2c_driver); 591 } 592 593 module_init(mv64xxx_i2c_init); 594 module_exit(mv64xxx_i2c_exit); 595 596 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>"); 597 MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver"); 598 MODULE_LICENSE("GPL"); 599