1 /* 2 * Driver for the i2c controller on the Marvell line of host bridges 3 * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family). 4 * 5 * Author: Mark A. Greer <mgreer@mvista.com> 6 * 7 * 2005 (c) MontaVista, Software, Inc. This file is licensed under 8 * the terms of the GNU General Public License version 2. This program 9 * is licensed "as is" without any warranty of any kind, whether express 10 * or implied. 11 */ 12 #include <linux/kernel.h> 13 #include <linux/slab.h> 14 #include <linux/module.h> 15 #include <linux/spinlock.h> 16 #include <linux/i2c.h> 17 #include <linux/interrupt.h> 18 #include <linux/mv643xx_i2c.h> 19 #include <linux/platform_device.h> 20 #include <linux/io.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_i2c.h> 24 #include <linux/clk.h> 25 #include <linux/err.h> 26 27 /* Register defines */ 28 #define MV64XXX_I2C_REG_SLAVE_ADDR 0x00 29 #define MV64XXX_I2C_REG_DATA 0x04 30 #define MV64XXX_I2C_REG_CONTROL 0x08 31 #define MV64XXX_I2C_REG_STATUS 0x0c 32 #define MV64XXX_I2C_REG_BAUD 0x0c 33 #define MV64XXX_I2C_REG_EXT_SLAVE_ADDR 0x10 34 #define MV64XXX_I2C_REG_SOFT_RESET 0x1c 35 36 #define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004 37 #define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008 38 #define MV64XXX_I2C_REG_CONTROL_STOP 0x00000010 39 #define MV64XXX_I2C_REG_CONTROL_START 0x00000020 40 #define MV64XXX_I2C_REG_CONTROL_TWSIEN 0x00000040 41 #define MV64XXX_I2C_REG_CONTROL_INTEN 0x00000080 42 43 /* Ctlr status values */ 44 #define MV64XXX_I2C_STATUS_BUS_ERR 0x00 45 #define MV64XXX_I2C_STATUS_MAST_START 0x08 46 #define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10 47 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18 48 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20 49 #define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28 50 #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30 51 #define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38 52 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40 53 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48 54 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50 55 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58 56 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0 57 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8 58 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0 59 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8 60 #define MV64XXX_I2C_STATUS_NO_STATUS 0xf8 61 62 /* Driver states */ 63 enum { 64 MV64XXX_I2C_STATE_INVALID, 65 MV64XXX_I2C_STATE_IDLE, 66 MV64XXX_I2C_STATE_WAITING_FOR_START_COND, 67 MV64XXX_I2C_STATE_WAITING_FOR_RESTART, 68 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK, 69 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK, 70 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK, 71 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA, 72 }; 73 74 /* Driver actions */ 75 enum { 76 MV64XXX_I2C_ACTION_INVALID, 77 MV64XXX_I2C_ACTION_CONTINUE, 78 MV64XXX_I2C_ACTION_SEND_START, 79 MV64XXX_I2C_ACTION_SEND_RESTART, 80 MV64XXX_I2C_ACTION_SEND_ADDR_1, 81 MV64XXX_I2C_ACTION_SEND_ADDR_2, 82 MV64XXX_I2C_ACTION_SEND_DATA, 83 MV64XXX_I2C_ACTION_RCV_DATA, 84 MV64XXX_I2C_ACTION_RCV_DATA_STOP, 85 MV64XXX_I2C_ACTION_SEND_STOP, 86 }; 87 88 struct mv64xxx_i2c_data { 89 int irq; 90 u32 state; 91 u32 action; 92 u32 aborting; 93 u32 cntl_bits; 94 void __iomem *reg_base; 95 u32 reg_base_p; 96 u32 reg_size; 97 u32 addr1; 98 u32 addr2; 99 u32 bytes_left; 100 u32 byte_posn; 101 u32 send_stop; 102 u32 block; 103 int rc; 104 u32 freq_m; 105 u32 freq_n; 106 #if defined(CONFIG_HAVE_CLK) 107 struct clk *clk; 108 #endif 109 wait_queue_head_t waitq; 110 spinlock_t lock; 111 struct i2c_msg *msg; 112 struct i2c_adapter adapter; 113 }; 114 115 /* 116 ***************************************************************************** 117 * 118 * Finite State Machine & Interrupt Routines 119 * 120 ***************************************************************************** 121 */ 122 123 /* Reset hardware and initialize FSM */ 124 static void 125 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data) 126 { 127 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET); 128 writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)), 129 drv_data->reg_base + MV64XXX_I2C_REG_BAUD); 130 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR); 131 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR); 132 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP, 133 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 134 drv_data->state = MV64XXX_I2C_STATE_IDLE; 135 } 136 137 static void 138 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status) 139 { 140 /* 141 * If state is idle, then this is likely the remnants of an old 142 * operation that driver has given up on or the user has killed. 143 * If so, issue the stop condition and go to idle. 144 */ 145 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) { 146 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 147 return; 148 } 149 150 /* The status from the ctlr [mostly] tells us what to do next */ 151 switch (status) { 152 /* Start condition interrupt */ 153 case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */ 154 case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */ 155 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1; 156 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK; 157 break; 158 159 /* Performing a write */ 160 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */ 161 if (drv_data->msg->flags & I2C_M_TEN) { 162 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2; 163 drv_data->state = 164 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK; 165 break; 166 } 167 /* FALLTHRU */ 168 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */ 169 case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */ 170 if ((drv_data->bytes_left == 0) 171 || (drv_data->aborting 172 && (drv_data->byte_posn != 0))) { 173 if (drv_data->send_stop) { 174 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 175 drv_data->state = MV64XXX_I2C_STATE_IDLE; 176 } else { 177 drv_data->action = 178 MV64XXX_I2C_ACTION_SEND_RESTART; 179 drv_data->state = 180 MV64XXX_I2C_STATE_WAITING_FOR_RESTART; 181 } 182 } else { 183 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA; 184 drv_data->state = 185 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK; 186 drv_data->bytes_left--; 187 } 188 break; 189 190 /* Performing a read */ 191 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */ 192 if (drv_data->msg->flags & I2C_M_TEN) { 193 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2; 194 drv_data->state = 195 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK; 196 break; 197 } 198 /* FALLTHRU */ 199 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */ 200 if (drv_data->bytes_left == 0) { 201 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 202 drv_data->state = MV64XXX_I2C_STATE_IDLE; 203 break; 204 } 205 /* FALLTHRU */ 206 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */ 207 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK) 208 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE; 209 else { 210 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA; 211 drv_data->bytes_left--; 212 } 213 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA; 214 215 if ((drv_data->bytes_left == 1) || drv_data->aborting) 216 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK; 217 break; 218 219 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */ 220 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP; 221 drv_data->state = MV64XXX_I2C_STATE_IDLE; 222 break; 223 224 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */ 225 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */ 226 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */ 227 /* Doesn't seem to be a device at other end */ 228 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 229 drv_data->state = MV64XXX_I2C_STATE_IDLE; 230 drv_data->rc = -ENODEV; 231 break; 232 233 default: 234 dev_err(&drv_data->adapter.dev, 235 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, " 236 "status: 0x%x, addr: 0x%x, flags: 0x%x\n", 237 drv_data->state, status, drv_data->msg->addr, 238 drv_data->msg->flags); 239 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 240 mv64xxx_i2c_hw_init(drv_data); 241 drv_data->rc = -EIO; 242 } 243 } 244 245 static void 246 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data) 247 { 248 switch(drv_data->action) { 249 case MV64XXX_I2C_ACTION_SEND_RESTART: 250 drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_START; 251 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; 252 writel(drv_data->cntl_bits, 253 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 254 drv_data->block = 0; 255 wake_up_interruptible(&drv_data->waitq); 256 break; 257 258 case MV64XXX_I2C_ACTION_CONTINUE: 259 writel(drv_data->cntl_bits, 260 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 261 break; 262 263 case MV64XXX_I2C_ACTION_SEND_START: 264 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START, 265 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 266 break; 267 268 case MV64XXX_I2C_ACTION_SEND_ADDR_1: 269 writel(drv_data->addr1, 270 drv_data->reg_base + MV64XXX_I2C_REG_DATA); 271 writel(drv_data->cntl_bits, 272 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 273 break; 274 275 case MV64XXX_I2C_ACTION_SEND_ADDR_2: 276 writel(drv_data->addr2, 277 drv_data->reg_base + MV64XXX_I2C_REG_DATA); 278 writel(drv_data->cntl_bits, 279 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 280 break; 281 282 case MV64XXX_I2C_ACTION_SEND_DATA: 283 writel(drv_data->msg->buf[drv_data->byte_posn++], 284 drv_data->reg_base + MV64XXX_I2C_REG_DATA); 285 writel(drv_data->cntl_bits, 286 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 287 break; 288 289 case MV64XXX_I2C_ACTION_RCV_DATA: 290 drv_data->msg->buf[drv_data->byte_posn++] = 291 readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA); 292 writel(drv_data->cntl_bits, 293 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 294 break; 295 296 case MV64XXX_I2C_ACTION_RCV_DATA_STOP: 297 drv_data->msg->buf[drv_data->byte_posn++] = 298 readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA); 299 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; 300 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, 301 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 302 drv_data->block = 0; 303 wake_up_interruptible(&drv_data->waitq); 304 break; 305 306 case MV64XXX_I2C_ACTION_INVALID: 307 default: 308 dev_err(&drv_data->adapter.dev, 309 "mv64xxx_i2c_do_action: Invalid action: %d\n", 310 drv_data->action); 311 drv_data->rc = -EIO; 312 /* FALLTHRU */ 313 case MV64XXX_I2C_ACTION_SEND_STOP: 314 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; 315 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, 316 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 317 drv_data->block = 0; 318 wake_up_interruptible(&drv_data->waitq); 319 break; 320 } 321 } 322 323 static irqreturn_t 324 mv64xxx_i2c_intr(int irq, void *dev_id) 325 { 326 struct mv64xxx_i2c_data *drv_data = dev_id; 327 unsigned long flags; 328 u32 status; 329 irqreturn_t rc = IRQ_NONE; 330 331 spin_lock_irqsave(&drv_data->lock, flags); 332 while (readl(drv_data->reg_base + MV64XXX_I2C_REG_CONTROL) & 333 MV64XXX_I2C_REG_CONTROL_IFLG) { 334 status = readl(drv_data->reg_base + MV64XXX_I2C_REG_STATUS); 335 mv64xxx_i2c_fsm(drv_data, status); 336 mv64xxx_i2c_do_action(drv_data); 337 rc = IRQ_HANDLED; 338 } 339 spin_unlock_irqrestore(&drv_data->lock, flags); 340 341 return rc; 342 } 343 344 /* 345 ***************************************************************************** 346 * 347 * I2C Msg Execution Routines 348 * 349 ***************************************************************************** 350 */ 351 static void 352 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data, 353 struct i2c_msg *msg) 354 { 355 u32 dir = 0; 356 357 drv_data->msg = msg; 358 drv_data->byte_posn = 0; 359 drv_data->bytes_left = msg->len; 360 drv_data->aborting = 0; 361 drv_data->rc = 0; 362 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK | 363 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN; 364 365 if (msg->flags & I2C_M_RD) 366 dir = 1; 367 368 if (msg->flags & I2C_M_TEN) { 369 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir; 370 drv_data->addr2 = (u32)msg->addr & 0xff; 371 } else { 372 drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir; 373 drv_data->addr2 = 0; 374 } 375 } 376 377 static void 378 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data) 379 { 380 long time_left; 381 unsigned long flags; 382 char abort = 0; 383 384 time_left = wait_event_interruptible_timeout(drv_data->waitq, 385 !drv_data->block, drv_data->adapter.timeout); 386 387 spin_lock_irqsave(&drv_data->lock, flags); 388 if (!time_left) { /* Timed out */ 389 drv_data->rc = -ETIMEDOUT; 390 abort = 1; 391 } else if (time_left < 0) { /* Interrupted/Error */ 392 drv_data->rc = time_left; /* errno value */ 393 abort = 1; 394 } 395 396 if (abort && drv_data->block) { 397 drv_data->aborting = 1; 398 spin_unlock_irqrestore(&drv_data->lock, flags); 399 400 time_left = wait_event_timeout(drv_data->waitq, 401 !drv_data->block, drv_data->adapter.timeout); 402 403 if ((time_left <= 0) && drv_data->block) { 404 drv_data->state = MV64XXX_I2C_STATE_IDLE; 405 dev_err(&drv_data->adapter.dev, 406 "mv64xxx: I2C bus locked, block: %d, " 407 "time_left: %d\n", drv_data->block, 408 (int)time_left); 409 mv64xxx_i2c_hw_init(drv_data); 410 } 411 } else 412 spin_unlock_irqrestore(&drv_data->lock, flags); 413 } 414 415 static int 416 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg, 417 int is_first, int is_last) 418 { 419 unsigned long flags; 420 421 spin_lock_irqsave(&drv_data->lock, flags); 422 mv64xxx_i2c_prepare_for_io(drv_data, msg); 423 424 if (unlikely(msg->flags & I2C_M_NOSTART)) { /* Skip start/addr phases */ 425 if (drv_data->msg->flags & I2C_M_RD) { 426 /* No action to do, wait for slave to send a byte */ 427 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE; 428 drv_data->state = 429 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA; 430 } else { 431 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA; 432 drv_data->state = 433 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK; 434 drv_data->bytes_left--; 435 } 436 } else { 437 if (is_first) { 438 drv_data->action = MV64XXX_I2C_ACTION_SEND_START; 439 drv_data->state = 440 MV64XXX_I2C_STATE_WAITING_FOR_START_COND; 441 } else { 442 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1; 443 drv_data->state = 444 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK; 445 } 446 } 447 448 drv_data->send_stop = is_last; 449 drv_data->block = 1; 450 mv64xxx_i2c_do_action(drv_data); 451 spin_unlock_irqrestore(&drv_data->lock, flags); 452 453 mv64xxx_i2c_wait_for_completion(drv_data); 454 return drv_data->rc; 455 } 456 457 /* 458 ***************************************************************************** 459 * 460 * I2C Core Support Routines (Interface to higher level I2C code) 461 * 462 ***************************************************************************** 463 */ 464 static u32 465 mv64xxx_i2c_functionality(struct i2c_adapter *adap) 466 { 467 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL; 468 } 469 470 static int 471 mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 472 { 473 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap); 474 int i, rc; 475 476 for (i = 0; i < num; i++) { 477 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i], 478 i == 0, i + 1 == num); 479 if (rc < 0) 480 return rc; 481 } 482 483 return num; 484 } 485 486 static const struct i2c_algorithm mv64xxx_i2c_algo = { 487 .master_xfer = mv64xxx_i2c_xfer, 488 .functionality = mv64xxx_i2c_functionality, 489 }; 490 491 /* 492 ***************************************************************************** 493 * 494 * Driver Interface & Early Init Routines 495 * 496 ***************************************************************************** 497 */ 498 static int __devinit 499 mv64xxx_i2c_map_regs(struct platform_device *pd, 500 struct mv64xxx_i2c_data *drv_data) 501 { 502 int size; 503 struct resource *r = platform_get_resource(pd, IORESOURCE_MEM, 0); 504 505 if (!r) 506 return -ENODEV; 507 508 size = resource_size(r); 509 510 if (!request_mem_region(r->start, size, drv_data->adapter.name)) 511 return -EBUSY; 512 513 drv_data->reg_base = ioremap(r->start, size); 514 drv_data->reg_base_p = r->start; 515 drv_data->reg_size = size; 516 517 return 0; 518 } 519 520 static void 521 mv64xxx_i2c_unmap_regs(struct mv64xxx_i2c_data *drv_data) 522 { 523 if (drv_data->reg_base) { 524 iounmap(drv_data->reg_base); 525 release_mem_region(drv_data->reg_base_p, drv_data->reg_size); 526 } 527 528 drv_data->reg_base = NULL; 529 drv_data->reg_base_p = 0; 530 } 531 532 #ifdef CONFIG_OF 533 static int __devinit 534 mv64xxx_calc_freq(const int tclk, const int n, const int m) 535 { 536 return tclk / (10 * (m + 1) * (2 << n)); 537 } 538 539 static bool __devinit 540 mv64xxx_find_baud_factors(const u32 req_freq, const u32 tclk, u32 *best_n, 541 u32 *best_m) 542 { 543 int freq, delta, best_delta = INT_MAX; 544 int m, n; 545 546 for (n = 0; n <= 7; n++) 547 for (m = 0; m <= 15; m++) { 548 freq = mv64xxx_calc_freq(tclk, n, m); 549 delta = req_freq - freq; 550 if (delta >= 0 && delta < best_delta) { 551 *best_m = m; 552 *best_n = n; 553 best_delta = delta; 554 } 555 if (best_delta == 0) 556 return true; 557 } 558 if (best_delta == INT_MAX) 559 return false; 560 return true; 561 } 562 563 static int __devinit 564 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data, 565 struct device_node *np) 566 { 567 u32 bus_freq, tclk; 568 int rc = 0; 569 570 /* CLK is mandatory when using DT to describe the i2c bus. We 571 * need to know tclk in order to calculate bus clock 572 * factors. 573 */ 574 #if !defined(CONFIG_HAVE_CLK) 575 /* Have OF but no CLK */ 576 return -ENODEV; 577 #else 578 if (IS_ERR(drv_data->clk)) { 579 rc = -ENODEV; 580 goto out; 581 } 582 tclk = clk_get_rate(drv_data->clk); 583 of_property_read_u32(np, "clock-frequency", &bus_freq); 584 if (!mv64xxx_find_baud_factors(bus_freq, tclk, 585 &drv_data->freq_n, &drv_data->freq_m)) { 586 rc = -EINVAL; 587 goto out; 588 } 589 drv_data->irq = irq_of_parse_and_map(np, 0); 590 591 /* Its not yet defined how timeouts will be specified in device tree. 592 * So hard code the value to 1 second. 593 */ 594 drv_data->adapter.timeout = HZ; 595 out: 596 return rc; 597 #endif 598 } 599 #else /* CONFIG_OF */ 600 static int __devinit 601 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data, 602 struct device_node *np) 603 { 604 return -ENODEV; 605 } 606 #endif /* CONFIG_OF */ 607 608 static int __devinit 609 mv64xxx_i2c_probe(struct platform_device *pd) 610 { 611 struct mv64xxx_i2c_data *drv_data; 612 struct mv64xxx_i2c_pdata *pdata = pd->dev.platform_data; 613 int rc; 614 615 if ((!pdata && !pd->dev.of_node)) 616 return -ENODEV; 617 618 drv_data = kzalloc(sizeof(struct mv64xxx_i2c_data), GFP_KERNEL); 619 if (!drv_data) 620 return -ENOMEM; 621 622 if (mv64xxx_i2c_map_regs(pd, drv_data)) { 623 rc = -ENODEV; 624 goto exit_kfree; 625 } 626 627 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter", 628 sizeof(drv_data->adapter.name)); 629 630 init_waitqueue_head(&drv_data->waitq); 631 spin_lock_init(&drv_data->lock); 632 633 #if defined(CONFIG_HAVE_CLK) 634 /* Not all platforms have a clk */ 635 drv_data->clk = clk_get(&pd->dev, NULL); 636 if (!IS_ERR(drv_data->clk)) { 637 clk_prepare(drv_data->clk); 638 clk_enable(drv_data->clk); 639 } 640 #endif 641 if (pdata) { 642 drv_data->freq_m = pdata->freq_m; 643 drv_data->freq_n = pdata->freq_n; 644 drv_data->irq = platform_get_irq(pd, 0); 645 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout); 646 } else if (pd->dev.of_node) { 647 rc = mv64xxx_of_config(drv_data, pd->dev.of_node); 648 if (rc) 649 goto exit_unmap_regs; 650 } 651 if (drv_data->irq < 0) { 652 rc = -ENXIO; 653 goto exit_unmap_regs; 654 } 655 656 drv_data->adapter.dev.parent = &pd->dev; 657 drv_data->adapter.algo = &mv64xxx_i2c_algo; 658 drv_data->adapter.owner = THIS_MODULE; 659 drv_data->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 660 drv_data->adapter.nr = pd->id; 661 drv_data->adapter.dev.of_node = pd->dev.of_node; 662 platform_set_drvdata(pd, drv_data); 663 i2c_set_adapdata(&drv_data->adapter, drv_data); 664 665 mv64xxx_i2c_hw_init(drv_data); 666 667 if (request_irq(drv_data->irq, mv64xxx_i2c_intr, 0, 668 MV64XXX_I2C_CTLR_NAME, drv_data)) { 669 dev_err(&drv_data->adapter.dev, 670 "mv64xxx: Can't register intr handler irq: %d\n", 671 drv_data->irq); 672 rc = -EINVAL; 673 goto exit_unmap_regs; 674 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) { 675 dev_err(&drv_data->adapter.dev, 676 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc); 677 goto exit_free_irq; 678 } 679 680 of_i2c_register_devices(&drv_data->adapter); 681 682 return 0; 683 684 exit_free_irq: 685 free_irq(drv_data->irq, drv_data); 686 exit_unmap_regs: 687 #if defined(CONFIG_HAVE_CLK) 688 /* Not all platforms have a clk */ 689 if (!IS_ERR(drv_data->clk)) { 690 clk_disable(drv_data->clk); 691 clk_unprepare(drv_data->clk); 692 } 693 #endif 694 mv64xxx_i2c_unmap_regs(drv_data); 695 exit_kfree: 696 kfree(drv_data); 697 return rc; 698 } 699 700 static int __devexit 701 mv64xxx_i2c_remove(struct platform_device *dev) 702 { 703 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev); 704 int rc; 705 706 rc = i2c_del_adapter(&drv_data->adapter); 707 free_irq(drv_data->irq, drv_data); 708 mv64xxx_i2c_unmap_regs(drv_data); 709 #if defined(CONFIG_HAVE_CLK) 710 /* Not all platforms have a clk */ 711 if (!IS_ERR(drv_data->clk)) { 712 clk_disable(drv_data->clk); 713 clk_unprepare(drv_data->clk); 714 } 715 #endif 716 kfree(drv_data); 717 718 return rc; 719 } 720 721 static const struct of_device_id mv64xxx_i2c_of_match_table[] __devinitdata = { 722 { .compatible = "marvell,mv64xxx-i2c", }, 723 {} 724 }; 725 MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table); 726 727 static struct platform_driver mv64xxx_i2c_driver = { 728 .probe = mv64xxx_i2c_probe, 729 .remove = __devexit_p(mv64xxx_i2c_remove), 730 .driver = { 731 .owner = THIS_MODULE, 732 .name = MV64XXX_I2C_CTLR_NAME, 733 .of_match_table = of_match_ptr(mv64xxx_i2c_of_match_table), 734 }, 735 }; 736 737 module_platform_driver(mv64xxx_i2c_driver); 738 739 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>"); 740 MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver"); 741 MODULE_LICENSE("GPL"); 742