1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Xudong Chen <xudong.chen@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/completion.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/err.h> 13 #include <linux/errno.h> 14 #include <linux/i2c.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/kernel.h> 20 #include <linux/mm.h> 21 #include <linux/module.h> 22 #include <linux/of_address.h> 23 #include <linux/of_device.h> 24 #include <linux/of_irq.h> 25 #include <linux/platform_device.h> 26 #include <linux/scatterlist.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 30 #define I2C_RS_TRANSFER (1 << 4) 31 #define I2C_ARB_LOST (1 << 3) 32 #define I2C_HS_NACKERR (1 << 2) 33 #define I2C_ACKERR (1 << 1) 34 #define I2C_TRANSAC_COMP (1 << 0) 35 #define I2C_TRANSAC_START (1 << 0) 36 #define I2C_RS_MUL_CNFG (1 << 15) 37 #define I2C_RS_MUL_TRIG (1 << 14) 38 #define I2C_DCM_DISABLE 0x0000 39 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 40 #define I2C_IO_CONFIG_PUSH_PULL 0x0000 41 #define I2C_SOFT_RST 0x0001 42 #define I2C_HANDSHAKE_RST 0x0020 43 #define I2C_FIFO_ADDR_CLR 0x0001 44 #define I2C_DELAY_LEN 0x0002 45 #define I2C_ST_START_CON 0x8001 46 #define I2C_FS_START_CON 0x1800 47 #define I2C_TIME_CLR_VALUE 0x0000 48 #define I2C_TIME_DEFAULT_VALUE 0x0003 49 #define I2C_WRRD_TRANAC_VALUE 0x0002 50 #define I2C_RD_TRANAC_VALUE 0x0001 51 #define I2C_SCL_MIS_COMP_VALUE 0x0000 52 #define I2C_CHN_CLR_FLAG 0x0000 53 #define I2C_RELIABILITY 0x0010 54 #define I2C_DMAACK_ENABLE 0x0008 55 56 #define I2C_DMA_CON_TX 0x0000 57 #define I2C_DMA_CON_RX 0x0001 58 #define I2C_DMA_ASYNC_MODE 0x0004 59 #define I2C_DMA_SKIP_CONFIG 0x0010 60 #define I2C_DMA_DIR_CHANGE 0x0200 61 #define I2C_DMA_START_EN 0x0001 62 #define I2C_DMA_INT_FLAG_NONE 0x0000 63 #define I2C_DMA_CLR_FLAG 0x0000 64 #define I2C_DMA_WARM_RST 0x0001 65 #define I2C_DMA_HARD_RST 0x0002 66 #define I2C_DMA_HANDSHAKE_RST 0x0004 67 68 #define MAX_SAMPLE_CNT_DIV 8 69 #define MAX_STEP_CNT_DIV 64 70 #define MAX_CLOCK_DIV_8BITS 256 71 #define MAX_CLOCK_DIV_5BITS 32 72 #define MAX_HS_STEP_CNT_DIV 8 73 #define I2C_STANDARD_MODE_BUFFER (1000 / 3) 74 #define I2C_FAST_MODE_BUFFER (300 / 3) 75 #define I2C_FAST_MODE_PLUS_BUFFER (20 / 3) 76 77 #define I2C_CONTROL_RS (0x1 << 1) 78 #define I2C_CONTROL_DMA_EN (0x1 << 2) 79 #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3) 80 #define I2C_CONTROL_DIR_CHANGE (0x1 << 4) 81 #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5) 82 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6) 83 #define I2C_CONTROL_DMAACK_EN (0x1 << 8) 84 #define I2C_CONTROL_ASYNC_MODE (0x1 << 9) 85 #define I2C_CONTROL_WRAPPER (0x1 << 0) 86 87 #define I2C_DRV_NAME "i2c-mt65xx" 88 89 /** 90 * enum i2c_mt65xx_clks - Clocks enumeration for MT65XX I2C 91 * 92 * @I2C_MT65XX_CLK_MAIN: main clock for i2c bus 93 * @I2C_MT65XX_CLK_DMA: DMA clock for i2c via DMA 94 * @I2C_MT65XX_CLK_PMIC: PMIC clock for i2c from PMIC 95 * @I2C_MT65XX_CLK_ARB: Arbitrator clock for i2c 96 * @I2C_MT65XX_CLK_MAX: Number of supported clocks 97 */ 98 enum i2c_mt65xx_clks { 99 I2C_MT65XX_CLK_MAIN = 0, 100 I2C_MT65XX_CLK_DMA, 101 I2C_MT65XX_CLK_PMIC, 102 I2C_MT65XX_CLK_ARB, 103 I2C_MT65XX_CLK_MAX 104 }; 105 106 static const char * const i2c_mt65xx_clk_ids[I2C_MT65XX_CLK_MAX] = { 107 "main", "dma", "pmic", "arb" 108 }; 109 110 enum DMA_REGS_OFFSET { 111 OFFSET_INT_FLAG = 0x0, 112 OFFSET_INT_EN = 0x04, 113 OFFSET_EN = 0x08, 114 OFFSET_RST = 0x0c, 115 OFFSET_CON = 0x18, 116 OFFSET_TX_MEM_ADDR = 0x1c, 117 OFFSET_RX_MEM_ADDR = 0x20, 118 OFFSET_TX_LEN = 0x24, 119 OFFSET_RX_LEN = 0x28, 120 OFFSET_TX_4G_MODE = 0x54, 121 OFFSET_RX_4G_MODE = 0x58, 122 }; 123 124 enum i2c_trans_st_rs { 125 I2C_TRANS_STOP = 0, 126 I2C_TRANS_REPEATED_START, 127 }; 128 129 enum mtk_trans_op { 130 I2C_MASTER_WR = 1, 131 I2C_MASTER_RD, 132 I2C_MASTER_WRRD, 133 }; 134 135 enum I2C_REGS_OFFSET { 136 OFFSET_DATA_PORT, 137 OFFSET_SLAVE_ADDR, 138 OFFSET_INTR_MASK, 139 OFFSET_INTR_STAT, 140 OFFSET_CONTROL, 141 OFFSET_TRANSFER_LEN, 142 OFFSET_TRANSAC_LEN, 143 OFFSET_DELAY_LEN, 144 OFFSET_TIMING, 145 OFFSET_START, 146 OFFSET_EXT_CONF, 147 OFFSET_FIFO_STAT, 148 OFFSET_FIFO_THRESH, 149 OFFSET_FIFO_ADDR_CLR, 150 OFFSET_IO_CONFIG, 151 OFFSET_RSV_DEBUG, 152 OFFSET_HS, 153 OFFSET_SOFTRESET, 154 OFFSET_DCM_EN, 155 OFFSET_MULTI_DMA, 156 OFFSET_PATH_DIR, 157 OFFSET_DEBUGSTAT, 158 OFFSET_DEBUGCTRL, 159 OFFSET_TRANSFER_LEN_AUX, 160 OFFSET_CLOCK_DIV, 161 OFFSET_LTIMING, 162 OFFSET_SCL_HIGH_LOW_RATIO, 163 OFFSET_HS_SCL_HIGH_LOW_RATIO, 164 OFFSET_SCL_MIS_COMP_POINT, 165 OFFSET_STA_STO_AC_TIMING, 166 OFFSET_HS_STA_STO_AC_TIMING, 167 OFFSET_SDA_TIMING, 168 }; 169 170 static const u16 mt_i2c_regs_v1[] = { 171 [OFFSET_DATA_PORT] = 0x0, 172 [OFFSET_SLAVE_ADDR] = 0x4, 173 [OFFSET_INTR_MASK] = 0x8, 174 [OFFSET_INTR_STAT] = 0xc, 175 [OFFSET_CONTROL] = 0x10, 176 [OFFSET_TRANSFER_LEN] = 0x14, 177 [OFFSET_TRANSAC_LEN] = 0x18, 178 [OFFSET_DELAY_LEN] = 0x1c, 179 [OFFSET_TIMING] = 0x20, 180 [OFFSET_START] = 0x24, 181 [OFFSET_EXT_CONF] = 0x28, 182 [OFFSET_FIFO_STAT] = 0x30, 183 [OFFSET_FIFO_THRESH] = 0x34, 184 [OFFSET_FIFO_ADDR_CLR] = 0x38, 185 [OFFSET_IO_CONFIG] = 0x40, 186 [OFFSET_RSV_DEBUG] = 0x44, 187 [OFFSET_HS] = 0x48, 188 [OFFSET_SOFTRESET] = 0x50, 189 [OFFSET_DCM_EN] = 0x54, 190 [OFFSET_PATH_DIR] = 0x60, 191 [OFFSET_DEBUGSTAT] = 0x64, 192 [OFFSET_DEBUGCTRL] = 0x68, 193 [OFFSET_TRANSFER_LEN_AUX] = 0x6c, 194 [OFFSET_CLOCK_DIV] = 0x70, 195 [OFFSET_SCL_HIGH_LOW_RATIO] = 0x74, 196 [OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78, 197 [OFFSET_SCL_MIS_COMP_POINT] = 0x7C, 198 [OFFSET_STA_STO_AC_TIMING] = 0x80, 199 [OFFSET_HS_STA_STO_AC_TIMING] = 0x84, 200 [OFFSET_SDA_TIMING] = 0x88, 201 }; 202 203 static const u16 mt_i2c_regs_v2[] = { 204 [OFFSET_DATA_PORT] = 0x0, 205 [OFFSET_SLAVE_ADDR] = 0x4, 206 [OFFSET_INTR_MASK] = 0x8, 207 [OFFSET_INTR_STAT] = 0xc, 208 [OFFSET_CONTROL] = 0x10, 209 [OFFSET_TRANSFER_LEN] = 0x14, 210 [OFFSET_TRANSAC_LEN] = 0x18, 211 [OFFSET_DELAY_LEN] = 0x1c, 212 [OFFSET_TIMING] = 0x20, 213 [OFFSET_START] = 0x24, 214 [OFFSET_EXT_CONF] = 0x28, 215 [OFFSET_LTIMING] = 0x2c, 216 [OFFSET_HS] = 0x30, 217 [OFFSET_IO_CONFIG] = 0x34, 218 [OFFSET_FIFO_ADDR_CLR] = 0x38, 219 [OFFSET_SDA_TIMING] = 0x3c, 220 [OFFSET_TRANSFER_LEN_AUX] = 0x44, 221 [OFFSET_CLOCK_DIV] = 0x48, 222 [OFFSET_SOFTRESET] = 0x50, 223 [OFFSET_MULTI_DMA] = 0x8c, 224 [OFFSET_SCL_MIS_COMP_POINT] = 0x90, 225 [OFFSET_DEBUGSTAT] = 0xe4, 226 [OFFSET_DEBUGCTRL] = 0xe8, 227 [OFFSET_FIFO_STAT] = 0xf4, 228 [OFFSET_FIFO_THRESH] = 0xf8, 229 [OFFSET_DCM_EN] = 0xf88, 230 }; 231 232 struct mtk_i2c_compatible { 233 const struct i2c_adapter_quirks *quirks; 234 const u16 *regs; 235 unsigned char pmic_i2c: 1; 236 unsigned char dcm: 1; 237 unsigned char auto_restart: 1; 238 unsigned char aux_len_reg: 1; 239 unsigned char timing_adjust: 1; 240 unsigned char dma_sync: 1; 241 unsigned char ltiming_adjust: 1; 242 unsigned char apdma_sync: 1; 243 unsigned char max_dma_support; 244 }; 245 246 struct mtk_i2c_ac_timing { 247 u16 htiming; 248 u16 ltiming; 249 u16 hs; 250 u16 ext; 251 u16 inter_clk_div; 252 u16 scl_hl_ratio; 253 u16 hs_scl_hl_ratio; 254 u16 sta_stop; 255 u16 hs_sta_stop; 256 u16 sda_timing; 257 }; 258 259 struct mtk_i2c { 260 struct i2c_adapter adap; /* i2c host adapter */ 261 struct device *dev; 262 struct completion msg_complete; 263 struct i2c_timings timing_info; 264 265 /* set in i2c probe */ 266 void __iomem *base; /* i2c base addr */ 267 void __iomem *pdmabase; /* dma base address*/ 268 struct clk_bulk_data clocks[I2C_MT65XX_CLK_MAX]; /* clocks for i2c */ 269 bool have_pmic; /* can use i2c pins from PMIC */ 270 bool use_push_pull; /* IO config push-pull mode */ 271 272 u16 irq_stat; /* interrupt status */ 273 unsigned int clk_src_div; 274 unsigned int speed_hz; /* The speed in transfer */ 275 enum mtk_trans_op op; 276 u16 timing_reg; 277 u16 high_speed_reg; 278 u16 ltiming_reg; 279 unsigned char auto_restart; 280 bool ignore_restart_irq; 281 struct mtk_i2c_ac_timing ac_timing; 282 const struct mtk_i2c_compatible *dev_comp; 283 }; 284 285 /** 286 * struct i2c_spec_values: 287 * @min_low_ns: min LOW period of the SCL clock 288 * @min_su_sta_ns: min set-up time for a repeated START condition 289 * @max_hd_dat_ns: max data hold time 290 * @min_su_dat_ns: min data set-up time 291 */ 292 struct i2c_spec_values { 293 unsigned int min_low_ns; 294 unsigned int min_su_sta_ns; 295 unsigned int max_hd_dat_ns; 296 unsigned int min_su_dat_ns; 297 }; 298 299 static const struct i2c_spec_values standard_mode_spec = { 300 .min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER, 301 .min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER, 302 .max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER, 303 .min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER, 304 }; 305 306 static const struct i2c_spec_values fast_mode_spec = { 307 .min_low_ns = 1300 + I2C_FAST_MODE_BUFFER, 308 .min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER, 309 .max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER, 310 .min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER, 311 }; 312 313 static const struct i2c_spec_values fast_mode_plus_spec = { 314 .min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER, 315 .min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER, 316 .max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER, 317 .min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER, 318 }; 319 320 static const struct i2c_adapter_quirks mt6577_i2c_quirks = { 321 .flags = I2C_AQ_COMB_WRITE_THEN_READ, 322 .max_num_msgs = 1, 323 .max_write_len = 255, 324 .max_read_len = 255, 325 .max_comb_1st_msg_len = 255, 326 .max_comb_2nd_msg_len = 31, 327 }; 328 329 static const struct i2c_adapter_quirks mt7622_i2c_quirks = { 330 .max_num_msgs = 255, 331 }; 332 333 static const struct i2c_adapter_quirks mt8183_i2c_quirks = { 334 .flags = I2C_AQ_NO_ZERO_LEN, 335 }; 336 337 static const struct mtk_i2c_compatible mt2712_compat = { 338 .regs = mt_i2c_regs_v1, 339 .pmic_i2c = 0, 340 .dcm = 1, 341 .auto_restart = 1, 342 .aux_len_reg = 1, 343 .timing_adjust = 1, 344 .dma_sync = 0, 345 .ltiming_adjust = 0, 346 .apdma_sync = 0, 347 .max_dma_support = 33, 348 }; 349 350 static const struct mtk_i2c_compatible mt6577_compat = { 351 .quirks = &mt6577_i2c_quirks, 352 .regs = mt_i2c_regs_v1, 353 .pmic_i2c = 0, 354 .dcm = 1, 355 .auto_restart = 0, 356 .aux_len_reg = 0, 357 .timing_adjust = 0, 358 .dma_sync = 0, 359 .ltiming_adjust = 0, 360 .apdma_sync = 0, 361 .max_dma_support = 32, 362 }; 363 364 static const struct mtk_i2c_compatible mt6589_compat = { 365 .quirks = &mt6577_i2c_quirks, 366 .regs = mt_i2c_regs_v1, 367 .pmic_i2c = 1, 368 .dcm = 0, 369 .auto_restart = 0, 370 .aux_len_reg = 0, 371 .timing_adjust = 0, 372 .dma_sync = 0, 373 .ltiming_adjust = 0, 374 .apdma_sync = 0, 375 .max_dma_support = 32, 376 }; 377 378 static const struct mtk_i2c_compatible mt7622_compat = { 379 .quirks = &mt7622_i2c_quirks, 380 .regs = mt_i2c_regs_v1, 381 .pmic_i2c = 0, 382 .dcm = 1, 383 .auto_restart = 1, 384 .aux_len_reg = 1, 385 .timing_adjust = 0, 386 .dma_sync = 0, 387 .ltiming_adjust = 0, 388 .apdma_sync = 0, 389 .max_dma_support = 32, 390 }; 391 392 static const struct mtk_i2c_compatible mt8168_compat = { 393 .regs = mt_i2c_regs_v1, 394 .pmic_i2c = 0, 395 .dcm = 1, 396 .auto_restart = 1, 397 .aux_len_reg = 1, 398 .timing_adjust = 1, 399 .dma_sync = 1, 400 .ltiming_adjust = 0, 401 .apdma_sync = 0, 402 .max_dma_support = 33, 403 }; 404 405 static const struct mtk_i2c_compatible mt8173_compat = { 406 .regs = mt_i2c_regs_v1, 407 .pmic_i2c = 0, 408 .dcm = 1, 409 .auto_restart = 1, 410 .aux_len_reg = 1, 411 .timing_adjust = 0, 412 .dma_sync = 0, 413 .ltiming_adjust = 0, 414 .apdma_sync = 0, 415 .max_dma_support = 33, 416 }; 417 418 static const struct mtk_i2c_compatible mt8183_compat = { 419 .quirks = &mt8183_i2c_quirks, 420 .regs = mt_i2c_regs_v2, 421 .pmic_i2c = 0, 422 .dcm = 0, 423 .auto_restart = 1, 424 .aux_len_reg = 1, 425 .timing_adjust = 1, 426 .dma_sync = 1, 427 .ltiming_adjust = 1, 428 .apdma_sync = 0, 429 .max_dma_support = 33, 430 }; 431 432 static const struct mtk_i2c_compatible mt8186_compat = { 433 .regs = mt_i2c_regs_v2, 434 .pmic_i2c = 0, 435 .dcm = 0, 436 .auto_restart = 1, 437 .aux_len_reg = 1, 438 .timing_adjust = 1, 439 .dma_sync = 0, 440 .ltiming_adjust = 1, 441 .apdma_sync = 0, 442 .max_dma_support = 36, 443 }; 444 445 static const struct mtk_i2c_compatible mt8192_compat = { 446 .quirks = &mt8183_i2c_quirks, 447 .regs = mt_i2c_regs_v2, 448 .pmic_i2c = 0, 449 .dcm = 0, 450 .auto_restart = 1, 451 .aux_len_reg = 1, 452 .timing_adjust = 1, 453 .dma_sync = 1, 454 .ltiming_adjust = 1, 455 .apdma_sync = 1, 456 .max_dma_support = 36, 457 }; 458 459 static const struct of_device_id mtk_i2c_of_match[] = { 460 { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat }, 461 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, 462 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, 463 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, 464 { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat }, 465 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, 466 { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, 467 { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat }, 468 { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat }, 469 {} 470 }; 471 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match); 472 473 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg) 474 { 475 return readw(i2c->base + i2c->dev_comp->regs[reg]); 476 } 477 478 static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val, 479 enum I2C_REGS_OFFSET reg) 480 { 481 writew(val, i2c->base + i2c->dev_comp->regs[reg]); 482 } 483 484 static void mtk_i2c_init_hw(struct mtk_i2c *i2c) 485 { 486 u16 control_reg; 487 u16 intr_stat_reg; 488 u16 ext_conf_val; 489 490 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_START); 491 intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); 492 mtk_i2c_writew(i2c, intr_stat_reg, OFFSET_INTR_STAT); 493 494 if (i2c->dev_comp->apdma_sync) { 495 writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST); 496 udelay(10); 497 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 498 udelay(10); 499 writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_HARD_RST, 500 i2c->pdmabase + OFFSET_RST); 501 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST, 502 OFFSET_SOFTRESET); 503 udelay(10); 504 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 505 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); 506 } else { 507 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); 508 udelay(50); 509 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 510 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET); 511 } 512 513 /* Set ioconfig */ 514 if (i2c->use_push_pull) 515 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG); 516 else 517 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG); 518 519 if (i2c->dev_comp->dcm) 520 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN); 521 522 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING); 523 mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS); 524 if (i2c->dev_comp->ltiming_adjust) 525 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING); 526 527 if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ) 528 ext_conf_val = I2C_ST_START_CON; 529 else 530 ext_conf_val = I2C_FS_START_CON; 531 532 if (i2c->dev_comp->timing_adjust) { 533 ext_conf_val = i2c->ac_timing.ext; 534 mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div, 535 OFFSET_CLOCK_DIV); 536 mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE, 537 OFFSET_SCL_MIS_COMP_POINT); 538 mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing, 539 OFFSET_SDA_TIMING); 540 541 if (i2c->dev_comp->ltiming_adjust) { 542 mtk_i2c_writew(i2c, i2c->ac_timing.htiming, 543 OFFSET_TIMING); 544 mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS); 545 mtk_i2c_writew(i2c, i2c->ac_timing.ltiming, 546 OFFSET_LTIMING); 547 } else { 548 mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio, 549 OFFSET_SCL_HIGH_LOW_RATIO); 550 mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio, 551 OFFSET_HS_SCL_HIGH_LOW_RATIO); 552 mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop, 553 OFFSET_STA_STO_AC_TIMING); 554 mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop, 555 OFFSET_HS_STA_STO_AC_TIMING); 556 } 557 } 558 mtk_i2c_writew(i2c, ext_conf_val, OFFSET_EXT_CONF); 559 560 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */ 561 if (i2c->have_pmic) 562 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR); 563 564 control_reg = I2C_CONTROL_ACKERR_DET_EN | 565 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN; 566 if (i2c->dev_comp->dma_sync) 567 control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE; 568 569 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 570 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN); 571 } 572 573 static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed) 574 { 575 if (speed <= I2C_MAX_STANDARD_MODE_FREQ) 576 return &standard_mode_spec; 577 else if (speed <= I2C_MAX_FAST_MODE_FREQ) 578 return &fast_mode_spec; 579 else 580 return &fast_mode_plus_spec; 581 } 582 583 static int mtk_i2c_max_step_cnt(unsigned int target_speed) 584 { 585 if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) 586 return MAX_HS_STEP_CNT_DIV; 587 else 588 return MAX_STEP_CNT_DIV; 589 } 590 591 static int mtk_i2c_get_clk_div_restri(struct mtk_i2c *i2c, 592 unsigned int sample_cnt) 593 { 594 int clk_div_restri = 0; 595 596 if (i2c->dev_comp->ltiming_adjust == 0) 597 return 0; 598 599 if (sample_cnt == 1) { 600 if (i2c->ac_timing.inter_clk_div == 0) 601 clk_div_restri = 0; 602 else 603 clk_div_restri = 1; 604 } else { 605 if (i2c->ac_timing.inter_clk_div == 0) 606 clk_div_restri = -1; 607 else if (i2c->ac_timing.inter_clk_div == 1) 608 clk_div_restri = 0; 609 else 610 clk_div_restri = 1; 611 } 612 613 return clk_div_restri; 614 } 615 616 /* 617 * Check and Calculate i2c ac-timing 618 * 619 * Hardware design: 620 * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src 621 * xxx_cnt_div = spec->min_xxx_ns / sample_ns 622 * 623 * Sample_ns is rounded down for xxx_cnt_div would be greater 624 * than the smallest spec. 625 * The sda_timing is chosen as the middle value between 626 * the largest and smallest. 627 */ 628 static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c, 629 unsigned int clk_src, 630 unsigned int check_speed, 631 unsigned int step_cnt, 632 unsigned int sample_cnt) 633 { 634 const struct i2c_spec_values *spec; 635 unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt; 636 unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f; 637 unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1), 638 clk_src); 639 640 if (!i2c->dev_comp->timing_adjust) 641 return 0; 642 643 if (i2c->dev_comp->ltiming_adjust) 644 max_sta_cnt = 0x100; 645 646 spec = mtk_i2c_get_spec(check_speed); 647 648 if (i2c->dev_comp->ltiming_adjust) 649 clk_ns = 1000000000 / clk_src; 650 else 651 clk_ns = sample_ns / 2; 652 653 su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns + 654 i2c->timing_info.scl_int_delay_ns, clk_ns); 655 if (su_sta_cnt > max_sta_cnt) 656 return -1; 657 658 low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns); 659 max_step_cnt = mtk_i2c_max_step_cnt(check_speed); 660 if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) { 661 if (low_cnt > step_cnt) { 662 high_cnt = 2 * step_cnt - low_cnt; 663 } else { 664 high_cnt = step_cnt; 665 low_cnt = step_cnt; 666 } 667 } else { 668 return -2; 669 } 670 671 sda_max = spec->max_hd_dat_ns / sample_ns; 672 if (sda_max > low_cnt) 673 sda_max = 0; 674 675 sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns); 676 if (sda_min < low_cnt) 677 sda_min = 0; 678 679 if (sda_min > sda_max) 680 return -3; 681 682 if (check_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) { 683 if (i2c->dev_comp->ltiming_adjust) { 684 i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE | 685 (sample_cnt << 12) | (high_cnt << 8); 686 i2c->ac_timing.ltiming &= ~GENMASK(15, 9); 687 i2c->ac_timing.ltiming |= (sample_cnt << 12) | 688 (low_cnt << 9); 689 i2c->ac_timing.ext &= ~GENMASK(7, 1); 690 i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0); 691 } else { 692 i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) | 693 (high_cnt << 6) | low_cnt; 694 i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) | 695 su_sta_cnt; 696 } 697 i2c->ac_timing.sda_timing &= ~GENMASK(11, 6); 698 i2c->ac_timing.sda_timing |= (1 << 12) | 699 ((sda_max + sda_min) / 2) << 6; 700 } else { 701 if (i2c->dev_comp->ltiming_adjust) { 702 i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt); 703 i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt); 704 i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0); 705 } else { 706 i2c->ac_timing.scl_hl_ratio = (1 << 12) | 707 (high_cnt << 6) | low_cnt; 708 i2c->ac_timing.sta_stop = (su_sta_cnt << 8) | 709 su_sta_cnt; 710 } 711 712 i2c->ac_timing.sda_timing = (1 << 12) | 713 (sda_max + sda_min) / 2; 714 } 715 716 return 0; 717 } 718 719 /* 720 * Calculate i2c port speed 721 * 722 * Hardware design: 723 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt) 724 * clock_div: fixed in hardware, but may be various in different SoCs 725 * 726 * The calculation want to pick the highest bus frequency that is still 727 * less than or equal to i2c->speed_hz. The calculation try to get 728 * sample_cnt and step_cn 729 */ 730 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src, 731 unsigned int target_speed, 732 unsigned int *timing_step_cnt, 733 unsigned int *timing_sample_cnt) 734 { 735 unsigned int step_cnt; 736 unsigned int sample_cnt; 737 unsigned int max_step_cnt; 738 unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV; 739 unsigned int base_step_cnt; 740 unsigned int opt_div; 741 unsigned int best_mul; 742 unsigned int cnt_mul; 743 int ret = -EINVAL; 744 int clk_div_restri = 0; 745 746 if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ) 747 target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ; 748 749 max_step_cnt = mtk_i2c_max_step_cnt(target_speed); 750 base_step_cnt = max_step_cnt; 751 /* Find the best combination */ 752 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); 753 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; 754 755 /* Search for the best pair (sample_cnt, step_cnt) with 756 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV 757 * 0 < step_cnt < max_step_cnt 758 * sample_cnt * step_cnt >= opt_div 759 * optimizing for sample_cnt * step_cnt being minimal 760 */ 761 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { 762 clk_div_restri = mtk_i2c_get_clk_div_restri(i2c, sample_cnt); 763 step_cnt = DIV_ROUND_UP(opt_div + clk_div_restri, sample_cnt); 764 cnt_mul = step_cnt * sample_cnt; 765 if (step_cnt > max_step_cnt) 766 continue; 767 768 if (cnt_mul < best_mul) { 769 ret = mtk_i2c_check_ac_timing(i2c, clk_src, 770 target_speed, step_cnt - 1, sample_cnt - 1); 771 if (ret) 772 continue; 773 774 best_mul = cnt_mul; 775 base_sample_cnt = sample_cnt; 776 base_step_cnt = step_cnt; 777 if (best_mul == (opt_div + clk_div_restri)) 778 break; 779 } 780 } 781 782 if (ret) 783 return -EINVAL; 784 785 sample_cnt = base_sample_cnt; 786 step_cnt = base_step_cnt; 787 788 if ((clk_src / (2 * (sample_cnt * step_cnt - clk_div_restri))) > 789 target_speed) { 790 /* In this case, hardware can't support such 791 * low i2c_bus_freq 792 */ 793 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed); 794 return -EINVAL; 795 } 796 797 *timing_step_cnt = step_cnt - 1; 798 *timing_sample_cnt = sample_cnt - 1; 799 800 return 0; 801 } 802 803 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) 804 { 805 unsigned int clk_src; 806 unsigned int step_cnt; 807 unsigned int sample_cnt; 808 unsigned int l_step_cnt; 809 unsigned int l_sample_cnt; 810 unsigned int target_speed; 811 unsigned int clk_div; 812 unsigned int max_clk_div; 813 int ret; 814 815 target_speed = i2c->speed_hz; 816 parent_clk /= i2c->clk_src_div; 817 818 if (i2c->dev_comp->timing_adjust && i2c->dev_comp->ltiming_adjust) 819 max_clk_div = MAX_CLOCK_DIV_5BITS; 820 else if (i2c->dev_comp->timing_adjust) 821 max_clk_div = MAX_CLOCK_DIV_8BITS; 822 else 823 max_clk_div = 1; 824 825 for (clk_div = 1; clk_div <= max_clk_div; clk_div++) { 826 clk_src = parent_clk / clk_div; 827 i2c->ac_timing.inter_clk_div = clk_div - 1; 828 829 if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) { 830 /* Set master code speed register */ 831 ret = mtk_i2c_calculate_speed(i2c, clk_src, 832 I2C_MAX_FAST_MODE_FREQ, 833 &l_step_cnt, 834 &l_sample_cnt); 835 if (ret < 0) 836 continue; 837 838 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; 839 840 /* Set the high speed mode register */ 841 ret = mtk_i2c_calculate_speed(i2c, clk_src, 842 target_speed, &step_cnt, 843 &sample_cnt); 844 if (ret < 0) 845 continue; 846 847 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | 848 (sample_cnt << 12) | (step_cnt << 8); 849 850 if (i2c->dev_comp->ltiming_adjust) 851 i2c->ltiming_reg = 852 (l_sample_cnt << 6) | l_step_cnt | 853 (sample_cnt << 12) | (step_cnt << 9); 854 } else { 855 ret = mtk_i2c_calculate_speed(i2c, clk_src, 856 target_speed, &l_step_cnt, 857 &l_sample_cnt); 858 if (ret < 0) 859 continue; 860 861 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; 862 863 /* Disable the high speed transaction */ 864 i2c->high_speed_reg = I2C_TIME_CLR_VALUE; 865 866 if (i2c->dev_comp->ltiming_adjust) 867 i2c->ltiming_reg = 868 (l_sample_cnt << 6) | l_step_cnt; 869 } 870 871 break; 872 } 873 874 875 return 0; 876 } 877 878 static void i2c_dump_register(struct mtk_i2c *i2c) 879 { 880 dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n", 881 mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR), 882 mtk_i2c_readw(i2c, OFFSET_INTR_MASK)); 883 dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n", 884 mtk_i2c_readw(i2c, OFFSET_INTR_STAT), 885 mtk_i2c_readw(i2c, OFFSET_CONTROL)); 886 dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n", 887 mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN), 888 mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN)); 889 dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n", 890 mtk_i2c_readw(i2c, OFFSET_DELAY_LEN), 891 mtk_i2c_readw(i2c, OFFSET_TIMING)); 892 dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n", 893 mtk_i2c_readw(i2c, OFFSET_START), 894 mtk_i2c_readw(i2c, OFFSET_EXT_CONF)); 895 dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n", 896 mtk_i2c_readw(i2c, OFFSET_HS), 897 mtk_i2c_readw(i2c, OFFSET_IO_CONFIG)); 898 dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n", 899 mtk_i2c_readw(i2c, OFFSET_DCM_EN), 900 mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX)); 901 dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n", 902 mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV), 903 mtk_i2c_readw(i2c, OFFSET_FIFO_STAT)); 904 dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n", 905 mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL), 906 mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT)); 907 if (i2c->dev_comp->regs == mt_i2c_regs_v2) { 908 dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n", 909 mtk_i2c_readw(i2c, OFFSET_LTIMING), 910 mtk_i2c_readw(i2c, OFFSET_MULTI_DMA)); 911 } 912 dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n", 913 readl(i2c->pdmabase + OFFSET_INT_FLAG), 914 readl(i2c->pdmabase + OFFSET_INT_EN)); 915 dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n", 916 readl(i2c->pdmabase + OFFSET_EN), 917 readl(i2c->pdmabase + OFFSET_CON)); 918 dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n", 919 readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR), 920 readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR)); 921 dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n", 922 readl(i2c->pdmabase + OFFSET_TX_LEN), 923 readl(i2c->pdmabase + OFFSET_RX_LEN)); 924 dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x", 925 readl(i2c->pdmabase + OFFSET_TX_4G_MODE), 926 readl(i2c->pdmabase + OFFSET_RX_4G_MODE)); 927 } 928 929 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, 930 int num, int left_num) 931 { 932 u16 addr_reg; 933 u16 start_reg; 934 u16 control_reg; 935 u16 restart_flag = 0; 936 u16 dma_sync = 0; 937 u32 reg_4g_mode; 938 u32 reg_dma_reset; 939 u8 *dma_rd_buf = NULL; 940 u8 *dma_wr_buf = NULL; 941 dma_addr_t rpaddr = 0; 942 dma_addr_t wpaddr = 0; 943 int ret; 944 945 i2c->irq_stat = 0; 946 947 if (i2c->auto_restart) 948 restart_flag = I2C_RS_TRANSFER; 949 950 reinit_completion(&i2c->msg_complete); 951 952 if (i2c->dev_comp->apdma_sync && 953 i2c->op != I2C_MASTER_WRRD && num > 1) { 954 mtk_i2c_writew(i2c, 0x00, OFFSET_DEBUGCTRL); 955 writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST, 956 i2c->pdmabase + OFFSET_RST); 957 958 ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST, 959 reg_dma_reset, 960 !(reg_dma_reset & I2C_DMA_WARM_RST), 961 0, 100); 962 if (ret) { 963 dev_err(i2c->dev, "DMA warm reset timeout\n"); 964 return -ETIMEDOUT; 965 } 966 967 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 968 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET); 969 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); 970 mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE, 971 OFFSET_DEBUGCTRL); 972 } 973 974 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & 975 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); 976 if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1)) 977 control_reg |= I2C_CONTROL_RS; 978 979 if (i2c->op == I2C_MASTER_WRRD) 980 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; 981 982 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 983 984 addr_reg = i2c_8bit_addr_from_msg(msgs); 985 mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR); 986 987 /* Clear interrupt status */ 988 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 989 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT); 990 991 mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR); 992 993 /* Enable interrupt */ 994 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 995 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK); 996 997 /* Set transfer and transaction len */ 998 if (i2c->op == I2C_MASTER_WRRD) { 999 if (i2c->dev_comp->aux_len_reg) { 1000 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); 1001 mtk_i2c_writew(i2c, (msgs + 1)->len, 1002 OFFSET_TRANSFER_LEN_AUX); 1003 } else { 1004 mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8, 1005 OFFSET_TRANSFER_LEN); 1006 } 1007 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN); 1008 } else { 1009 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); 1010 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN); 1011 } 1012 1013 if (i2c->dev_comp->apdma_sync) { 1014 dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE; 1015 if (i2c->op == I2C_MASTER_WRRD) 1016 dma_sync |= I2C_DMA_DIR_CHANGE; 1017 } 1018 1019 /* Prepare buffer data to start transfer */ 1020 if (i2c->op == I2C_MASTER_RD) { 1021 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 1022 writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON); 1023 1024 dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 1025 if (!dma_rd_buf) 1026 return -ENOMEM; 1027 1028 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, 1029 msgs->len, DMA_FROM_DEVICE); 1030 if (dma_mapping_error(i2c->dev, rpaddr)) { 1031 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, false); 1032 1033 return -ENOMEM; 1034 } 1035 1036 if (i2c->dev_comp->max_dma_support > 32) { 1037 reg_4g_mode = upper_32_bits(rpaddr); 1038 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 1039 } 1040 1041 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 1042 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN); 1043 } else if (i2c->op == I2C_MASTER_WR) { 1044 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 1045 writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON); 1046 1047 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 1048 if (!dma_wr_buf) 1049 return -ENOMEM; 1050 1051 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, 1052 msgs->len, DMA_TO_DEVICE); 1053 if (dma_mapping_error(i2c->dev, wpaddr)) { 1054 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 1055 1056 return -ENOMEM; 1057 } 1058 1059 if (i2c->dev_comp->max_dma_support > 32) { 1060 reg_4g_mode = upper_32_bits(wpaddr); 1061 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 1062 } 1063 1064 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 1065 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 1066 } else { 1067 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG); 1068 writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON); 1069 1070 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 1071 if (!dma_wr_buf) 1072 return -ENOMEM; 1073 1074 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, 1075 msgs->len, DMA_TO_DEVICE); 1076 if (dma_mapping_error(i2c->dev, wpaddr)) { 1077 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 1078 1079 return -ENOMEM; 1080 } 1081 1082 dma_rd_buf = i2c_get_dma_safe_msg_buf((msgs + 1), 1); 1083 if (!dma_rd_buf) { 1084 dma_unmap_single(i2c->dev, wpaddr, 1085 msgs->len, DMA_TO_DEVICE); 1086 1087 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 1088 1089 return -ENOMEM; 1090 } 1091 1092 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, 1093 (msgs + 1)->len, 1094 DMA_FROM_DEVICE); 1095 if (dma_mapping_error(i2c->dev, rpaddr)) { 1096 dma_unmap_single(i2c->dev, wpaddr, 1097 msgs->len, DMA_TO_DEVICE); 1098 1099 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 1100 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), false); 1101 1102 return -ENOMEM; 1103 } 1104 1105 if (i2c->dev_comp->max_dma_support > 32) { 1106 reg_4g_mode = upper_32_bits(wpaddr); 1107 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 1108 1109 reg_4g_mode = upper_32_bits(rpaddr); 1110 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 1111 } 1112 1113 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 1114 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 1115 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 1116 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN); 1117 } 1118 1119 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN); 1120 1121 if (!i2c->auto_restart) { 1122 start_reg = I2C_TRANSAC_START; 1123 } else { 1124 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG; 1125 if (left_num >= 1) 1126 start_reg |= I2C_RS_MUL_CNFG; 1127 } 1128 mtk_i2c_writew(i2c, start_reg, OFFSET_START); 1129 1130 ret = wait_for_completion_timeout(&i2c->msg_complete, 1131 i2c->adap.timeout); 1132 1133 /* Clear interrupt mask */ 1134 mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 1135 I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK); 1136 1137 if (i2c->op == I2C_MASTER_WR) { 1138 dma_unmap_single(i2c->dev, wpaddr, 1139 msgs->len, DMA_TO_DEVICE); 1140 1141 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true); 1142 } else if (i2c->op == I2C_MASTER_RD) { 1143 dma_unmap_single(i2c->dev, rpaddr, 1144 msgs->len, DMA_FROM_DEVICE); 1145 1146 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true); 1147 } else { 1148 dma_unmap_single(i2c->dev, wpaddr, msgs->len, 1149 DMA_TO_DEVICE); 1150 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len, 1151 DMA_FROM_DEVICE); 1152 1153 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true); 1154 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), true); 1155 } 1156 1157 if (ret == 0) { 1158 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); 1159 i2c_dump_register(i2c); 1160 mtk_i2c_init_hw(i2c); 1161 return -ETIMEDOUT; 1162 } 1163 1164 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) { 1165 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr); 1166 mtk_i2c_init_hw(i2c); 1167 return -ENXIO; 1168 } 1169 1170 return 0; 1171 } 1172 1173 static int mtk_i2c_transfer(struct i2c_adapter *adap, 1174 struct i2c_msg msgs[], int num) 1175 { 1176 int ret; 1177 int left_num = num; 1178 struct mtk_i2c *i2c = i2c_get_adapdata(adap); 1179 1180 ret = clk_bulk_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1181 if (ret) 1182 return ret; 1183 1184 i2c->auto_restart = i2c->dev_comp->auto_restart; 1185 1186 /* checking if we can skip restart and optimize using WRRD mode */ 1187 if (i2c->auto_restart && num == 2) { 1188 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) && 1189 msgs[0].addr == msgs[1].addr) { 1190 i2c->auto_restart = 0; 1191 } 1192 } 1193 1194 if (i2c->auto_restart && num >= 2 && 1195 i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) 1196 /* ignore the first restart irq after the master code, 1197 * otherwise the first transfer will be discarded. 1198 */ 1199 i2c->ignore_restart_irq = true; 1200 else 1201 i2c->ignore_restart_irq = false; 1202 1203 while (left_num--) { 1204 if (!msgs->buf) { 1205 dev_dbg(i2c->dev, "data buffer is NULL.\n"); 1206 ret = -EINVAL; 1207 goto err_exit; 1208 } 1209 1210 if (msgs->flags & I2C_M_RD) 1211 i2c->op = I2C_MASTER_RD; 1212 else 1213 i2c->op = I2C_MASTER_WR; 1214 1215 if (!i2c->auto_restart) { 1216 if (num > 1) { 1217 /* combined two messages into one transaction */ 1218 i2c->op = I2C_MASTER_WRRD; 1219 left_num--; 1220 } 1221 } 1222 1223 /* always use DMA mode. */ 1224 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num); 1225 if (ret < 0) 1226 goto err_exit; 1227 1228 msgs++; 1229 } 1230 /* the return value is number of executed messages */ 1231 ret = num; 1232 1233 err_exit: 1234 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1235 return ret; 1236 } 1237 1238 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id) 1239 { 1240 struct mtk_i2c *i2c = dev_id; 1241 u16 restart_flag = 0; 1242 u16 intr_stat; 1243 1244 if (i2c->auto_restart) 1245 restart_flag = I2C_RS_TRANSFER; 1246 1247 intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); 1248 mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT); 1249 1250 /* 1251 * when occurs ack error, i2c controller generate two interrupts 1252 * first is the ack error interrupt, then the complete interrupt 1253 * i2c->irq_stat need keep the two interrupt value. 1254 */ 1255 i2c->irq_stat |= intr_stat; 1256 1257 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) { 1258 i2c->ignore_restart_irq = false; 1259 i2c->irq_stat = 0; 1260 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | 1261 I2C_TRANSAC_START, OFFSET_START); 1262 } else { 1263 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag)) 1264 complete(&i2c->msg_complete); 1265 } 1266 1267 return IRQ_HANDLED; 1268 } 1269 1270 static u32 mtk_i2c_functionality(struct i2c_adapter *adap) 1271 { 1272 if (i2c_check_quirks(adap, I2C_AQ_NO_ZERO_LEN)) 1273 return I2C_FUNC_I2C | 1274 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 1275 else 1276 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1277 } 1278 1279 static const struct i2c_algorithm mtk_i2c_algorithm = { 1280 .master_xfer = mtk_i2c_transfer, 1281 .functionality = mtk_i2c_functionality, 1282 }; 1283 1284 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c) 1285 { 1286 int ret; 1287 1288 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz); 1289 if (ret < 0) 1290 i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ; 1291 1292 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div); 1293 if (ret < 0) 1294 return ret; 1295 1296 if (i2c->clk_src_div == 0) 1297 return -EINVAL; 1298 1299 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic"); 1300 i2c->use_push_pull = 1301 of_property_read_bool(np, "mediatek,use-push-pull"); 1302 1303 i2c_parse_fw_timings(i2c->dev, &i2c->timing_info, true); 1304 1305 return 0; 1306 } 1307 1308 static int mtk_i2c_probe(struct platform_device *pdev) 1309 { 1310 int ret = 0; 1311 struct mtk_i2c *i2c; 1312 struct resource *res; 1313 int i, irq, speed_clk; 1314 1315 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 1316 if (!i2c) 1317 return -ENOMEM; 1318 1319 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1320 i2c->base = devm_ioremap_resource(&pdev->dev, res); 1321 if (IS_ERR(i2c->base)) 1322 return PTR_ERR(i2c->base); 1323 1324 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1325 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res); 1326 if (IS_ERR(i2c->pdmabase)) 1327 return PTR_ERR(i2c->pdmabase); 1328 1329 irq = platform_get_irq(pdev, 0); 1330 if (irq < 0) 1331 return irq; 1332 1333 init_completion(&i2c->msg_complete); 1334 1335 i2c->dev_comp = of_device_get_match_data(&pdev->dev); 1336 i2c->adap.dev.of_node = pdev->dev.of_node; 1337 i2c->dev = &pdev->dev; 1338 i2c->adap.dev.parent = &pdev->dev; 1339 i2c->adap.owner = THIS_MODULE; 1340 i2c->adap.algo = &mtk_i2c_algorithm; 1341 i2c->adap.quirks = i2c->dev_comp->quirks; 1342 i2c->adap.timeout = 2 * HZ; 1343 i2c->adap.retries = 1; 1344 i2c->adap.bus_regulator = devm_regulator_get_optional(&pdev->dev, "vbus"); 1345 if (IS_ERR(i2c->adap.bus_regulator)) { 1346 if (PTR_ERR(i2c->adap.bus_regulator) == -ENODEV) 1347 i2c->adap.bus_regulator = NULL; 1348 else 1349 return PTR_ERR(i2c->adap.bus_regulator); 1350 } 1351 1352 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c); 1353 if (ret) 1354 return -EINVAL; 1355 1356 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) 1357 return -EINVAL; 1358 1359 /* Fill in clk-bulk IDs */ 1360 for (i = 0; i < I2C_MT65XX_CLK_MAX; i++) 1361 i2c->clocks[i].id = i2c_mt65xx_clk_ids[i]; 1362 1363 /* Get clocks one by one, some may be optional */ 1364 i2c->clocks[I2C_MT65XX_CLK_MAIN].clk = devm_clk_get(&pdev->dev, "main"); 1365 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk)) { 1366 dev_err(&pdev->dev, "cannot get main clock\n"); 1367 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk); 1368 } 1369 1370 i2c->clocks[I2C_MT65XX_CLK_DMA].clk = devm_clk_get(&pdev->dev, "dma"); 1371 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk)) { 1372 dev_err(&pdev->dev, "cannot get dma clock\n"); 1373 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk); 1374 } 1375 1376 i2c->clocks[I2C_MT65XX_CLK_ARB].clk = devm_clk_get_optional(&pdev->dev, "arb"); 1377 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk)) 1378 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk); 1379 1380 if (i2c->have_pmic) { 1381 i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic"); 1382 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) { 1383 dev_err(&pdev->dev, "cannot get pmic clock\n"); 1384 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk); 1385 } 1386 speed_clk = I2C_MT65XX_CLK_PMIC; 1387 } else { 1388 i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL; 1389 speed_clk = I2C_MT65XX_CLK_MAIN; 1390 } 1391 1392 strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); 1393 1394 ret = mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk)); 1395 if (ret) { 1396 dev_err(&pdev->dev, "Failed to set the speed.\n"); 1397 return -EINVAL; 1398 } 1399 1400 if (i2c->dev_comp->max_dma_support > 32) { 1401 ret = dma_set_mask(&pdev->dev, 1402 DMA_BIT_MASK(i2c->dev_comp->max_dma_support)); 1403 if (ret) { 1404 dev_err(&pdev->dev, "dma_set_mask return error.\n"); 1405 return ret; 1406 } 1407 } 1408 1409 ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1410 if (ret) { 1411 dev_err(&pdev->dev, "clock enable failed!\n"); 1412 return ret; 1413 } 1414 mtk_i2c_init_hw(i2c); 1415 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1416 1417 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, 1418 IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE, 1419 dev_name(&pdev->dev), i2c); 1420 if (ret < 0) { 1421 dev_err(&pdev->dev, 1422 "Request I2C IRQ %d fail\n", irq); 1423 return ret; 1424 } 1425 1426 i2c_set_adapdata(&i2c->adap, i2c); 1427 ret = i2c_add_adapter(&i2c->adap); 1428 if (ret) 1429 return ret; 1430 1431 platform_set_drvdata(pdev, i2c); 1432 1433 return 0; 1434 } 1435 1436 static int mtk_i2c_remove(struct platform_device *pdev) 1437 { 1438 struct mtk_i2c *i2c = platform_get_drvdata(pdev); 1439 1440 i2c_del_adapter(&i2c->adap); 1441 1442 clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); 1443 1444 return 0; 1445 } 1446 1447 #ifdef CONFIG_PM_SLEEP 1448 static int mtk_i2c_suspend_noirq(struct device *dev) 1449 { 1450 struct mtk_i2c *i2c = dev_get_drvdata(dev); 1451 1452 i2c_mark_adapter_suspended(&i2c->adap); 1453 clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks); 1454 1455 return 0; 1456 } 1457 1458 static int mtk_i2c_resume_noirq(struct device *dev) 1459 { 1460 int ret; 1461 struct mtk_i2c *i2c = dev_get_drvdata(dev); 1462 1463 ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1464 if (ret) { 1465 dev_err(dev, "clock enable failed!\n"); 1466 return ret; 1467 } 1468 1469 mtk_i2c_init_hw(i2c); 1470 1471 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1472 1473 i2c_mark_adapter_resumed(&i2c->adap); 1474 1475 return 0; 1476 } 1477 #endif 1478 1479 static const struct dev_pm_ops mtk_i2c_pm = { 1480 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_i2c_suspend_noirq, 1481 mtk_i2c_resume_noirq) 1482 }; 1483 1484 static struct platform_driver mtk_i2c_driver = { 1485 .probe = mtk_i2c_probe, 1486 .remove = mtk_i2c_remove, 1487 .driver = { 1488 .name = I2C_DRV_NAME, 1489 .pm = &mtk_i2c_pm, 1490 .of_match_table = of_match_ptr(mtk_i2c_of_match), 1491 }, 1492 }; 1493 1494 module_platform_driver(mtk_i2c_driver); 1495 1496 MODULE_LICENSE("GPL v2"); 1497 MODULE_DESCRIPTION("MediaTek I2C Bus Driver"); 1498 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>"); 1499