1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This is a combined i2c adapter and algorithm driver for the 4 * MPC107/Tsi107 PowerPC northbridge and processors that include 5 * the same I2C unit (8240, 8245, 85xx). 6 * 7 * Copyright (C) 2003-2004 Humboldt Solutions Ltd, adrian@humboldt.co.uk 8 * Copyright (C) 2021 Allied Telesis Labs 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/sched/signal.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/of_irq.h> 17 #include <linux/platform_device.h> 18 #include <linux/property.h> 19 #include <linux/slab.h> 20 21 #include <linux/clk.h> 22 #include <linux/io.h> 23 #include <linux/iopoll.h> 24 #include <linux/fsl_devices.h> 25 #include <linux/i2c.h> 26 #include <linux/interrupt.h> 27 #include <linux/delay.h> 28 29 #include <asm/mpc52xx.h> 30 #include <asm/mpc85xx.h> 31 #include <sysdev/fsl_soc.h> 32 33 #define MPC_I2C_CLOCK_LEGACY 0 34 #define MPC_I2C_CLOCK_PRESERVE (~0U) 35 36 #define MPC_I2C_FDR 0x04 37 #define MPC_I2C_CR 0x08 38 #define MPC_I2C_SR 0x0c 39 #define MPC_I2C_DR 0x10 40 #define MPC_I2C_DFSRR 0x14 41 42 #define CCR_MEN 0x80 43 #define CCR_MIEN 0x40 44 #define CCR_MSTA 0x20 45 #define CCR_MTX 0x10 46 #define CCR_TXAK 0x08 47 #define CCR_RSTA 0x04 48 #define CCR_RSVD 0x02 49 50 #define CSR_MCF 0x80 51 #define CSR_MAAS 0x40 52 #define CSR_MBB 0x20 53 #define CSR_MAL 0x10 54 #define CSR_SRW 0x04 55 #define CSR_MIF 0x02 56 #define CSR_RXAK 0x01 57 58 enum mpc_i2c_action { 59 MPC_I2C_ACTION_START = 1, 60 MPC_I2C_ACTION_RESTART, 61 MPC_I2C_ACTION_READ_BEGIN, 62 MPC_I2C_ACTION_READ_BYTE, 63 MPC_I2C_ACTION_WRITE, 64 MPC_I2C_ACTION_STOP, 65 66 __MPC_I2C_ACTION_CNT 67 }; 68 69 static const char * const action_str[] = { 70 "invalid", 71 "start", 72 "restart", 73 "read begin", 74 "read", 75 "write", 76 "stop", 77 }; 78 79 static_assert(ARRAY_SIZE(action_str) == __MPC_I2C_ACTION_CNT); 80 81 struct mpc_i2c { 82 struct device *dev; 83 void __iomem *base; 84 u32 interrupt; 85 wait_queue_head_t waitq; 86 spinlock_t lock; 87 struct i2c_adapter adap; 88 int irq; 89 u32 real_clk; 90 u8 fdr, dfsrr; 91 struct clk *clk_per; 92 u32 cntl_bits; 93 enum mpc_i2c_action action; 94 struct i2c_msg *msgs; 95 int num_msgs; 96 int curr_msg; 97 u32 byte_posn; 98 u32 block; 99 int rc; 100 int expect_rxack; 101 bool has_errata_A004447; 102 }; 103 104 struct mpc_i2c_divider { 105 u16 divider; 106 u16 fdr; /* including dfsrr */ 107 }; 108 109 struct mpc_i2c_data { 110 void (*setup)(struct device_node *node, struct mpc_i2c *i2c, u32 clock); 111 }; 112 113 static inline void writeccr(struct mpc_i2c *i2c, u32 x) 114 { 115 writeb(x, i2c->base + MPC_I2C_CR); 116 } 117 118 /* Sometimes 9th clock pulse isn't generated, and target doesn't release 119 * the bus, because it wants to send ACK. 120 * Following sequence of enabling/disabling and sending start/stop generates 121 * the 9 pulses, each with a START then ending with STOP, so it's all OK. 122 */ 123 static void mpc_i2c_fixup(struct mpc_i2c *i2c) 124 { 125 int k; 126 unsigned long flags; 127 128 for (k = 9; k; k--) { 129 writeccr(i2c, 0); 130 writeb(0, i2c->base + MPC_I2C_SR); /* clear any status bits */ 131 writeccr(i2c, CCR_MEN | CCR_MSTA); /* START */ 132 readb(i2c->base + MPC_I2C_DR); /* init xfer */ 133 udelay(15); /* let it hit the bus */ 134 local_irq_save(flags); /* should not be delayed further */ 135 writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSTA); /* delay SDA */ 136 readb(i2c->base + MPC_I2C_DR); 137 if (k != 1) 138 udelay(5); 139 local_irq_restore(flags); 140 } 141 writeccr(i2c, CCR_MEN); /* Initiate STOP */ 142 readb(i2c->base + MPC_I2C_DR); 143 udelay(15); /* Let STOP propagate */ 144 writeccr(i2c, 0); 145 } 146 147 static int i2c_mpc_wait_sr(struct mpc_i2c *i2c, int mask) 148 { 149 void __iomem *addr = i2c->base + MPC_I2C_SR; 150 u8 val; 151 152 return readb_poll_timeout(addr, val, val & mask, 0, 100); 153 } 154 155 /* 156 * Workaround for Erratum A004447. From the P2040CE Rev Q 157 * 158 * 1. Set up the frequency divider and sampling rate. 159 * 2. I2CCR - a0h 160 * 3. Poll for I2CSR[MBB] to get set. 161 * 4. If I2CSR[MAL] is set (an indication that SDA is stuck low), then go to 162 * step 5. If MAL is not set, then go to step 13. 163 * 5. I2CCR - 00h 164 * 6. I2CCR - 22h 165 * 7. I2CCR - a2h 166 * 8. Poll for I2CSR[MBB] to get set. 167 * 9. Issue read to I2CDR. 168 * 10. Poll for I2CSR[MIF] to be set. 169 * 11. I2CCR - 82h 170 * 12. Workaround complete. Skip the next steps. 171 * 13. Issue read to I2CDR. 172 * 14. Poll for I2CSR[MIF] to be set. 173 * 15. I2CCR - 80h 174 */ 175 static void mpc_i2c_fixup_A004447(struct mpc_i2c *i2c) 176 { 177 int ret; 178 u32 val; 179 180 writeccr(i2c, CCR_MEN | CCR_MSTA); 181 ret = i2c_mpc_wait_sr(i2c, CSR_MBB); 182 if (ret) { 183 dev_err(i2c->dev, "timeout waiting for CSR_MBB\n"); 184 return; 185 } 186 187 val = readb(i2c->base + MPC_I2C_SR); 188 189 if (val & CSR_MAL) { 190 writeccr(i2c, 0x00); 191 writeccr(i2c, CCR_MSTA | CCR_RSVD); 192 writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSVD); 193 ret = i2c_mpc_wait_sr(i2c, CSR_MBB); 194 if (ret) { 195 dev_err(i2c->dev, "timeout waiting for CSR_MBB\n"); 196 return; 197 } 198 val = readb(i2c->base + MPC_I2C_DR); 199 ret = i2c_mpc_wait_sr(i2c, CSR_MIF); 200 if (ret) { 201 dev_err(i2c->dev, "timeout waiting for CSR_MIF\n"); 202 return; 203 } 204 writeccr(i2c, CCR_MEN | CCR_RSVD); 205 } else { 206 val = readb(i2c->base + MPC_I2C_DR); 207 ret = i2c_mpc_wait_sr(i2c, CSR_MIF); 208 if (ret) { 209 dev_err(i2c->dev, "timeout waiting for CSR_MIF\n"); 210 return; 211 } 212 writeccr(i2c, CCR_MEN); 213 } 214 } 215 216 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x) 217 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = { 218 {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23}, 219 {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02}, 220 {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28}, 221 {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a}, 222 {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09}, 223 {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81}, 224 {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30}, 225 {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32}, 226 {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10}, 227 {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a}, 228 {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14}, 229 {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17}, 230 {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d}, 231 {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c}, 232 {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f}, 233 {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e}, 234 {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c}, 235 {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f} 236 }; 237 238 static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, 239 u32 *real_clk) 240 { 241 struct fwnode_handle *fwnode = of_fwnode_handle(node); 242 const struct mpc_i2c_divider *div = NULL; 243 unsigned int pvr = mfspr(SPRN_PVR); 244 u32 divider; 245 int i; 246 247 if (clock == MPC_I2C_CLOCK_LEGACY) { 248 /* see below - default fdr = 0x3f -> div = 2048 */ 249 *real_clk = mpc5xxx_fwnode_get_bus_frequency(fwnode) / 2048; 250 return -EINVAL; 251 } 252 253 /* Determine divider value */ 254 divider = mpc5xxx_fwnode_get_bus_frequency(fwnode) / clock; 255 256 /* 257 * We want to choose an FDR/DFSR that generates an I2C bus speed that 258 * is equal to or lower than the requested speed. 259 */ 260 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) { 261 div = &mpc_i2c_dividers_52xx[i]; 262 /* Old MPC5200 rev A CPUs do not support the high bits */ 263 if (div->fdr & 0xc0 && pvr == 0x80822011) 264 continue; 265 if (div->divider >= divider) 266 break; 267 } 268 269 *real_clk = mpc5xxx_fwnode_get_bus_frequency(fwnode) / div->divider; 270 return (int)div->fdr; 271 } 272 273 static void mpc_i2c_setup_52xx(struct device_node *node, 274 struct mpc_i2c *i2c, 275 u32 clock) 276 { 277 int ret, fdr; 278 279 if (clock == MPC_I2C_CLOCK_PRESERVE) { 280 dev_dbg(i2c->dev, "using fdr %d\n", 281 readb(i2c->base + MPC_I2C_FDR)); 282 return; 283 } 284 285 ret = mpc_i2c_get_fdr_52xx(node, clock, &i2c->real_clk); 286 fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */ 287 288 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); 289 290 if (ret >= 0) 291 dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk, 292 fdr); 293 } 294 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */ 295 static void mpc_i2c_setup_52xx(struct device_node *node, 296 struct mpc_i2c *i2c, 297 u32 clock) 298 { 299 } 300 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */ 301 302 #ifdef CONFIG_PPC_MPC512x 303 static void mpc_i2c_setup_512x(struct device_node *node, 304 struct mpc_i2c *i2c, 305 u32 clock) 306 { 307 void __iomem *ctrl; 308 u32 idx; 309 310 /* Enable I2C interrupts for mpc5121 */ 311 struct device_node *node_ctrl __free(device_node) = 312 of_find_compatible_node(NULL, NULL, "fsl,mpc5121-i2c-ctrl"); 313 if (node_ctrl) { 314 ctrl = of_iomap(node_ctrl, 0); 315 if (ctrl) { 316 u64 addr; 317 /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */ 318 of_property_read_reg(node, 0, &addr, NULL); 319 idx = (addr & 0xff) / 0x20; 320 setbits32(ctrl, 1 << (24 + idx * 2)); 321 iounmap(ctrl); 322 } 323 } 324 325 /* The clock setup for the 52xx works also fine for the 512x */ 326 mpc_i2c_setup_52xx(node, i2c, clock); 327 } 328 #else /* CONFIG_PPC_MPC512x */ 329 static void mpc_i2c_setup_512x(struct device_node *node, 330 struct mpc_i2c *i2c, 331 u32 clock) 332 { 333 } 334 #endif /* CONFIG_PPC_MPC512x */ 335 336 #ifdef CONFIG_FSL_SOC 337 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = { 338 {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123}, 339 {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102}, 340 {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127}, 341 {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105}, 342 {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106}, 343 {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107}, 344 {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07}, 345 {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a}, 346 {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b}, 347 {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e}, 348 {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133}, 349 {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136}, 350 {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115}, 351 {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b}, 352 {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e}, 353 {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d}, 354 {49152, 0x011e}, {61440, 0x011f} 355 }; 356 357 static u32 mpc_i2c_get_sec_cfg_8xxx(void) 358 { 359 u32 __iomem *reg; 360 u32 val = 0; 361 362 struct device_node *node __free(device_node) = 363 of_find_node_by_name(NULL, "global-utilities"); 364 if (node) { 365 const u32 *prop = of_get_property(node, "reg", NULL); 366 if (prop) { 367 /* 368 * Map and check POR Device Status Register 2 369 * (PORDEVSR2) at 0xE0014. Note than while MPC8533 370 * and MPC8544 indicate SEC frequency ratio 371 * configuration as bit 26 in PORDEVSR2, other MPC8xxx 372 * parts may store it differently or may not have it 373 * at all. 374 */ 375 reg = ioremap(get_immrbase() + *prop + 0x14, 0x4); 376 if (!reg) 377 printk(KERN_ERR 378 "Error: couldn't map PORDEVSR2\n"); 379 else 380 val = in_be32(reg) & 0x00000020; /* sec-cfg */ 381 iounmap(reg); 382 } 383 } 384 385 return val; 386 } 387 388 static u32 mpc_i2c_get_prescaler_8xxx(void) 389 { 390 /* 391 * According to the AN2919 all MPC824x have prescaler 1, while MPC83xx 392 * may have prescaler 1, 2, or 3, depending on the power-on 393 * configuration. 394 */ 395 u32 prescaler = 1; 396 397 /* mpc85xx */ 398 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2) 399 || pvr_version_is(PVR_VER_E500MC) 400 || pvr_version_is(PVR_VER_E5500) 401 || pvr_version_is(PVR_VER_E6500)) { 402 unsigned int svr = mfspr(SPRN_SVR); 403 404 if ((SVR_SOC_VER(svr) == SVR_8540) 405 || (SVR_SOC_VER(svr) == SVR_8541) 406 || (SVR_SOC_VER(svr) == SVR_8560) 407 || (SVR_SOC_VER(svr) == SVR_8555) 408 || (SVR_SOC_VER(svr) == SVR_8610)) 409 /* the above 85xx SoCs have prescaler 1 */ 410 prescaler = 1; 411 else if ((SVR_SOC_VER(svr) == SVR_8533) 412 || (SVR_SOC_VER(svr) == SVR_8544)) 413 /* the above 85xx SoCs have prescaler 3 or 2 */ 414 prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2; 415 else 416 /* all the other 85xx have prescaler 2 */ 417 prescaler = 2; 418 } 419 420 return prescaler; 421 } 422 423 static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, 424 u32 *real_clk) 425 { 426 const struct mpc_i2c_divider *div = NULL; 427 u32 prescaler = mpc_i2c_get_prescaler_8xxx(); 428 u32 divider; 429 int i; 430 431 if (clock == MPC_I2C_CLOCK_LEGACY) { 432 /* see below - default fdr = 0x1031 -> div = 16 * 3072 */ 433 *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072); 434 return -EINVAL; 435 } 436 437 divider = fsl_get_sys_freq() / clock / prescaler; 438 439 pr_debug("I2C: src_clock=%d clock=%d divider=%d\n", 440 fsl_get_sys_freq(), clock, divider); 441 442 /* 443 * We want to choose an FDR/DFSR that generates an I2C bus speed that 444 * is equal to or lower than the requested speed. 445 */ 446 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) { 447 div = &mpc_i2c_dividers_8xxx[i]; 448 if (div->divider >= divider) 449 break; 450 } 451 452 *real_clk = fsl_get_sys_freq() / prescaler / div->divider; 453 return (int)div->fdr; 454 } 455 456 static void mpc_i2c_setup_8xxx(struct device_node *node, 457 struct mpc_i2c *i2c, 458 u32 clock) 459 { 460 int ret, fdr; 461 462 if (clock == MPC_I2C_CLOCK_PRESERVE) { 463 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n", 464 readb(i2c->base + MPC_I2C_DFSRR), 465 readb(i2c->base + MPC_I2C_FDR)); 466 return; 467 } 468 469 ret = mpc_i2c_get_fdr_8xxx(node, clock, &i2c->real_clk); 470 fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */ 471 472 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); 473 writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR); 474 475 if (ret >= 0) 476 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n", 477 i2c->real_clk, fdr >> 8, fdr & 0xff); 478 } 479 480 #else /* !CONFIG_FSL_SOC */ 481 static void mpc_i2c_setup_8xxx(struct device_node *node, 482 struct mpc_i2c *i2c, 483 u32 clock) 484 { 485 } 486 #endif /* CONFIG_FSL_SOC */ 487 488 static void mpc_i2c_finish(struct mpc_i2c *i2c, int rc) 489 { 490 i2c->rc = rc; 491 i2c->block = 0; 492 i2c->cntl_bits = CCR_MEN; 493 writeccr(i2c, i2c->cntl_bits); 494 wake_up(&i2c->waitq); 495 } 496 497 static void mpc_i2c_do_action(struct mpc_i2c *i2c) 498 { 499 struct i2c_msg *msg = NULL; 500 int dir = 0; 501 int recv_len = 0; 502 u8 byte; 503 504 dev_dbg(i2c->dev, "action = %s\n", action_str[i2c->action]); 505 506 i2c->cntl_bits &= ~(CCR_RSTA | CCR_MTX | CCR_TXAK); 507 508 if (i2c->action != MPC_I2C_ACTION_STOP) { 509 msg = &i2c->msgs[i2c->curr_msg]; 510 if (msg->flags & I2C_M_RD) 511 dir = 1; 512 if (msg->flags & I2C_M_RECV_LEN) 513 recv_len = 1; 514 } 515 516 switch (i2c->action) { 517 case MPC_I2C_ACTION_RESTART: 518 i2c->cntl_bits |= CCR_RSTA; 519 fallthrough; 520 521 case MPC_I2C_ACTION_START: 522 i2c->cntl_bits |= CCR_MSTA | CCR_MTX; 523 writeccr(i2c, i2c->cntl_bits); 524 writeb((msg->addr << 1) | dir, i2c->base + MPC_I2C_DR); 525 i2c->expect_rxack = 1; 526 i2c->action = dir ? MPC_I2C_ACTION_READ_BEGIN : MPC_I2C_ACTION_WRITE; 527 break; 528 529 case MPC_I2C_ACTION_READ_BEGIN: 530 if (msg->len) { 531 if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN)) 532 i2c->cntl_bits |= CCR_TXAK; 533 534 writeccr(i2c, i2c->cntl_bits); 535 /* Dummy read */ 536 readb(i2c->base + MPC_I2C_DR); 537 } 538 i2c->action = MPC_I2C_ACTION_READ_BYTE; 539 break; 540 541 case MPC_I2C_ACTION_READ_BYTE: 542 if (i2c->byte_posn || !recv_len) { 543 /* Generate Tx ACK on next to last byte */ 544 if (i2c->byte_posn == msg->len - 2) 545 i2c->cntl_bits |= CCR_TXAK; 546 /* Do not generate stop on last byte */ 547 if (i2c->byte_posn == msg->len - 1) 548 i2c->cntl_bits |= CCR_MTX; 549 550 writeccr(i2c, i2c->cntl_bits); 551 } 552 553 byte = readb(i2c->base + MPC_I2C_DR); 554 555 if (i2c->byte_posn == 0 && recv_len) { 556 if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX) { 557 mpc_i2c_finish(i2c, -EPROTO); 558 return; 559 } 560 msg->len += byte; 561 /* 562 * For block reads, generate Tx ACK here if data length 563 * is 1 byte (total length is 2 bytes). 564 */ 565 if (msg->len == 2) { 566 i2c->cntl_bits |= CCR_TXAK; 567 writeccr(i2c, i2c->cntl_bits); 568 } 569 } 570 571 dev_dbg(i2c->dev, "%s %02x\n", action_str[i2c->action], byte); 572 msg->buf[i2c->byte_posn++] = byte; 573 break; 574 575 case MPC_I2C_ACTION_WRITE: 576 dev_dbg(i2c->dev, "%s %02x\n", action_str[i2c->action], 577 msg->buf[i2c->byte_posn]); 578 writeb(msg->buf[i2c->byte_posn++], i2c->base + MPC_I2C_DR); 579 i2c->expect_rxack = 1; 580 break; 581 582 case MPC_I2C_ACTION_STOP: 583 mpc_i2c_finish(i2c, 0); 584 break; 585 586 default: 587 WARN(1, "Unexpected action %d\n", i2c->action); 588 break; 589 } 590 591 if (msg && msg->len == i2c->byte_posn) { 592 i2c->curr_msg++; 593 i2c->byte_posn = 0; 594 595 if (i2c->curr_msg == i2c->num_msgs) { 596 i2c->action = MPC_I2C_ACTION_STOP; 597 /* 598 * We don't get another interrupt on read so 599 * finish the transfer now 600 */ 601 if (dir) 602 mpc_i2c_finish(i2c, 0); 603 } else { 604 i2c->action = MPC_I2C_ACTION_RESTART; 605 } 606 } 607 } 608 609 static void mpc_i2c_do_intr(struct mpc_i2c *i2c, u8 status) 610 { 611 spin_lock(&i2c->lock); 612 613 if (!(status & CSR_MCF)) { 614 dev_dbg(i2c->dev, "unfinished\n"); 615 mpc_i2c_finish(i2c, -EIO); 616 goto out; 617 } 618 619 if (status & CSR_MAL) { 620 dev_dbg(i2c->dev, "arbitration lost\n"); 621 mpc_i2c_finish(i2c, -EAGAIN); 622 goto out; 623 } 624 625 if (i2c->expect_rxack && (status & CSR_RXAK)) { 626 dev_dbg(i2c->dev, "no Rx ACK\n"); 627 mpc_i2c_finish(i2c, -ENXIO); 628 goto out; 629 } 630 i2c->expect_rxack = 0; 631 632 mpc_i2c_do_action(i2c); 633 634 out: 635 spin_unlock(&i2c->lock); 636 } 637 638 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id) 639 { 640 struct mpc_i2c *i2c = dev_id; 641 u8 status; 642 643 status = readb(i2c->base + MPC_I2C_SR); 644 if (status & CSR_MIF) { 645 /* Wait up to 100us for transfer to properly complete */ 646 readb_poll_timeout_atomic(i2c->base + MPC_I2C_SR, status, status & CSR_MCF, 0, 100); 647 writeb(0, i2c->base + MPC_I2C_SR); 648 mpc_i2c_do_intr(i2c, status); 649 return IRQ_HANDLED; 650 } 651 return IRQ_NONE; 652 } 653 654 static int mpc_i2c_wait_for_completion(struct mpc_i2c *i2c) 655 { 656 long time_left; 657 658 time_left = wait_event_timeout(i2c->waitq, !i2c->block, i2c->adap.timeout); 659 if (!time_left) 660 return -ETIMEDOUT; 661 if (time_left < 0) 662 return time_left; 663 664 return 0; 665 } 666 667 static int mpc_i2c_execute_msg(struct mpc_i2c *i2c) 668 { 669 unsigned long orig_jiffies; 670 unsigned long flags; 671 int ret; 672 673 spin_lock_irqsave(&i2c->lock, flags); 674 675 i2c->curr_msg = 0; 676 i2c->rc = 0; 677 i2c->byte_posn = 0; 678 i2c->block = 1; 679 i2c->action = MPC_I2C_ACTION_START; 680 681 i2c->cntl_bits = CCR_MEN | CCR_MIEN; 682 writeb(0, i2c->base + MPC_I2C_SR); 683 writeccr(i2c, i2c->cntl_bits); 684 685 mpc_i2c_do_action(i2c); 686 687 spin_unlock_irqrestore(&i2c->lock, flags); 688 689 ret = mpc_i2c_wait_for_completion(i2c); 690 if (ret) 691 i2c->rc = ret; 692 693 if (i2c->rc == -EIO || i2c->rc == -EAGAIN || i2c->rc == -ETIMEDOUT) 694 i2c_recover_bus(&i2c->adap); 695 696 orig_jiffies = jiffies; 697 /* Wait until STOP is seen, allow up to 1 s */ 698 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) { 699 if (time_after(jiffies, orig_jiffies + HZ)) { 700 u8 status = readb(i2c->base + MPC_I2C_SR); 701 702 dev_dbg(i2c->dev, "timeout\n"); 703 if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) { 704 writeb(status & ~CSR_MAL, 705 i2c->base + MPC_I2C_SR); 706 i2c_recover_bus(&i2c->adap); 707 } 708 return -EIO; 709 } 710 cond_resched(); 711 } 712 713 return i2c->rc; 714 } 715 716 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 717 { 718 int rc, ret = num; 719 struct mpc_i2c *i2c = i2c_get_adapdata(adap); 720 int i; 721 722 dev_dbg(i2c->dev, "num = %d\n", num); 723 for (i = 0; i < num; i++) 724 dev_dbg(i2c->dev, " addr = %02x, flags = %02x, len = %d, %*ph\n", 725 msgs[i].addr, msgs[i].flags, msgs[i].len, 726 msgs[i].flags & I2C_M_RD ? 0 : msgs[i].len, 727 msgs[i].buf); 728 729 WARN_ON(i2c->msgs != NULL); 730 i2c->msgs = msgs; 731 i2c->num_msgs = num; 732 733 rc = mpc_i2c_execute_msg(i2c); 734 if (rc < 0) 735 ret = rc; 736 737 i2c->num_msgs = 0; 738 i2c->msgs = NULL; 739 740 return ret; 741 } 742 743 static u32 mpc_functionality(struct i2c_adapter *adap) 744 { 745 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 746 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL; 747 } 748 749 static int fsl_i2c_bus_recovery(struct i2c_adapter *adap) 750 { 751 struct mpc_i2c *i2c = i2c_get_adapdata(adap); 752 753 if (i2c->has_errata_A004447) 754 mpc_i2c_fixup_A004447(i2c); 755 else 756 mpc_i2c_fixup(i2c); 757 758 return 0; 759 } 760 761 static const struct i2c_algorithm mpc_algo = { 762 .xfer = mpc_xfer, 763 .functionality = mpc_functionality, 764 }; 765 766 static struct i2c_adapter mpc_ops = { 767 .owner = THIS_MODULE, 768 .algo = &mpc_algo, 769 }; 770 771 static struct i2c_bus_recovery_info fsl_i2c_recovery_info = { 772 .recover_bus = fsl_i2c_bus_recovery, 773 }; 774 775 static int fsl_i2c_probe(struct platform_device *op) 776 { 777 const struct mpc_i2c_data *data; 778 struct mpc_i2c *i2c; 779 struct clk *clk; 780 int result; 781 u32 clock; 782 int err; 783 784 i2c = devm_kzalloc(&op->dev, sizeof(*i2c), GFP_KERNEL); 785 if (!i2c) 786 return -ENOMEM; 787 788 i2c->dev = &op->dev; /* for debug and error output */ 789 790 init_waitqueue_head(&i2c->waitq); 791 spin_lock_init(&i2c->lock); 792 793 i2c->base = devm_platform_ioremap_resource(op, 0); 794 if (IS_ERR(i2c->base)) 795 return PTR_ERR(i2c->base); 796 797 i2c->irq = platform_get_irq(op, 0); 798 if (i2c->irq < 0) 799 return i2c->irq; 800 801 result = devm_request_irq(&op->dev, i2c->irq, mpc_i2c_isr, 802 IRQF_SHARED, "i2c-mpc", i2c); 803 if (result < 0) { 804 dev_err(i2c->dev, "failed to attach interrupt\n"); 805 return result; 806 } 807 808 /* 809 * enable clock for the I2C peripheral (non fatal), 810 * keep a reference upon successful allocation 811 */ 812 clk = devm_clk_get_optional(&op->dev, NULL); 813 if (IS_ERR(clk)) 814 return PTR_ERR(clk); 815 816 err = clk_prepare_enable(clk); 817 if (err) { 818 dev_err(&op->dev, "failed to enable clock\n"); 819 return err; 820 } 821 822 i2c->clk_per = clk; 823 824 if (of_property_read_bool(op->dev.of_node, "fsl,preserve-clocking")) { 825 clock = MPC_I2C_CLOCK_PRESERVE; 826 } else { 827 result = of_property_read_u32(op->dev.of_node, 828 "clock-frequency", &clock); 829 if (result) 830 clock = MPC_I2C_CLOCK_LEGACY; 831 } 832 833 data = device_get_match_data(&op->dev); 834 if (data) { 835 data->setup(op->dev.of_node, i2c, clock); 836 } else { 837 /* Backwards compatibility */ 838 if (of_property_read_bool(op->dev.of_node, "dfsrr")) 839 mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock); 840 } 841 842 /* Sadly, we have to support two deprecated bindings here */ 843 result = of_property_read_u32(op->dev.of_node, 844 "i2c-transfer-timeout-us", 845 &mpc_ops.timeout); 846 if (result == -EINVAL) 847 result = of_property_read_u32(op->dev.of_node, 848 "i2c-scl-clk-low-timeout-us", 849 &mpc_ops.timeout); 850 if (result == -EINVAL) 851 result = of_property_read_u32(op->dev.of_node, 852 "fsl,timeout", &mpc_ops.timeout); 853 854 if (!result) { 855 mpc_ops.timeout *= HZ / 1000000; 856 if (mpc_ops.timeout < 5) 857 mpc_ops.timeout = 5; 858 } else { 859 mpc_ops.timeout = HZ; 860 } 861 862 dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ); 863 864 if (of_property_read_bool(op->dev.of_node, "fsl,i2c-erratum-a004447")) 865 i2c->has_errata_A004447 = true; 866 867 i2c->adap = mpc_ops; 868 scnprintf(i2c->adap.name, sizeof(i2c->adap.name), 869 "MPC adapter (%s)", of_node_full_name(op->dev.of_node)); 870 i2c->adap.dev.parent = &op->dev; 871 i2c->adap.nr = op->id; 872 i2c->adap.dev.of_node = of_node_get(op->dev.of_node); 873 i2c->adap.bus_recovery_info = &fsl_i2c_recovery_info; 874 platform_set_drvdata(op, i2c); 875 i2c_set_adapdata(&i2c->adap, i2c); 876 877 result = i2c_add_numbered_adapter(&i2c->adap); 878 if (result) 879 goto fail_add; 880 881 return 0; 882 883 fail_add: 884 clk_disable_unprepare(i2c->clk_per); 885 886 return result; 887 }; 888 889 static void fsl_i2c_remove(struct platform_device *op) 890 { 891 struct mpc_i2c *i2c = platform_get_drvdata(op); 892 893 i2c_del_adapter(&i2c->adap); 894 895 clk_disable_unprepare(i2c->clk_per); 896 }; 897 898 static int __maybe_unused mpc_i2c_suspend(struct device *dev) 899 { 900 struct mpc_i2c *i2c = dev_get_drvdata(dev); 901 902 i2c->fdr = readb(i2c->base + MPC_I2C_FDR); 903 i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR); 904 905 return 0; 906 } 907 908 static int __maybe_unused mpc_i2c_resume(struct device *dev) 909 { 910 struct mpc_i2c *i2c = dev_get_drvdata(dev); 911 912 writeb(i2c->fdr, i2c->base + MPC_I2C_FDR); 913 writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR); 914 915 return 0; 916 } 917 static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume); 918 919 static const struct mpc_i2c_data mpc_i2c_data_512x = { 920 .setup = mpc_i2c_setup_512x, 921 }; 922 923 static const struct mpc_i2c_data mpc_i2c_data_52xx = { 924 .setup = mpc_i2c_setup_52xx, 925 }; 926 927 static const struct mpc_i2c_data mpc_i2c_data_8313 = { 928 .setup = mpc_i2c_setup_8xxx, 929 }; 930 931 static const struct mpc_i2c_data mpc_i2c_data_8543 = { 932 .setup = mpc_i2c_setup_8xxx, 933 }; 934 935 static const struct mpc_i2c_data mpc_i2c_data_8544 = { 936 .setup = mpc_i2c_setup_8xxx, 937 }; 938 939 static const struct of_device_id mpc_i2c_of_match[] = { 940 {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, }, 941 {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, }, 942 {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, }, 943 {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, }, 944 {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, }, 945 {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, }, 946 {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, }, 947 /* Backward compatibility */ 948 {.compatible = "fsl-i2c", }, 949 {}, 950 }; 951 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match); 952 953 /* Structure for a device driver */ 954 static struct platform_driver mpc_i2c_driver = { 955 .probe = fsl_i2c_probe, 956 .remove_new = fsl_i2c_remove, 957 .driver = { 958 .name = "mpc-i2c", 959 .of_match_table = mpc_i2c_of_match, 960 .pm = &mpc_i2c_pm_ops, 961 }, 962 }; 963 964 module_platform_driver(mpc_i2c_driver); 965 966 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>"); 967 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and " 968 "MPC824x/83xx/85xx/86xx/512x/52xx processors"); 969 MODULE_LICENSE("GPL"); 970