1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * This is a combined i2c adapter and algorithm driver for the
4 * MPC107/Tsi107 PowerPC northbridge and processors that include
5 * the same I2C unit (8240, 8245, 85xx).
6 *
7 * Copyright (C) 2003-2004 Humboldt Solutions Ltd, adrian@humboldt.co.uk
8 * Copyright (C) 2021 Allied Telesis Labs
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/sched/signal.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/platform_device.h>
18 #include <linux/property.h>
19 #include <linux/slab.h>
20
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/iopoll.h>
24 #include <linux/fsl_devices.h>
25 #include <linux/i2c.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28
29 #include <asm/mpc52xx.h>
30 #include <asm/mpc85xx.h>
31 #include <sysdev/fsl_soc.h>
32
33 #define MPC_I2C_CLOCK_LEGACY 0
34 #define MPC_I2C_CLOCK_PRESERVE (~0U)
35
36 #define MPC_I2C_FDR 0x04
37 #define MPC_I2C_CR 0x08
38 #define MPC_I2C_SR 0x0c
39 #define MPC_I2C_DR 0x10
40 #define MPC_I2C_DFSRR 0x14
41
42 #define CCR_MEN 0x80
43 #define CCR_MIEN 0x40
44 #define CCR_MSTA 0x20
45 #define CCR_MTX 0x10
46 #define CCR_TXAK 0x08
47 #define CCR_RSTA 0x04
48 #define CCR_RSVD 0x02
49
50 #define CSR_MCF 0x80
51 #define CSR_MAAS 0x40
52 #define CSR_MBB 0x20
53 #define CSR_MAL 0x10
54 #define CSR_SRW 0x04
55 #define CSR_MIF 0x02
56 #define CSR_RXAK 0x01
57
58 enum mpc_i2c_action {
59 MPC_I2C_ACTION_START = 1,
60 MPC_I2C_ACTION_RESTART,
61 MPC_I2C_ACTION_READ_BEGIN,
62 MPC_I2C_ACTION_READ_BYTE,
63 MPC_I2C_ACTION_WRITE,
64 MPC_I2C_ACTION_STOP,
65
66 __MPC_I2C_ACTION_CNT
67 };
68
69 static const char * const action_str[] = {
70 "invalid",
71 "start",
72 "restart",
73 "read begin",
74 "read",
75 "write",
76 "stop",
77 };
78
79 static_assert(ARRAY_SIZE(action_str) == __MPC_I2C_ACTION_CNT);
80
81 struct mpc_i2c {
82 struct device *dev;
83 void __iomem *base;
84 u32 interrupt;
85 wait_queue_head_t waitq;
86 spinlock_t lock;
87 struct i2c_adapter adap;
88 int irq;
89 u32 real_clk;
90 u8 fdr, dfsrr;
91 u32 cntl_bits;
92 enum mpc_i2c_action action;
93 struct i2c_msg *msgs;
94 int num_msgs;
95 int curr_msg;
96 u32 byte_posn;
97 u32 block;
98 int rc;
99 int expect_rxack;
100 bool has_errata_A004447;
101 };
102
103 struct mpc_i2c_divider {
104 u16 divider;
105 u16 fdr; /* including dfsrr */
106 };
107
108 struct mpc_i2c_data {
109 void (*setup)(struct device_node *node, struct mpc_i2c *i2c, u32 clock);
110 };
111
writeccr(struct mpc_i2c * i2c,u32 x)112 static inline void writeccr(struct mpc_i2c *i2c, u32 x)
113 {
114 writeb(x, i2c->base + MPC_I2C_CR);
115 }
116
117 /* Sometimes 9th clock pulse isn't generated, and target doesn't release
118 * the bus, because it wants to send ACK.
119 * Following sequence of enabling/disabling and sending start/stop generates
120 * the 9 pulses, each with a START then ending with STOP, so it's all OK.
121 */
mpc_i2c_fixup(struct mpc_i2c * i2c)122 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
123 {
124 int k;
125 unsigned long flags;
126
127 for (k = 9; k; k--) {
128 writeccr(i2c, 0);
129 writeb(0, i2c->base + MPC_I2C_SR); /* clear any status bits */
130 writeccr(i2c, CCR_MEN | CCR_MSTA); /* START */
131 readb(i2c->base + MPC_I2C_DR); /* init xfer */
132 udelay(15); /* let it hit the bus */
133 local_irq_save(flags); /* should not be delayed further */
134 writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSTA); /* delay SDA */
135 readb(i2c->base + MPC_I2C_DR);
136 if (k != 1)
137 udelay(5);
138 local_irq_restore(flags);
139 }
140 writeccr(i2c, CCR_MEN); /* Initiate STOP */
141 readb(i2c->base + MPC_I2C_DR);
142 udelay(15); /* Let STOP propagate */
143 writeccr(i2c, 0);
144 }
145
i2c_mpc_wait_sr(struct mpc_i2c * i2c,int mask)146 static int i2c_mpc_wait_sr(struct mpc_i2c *i2c, int mask)
147 {
148 void __iomem *addr = i2c->base + MPC_I2C_SR;
149 u8 val;
150
151 return readb_poll_timeout(addr, val, val & mask, 0, 100);
152 }
153
154 /*
155 * Workaround for Erratum A004447. From the P2040CE Rev Q
156 *
157 * 1. Set up the frequency divider and sampling rate.
158 * 2. I2CCR - a0h
159 * 3. Poll for I2CSR[MBB] to get set.
160 * 4. If I2CSR[MAL] is set (an indication that SDA is stuck low), then go to
161 * step 5. If MAL is not set, then go to step 13.
162 * 5. I2CCR - 00h
163 * 6. I2CCR - 22h
164 * 7. I2CCR - a2h
165 * 8. Poll for I2CSR[MBB] to get set.
166 * 9. Issue read to I2CDR.
167 * 10. Poll for I2CSR[MIF] to be set.
168 * 11. I2CCR - 82h
169 * 12. Workaround complete. Skip the next steps.
170 * 13. Issue read to I2CDR.
171 * 14. Poll for I2CSR[MIF] to be set.
172 * 15. I2CCR - 80h
173 */
mpc_i2c_fixup_A004447(struct mpc_i2c * i2c)174 static void mpc_i2c_fixup_A004447(struct mpc_i2c *i2c)
175 {
176 int ret;
177 u32 val;
178
179 writeccr(i2c, CCR_MEN | CCR_MSTA);
180 ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
181 if (ret) {
182 dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
183 return;
184 }
185
186 val = readb(i2c->base + MPC_I2C_SR);
187
188 if (val & CSR_MAL) {
189 writeccr(i2c, 0x00);
190 writeccr(i2c, CCR_MSTA | CCR_RSVD);
191 writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSVD);
192 ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
193 if (ret) {
194 dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
195 return;
196 }
197 val = readb(i2c->base + MPC_I2C_DR);
198 ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
199 if (ret) {
200 dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
201 return;
202 }
203 writeccr(i2c, CCR_MEN | CCR_RSVD);
204 } else {
205 val = readb(i2c->base + MPC_I2C_DR);
206 ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
207 if (ret) {
208 dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
209 return;
210 }
211 writeccr(i2c, CCR_MEN);
212 }
213 }
214
215 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
216 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
217 {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
218 {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
219 {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
220 {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
221 {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
222 {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
223 {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
224 {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
225 {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
226 {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
227 {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
228 {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
229 {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
230 {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
231 {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
232 {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
233 {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
234 {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
235 };
236
mpc_i2c_get_fdr_52xx(struct device_node * node,u32 clock,u32 * real_clk)237 static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
238 u32 *real_clk)
239 {
240 struct fwnode_handle *fwnode = of_fwnode_handle(node);
241 const struct mpc_i2c_divider *div = NULL;
242 unsigned int pvr = mfspr(SPRN_PVR);
243 u32 divider;
244 int i;
245
246 if (clock == MPC_I2C_CLOCK_LEGACY) {
247 /* see below - default fdr = 0x3f -> div = 2048 */
248 *real_clk = mpc5xxx_fwnode_get_bus_frequency(fwnode) / 2048;
249 return -EINVAL;
250 }
251
252 /* Determine divider value */
253 divider = mpc5xxx_fwnode_get_bus_frequency(fwnode) / clock;
254
255 /*
256 * We want to choose an FDR/DFSR that generates an I2C bus speed that
257 * is equal to or lower than the requested speed.
258 */
259 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
260 div = &mpc_i2c_dividers_52xx[i];
261 /* Old MPC5200 rev A CPUs do not support the high bits */
262 if (div->fdr & 0xc0 && pvr == 0x80822011)
263 continue;
264 if (div->divider >= divider)
265 break;
266 }
267
268 *real_clk = mpc5xxx_fwnode_get_bus_frequency(fwnode) / div->divider;
269 return (int)div->fdr;
270 }
271
mpc_i2c_setup_52xx(struct device_node * node,struct mpc_i2c * i2c,u32 clock)272 static void mpc_i2c_setup_52xx(struct device_node *node,
273 struct mpc_i2c *i2c,
274 u32 clock)
275 {
276 int ret, fdr;
277
278 if (clock == MPC_I2C_CLOCK_PRESERVE) {
279 dev_dbg(i2c->dev, "using fdr %d\n",
280 readb(i2c->base + MPC_I2C_FDR));
281 return;
282 }
283
284 ret = mpc_i2c_get_fdr_52xx(node, clock, &i2c->real_clk);
285 fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
286
287 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
288
289 if (ret >= 0)
290 dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
291 fdr);
292 }
293 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
mpc_i2c_setup_52xx(struct device_node * node,struct mpc_i2c * i2c,u32 clock)294 static void mpc_i2c_setup_52xx(struct device_node *node,
295 struct mpc_i2c *i2c,
296 u32 clock)
297 {
298 }
299 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
300
301 #ifdef CONFIG_PPC_MPC512x
mpc_i2c_setup_512x(struct device_node * node,struct mpc_i2c * i2c,u32 clock)302 static void mpc_i2c_setup_512x(struct device_node *node,
303 struct mpc_i2c *i2c,
304 u32 clock)
305 {
306 void __iomem *ctrl;
307 u32 idx;
308
309 /* Enable I2C interrupts for mpc5121 */
310 struct device_node *node_ctrl __free(device_node) =
311 of_find_compatible_node(NULL, NULL, "fsl,mpc5121-i2c-ctrl");
312 if (node_ctrl) {
313 ctrl = of_iomap(node_ctrl, 0);
314 if (ctrl) {
315 u64 addr;
316 /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
317 of_property_read_reg(node, 0, &addr, NULL);
318 idx = (addr & 0xff) / 0x20;
319 setbits32(ctrl, 1 << (24 + idx * 2));
320 iounmap(ctrl);
321 }
322 }
323
324 /* The clock setup for the 52xx works also fine for the 512x */
325 mpc_i2c_setup_52xx(node, i2c, clock);
326 }
327 #else /* CONFIG_PPC_MPC512x */
mpc_i2c_setup_512x(struct device_node * node,struct mpc_i2c * i2c,u32 clock)328 static void mpc_i2c_setup_512x(struct device_node *node,
329 struct mpc_i2c *i2c,
330 u32 clock)
331 {
332 }
333 #endif /* CONFIG_PPC_MPC512x */
334
335 #ifdef CONFIG_FSL_SOC
336 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
337 {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
338 {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
339 {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
340 {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
341 {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
342 {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
343 {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
344 {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
345 {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
346 {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
347 {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
348 {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
349 {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
350 {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
351 {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
352 {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
353 {49152, 0x011e}, {61440, 0x011f}
354 };
355
mpc_i2c_get_sec_cfg_8xxx(void)356 static u32 mpc_i2c_get_sec_cfg_8xxx(void)
357 {
358 u32 __iomem *reg;
359 u32 val = 0;
360
361 struct device_node *node __free(device_node) =
362 of_find_node_by_name(NULL, "global-utilities");
363 if (node) {
364 const u32 *prop = of_get_property(node, "reg", NULL);
365 if (prop) {
366 /*
367 * Map and check POR Device Status Register 2
368 * (PORDEVSR2) at 0xE0014. Note than while MPC8533
369 * and MPC8544 indicate SEC frequency ratio
370 * configuration as bit 26 in PORDEVSR2, other MPC8xxx
371 * parts may store it differently or may not have it
372 * at all.
373 */
374 reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
375 if (!reg)
376 printk(KERN_ERR
377 "Error: couldn't map PORDEVSR2\n");
378 else
379 val = in_be32(reg) & 0x00000020; /* sec-cfg */
380 iounmap(reg);
381 }
382 }
383
384 return val;
385 }
386
mpc_i2c_get_prescaler_8xxx(void)387 static u32 mpc_i2c_get_prescaler_8xxx(void)
388 {
389 /*
390 * According to the AN2919 all MPC824x have prescaler 1, while MPC83xx
391 * may have prescaler 1, 2, or 3, depending on the power-on
392 * configuration.
393 */
394 u32 prescaler = 1;
395
396 /* mpc85xx */
397 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)
398 || pvr_version_is(PVR_VER_E500MC)
399 || pvr_version_is(PVR_VER_E5500)
400 || pvr_version_is(PVR_VER_E6500)) {
401 unsigned int svr = mfspr(SPRN_SVR);
402
403 if ((SVR_SOC_VER(svr) == SVR_8540)
404 || (SVR_SOC_VER(svr) == SVR_8541)
405 || (SVR_SOC_VER(svr) == SVR_8560)
406 || (SVR_SOC_VER(svr) == SVR_8555)
407 || (SVR_SOC_VER(svr) == SVR_8610))
408 /* the above 85xx SoCs have prescaler 1 */
409 prescaler = 1;
410 else if ((SVR_SOC_VER(svr) == SVR_8533)
411 || (SVR_SOC_VER(svr) == SVR_8544))
412 /* the above 85xx SoCs have prescaler 3 or 2 */
413 prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
414 else
415 /* all the other 85xx have prescaler 2 */
416 prescaler = 2;
417 }
418
419 return prescaler;
420 }
421
mpc_i2c_get_fdr_8xxx(struct device_node * node,u32 clock,u32 * real_clk)422 static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
423 u32 *real_clk)
424 {
425 const struct mpc_i2c_divider *div = NULL;
426 u32 prescaler = mpc_i2c_get_prescaler_8xxx();
427 u32 divider;
428 int i;
429
430 if (clock == MPC_I2C_CLOCK_LEGACY) {
431 /* see below - default fdr = 0x1031 -> div = 16 * 3072 */
432 *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
433 return -EINVAL;
434 }
435
436 divider = fsl_get_sys_freq() / clock / prescaler;
437
438 pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
439 fsl_get_sys_freq(), clock, divider);
440
441 /*
442 * We want to choose an FDR/DFSR that generates an I2C bus speed that
443 * is equal to or lower than the requested speed.
444 */
445 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
446 div = &mpc_i2c_dividers_8xxx[i];
447 if (div->divider >= divider)
448 break;
449 }
450
451 *real_clk = fsl_get_sys_freq() / prescaler / div->divider;
452 return (int)div->fdr;
453 }
454
mpc_i2c_setup_8xxx(struct device_node * node,struct mpc_i2c * i2c,u32 clock)455 static void mpc_i2c_setup_8xxx(struct device_node *node,
456 struct mpc_i2c *i2c,
457 u32 clock)
458 {
459 int ret, fdr;
460
461 if (clock == MPC_I2C_CLOCK_PRESERVE) {
462 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
463 readb(i2c->base + MPC_I2C_DFSRR),
464 readb(i2c->base + MPC_I2C_FDR));
465 return;
466 }
467
468 ret = mpc_i2c_get_fdr_8xxx(node, clock, &i2c->real_clk);
469 fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
470
471 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
472 writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
473
474 if (ret >= 0)
475 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
476 i2c->real_clk, fdr >> 8, fdr & 0xff);
477 }
478
479 #else /* !CONFIG_FSL_SOC */
mpc_i2c_setup_8xxx(struct device_node * node,struct mpc_i2c * i2c,u32 clock)480 static void mpc_i2c_setup_8xxx(struct device_node *node,
481 struct mpc_i2c *i2c,
482 u32 clock)
483 {
484 }
485 #endif /* CONFIG_FSL_SOC */
486
mpc_i2c_finish(struct mpc_i2c * i2c,int rc)487 static void mpc_i2c_finish(struct mpc_i2c *i2c, int rc)
488 {
489 i2c->rc = rc;
490 i2c->block = 0;
491 i2c->cntl_bits = CCR_MEN;
492 writeccr(i2c, i2c->cntl_bits);
493 wake_up(&i2c->waitq);
494 }
495
mpc_i2c_do_action(struct mpc_i2c * i2c)496 static void mpc_i2c_do_action(struct mpc_i2c *i2c)
497 {
498 struct i2c_msg *msg = NULL;
499 int dir = 0;
500 int recv_len = 0;
501 u8 byte;
502
503 dev_dbg(i2c->dev, "action = %s\n", action_str[i2c->action]);
504
505 i2c->cntl_bits &= ~(CCR_RSTA | CCR_MTX | CCR_TXAK);
506
507 if (i2c->action != MPC_I2C_ACTION_STOP) {
508 msg = &i2c->msgs[i2c->curr_msg];
509 if (msg->flags & I2C_M_RD)
510 dir = 1;
511 if (msg->flags & I2C_M_RECV_LEN)
512 recv_len = 1;
513 }
514
515 switch (i2c->action) {
516 case MPC_I2C_ACTION_RESTART:
517 i2c->cntl_bits |= CCR_RSTA;
518 fallthrough;
519
520 case MPC_I2C_ACTION_START:
521 i2c->cntl_bits |= CCR_MSTA | CCR_MTX;
522 writeccr(i2c, i2c->cntl_bits);
523 writeb((msg->addr << 1) | dir, i2c->base + MPC_I2C_DR);
524 i2c->expect_rxack = 1;
525 i2c->action = dir ? MPC_I2C_ACTION_READ_BEGIN : MPC_I2C_ACTION_WRITE;
526 break;
527
528 case MPC_I2C_ACTION_READ_BEGIN:
529 if (msg->len) {
530 if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN))
531 i2c->cntl_bits |= CCR_TXAK;
532
533 writeccr(i2c, i2c->cntl_bits);
534 /* Dummy read */
535 readb(i2c->base + MPC_I2C_DR);
536 }
537 i2c->action = MPC_I2C_ACTION_READ_BYTE;
538 break;
539
540 case MPC_I2C_ACTION_READ_BYTE:
541 if (i2c->byte_posn || !recv_len) {
542 /* Generate Tx ACK on next to last byte */
543 if (i2c->byte_posn == msg->len - 2)
544 i2c->cntl_bits |= CCR_TXAK;
545 /* Do not generate stop on last byte */
546 if (i2c->byte_posn == msg->len - 1)
547 i2c->cntl_bits |= CCR_MTX;
548
549 writeccr(i2c, i2c->cntl_bits);
550 }
551
552 byte = readb(i2c->base + MPC_I2C_DR);
553
554 if (i2c->byte_posn == 0 && recv_len) {
555 if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX) {
556 mpc_i2c_finish(i2c, -EPROTO);
557 return;
558 }
559 msg->len += byte;
560 /*
561 * For block reads, generate Tx ACK here if data length
562 * is 1 byte (total length is 2 bytes).
563 */
564 if (msg->len == 2) {
565 i2c->cntl_bits |= CCR_TXAK;
566 writeccr(i2c, i2c->cntl_bits);
567 }
568 }
569
570 dev_dbg(i2c->dev, "%s %02x\n", action_str[i2c->action], byte);
571 msg->buf[i2c->byte_posn++] = byte;
572 break;
573
574 case MPC_I2C_ACTION_WRITE:
575 dev_dbg(i2c->dev, "%s %02x\n", action_str[i2c->action],
576 msg->buf[i2c->byte_posn]);
577 writeb(msg->buf[i2c->byte_posn++], i2c->base + MPC_I2C_DR);
578 i2c->expect_rxack = 1;
579 break;
580
581 case MPC_I2C_ACTION_STOP:
582 mpc_i2c_finish(i2c, 0);
583 break;
584
585 default:
586 WARN(1, "Unexpected action %d\n", i2c->action);
587 break;
588 }
589
590 if (msg && msg->len == i2c->byte_posn) {
591 i2c->curr_msg++;
592 i2c->byte_posn = 0;
593
594 if (i2c->curr_msg == i2c->num_msgs) {
595 i2c->action = MPC_I2C_ACTION_STOP;
596 /*
597 * We don't get another interrupt on read so
598 * finish the transfer now
599 */
600 if (dir)
601 mpc_i2c_finish(i2c, 0);
602 } else {
603 i2c->action = MPC_I2C_ACTION_RESTART;
604 }
605 }
606 }
607
mpc_i2c_do_intr(struct mpc_i2c * i2c,u8 status)608 static void mpc_i2c_do_intr(struct mpc_i2c *i2c, u8 status)
609 {
610 spin_lock(&i2c->lock);
611
612 if (!(status & CSR_MCF)) {
613 dev_dbg(i2c->dev, "unfinished\n");
614 mpc_i2c_finish(i2c, -EIO);
615 goto out;
616 }
617
618 if (status & CSR_MAL) {
619 dev_dbg(i2c->dev, "arbitration lost\n");
620 mpc_i2c_finish(i2c, -EAGAIN);
621 goto out;
622 }
623
624 if (i2c->expect_rxack && (status & CSR_RXAK)) {
625 dev_dbg(i2c->dev, "no Rx ACK\n");
626 mpc_i2c_finish(i2c, -ENXIO);
627 goto out;
628 }
629 i2c->expect_rxack = 0;
630
631 mpc_i2c_do_action(i2c);
632
633 out:
634 spin_unlock(&i2c->lock);
635 }
636
mpc_i2c_isr(int irq,void * dev_id)637 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
638 {
639 struct mpc_i2c *i2c = dev_id;
640 u8 status;
641
642 status = readb(i2c->base + MPC_I2C_SR);
643 if (status & CSR_MIF) {
644 /* Wait up to 100us for transfer to properly complete */
645 readb_poll_timeout_atomic(i2c->base + MPC_I2C_SR, status, status & CSR_MCF, 0, 100);
646 writeb(0, i2c->base + MPC_I2C_SR);
647 mpc_i2c_do_intr(i2c, status);
648 return IRQ_HANDLED;
649 }
650 return IRQ_NONE;
651 }
652
mpc_i2c_wait_for_completion(struct mpc_i2c * i2c)653 static int mpc_i2c_wait_for_completion(struct mpc_i2c *i2c)
654 {
655 long time_left;
656
657 time_left = wait_event_timeout(i2c->waitq, !i2c->block, i2c->adap.timeout);
658 if (!time_left)
659 return -ETIMEDOUT;
660 if (time_left < 0)
661 return time_left;
662
663 return 0;
664 }
665
mpc_i2c_execute_msg(struct mpc_i2c * i2c)666 static int mpc_i2c_execute_msg(struct mpc_i2c *i2c)
667 {
668 unsigned long orig_jiffies;
669 unsigned long flags;
670 int ret;
671
672 spin_lock_irqsave(&i2c->lock, flags);
673
674 i2c->curr_msg = 0;
675 i2c->rc = 0;
676 i2c->byte_posn = 0;
677 i2c->block = 1;
678 i2c->action = MPC_I2C_ACTION_START;
679
680 i2c->cntl_bits = CCR_MEN | CCR_MIEN;
681 writeb(0, i2c->base + MPC_I2C_SR);
682 writeccr(i2c, i2c->cntl_bits);
683
684 mpc_i2c_do_action(i2c);
685
686 spin_unlock_irqrestore(&i2c->lock, flags);
687
688 ret = mpc_i2c_wait_for_completion(i2c);
689 if (ret)
690 i2c->rc = ret;
691
692 if (i2c->rc == -EIO || i2c->rc == -EAGAIN || i2c->rc == -ETIMEDOUT)
693 i2c_recover_bus(&i2c->adap);
694
695 orig_jiffies = jiffies;
696 /* Wait until STOP is seen, allow up to 1 s */
697 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
698 if (time_after(jiffies, orig_jiffies + HZ)) {
699 u8 status = readb(i2c->base + MPC_I2C_SR);
700
701 dev_dbg(i2c->dev, "timeout\n");
702 if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
703 writeb(status & ~CSR_MAL,
704 i2c->base + MPC_I2C_SR);
705 i2c_recover_bus(&i2c->adap);
706 }
707 return -EIO;
708 }
709 cond_resched();
710 }
711
712 return i2c->rc;
713 }
714
mpc_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)715 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
716 {
717 int rc, ret = num;
718 struct mpc_i2c *i2c = i2c_get_adapdata(adap);
719 int i;
720
721 dev_dbg(i2c->dev, "num = %d\n", num);
722 for (i = 0; i < num; i++)
723 dev_dbg(i2c->dev, " addr = %02x, flags = %02x, len = %d, %*ph\n",
724 msgs[i].addr, msgs[i].flags, msgs[i].len,
725 msgs[i].flags & I2C_M_RD ? 0 : msgs[i].len,
726 msgs[i].buf);
727
728 WARN_ON(i2c->msgs != NULL);
729 i2c->msgs = msgs;
730 i2c->num_msgs = num;
731
732 rc = mpc_i2c_execute_msg(i2c);
733 if (rc < 0)
734 ret = rc;
735
736 i2c->num_msgs = 0;
737 i2c->msgs = NULL;
738
739 return ret;
740 }
741
mpc_functionality(struct i2c_adapter * adap)742 static u32 mpc_functionality(struct i2c_adapter *adap)
743 {
744 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
745 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL;
746 }
747
fsl_i2c_bus_recovery(struct i2c_adapter * adap)748 static int fsl_i2c_bus_recovery(struct i2c_adapter *adap)
749 {
750 struct mpc_i2c *i2c = i2c_get_adapdata(adap);
751
752 if (i2c->has_errata_A004447)
753 mpc_i2c_fixup_A004447(i2c);
754 else
755 mpc_i2c_fixup(i2c);
756
757 return 0;
758 }
759
760 static const struct i2c_algorithm mpc_algo = {
761 .xfer = mpc_xfer,
762 .functionality = mpc_functionality,
763 };
764
765 static struct i2c_adapter mpc_ops = {
766 .owner = THIS_MODULE,
767 .algo = &mpc_algo,
768 };
769
770 static struct i2c_bus_recovery_info fsl_i2c_recovery_info = {
771 .recover_bus = fsl_i2c_bus_recovery,
772 };
773
fsl_i2c_probe(struct platform_device * op)774 static int fsl_i2c_probe(struct platform_device *op)
775 {
776 const struct mpc_i2c_data *data;
777 struct mpc_i2c *i2c;
778 struct clk *clk;
779 int result;
780 u32 clock;
781
782 i2c = devm_kzalloc(&op->dev, sizeof(*i2c), GFP_KERNEL);
783 if (!i2c)
784 return -ENOMEM;
785
786 i2c->dev = &op->dev; /* for debug and error output */
787
788 init_waitqueue_head(&i2c->waitq);
789 spin_lock_init(&i2c->lock);
790
791 i2c->base = devm_platform_ioremap_resource(op, 0);
792 if (IS_ERR(i2c->base))
793 return PTR_ERR(i2c->base);
794
795 i2c->irq = platform_get_irq(op, 0);
796 if (i2c->irq < 0)
797 return i2c->irq;
798
799 result = devm_request_irq(&op->dev, i2c->irq, mpc_i2c_isr,
800 IRQF_SHARED, "i2c-mpc", i2c);
801 if (result < 0) {
802 dev_err(i2c->dev, "failed to attach interrupt\n");
803 return result;
804 }
805
806 /*
807 * enable clock for the I2C peripheral (non fatal),
808 * keep a reference upon successful allocation
809 */
810 clk = devm_clk_get_optional_enabled(&op->dev, NULL);
811 if (IS_ERR(clk)) {
812 dev_err(&op->dev, "failed to enable clock\n");
813 return PTR_ERR(clk);
814 }
815
816 if (of_property_read_bool(op->dev.of_node, "fsl,preserve-clocking")) {
817 clock = MPC_I2C_CLOCK_PRESERVE;
818 } else {
819 result = of_property_read_u32(op->dev.of_node,
820 "clock-frequency", &clock);
821 if (result)
822 clock = MPC_I2C_CLOCK_LEGACY;
823 }
824
825 data = device_get_match_data(&op->dev);
826 if (data) {
827 data->setup(op->dev.of_node, i2c, clock);
828 } else {
829 /* Backwards compatibility */
830 if (of_property_read_bool(op->dev.of_node, "dfsrr"))
831 mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock);
832 }
833
834 /* Sadly, we have to support two deprecated bindings here */
835 result = of_property_read_u32(op->dev.of_node,
836 "i2c-transfer-timeout-us",
837 &mpc_ops.timeout);
838 if (result == -EINVAL)
839 result = of_property_read_u32(op->dev.of_node,
840 "i2c-scl-clk-low-timeout-us",
841 &mpc_ops.timeout);
842 if (result == -EINVAL)
843 result = of_property_read_u32(op->dev.of_node,
844 "fsl,timeout", &mpc_ops.timeout);
845
846 if (!result) {
847 mpc_ops.timeout *= HZ / 1000000;
848 if (mpc_ops.timeout < 5)
849 mpc_ops.timeout = 5;
850 } else {
851 mpc_ops.timeout = HZ;
852 }
853
854 dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
855
856 if (of_property_read_bool(op->dev.of_node, "fsl,i2c-erratum-a004447"))
857 i2c->has_errata_A004447 = true;
858
859 i2c->adap = mpc_ops;
860 scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
861 "MPC adapter (%s)", of_node_full_name(op->dev.of_node));
862 i2c->adap.dev.parent = &op->dev;
863 i2c->adap.nr = op->id;
864 i2c->adap.dev.of_node = of_node_get(op->dev.of_node);
865 i2c->adap.bus_recovery_info = &fsl_i2c_recovery_info;
866 platform_set_drvdata(op, i2c);
867 i2c_set_adapdata(&i2c->adap, i2c);
868
869 result = i2c_add_numbered_adapter(&i2c->adap);
870 if (result)
871 return result;
872
873 return 0;
874 };
875
fsl_i2c_remove(struct platform_device * op)876 static void fsl_i2c_remove(struct platform_device *op)
877 {
878 struct mpc_i2c *i2c = platform_get_drvdata(op);
879
880 i2c_del_adapter(&i2c->adap);
881 };
882
mpc_i2c_suspend(struct device * dev)883 static int __maybe_unused mpc_i2c_suspend(struct device *dev)
884 {
885 struct mpc_i2c *i2c = dev_get_drvdata(dev);
886
887 i2c->fdr = readb(i2c->base + MPC_I2C_FDR);
888 i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR);
889
890 return 0;
891 }
892
mpc_i2c_resume(struct device * dev)893 static int __maybe_unused mpc_i2c_resume(struct device *dev)
894 {
895 struct mpc_i2c *i2c = dev_get_drvdata(dev);
896
897 writeb(i2c->fdr, i2c->base + MPC_I2C_FDR);
898 writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR);
899
900 return 0;
901 }
902 static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume);
903
904 static const struct mpc_i2c_data mpc_i2c_data_512x = {
905 .setup = mpc_i2c_setup_512x,
906 };
907
908 static const struct mpc_i2c_data mpc_i2c_data_52xx = {
909 .setup = mpc_i2c_setup_52xx,
910 };
911
912 static const struct mpc_i2c_data mpc_i2c_data_8313 = {
913 .setup = mpc_i2c_setup_8xxx,
914 };
915
916 static const struct mpc_i2c_data mpc_i2c_data_8543 = {
917 .setup = mpc_i2c_setup_8xxx,
918 };
919
920 static const struct mpc_i2c_data mpc_i2c_data_8544 = {
921 .setup = mpc_i2c_setup_8xxx,
922 };
923
924 static const struct of_device_id mpc_i2c_of_match[] = {
925 {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
926 {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
927 {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
928 {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
929 {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
930 {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
931 {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
932 /* Backward compatibility */
933 {.compatible = "fsl-i2c", },
934 {},
935 };
936 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
937
938 /* Structure for a device driver */
939 static struct platform_driver mpc_i2c_driver = {
940 .probe = fsl_i2c_probe,
941 .remove = fsl_i2c_remove,
942 .driver = {
943 .name = "mpc-i2c",
944 .of_match_table = mpc_i2c_of_match,
945 .pm = &mpc_i2c_pm_ops,
946 },
947 };
948
949 module_platform_driver(mpc_i2c_driver);
950
951 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
952 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
953 "MPC824x/83xx/85xx/86xx/512x/52xx processors");
954 MODULE_LICENSE("GPL");
955