1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Mellanox BlueField I2C bus driver 4 * 5 * Copyright (C) 2020 Mellanox Technologies, Ltd. 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/bitfield.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/interrupt.h> 13 #include <linux/i2c.h> 14 #include <linux/io.h> 15 #include <linux/iopoll.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/string.h> 22 23 /* Defines what functionality is present. */ 24 #define MLXBF_I2C_FUNC_SMBUS_BLOCK \ 25 (I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL) 26 27 #define MLXBF_I2C_FUNC_SMBUS_DEFAULT \ 28 (I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | \ 29 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_I2C_BLOCK | \ 30 I2C_FUNC_SMBUS_PROC_CALL) 31 32 #define MLXBF_I2C_FUNC_ALL \ 33 (MLXBF_I2C_FUNC_SMBUS_DEFAULT | MLXBF_I2C_FUNC_SMBUS_BLOCK | \ 34 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SLAVE) 35 36 /* Shared resources info in BlueField platforms. */ 37 38 #define MLXBF_I2C_COALESCE_TYU_ADDR 0x02801300 39 #define MLXBF_I2C_COALESCE_TYU_SIZE 0x010 40 41 #define MLXBF_I2C_GPIO_TYU_ADDR 0x02802000 42 #define MLXBF_I2C_GPIO_TYU_SIZE 0x100 43 44 #define MLXBF_I2C_COREPLL_TYU_ADDR 0x02800358 45 #define MLXBF_I2C_COREPLL_TYU_SIZE 0x008 46 47 #define MLXBF_I2C_COREPLL_YU_ADDR 0x02800c30 48 #define MLXBF_I2C_COREPLL_YU_SIZE 0x00c 49 50 #define MLXBF_I2C_COREPLL_RSH_YU_ADDR 0x13409824 51 #define MLXBF_I2C_COREPLL_RSH_YU_SIZE 0x00c 52 53 #define MLXBF_I2C_SHARED_RES_MAX 3 54 55 /* 56 * Note that the following SMBus, CAUSE, GPIO and PLL register addresses 57 * refer to their respective offsets relative to the corresponding 58 * memory-mapped region whose addresses are specified in either the DT or 59 * the ACPI tables or above. 60 */ 61 62 /* 63 * SMBus Master core clock frequency. Timing configurations are 64 * strongly dependent on the core clock frequency of the SMBus 65 * Master. Default value is set to 400MHz. 66 */ 67 #define MLXBF_I2C_TYU_PLL_OUT_FREQ (400 * 1000 * 1000) 68 /* Reference clock for Bluefield - 156 MHz. */ 69 #define MLXBF_I2C_PLL_IN_FREQ 156250000ULL 70 71 /* Constant used to determine the PLL frequency. */ 72 #define MLNXBF_I2C_COREPLL_CONST 16384ULL 73 74 #define MLXBF_I2C_FREQUENCY_1GHZ 1000000000ULL 75 76 /* PLL registers. */ 77 #define MLXBF_I2C_CORE_PLL_REG1 0x4 78 #define MLXBF_I2C_CORE_PLL_REG2 0x8 79 80 /* OR cause register. */ 81 #define MLXBF_I2C_CAUSE_OR_EVTEN0 0x14 82 #define MLXBF_I2C_CAUSE_OR_CLEAR 0x18 83 84 /* Arbiter Cause Register. */ 85 #define MLXBF_I2C_CAUSE_ARBITER 0x1c 86 87 /* 88 * Cause Status flags. Note that those bits might be considered 89 * as interrupt enabled bits. 90 */ 91 92 /* Transaction ended with STOP. */ 93 #define MLXBF_I2C_CAUSE_TRANSACTION_ENDED BIT(0) 94 /* Master arbitration lost. */ 95 #define MLXBF_I2C_CAUSE_M_ARBITRATION_LOST BIT(1) 96 /* Unexpected start detected. */ 97 #define MLXBF_I2C_CAUSE_UNEXPECTED_START BIT(2) 98 /* Unexpected stop detected. */ 99 #define MLXBF_I2C_CAUSE_UNEXPECTED_STOP BIT(3) 100 /* Wait for transfer continuation. */ 101 #define MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA BIT(4) 102 /* Failed to generate STOP. */ 103 #define MLXBF_I2C_CAUSE_PUT_STOP_FAILED BIT(5) 104 /* Failed to generate START. */ 105 #define MLXBF_I2C_CAUSE_PUT_START_FAILED BIT(6) 106 /* Clock toggle completed. */ 107 #define MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE BIT(7) 108 /* Transfer timeout occurred. */ 109 #define MLXBF_I2C_CAUSE_M_FW_TIMEOUT BIT(8) 110 /* Master busy bit reset. */ 111 #define MLXBF_I2C_CAUSE_M_GW_BUSY_FALL BIT(9) 112 113 #define MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK GENMASK(9, 0) 114 115 #define MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR \ 116 (MLXBF_I2C_CAUSE_M_ARBITRATION_LOST | \ 117 MLXBF_I2C_CAUSE_UNEXPECTED_START | \ 118 MLXBF_I2C_CAUSE_UNEXPECTED_STOP | \ 119 MLXBF_I2C_CAUSE_PUT_STOP_FAILED | \ 120 MLXBF_I2C_CAUSE_PUT_START_FAILED | \ 121 MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE | \ 122 MLXBF_I2C_CAUSE_M_FW_TIMEOUT) 123 124 /* 125 * Slave cause status flags. Note that those bits might be considered 126 * as interrupt enabled bits. 127 */ 128 129 /* Write transaction received successfully. */ 130 #define MLXBF_I2C_CAUSE_WRITE_SUCCESS BIT(0) 131 /* Read transaction received, waiting for response. */ 132 #define MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE BIT(13) 133 /* Slave busy bit reset. */ 134 #define MLXBF_I2C_CAUSE_S_GW_BUSY_FALL BIT(18) 135 136 /* Cause coalesce registers. */ 137 #define MLXBF_I2C_CAUSE_COALESCE_0 0x00 138 139 #define MLXBF_I2C_CAUSE_TYU_SLAVE_BIT 3 140 #define MLXBF_I2C_CAUSE_YU_SLAVE_BIT 1 141 142 /* Functional enable register. */ 143 #define MLXBF_I2C_GPIO_0_FUNC_EN_0 0x28 144 /* Force OE enable register. */ 145 #define MLXBF_I2C_GPIO_0_FORCE_OE_EN 0x30 146 /* 147 * Note that Smbus GWs are on GPIOs 30:25. Two pins are used to control 148 * SDA/SCL lines: 149 * 150 * SMBUS GW0 -> bits[26:25] 151 * SMBUS GW1 -> bits[28:27] 152 * SMBUS GW2 -> bits[30:29] 153 */ 154 #define MLXBF_I2C_GPIO_SMBUS_GW_PINS(num) (25 + ((num) << 1)) 155 156 /* Note that gw_id can be 0,1 or 2. */ 157 #define MLXBF_I2C_GPIO_SMBUS_GW_MASK(num) \ 158 (0xffffffff & (~(0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num)))) 159 160 #define MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(num, val) \ 161 ((val) & MLXBF_I2C_GPIO_SMBUS_GW_MASK(num)) 162 163 #define MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(num, val) \ 164 ((val) | (0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num))) 165 166 /* 167 * Defines SMBus operating frequency and core clock frequency. 168 * According to ADB files, default values are compliant to 100KHz SMBus 169 * @ 400MHz core clock. The driver should be able to calculate core 170 * frequency based on PLL parameters. 171 */ 172 #define MLXBF_I2C_COREPLL_FREQ MLXBF_I2C_TYU_PLL_OUT_FREQ 173 174 /* Core PLL TYU configuration. */ 175 #define MLXBF_I2C_COREPLL_CORE_F_TYU_MASK GENMASK(15, 3) 176 #define MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK GENMASK(19, 16) 177 #define MLXBF_I2C_COREPLL_CORE_R_TYU_MASK GENMASK(25, 20) 178 179 /* Core PLL YU configuration. */ 180 #define MLXBF_I2C_COREPLL_CORE_F_YU_MASK GENMASK(25, 0) 181 #define MLXBF_I2C_COREPLL_CORE_OD_YU_MASK GENMASK(3, 0) 182 #define MLXBF_I2C_COREPLL_CORE_R_YU_MASK GENMASK(31, 26) 183 184 /* SMBus timing parameters. */ 185 #define MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH 0x00 186 #define MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE 0x04 187 #define MLXBF_I2C_SMBUS_TIMER_THOLD 0x08 188 #define MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP 0x0c 189 #define MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA 0x10 190 #define MLXBF_I2C_SMBUS_THIGH_MAX_TBUF 0x14 191 #define MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT 0x18 192 193 #define MLXBF_I2C_SHIFT_0 0 194 #define MLXBF_I2C_SHIFT_8 8 195 #define MLXBF_I2C_SHIFT_16 16 196 #define MLXBF_I2C_SHIFT_24 24 197 198 #define MLXBF_I2C_MASK_8 GENMASK(7, 0) 199 #define MLXBF_I2C_MASK_16 GENMASK(15, 0) 200 201 #define MLXBF_I2C_MST_ADDR_OFFSET 0x200 202 203 /* SMBus Master GW. */ 204 #define MLXBF_I2C_SMBUS_MASTER_GW 0x0 205 /* Number of bytes received and sent. */ 206 #define MLXBF_I2C_YU_SMBUS_RS_BYTES 0x100 207 #define MLXBF_I2C_RSH_YU_SMBUS_RS_BYTES 0x10c 208 /* Packet error check (PEC) value. */ 209 #define MLXBF_I2C_SMBUS_MASTER_PEC 0x104 210 /* Status bits (ACK/NACK/FW Timeout). */ 211 #define MLXBF_I2C_SMBUS_MASTER_STATUS 0x108 212 /* SMbus Master Finite State Machine. */ 213 #define MLXBF_I2C_YU_SMBUS_MASTER_FSM 0x110 214 #define MLXBF_I2C_RSH_YU_SMBUS_MASTER_FSM 0x100 215 216 /* SMBus master GW control bits offset in MLXBF_I2C_SMBUS_MASTER_GW[31:3]. */ 217 #define MLXBF_I2C_MASTER_LOCK_BIT BIT(31) /* Lock bit. */ 218 #define MLXBF_I2C_MASTER_BUSY_BIT BIT(30) /* Busy bit. */ 219 #define MLXBF_I2C_MASTER_START_BIT BIT(29) /* Control start. */ 220 #define MLXBF_I2C_MASTER_CTL_WRITE_BIT BIT(28) /* Control write phase. */ 221 #define MLXBF_I2C_MASTER_CTL_READ_BIT BIT(19) /* Control read phase. */ 222 #define MLXBF_I2C_MASTER_STOP_BIT BIT(3) /* Control stop. */ 223 224 #define MLXBF_I2C_MASTER_ENABLE \ 225 (MLXBF_I2C_MASTER_LOCK_BIT | MLXBF_I2C_MASTER_BUSY_BIT | \ 226 MLXBF_I2C_MASTER_START_BIT | MLXBF_I2C_MASTER_STOP_BIT) 227 228 #define MLXBF_I2C_MASTER_ENABLE_WRITE \ 229 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_WRITE_BIT) 230 231 #define MLXBF_I2C_MASTER_ENABLE_READ \ 232 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_READ_BIT) 233 234 #define MLXBF_I2C_MASTER_WRITE_SHIFT 21 /* Control write bytes */ 235 #define MLXBF_I2C_MASTER_SEND_PEC_SHIFT 20 /* Send PEC byte when set to 1 */ 236 #define MLXBF_I2C_MASTER_PARSE_EXP_SHIFT 11 /* Control parse expected bytes */ 237 #define MLXBF_I2C_MASTER_SLV_ADDR_SHIFT 12 /* Slave address */ 238 #define MLXBF_I2C_MASTER_READ_SHIFT 4 /* Control read bytes */ 239 240 /* SMBus master GW Data descriptor. */ 241 #define MLXBF_I2C_MASTER_DATA_DESC_ADDR 0x80 242 #define MLXBF_I2C_MASTER_DATA_DESC_SIZE 0x80 /* Size in bytes. */ 243 244 /* Maximum bytes to read/write per SMBus transaction. */ 245 #define MLXBF_I2C_MASTER_DATA_R_LENGTH MLXBF_I2C_MASTER_DATA_DESC_SIZE 246 #define MLXBF_I2C_MASTER_DATA_W_LENGTH (MLXBF_I2C_MASTER_DATA_DESC_SIZE - 1) 247 248 /* All bytes were transmitted. */ 249 #define MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE BIT(0) 250 /* NACK received. */ 251 #define MLXBF_I2C_SMBUS_STATUS_NACK_RCV BIT(1) 252 /* Slave's byte count >128 bytes. */ 253 #define MLXBF_I2C_SMBUS_STATUS_READ_ERR BIT(2) 254 /* Timeout occurred. */ 255 #define MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT BIT(3) 256 257 #define MLXBF_I2C_SMBUS_MASTER_STATUS_MASK GENMASK(3, 0) 258 259 #define MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR \ 260 (MLXBF_I2C_SMBUS_STATUS_NACK_RCV | \ 261 MLXBF_I2C_SMBUS_STATUS_READ_ERR | \ 262 MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT) 263 264 #define MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK BIT(31) 265 #define MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK BIT(15) 266 267 #define MLXBF_I2C_SLV_ADDR_OFFSET 0x400 268 269 /* SMBus slave GW. */ 270 #define MLXBF_I2C_SMBUS_SLAVE_GW 0x0 271 /* Number of bytes received and sent from/to master. */ 272 #define MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES 0x100 273 /* Packet error check (PEC) value. */ 274 #define MLXBF_I2C_SMBUS_SLAVE_PEC 0x104 275 /* SMBus slave Finite State Machine (FSM). */ 276 #define MLXBF_I2C_SMBUS_SLAVE_FSM 0x110 277 /* 278 * Should be set when all raised causes handled, and cleared by HW on 279 * every new cause. 280 */ 281 #define MLXBF_I2C_SMBUS_SLAVE_READY 0x12c 282 283 /* SMBus slave GW control bits offset in MLXBF_I2C_SMBUS_SLAVE_GW[31:19]. */ 284 #define MLXBF_I2C_SLAVE_BUSY_BIT BIT(30) /* Busy bit. */ 285 #define MLXBF_I2C_SLAVE_WRITE_BIT BIT(29) /* Control write enable. */ 286 287 #define MLXBF_I2C_SLAVE_ENABLE \ 288 (MLXBF_I2C_SLAVE_BUSY_BIT | MLXBF_I2C_SLAVE_WRITE_BIT) 289 290 #define MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT 22 /* Number of bytes to write. */ 291 #define MLXBF_I2C_SLAVE_SEND_PEC_SHIFT 21 /* Send PEC byte shift. */ 292 293 /* SMBus slave GW Data descriptor. */ 294 #define MLXBF_I2C_SLAVE_DATA_DESC_ADDR 0x80 295 #define MLXBF_I2C_SLAVE_DATA_DESC_SIZE 0x80 /* Size in bytes. */ 296 297 /* SMbus slave configuration registers. */ 298 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG 0x114 299 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT 16 300 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT BIT(7) 301 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK GENMASK(6, 0) 302 303 /* 304 * Timeout is given in microsends. Note also that timeout handling is not 305 * exact. 306 */ 307 #define MLXBF_I2C_SMBUS_TIMEOUT (300 * 1000) /* 300ms */ 308 #define MLXBF_I2C_SMBUS_LOCK_POLL_TIMEOUT (300 * 1000) /* 300ms */ 309 310 /* Polling frequency in microseconds. */ 311 #define MLXBF_I2C_POLL_FREQ_IN_USEC 200 312 313 #define MLXBF_I2C_SMBUS_OP_CNT_1 1 314 #define MLXBF_I2C_SMBUS_OP_CNT_2 2 315 #define MLXBF_I2C_SMBUS_OP_CNT_3 3 316 #define MLXBF_I2C_SMBUS_MAX_OP_CNT MLXBF_I2C_SMBUS_OP_CNT_3 317 318 /* Helper macro to define an I2C resource parameters. */ 319 #define MLXBF_I2C_RES_PARAMS(addr, size, str) \ 320 { \ 321 .start = (addr), \ 322 .end = (addr) + (size) - 1, \ 323 .name = (str) \ 324 } 325 326 enum { 327 MLXBF_I2C_TIMING_100KHZ = 100000, 328 MLXBF_I2C_TIMING_400KHZ = 400000, 329 MLXBF_I2C_TIMING_1000KHZ = 1000000, 330 }; 331 332 enum { 333 MLXBF_I2C_F_READ = BIT(0), 334 MLXBF_I2C_F_WRITE = BIT(1), 335 MLXBF_I2C_F_NORESTART = BIT(3), 336 MLXBF_I2C_F_SMBUS_OPERATION = BIT(4), 337 MLXBF_I2C_F_SMBUS_BLOCK = BIT(5), 338 MLXBF_I2C_F_SMBUS_PEC = BIT(6), 339 MLXBF_I2C_F_SMBUS_PROCESS_CALL = BIT(7), 340 }; 341 342 /* Mellanox BlueField chip type. */ 343 enum mlxbf_i2c_chip_type { 344 MLXBF_I2C_CHIP_TYPE_1, /* Mellanox BlueField-1 chip. */ 345 MLXBF_I2C_CHIP_TYPE_2, /* Mellanox BlueField-2 chip. */ 346 MLXBF_I2C_CHIP_TYPE_3 /* Mellanox BlueField-3 chip. */ 347 }; 348 349 /* List of chip resources that are being accessed by the driver. */ 350 enum { 351 MLXBF_I2C_SMBUS_RES, 352 MLXBF_I2C_MST_CAUSE_RES, 353 MLXBF_I2C_SLV_CAUSE_RES, 354 MLXBF_I2C_COALESCE_RES, 355 MLXBF_I2C_SMBUS_TIMER_RES, 356 MLXBF_I2C_SMBUS_MST_RES, 357 MLXBF_I2C_SMBUS_SLV_RES, 358 MLXBF_I2C_COREPLL_RES, 359 MLXBF_I2C_GPIO_RES, 360 MLXBF_I2C_END_RES 361 }; 362 363 /* Encapsulates timing parameters. */ 364 struct mlxbf_i2c_timings { 365 u16 scl_high; /* Clock high period. */ 366 u16 scl_low; /* Clock low period. */ 367 u8 sda_rise; /* Data rise time. */ 368 u8 sda_fall; /* Data fall time. */ 369 u8 scl_rise; /* Clock rise time. */ 370 u8 scl_fall; /* Clock fall time. */ 371 u16 hold_start; /* Hold time after (REPEATED) START. */ 372 u16 hold_data; /* Data hold time. */ 373 u16 setup_start; /* REPEATED START condition setup time. */ 374 u16 setup_stop; /* STOP condition setup time. */ 375 u16 setup_data; /* Data setup time. */ 376 u16 pad; /* Padding. */ 377 u16 buf; /* Bus free time between STOP and START. */ 378 u16 thigh_max; /* Thigh max. */ 379 u32 timeout; /* Detect clock low timeout. */ 380 }; 381 382 struct mlxbf_i2c_smbus_operation { 383 u32 flags; 384 u32 length; /* Buffer length in bytes. */ 385 u8 *buffer; 386 }; 387 388 struct mlxbf_i2c_smbus_request { 389 u8 slave; 390 u8 operation_cnt; 391 struct mlxbf_i2c_smbus_operation operation[MLXBF_I2C_SMBUS_MAX_OP_CNT]; 392 }; 393 394 struct mlxbf_i2c_resource { 395 void __iomem *io; 396 struct resource *params; 397 struct mutex *lock; /* Mutex to protect mlxbf_i2c_resource. */ 398 u8 type; 399 }; 400 401 struct mlxbf_i2c_chip_info { 402 enum mlxbf_i2c_chip_type type; 403 /* Chip shared resources that are being used by the I2C controller. */ 404 struct mlxbf_i2c_resource *shared_res[MLXBF_I2C_SHARED_RES_MAX]; 405 406 /* Callback to calculate the core PLL frequency. */ 407 u64 (*calculate_freq)(struct mlxbf_i2c_resource *corepll_res); 408 409 /* Registers' address offset */ 410 u32 smbus_master_rs_bytes_off; 411 u32 smbus_master_fsm_off; 412 }; 413 414 struct mlxbf_i2c_priv { 415 const struct mlxbf_i2c_chip_info *chip; 416 struct i2c_adapter adap; 417 struct mlxbf_i2c_resource *smbus; 418 struct mlxbf_i2c_resource *timer; 419 struct mlxbf_i2c_resource *mst; 420 struct mlxbf_i2c_resource *slv; 421 struct mlxbf_i2c_resource *mst_cause; 422 struct mlxbf_i2c_resource *slv_cause; 423 struct mlxbf_i2c_resource *coalesce; 424 u64 frequency; /* Core frequency in Hz. */ 425 int bus; /* Physical bus identifier. */ 426 int irq; 427 struct i2c_client *slave[MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT]; 428 u32 resource_version; 429 }; 430 431 /* Core PLL frequency. */ 432 static u64 mlxbf_i2c_corepll_frequency; 433 434 static struct resource mlxbf_i2c_coalesce_tyu_params = 435 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COALESCE_TYU_ADDR, 436 MLXBF_I2C_COALESCE_TYU_SIZE, 437 "COALESCE_MEM"); 438 static struct resource mlxbf_i2c_corepll_tyu_params = 439 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_TYU_ADDR, 440 MLXBF_I2C_COREPLL_TYU_SIZE, 441 "COREPLL_MEM"); 442 static struct resource mlxbf_i2c_corepll_yu_params = 443 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_YU_ADDR, 444 MLXBF_I2C_COREPLL_YU_SIZE, 445 "COREPLL_MEM"); 446 static struct resource mlxbf_i2c_corepll_rsh_yu_params = 447 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_RSH_YU_ADDR, 448 MLXBF_I2C_COREPLL_RSH_YU_SIZE, 449 "COREPLL_MEM"); 450 static struct resource mlxbf_i2c_gpio_tyu_params = 451 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_GPIO_TYU_ADDR, 452 MLXBF_I2C_GPIO_TYU_SIZE, 453 "GPIO_MEM"); 454 455 static struct mutex mlxbf_i2c_coalesce_lock; 456 static struct mutex mlxbf_i2c_corepll_lock; 457 static struct mutex mlxbf_i2c_gpio_lock; 458 459 static struct mlxbf_i2c_resource mlxbf_i2c_coalesce_res[] = { 460 [MLXBF_I2C_CHIP_TYPE_1] = { 461 .params = &mlxbf_i2c_coalesce_tyu_params, 462 .lock = &mlxbf_i2c_coalesce_lock, 463 .type = MLXBF_I2C_COALESCE_RES 464 }, 465 {} 466 }; 467 468 static struct mlxbf_i2c_resource mlxbf_i2c_corepll_res[] = { 469 [MLXBF_I2C_CHIP_TYPE_1] = { 470 .params = &mlxbf_i2c_corepll_tyu_params, 471 .lock = &mlxbf_i2c_corepll_lock, 472 .type = MLXBF_I2C_COREPLL_RES 473 }, 474 [MLXBF_I2C_CHIP_TYPE_2] = { 475 .params = &mlxbf_i2c_corepll_yu_params, 476 .lock = &mlxbf_i2c_corepll_lock, 477 .type = MLXBF_I2C_COREPLL_RES, 478 }, 479 [MLXBF_I2C_CHIP_TYPE_3] = { 480 .params = &mlxbf_i2c_corepll_rsh_yu_params, 481 .lock = &mlxbf_i2c_corepll_lock, 482 .type = MLXBF_I2C_COREPLL_RES, 483 } 484 }; 485 486 static struct mlxbf_i2c_resource mlxbf_i2c_gpio_res[] = { 487 [MLXBF_I2C_CHIP_TYPE_1] = { 488 .params = &mlxbf_i2c_gpio_tyu_params, 489 .lock = &mlxbf_i2c_gpio_lock, 490 .type = MLXBF_I2C_GPIO_RES 491 }, 492 {} 493 }; 494 495 static u8 mlxbf_i2c_bus_count; 496 497 static struct mutex mlxbf_i2c_bus_lock; 498 499 static bool mlxbf_i2c_smbus_transaction_success(u32 master_status, 500 u32 cause_status) 501 { 502 /* 503 * When transaction ended with STOP, all bytes were transmitted, 504 * and no NACK received, then the transaction ended successfully. 505 * On the other hand, when the GW is configured with the stop bit 506 * de-asserted then the SMBus expects the following GW configuration 507 * for transfer continuation. 508 */ 509 if ((cause_status & MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA) || 510 ((cause_status & MLXBF_I2C_CAUSE_TRANSACTION_ENDED) && 511 (master_status & MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE) && 512 !(master_status & MLXBF_I2C_SMBUS_STATUS_NACK_RCV))) 513 return true; 514 515 return false; 516 } 517 518 /* 519 * Poll SMBus master status and return transaction status, 520 * i.e. whether succeeded or failed. I2C and SMBus fault codes 521 * are returned as negative numbers from most calls, with zero 522 * or some positive number indicating a non-fault return. 523 */ 524 static int mlxbf_i2c_smbus_check_status(struct mlxbf_i2c_priv *priv) 525 { 526 u32 master_status_bits; 527 u32 cause_status_bits; 528 u32 bits; 529 530 /* 531 * GW busy bit is raised by the driver and cleared by the HW 532 * when the transaction is completed. The busy bit is a good 533 * indicator of transaction status. So poll the busy bit, and 534 * then read the cause and master status bits to determine if 535 * errors occurred during the transaction. 536 */ 537 readl_poll_timeout_atomic(priv->mst->io + MLXBF_I2C_SMBUS_MASTER_GW, 538 bits, !(bits & MLXBF_I2C_MASTER_BUSY_BIT), 539 MLXBF_I2C_POLL_FREQ_IN_USEC, MLXBF_I2C_SMBUS_TIMEOUT); 540 541 /* Read cause status bits. */ 542 cause_status_bits = readl(priv->mst_cause->io + 543 MLXBF_I2C_CAUSE_ARBITER); 544 cause_status_bits &= MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK; 545 546 /* 547 * Parse both Cause and Master GW bits, then return transaction status. 548 */ 549 550 master_status_bits = readl(priv->mst->io + 551 MLXBF_I2C_SMBUS_MASTER_STATUS); 552 master_status_bits &= MLXBF_I2C_SMBUS_MASTER_STATUS_MASK; 553 554 if (mlxbf_i2c_smbus_transaction_success(master_status_bits, 555 cause_status_bits)) 556 return 0; 557 558 /* 559 * In case of timeout on GW busy, the ISR will clear busy bit but 560 * transaction ended bits cause will not be set so the transaction 561 * fails. Then, we must check Master GW status bits. 562 */ 563 if ((master_status_bits & MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR) && 564 (cause_status_bits & (MLXBF_I2C_CAUSE_TRANSACTION_ENDED | 565 MLXBF_I2C_CAUSE_M_GW_BUSY_FALL))) 566 return -EIO; 567 568 if (cause_status_bits & MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR) 569 return -EAGAIN; 570 571 return -ETIMEDOUT; 572 } 573 574 static void mlxbf_i2c_smbus_write_data(struct mlxbf_i2c_priv *priv, 575 const u8 *data, u8 length, u32 addr, 576 bool is_master) 577 { 578 u8 offset, aligned_length; 579 u32 data32; 580 581 aligned_length = round_up(length, 4); 582 583 /* 584 * Copy data bytes from 4-byte aligned source buffer. 585 * Data copied to the Master GW Data Descriptor MUST be shifted 586 * left so the data starts at the MSB of the descriptor registers 587 * as required by the underlying hardware. Enable byte swapping 588 * when writing data bytes to the 32 * 32-bit HW Data registers 589 * a.k.a Master GW Data Descriptor. 590 */ 591 for (offset = 0; offset < aligned_length; offset += sizeof(u32)) { 592 data32 = *((u32 *)(data + offset)); 593 if (is_master) 594 iowrite32be(data32, priv->mst->io + addr + offset); 595 else 596 iowrite32be(data32, priv->slv->io + addr + offset); 597 } 598 } 599 600 static void mlxbf_i2c_smbus_read_data(struct mlxbf_i2c_priv *priv, 601 u8 *data, u8 length, u32 addr, 602 bool is_master) 603 { 604 u32 data32, mask; 605 u8 byte, offset; 606 607 mask = sizeof(u32) - 1; 608 609 /* 610 * Data bytes in the Master GW Data Descriptor are shifted left 611 * so the data starts at the MSB of the descriptor registers as 612 * set by the underlying hardware. Enable byte swapping while 613 * reading data bytes from the 32 * 32-bit HW Data registers 614 * a.k.a Master GW Data Descriptor. 615 */ 616 617 for (offset = 0; offset < (length & ~mask); offset += sizeof(u32)) { 618 if (is_master) 619 data32 = ioread32be(priv->mst->io + addr + offset); 620 else 621 data32 = ioread32be(priv->slv->io + addr + offset); 622 *((u32 *)(data + offset)) = data32; 623 } 624 625 if (!(length & mask)) 626 return; 627 628 if (is_master) 629 data32 = ioread32be(priv->mst->io + addr + offset); 630 else 631 data32 = ioread32be(priv->slv->io + addr + offset); 632 633 for (byte = 0; byte < (length & mask); byte++) { 634 data[offset + byte] = data32 & GENMASK(7, 0); 635 data32 = ror32(data32, MLXBF_I2C_SHIFT_8); 636 } 637 } 638 639 static int mlxbf_i2c_smbus_enable(struct mlxbf_i2c_priv *priv, u8 slave, 640 u8 len, u8 block_en, u8 pec_en, bool read) 641 { 642 u32 command; 643 644 /* Set Master GW control word. */ 645 if (read) { 646 command = MLXBF_I2C_MASTER_ENABLE_READ; 647 command |= rol32(len, MLXBF_I2C_MASTER_READ_SHIFT); 648 } else { 649 command = MLXBF_I2C_MASTER_ENABLE_WRITE; 650 command |= rol32(len, MLXBF_I2C_MASTER_WRITE_SHIFT); 651 } 652 command |= rol32(slave, MLXBF_I2C_MASTER_SLV_ADDR_SHIFT); 653 command |= rol32(block_en, MLXBF_I2C_MASTER_PARSE_EXP_SHIFT); 654 command |= rol32(pec_en, MLXBF_I2C_MASTER_SEND_PEC_SHIFT); 655 656 /* Clear status bits. */ 657 writel(0x0, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_STATUS); 658 /* Set the cause data. */ 659 writel(~0x0, priv->mst_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR); 660 /* Zero PEC byte. */ 661 writel(0x0, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_PEC); 662 /* Zero byte count. */ 663 writel(0x0, priv->mst->io + priv->chip->smbus_master_rs_bytes_off); 664 665 /* GW activation. */ 666 writel(command, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_GW); 667 668 /* 669 * Poll master status and check status bits. An ACK is sent when 670 * completing writing data to the bus (Master 'byte_count_done' bit 671 * is set to 1). 672 */ 673 return mlxbf_i2c_smbus_check_status(priv); 674 } 675 676 static int 677 mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv, 678 struct mlxbf_i2c_smbus_request *request) 679 { 680 u8 data_desc[MLXBF_I2C_MASTER_DATA_DESC_SIZE] = { 0 }; 681 u8 op_idx, data_idx, data_len, write_len, read_len; 682 struct mlxbf_i2c_smbus_operation *operation; 683 u8 read_en, write_en, block_en, pec_en; 684 u8 slave, flags, addr; 685 u8 *read_buf; 686 u32 bits; 687 int ret; 688 689 if (request->operation_cnt > MLXBF_I2C_SMBUS_MAX_OP_CNT) 690 return -EINVAL; 691 692 read_buf = NULL; 693 data_idx = 0; 694 read_en = 0; 695 write_en = 0; 696 write_len = 0; 697 read_len = 0; 698 block_en = 0; 699 pec_en = 0; 700 slave = request->slave & GENMASK(6, 0); 701 addr = slave << 1; 702 703 /* 704 * Try to acquire the smbus gw lock before any reads of the GW register since 705 * a read sets the lock. 706 */ 707 ret = readl_poll_timeout_atomic(priv->mst->io + MLXBF_I2C_SMBUS_MASTER_GW, 708 bits, !(bits & MLXBF_I2C_MASTER_LOCK_BIT), 709 MLXBF_I2C_POLL_FREQ_IN_USEC, 710 MLXBF_I2C_SMBUS_LOCK_POLL_TIMEOUT); 711 if (WARN_ON(ret)) 712 return -EBUSY; 713 714 /* 715 * SW must make sure that the SMBus Master GW is idle before starting 716 * a transaction. Accordingly, this call polls the Master FSM stop bit; 717 * it returns -ETIMEDOUT when the bit is asserted, 0 if not. 718 */ 719 ret = readl_poll_timeout_atomic(priv->mst->io + priv->chip->smbus_master_fsm_off, 720 bits, !(bits & MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK), 721 MLXBF_I2C_POLL_FREQ_IN_USEC, MLXBF_I2C_SMBUS_TIMEOUT); 722 if (WARN_ON(ret)) { 723 ret = -EBUSY; 724 goto out_unlock; 725 } 726 727 /* Set first byte. */ 728 data_desc[data_idx++] = addr; 729 730 for (op_idx = 0; op_idx < request->operation_cnt; op_idx++) { 731 operation = &request->operation[op_idx]; 732 flags = operation->flags; 733 734 /* 735 * Note that read and write operations might be handled by a 736 * single command. If the MLXBF_I2C_F_SMBUS_OPERATION is set 737 * then write command byte and set the optional SMBus specific 738 * bits such as block_en and pec_en. These bits MUST be 739 * submitted by the first operation only. 740 */ 741 if (op_idx == 0 && flags & MLXBF_I2C_F_SMBUS_OPERATION) { 742 block_en = flags & MLXBF_I2C_F_SMBUS_BLOCK; 743 pec_en = flags & MLXBF_I2C_F_SMBUS_PEC; 744 } 745 746 if (flags & MLXBF_I2C_F_WRITE) { 747 write_en = 1; 748 write_len += operation->length; 749 if (data_idx + operation->length > 750 MLXBF_I2C_MASTER_DATA_DESC_SIZE) { 751 ret = -ENOBUFS; 752 goto out_unlock; 753 } 754 memcpy(data_desc + data_idx, 755 operation->buffer, operation->length); 756 data_idx += operation->length; 757 } 758 /* 759 * We assume that read operations are performed only once per 760 * SMBus transaction. *TBD* protect this statement so it won't 761 * be executed twice? or return an error if we try to read more 762 * than once? 763 */ 764 if (flags & MLXBF_I2C_F_READ) { 765 read_en = 1; 766 /* Subtract 1 as required by HW. */ 767 read_len = operation->length - 1; 768 read_buf = operation->buffer; 769 } 770 } 771 772 /* Set Master GW data descriptor. */ 773 data_len = write_len + 1; /* Add one byte of the slave address. */ 774 /* 775 * Note that data_len cannot be 0. Indeed, the slave address byte 776 * must be written to the data registers. 777 */ 778 mlxbf_i2c_smbus_write_data(priv, (const u8 *)data_desc, data_len, 779 MLXBF_I2C_MASTER_DATA_DESC_ADDR, true); 780 781 if (write_en) { 782 ret = mlxbf_i2c_smbus_enable(priv, slave, write_len, block_en, 783 pec_en, 0); 784 if (ret) 785 goto out_unlock; 786 } 787 788 if (read_en) { 789 /* Write slave address to Master GW data descriptor. */ 790 mlxbf_i2c_smbus_write_data(priv, (const u8 *)&addr, 1, 791 MLXBF_I2C_MASTER_DATA_DESC_ADDR, true); 792 ret = mlxbf_i2c_smbus_enable(priv, slave, read_len, block_en, 793 pec_en, 1); 794 if (!ret) { 795 /* Get Master GW data descriptor. */ 796 mlxbf_i2c_smbus_read_data(priv, data_desc, read_len + 1, 797 MLXBF_I2C_MASTER_DATA_DESC_ADDR, true); 798 799 /* Get data from Master GW data descriptor. */ 800 memcpy(read_buf, data_desc, read_len + 1); 801 } 802 803 /* 804 * After a read operation the SMBus FSM ps (present state) 805 * needs to be 'manually' reset. This should be removed in 806 * next tag integration. 807 */ 808 writel(MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK, 809 priv->mst->io + priv->chip->smbus_master_fsm_off); 810 } 811 812 out_unlock: 813 /* Clear the gw to clear the lock */ 814 writel(0, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_GW); 815 816 return ret; 817 } 818 819 /* I2C SMBus protocols. */ 820 821 static void 822 mlxbf_i2c_smbus_quick_command(struct mlxbf_i2c_smbus_request *request, 823 u8 read) 824 { 825 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1; 826 827 request->operation[0].length = 0; 828 request->operation[0].flags = MLXBF_I2C_F_WRITE; 829 request->operation[0].flags |= read ? MLXBF_I2C_F_READ : 0; 830 } 831 832 static void mlxbf_i2c_smbus_byte_func(struct mlxbf_i2c_smbus_request *request, 833 u8 *data, bool read, bool pec_check) 834 { 835 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1; 836 837 request->operation[0].length = 1; 838 request->operation[0].length += pec_check; 839 840 request->operation[0].flags = MLXBF_I2C_F_SMBUS_OPERATION; 841 request->operation[0].flags |= read ? 842 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 843 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 844 845 request->operation[0].buffer = data; 846 } 847 848 static void 849 mlxbf_i2c_smbus_data_byte_func(struct mlxbf_i2c_smbus_request *request, 850 u8 *command, u8 *data, bool read, bool pec_check) 851 { 852 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 853 854 request->operation[0].length = 1; 855 request->operation[0].flags = 856 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 857 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 858 request->operation[0].buffer = command; 859 860 request->operation[1].length = 1; 861 request->operation[1].length += pec_check; 862 request->operation[1].flags = read ? 863 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 864 request->operation[1].buffer = data; 865 } 866 867 static void 868 mlxbf_i2c_smbus_data_word_func(struct mlxbf_i2c_smbus_request *request, 869 u8 *command, u8 *data, bool read, bool pec_check) 870 { 871 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 872 873 request->operation[0].length = 1; 874 request->operation[0].flags = 875 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 876 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 877 request->operation[0].buffer = command; 878 879 request->operation[1].length = 2; 880 request->operation[1].length += pec_check; 881 request->operation[1].flags = read ? 882 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 883 request->operation[1].buffer = data; 884 } 885 886 static void 887 mlxbf_i2c_smbus_i2c_block_func(struct mlxbf_i2c_smbus_request *request, 888 u8 *command, u8 *data, u8 *data_len, bool read, 889 bool pec_check) 890 { 891 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 892 893 request->operation[0].length = 1; 894 request->operation[0].flags = 895 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 896 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 897 request->operation[0].buffer = command; 898 899 /* 900 * As specified in the standard, the max number of bytes to read/write 901 * per block operation is 32 bytes. In Golan code, the controller can 902 * read up to 128 bytes and write up to 127 bytes. 903 */ 904 request->operation[1].length = 905 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 906 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 907 request->operation[1].flags = read ? 908 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 909 /* 910 * Skip the first data byte, which corresponds to the number of bytes 911 * to read/write. 912 */ 913 request->operation[1].buffer = data + 1; 914 915 *data_len = request->operation[1].length; 916 917 /* Set the number of byte to read. This will be used by userspace. */ 918 if (read) 919 data[0] = *data_len; 920 } 921 922 static void mlxbf_i2c_smbus_block_func(struct mlxbf_i2c_smbus_request *request, 923 u8 *command, u8 *data, u8 *data_len, 924 bool read, bool pec_check) 925 { 926 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 927 928 request->operation[0].length = 1; 929 request->operation[0].flags = 930 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 931 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 932 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 933 request->operation[0].buffer = command; 934 935 request->operation[1].length = 936 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 937 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 938 request->operation[1].flags = read ? 939 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 940 request->operation[1].buffer = data + 1; 941 942 *data_len = request->operation[1].length; 943 944 /* Set the number of bytes to read. This will be used by userspace. */ 945 if (read) 946 data[0] = *data_len; 947 } 948 949 static void 950 mlxbf_i2c_smbus_process_call_func(struct mlxbf_i2c_smbus_request *request, 951 u8 *command, u8 *data, bool pec_check) 952 { 953 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3; 954 955 request->operation[0].length = 1; 956 request->operation[0].flags = 957 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 958 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 959 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 960 request->operation[0].buffer = command; 961 962 request->operation[1].length = 2; 963 request->operation[1].flags = MLXBF_I2C_F_WRITE; 964 request->operation[1].buffer = data; 965 966 request->operation[2].length = 3; 967 request->operation[2].flags = MLXBF_I2C_F_READ; 968 request->operation[2].buffer = data; 969 } 970 971 static void 972 mlxbf_i2c_smbus_blk_process_call_func(struct mlxbf_i2c_smbus_request *request, 973 u8 *command, u8 *data, u8 *data_len, 974 bool pec_check) 975 { 976 u32 length; 977 978 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3; 979 980 request->operation[0].length = 1; 981 request->operation[0].flags = 982 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 983 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 984 request->operation[0].flags |= (pec_check) ? MLXBF_I2C_F_SMBUS_PEC : 0; 985 request->operation[0].buffer = command; 986 987 length = (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 988 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 989 990 request->operation[1].length = length - pec_check; 991 request->operation[1].flags = MLXBF_I2C_F_WRITE; 992 request->operation[1].buffer = data; 993 994 request->operation[2].length = length; 995 request->operation[2].flags = MLXBF_I2C_F_READ; 996 request->operation[2].buffer = data; 997 998 *data_len = length; /* including PEC byte. */ 999 } 1000 1001 /* Initialization functions. */ 1002 1003 static bool mlxbf_i2c_has_chip_type(struct mlxbf_i2c_priv *priv, u8 type) 1004 { 1005 return priv->chip->type == type; 1006 } 1007 1008 static struct mlxbf_i2c_resource * 1009 mlxbf_i2c_get_shared_resource(struct mlxbf_i2c_priv *priv, u8 type) 1010 { 1011 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1012 struct mlxbf_i2c_resource *res; 1013 u8 res_idx = 0; 1014 1015 for (res_idx = 0; res_idx < MLXBF_I2C_SHARED_RES_MAX; res_idx++) { 1016 res = chip->shared_res[res_idx]; 1017 if (res && res->type == type) 1018 return res; 1019 } 1020 1021 return NULL; 1022 } 1023 1024 static int mlxbf_i2c_init_resource(struct platform_device *pdev, 1025 struct mlxbf_i2c_resource **res, 1026 u8 type) 1027 { 1028 struct mlxbf_i2c_resource *tmp_res; 1029 struct device *dev = &pdev->dev; 1030 1031 if (!res || *res || type >= MLXBF_I2C_END_RES) 1032 return -EINVAL; 1033 1034 tmp_res = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), 1035 GFP_KERNEL); 1036 if (!tmp_res) 1037 return -ENOMEM; 1038 1039 tmp_res->io = devm_platform_get_and_ioremap_resource(pdev, type, &tmp_res->params); 1040 if (IS_ERR(tmp_res->io)) { 1041 devm_kfree(dev, tmp_res); 1042 return PTR_ERR(tmp_res->io); 1043 } 1044 1045 tmp_res->type = type; 1046 1047 *res = tmp_res; 1048 1049 return 0; 1050 } 1051 1052 static u32 mlxbf_i2c_get_ticks(struct mlxbf_i2c_priv *priv, u64 nanoseconds, 1053 bool minimum) 1054 { 1055 u64 frequency; 1056 u32 ticks; 1057 1058 /* 1059 * Compute ticks as follow: 1060 * 1061 * Ticks 1062 * Time = --------- x 10^9 => Ticks = Time x Frequency x 10^-9 1063 * Frequency 1064 */ 1065 frequency = priv->frequency; 1066 ticks = (nanoseconds * frequency) / MLXBF_I2C_FREQUENCY_1GHZ; 1067 /* 1068 * The number of ticks is rounded down and if minimum is equal to 1 1069 * then add one tick. 1070 */ 1071 if (minimum) 1072 ticks++; 1073 1074 return ticks; 1075 } 1076 1077 static u32 mlxbf_i2c_set_timer(struct mlxbf_i2c_priv *priv, u64 nsec, bool opt, 1078 u32 mask, u8 shift) 1079 { 1080 u32 val = (mlxbf_i2c_get_ticks(priv, nsec, opt) & mask) << shift; 1081 1082 return val; 1083 } 1084 1085 static void mlxbf_i2c_set_timings(struct mlxbf_i2c_priv *priv, 1086 const struct mlxbf_i2c_timings *timings) 1087 { 1088 u32 timer; 1089 1090 timer = mlxbf_i2c_set_timer(priv, timings->scl_high, 1091 false, MLXBF_I2C_MASK_16, 1092 MLXBF_I2C_SHIFT_0); 1093 timer |= mlxbf_i2c_set_timer(priv, timings->scl_low, 1094 false, MLXBF_I2C_MASK_16, 1095 MLXBF_I2C_SHIFT_16); 1096 writel(timer, priv->timer->io + 1097 MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH); 1098 1099 timer = mlxbf_i2c_set_timer(priv, timings->sda_rise, false, 1100 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_0); 1101 timer |= mlxbf_i2c_set_timer(priv, timings->sda_fall, false, 1102 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_8); 1103 timer |= mlxbf_i2c_set_timer(priv, timings->scl_rise, false, 1104 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_16); 1105 timer |= mlxbf_i2c_set_timer(priv, timings->scl_fall, false, 1106 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_24); 1107 writel(timer, priv->timer->io + 1108 MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE); 1109 1110 timer = mlxbf_i2c_set_timer(priv, timings->hold_start, true, 1111 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1112 timer |= mlxbf_i2c_set_timer(priv, timings->hold_data, true, 1113 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1114 writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_TIMER_THOLD); 1115 1116 timer = mlxbf_i2c_set_timer(priv, timings->setup_start, true, 1117 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1118 timer |= mlxbf_i2c_set_timer(priv, timings->setup_stop, true, 1119 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1120 writel(timer, priv->timer->io + 1121 MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP); 1122 1123 timer = mlxbf_i2c_set_timer(priv, timings->setup_data, true, 1124 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1125 writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA); 1126 1127 timer = mlxbf_i2c_set_timer(priv, timings->buf, false, 1128 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1129 timer |= mlxbf_i2c_set_timer(priv, timings->thigh_max, false, 1130 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1131 writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_THIGH_MAX_TBUF); 1132 1133 timer = timings->timeout; 1134 writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT); 1135 } 1136 1137 enum mlxbf_i2c_timings_config { 1138 MLXBF_I2C_TIMING_CONFIG_100KHZ, 1139 MLXBF_I2C_TIMING_CONFIG_400KHZ, 1140 MLXBF_I2C_TIMING_CONFIG_1000KHZ, 1141 }; 1142 1143 /* 1144 * Note that the mlxbf_i2c_timings->timeout value is not related to the 1145 * bus frequency, it is impacted by the time it takes the driver to 1146 * complete data transmission before transaction abort. 1147 */ 1148 static const struct mlxbf_i2c_timings mlxbf_i2c_timings[] = { 1149 [MLXBF_I2C_TIMING_CONFIG_100KHZ] = { 1150 .scl_high = 4810, 1151 .scl_low = 5000, 1152 .hold_start = 4000, 1153 .setup_start = 4800, 1154 .setup_stop = 4000, 1155 .setup_data = 250, 1156 .sda_rise = 50, 1157 .sda_fall = 50, 1158 .scl_rise = 50, 1159 .scl_fall = 50, 1160 .hold_data = 300, 1161 .buf = 20000, 1162 .thigh_max = 5000, 1163 .timeout = 106500 1164 }, 1165 [MLXBF_I2C_TIMING_CONFIG_400KHZ] = { 1166 .scl_high = 1011, 1167 .scl_low = 1300, 1168 .hold_start = 600, 1169 .setup_start = 700, 1170 .setup_stop = 600, 1171 .setup_data = 100, 1172 .sda_rise = 50, 1173 .sda_fall = 50, 1174 .scl_rise = 50, 1175 .scl_fall = 50, 1176 .hold_data = 300, 1177 .buf = 20000, 1178 .thigh_max = 5000, 1179 .timeout = 106500 1180 }, 1181 [MLXBF_I2C_TIMING_CONFIG_1000KHZ] = { 1182 .scl_high = 600, 1183 .scl_low = 1300, 1184 .hold_start = 600, 1185 .setup_start = 600, 1186 .setup_stop = 600, 1187 .setup_data = 100, 1188 .sda_rise = 50, 1189 .sda_fall = 50, 1190 .scl_rise = 50, 1191 .scl_fall = 50, 1192 .hold_data = 300, 1193 .buf = 20000, 1194 .thigh_max = 5000, 1195 .timeout = 106500 1196 } 1197 }; 1198 1199 static int mlxbf_i2c_init_timings(struct platform_device *pdev, 1200 struct mlxbf_i2c_priv *priv) 1201 { 1202 enum mlxbf_i2c_timings_config config_idx; 1203 struct device *dev = &pdev->dev; 1204 u32 config_khz; 1205 1206 int ret; 1207 1208 ret = device_property_read_u32(dev, "clock-frequency", &config_khz); 1209 if (ret < 0) 1210 config_khz = I2C_MAX_STANDARD_MODE_FREQ; 1211 1212 switch (config_khz) { 1213 default: 1214 /* Default settings is 100 KHz. */ 1215 pr_warn("Illegal value %d: defaulting to 100 KHz\n", 1216 config_khz); 1217 fallthrough; 1218 case I2C_MAX_STANDARD_MODE_FREQ: 1219 config_idx = MLXBF_I2C_TIMING_CONFIG_100KHZ; 1220 break; 1221 1222 case I2C_MAX_FAST_MODE_FREQ: 1223 config_idx = MLXBF_I2C_TIMING_CONFIG_400KHZ; 1224 break; 1225 1226 case I2C_MAX_FAST_MODE_PLUS_FREQ: 1227 config_idx = MLXBF_I2C_TIMING_CONFIG_1000KHZ; 1228 break; 1229 } 1230 1231 mlxbf_i2c_set_timings(priv, &mlxbf_i2c_timings[config_idx]); 1232 1233 return 0; 1234 } 1235 1236 static int mlxbf_i2c_get_gpio(struct platform_device *pdev, 1237 struct mlxbf_i2c_priv *priv) 1238 { 1239 struct mlxbf_i2c_resource *gpio_res; 1240 struct device *dev = &pdev->dev; 1241 struct resource *params; 1242 resource_size_t size; 1243 1244 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1245 if (!gpio_res) 1246 return -EPERM; 1247 1248 /* 1249 * The GPIO region in TYU space is shared among I2C busses. 1250 * This function MUST be serialized to avoid racing when 1251 * claiming the memory region and/or setting up the GPIO. 1252 */ 1253 lockdep_assert_held(gpio_res->lock); 1254 1255 /* Check whether the memory map exist. */ 1256 if (gpio_res->io) 1257 return 0; 1258 1259 params = gpio_res->params; 1260 size = resource_size(params); 1261 1262 if (!devm_request_mem_region(dev, params->start, size, params->name)) 1263 return -EFAULT; 1264 1265 gpio_res->io = devm_ioremap(dev, params->start, size); 1266 if (!gpio_res->io) { 1267 devm_release_mem_region(dev, params->start, size); 1268 return -ENOMEM; 1269 } 1270 1271 return 0; 1272 } 1273 1274 static int mlxbf_i2c_release_gpio(struct platform_device *pdev, 1275 struct mlxbf_i2c_priv *priv) 1276 { 1277 struct mlxbf_i2c_resource *gpio_res; 1278 struct device *dev = &pdev->dev; 1279 struct resource *params; 1280 1281 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1282 if (!gpio_res) 1283 return 0; 1284 1285 mutex_lock(gpio_res->lock); 1286 1287 if (gpio_res->io) { 1288 /* Release the GPIO resource. */ 1289 params = gpio_res->params; 1290 devm_iounmap(dev, gpio_res->io); 1291 devm_release_mem_region(dev, params->start, 1292 resource_size(params)); 1293 } 1294 1295 mutex_unlock(gpio_res->lock); 1296 1297 return 0; 1298 } 1299 1300 static int mlxbf_i2c_get_corepll(struct platform_device *pdev, 1301 struct mlxbf_i2c_priv *priv) 1302 { 1303 struct mlxbf_i2c_resource *corepll_res; 1304 struct device *dev = &pdev->dev; 1305 struct resource *params; 1306 resource_size_t size; 1307 1308 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1309 MLXBF_I2C_COREPLL_RES); 1310 if (!corepll_res) 1311 return -EPERM; 1312 1313 /* 1314 * The COREPLL region in TYU space is shared among I2C busses. 1315 * This function MUST be serialized to avoid racing when 1316 * claiming the memory region. 1317 */ 1318 lockdep_assert_held(corepll_res->lock); 1319 1320 /* Check whether the memory map exist. */ 1321 if (corepll_res->io) 1322 return 0; 1323 1324 params = corepll_res->params; 1325 size = resource_size(params); 1326 1327 if (!devm_request_mem_region(dev, params->start, size, params->name)) 1328 return -EFAULT; 1329 1330 corepll_res->io = devm_ioremap(dev, params->start, size); 1331 if (!corepll_res->io) { 1332 devm_release_mem_region(dev, params->start, size); 1333 return -ENOMEM; 1334 } 1335 1336 return 0; 1337 } 1338 1339 static int mlxbf_i2c_release_corepll(struct platform_device *pdev, 1340 struct mlxbf_i2c_priv *priv) 1341 { 1342 struct mlxbf_i2c_resource *corepll_res; 1343 struct device *dev = &pdev->dev; 1344 struct resource *params; 1345 1346 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1347 MLXBF_I2C_COREPLL_RES); 1348 1349 mutex_lock(corepll_res->lock); 1350 1351 if (corepll_res->io) { 1352 /* Release the CorePLL resource. */ 1353 params = corepll_res->params; 1354 devm_iounmap(dev, corepll_res->io); 1355 devm_release_mem_region(dev, params->start, 1356 resource_size(params)); 1357 } 1358 1359 mutex_unlock(corepll_res->lock); 1360 1361 return 0; 1362 } 1363 1364 static int mlxbf_i2c_init_master(struct platform_device *pdev, 1365 struct mlxbf_i2c_priv *priv) 1366 { 1367 struct mlxbf_i2c_resource *gpio_res; 1368 struct device *dev = &pdev->dev; 1369 u32 config_reg; 1370 int ret; 1371 1372 /* This configuration is only needed for BlueField 1. */ 1373 if (!mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) 1374 return 0; 1375 1376 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1377 if (!gpio_res) 1378 return -EPERM; 1379 1380 /* 1381 * The GPIO region in TYU space is shared among I2C busses. 1382 * This function MUST be serialized to avoid racing when 1383 * claiming the memory region and/or setting up the GPIO. 1384 */ 1385 1386 mutex_lock(gpio_res->lock); 1387 1388 ret = mlxbf_i2c_get_gpio(pdev, priv); 1389 if (ret < 0) { 1390 dev_err(dev, "Failed to get gpio resource"); 1391 mutex_unlock(gpio_res->lock); 1392 return ret; 1393 } 1394 1395 /* 1396 * TYU - Configuration for GPIO pins. Those pins must be asserted in 1397 * MLXBF_I2C_GPIO_0_FUNC_EN_0, i.e. GPIO 0 is controlled by HW, and must 1398 * be reset in MLXBF_I2C_GPIO_0_FORCE_OE_EN, i.e. GPIO_OE will be driven 1399 * instead of HW_OE. 1400 * For now, we do not reset the GPIO state when the driver is removed. 1401 * First, it is not necessary to disable the bus since we are using 1402 * the same busses. Then, some busses might be shared among Linux and 1403 * platform firmware; disabling the bus might compromise the system 1404 * functionality. 1405 */ 1406 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0); 1407 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(priv->bus, 1408 config_reg); 1409 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0); 1410 1411 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN); 1412 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(priv->bus, 1413 config_reg); 1414 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN); 1415 1416 mutex_unlock(gpio_res->lock); 1417 1418 return 0; 1419 } 1420 1421 static u64 mlxbf_i2c_calculate_freq_from_tyu(struct mlxbf_i2c_resource *corepll_res) 1422 { 1423 u64 core_frequency; 1424 u8 core_od, core_r; 1425 u32 corepll_val; 1426 u16 core_f; 1427 1428 corepll_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1); 1429 1430 /* Get Core PLL configuration bits. */ 1431 core_f = FIELD_GET(MLXBF_I2C_COREPLL_CORE_F_TYU_MASK, corepll_val); 1432 core_od = FIELD_GET(MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK, corepll_val); 1433 core_r = FIELD_GET(MLXBF_I2C_COREPLL_CORE_R_TYU_MASK, corepll_val); 1434 1435 /* 1436 * Compute PLL output frequency as follow: 1437 * 1438 * CORE_F + 1 1439 * PLL_OUT_FREQ = PLL_IN_FREQ * ---------------------------- 1440 * (CORE_R + 1) * (CORE_OD + 1) 1441 * 1442 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency 1443 * and PadFrequency, respectively. 1444 */ 1445 core_frequency = MLXBF_I2C_PLL_IN_FREQ * (++core_f); 1446 core_frequency /= (++core_r) * (++core_od); 1447 1448 return core_frequency; 1449 } 1450 1451 static u64 mlxbf_i2c_calculate_freq_from_yu(struct mlxbf_i2c_resource *corepll_res) 1452 { 1453 u32 corepll_reg1_val, corepll_reg2_val; 1454 u64 corepll_frequency; 1455 u8 core_od, core_r; 1456 u32 core_f; 1457 1458 corepll_reg1_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1); 1459 corepll_reg2_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG2); 1460 1461 /* Get Core PLL configuration bits */ 1462 core_f = FIELD_GET(MLXBF_I2C_COREPLL_CORE_F_YU_MASK, corepll_reg1_val); 1463 core_r = FIELD_GET(MLXBF_I2C_COREPLL_CORE_R_YU_MASK, corepll_reg1_val); 1464 core_od = FIELD_GET(MLXBF_I2C_COREPLL_CORE_OD_YU_MASK, corepll_reg2_val); 1465 1466 /* 1467 * Compute PLL output frequency as follow: 1468 * 1469 * CORE_F / 16384 1470 * PLL_OUT_FREQ = PLL_IN_FREQ * ---------------------------- 1471 * (CORE_R + 1) * (CORE_OD + 1) 1472 * 1473 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency 1474 * and PadFrequency, respectively. 1475 */ 1476 corepll_frequency = (MLXBF_I2C_PLL_IN_FREQ * core_f) / MLNXBF_I2C_COREPLL_CONST; 1477 corepll_frequency /= (++core_r) * (++core_od); 1478 1479 return corepll_frequency; 1480 } 1481 1482 static int mlxbf_i2c_calculate_corepll_freq(struct platform_device *pdev, 1483 struct mlxbf_i2c_priv *priv) 1484 { 1485 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1486 struct mlxbf_i2c_resource *corepll_res; 1487 struct device *dev = &pdev->dev; 1488 u64 *freq = &priv->frequency; 1489 int ret; 1490 1491 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1492 MLXBF_I2C_COREPLL_RES); 1493 if (!corepll_res) 1494 return -EPERM; 1495 1496 /* 1497 * First, check whether the TYU core Clock frequency is set. 1498 * The TYU core frequency is the same for all I2C busses; when 1499 * the first device gets probed the frequency is determined and 1500 * stored into a globally visible variable. So, first of all, 1501 * check whether the frequency is already set. Here, we assume 1502 * that the frequency is expected to be greater than 0. 1503 */ 1504 mutex_lock(corepll_res->lock); 1505 if (!mlxbf_i2c_corepll_frequency) { 1506 if (!chip->calculate_freq) { 1507 mutex_unlock(corepll_res->lock); 1508 return -EPERM; 1509 } 1510 1511 ret = mlxbf_i2c_get_corepll(pdev, priv); 1512 if (ret < 0) { 1513 dev_err(dev, "Failed to get corePLL resource"); 1514 mutex_unlock(corepll_res->lock); 1515 return ret; 1516 } 1517 1518 mlxbf_i2c_corepll_frequency = chip->calculate_freq(corepll_res); 1519 } 1520 mutex_unlock(corepll_res->lock); 1521 1522 *freq = mlxbf_i2c_corepll_frequency; 1523 1524 return 0; 1525 } 1526 1527 static int mlxbf_i2c_slave_enable(struct mlxbf_i2c_priv *priv, 1528 struct i2c_client *slave) 1529 { 1530 u8 reg, reg_cnt, byte, addr_tmp; 1531 u32 slave_reg, slave_reg_tmp; 1532 1533 if (!priv) 1534 return -EPERM; 1535 1536 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2; 1537 1538 /* 1539 * Read the slave registers. There are 4 * 32-bit slave registers. 1540 * Each slave register can hold up to 4 * 8-bit slave configuration: 1541 * 1) A 7-bit address 1542 * 2) And a status bit (1 if enabled, 0 if not). 1543 * Look for the next available slave register slot. 1544 */ 1545 for (reg = 0; reg < reg_cnt; reg++) { 1546 slave_reg = readl(priv->slv->io + 1547 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4); 1548 /* 1549 * Each register holds 4 slave addresses. So, we have to keep 1550 * the byte order consistent with the value read in order to 1551 * update the register correctly, if needed. 1552 */ 1553 slave_reg_tmp = slave_reg; 1554 for (byte = 0; byte < 4; byte++) { 1555 addr_tmp = slave_reg_tmp & GENMASK(7, 0); 1556 1557 /* 1558 * If an enable bit is not set in the 1559 * MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG register, then the 1560 * slave address slot associated with that bit is 1561 * free. So set the enable bit and write the 1562 * slave address bits. 1563 */ 1564 if (!(addr_tmp & MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT)) { 1565 slave_reg &= ~(MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK << (byte * 8)); 1566 slave_reg |= (slave->addr << (byte * 8)); 1567 slave_reg |= MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT << (byte * 8); 1568 writel(slave_reg, priv->slv->io + 1569 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + 1570 (reg * 0x4)); 1571 1572 /* 1573 * Set the slave at the corresponding index. 1574 */ 1575 priv->slave[(reg * 4) + byte] = slave; 1576 1577 return 0; 1578 } 1579 1580 /* Parse next byte. */ 1581 slave_reg_tmp >>= 8; 1582 } 1583 } 1584 1585 return -EBUSY; 1586 } 1587 1588 static int mlxbf_i2c_slave_disable(struct mlxbf_i2c_priv *priv, u8 addr) 1589 { 1590 u8 addr_tmp, reg, reg_cnt, byte; 1591 u32 slave_reg, slave_reg_tmp; 1592 1593 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2; 1594 1595 /* 1596 * Read the slave registers. There are 4 * 32-bit slave registers. 1597 * Each slave register can hold up to 4 * 8-bit slave configuration: 1598 * 1) A 7-bit address 1599 * 2) And a status bit (1 if enabled, 0 if not). 1600 * Check if addr is present in the registers. 1601 */ 1602 for (reg = 0; reg < reg_cnt; reg++) { 1603 slave_reg = readl(priv->slv->io + 1604 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4); 1605 1606 /* Check whether the address slots are empty. */ 1607 if (!slave_reg) 1608 continue; 1609 1610 /* 1611 * Check if addr matches any of the 4 slave addresses 1612 * in the register. 1613 */ 1614 slave_reg_tmp = slave_reg; 1615 for (byte = 0; byte < 4; byte++) { 1616 addr_tmp = slave_reg_tmp & MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK; 1617 /* 1618 * Parse slave address bytes and check whether the 1619 * slave address already exists. 1620 */ 1621 if (addr_tmp == addr) { 1622 /* Clear the slave address slot. */ 1623 slave_reg &= ~(GENMASK(7, 0) << (byte * 8)); 1624 writel(slave_reg, priv->slv->io + 1625 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + 1626 (reg * 0x4)); 1627 /* Free slave at the corresponding index */ 1628 priv->slave[(reg * 4) + byte] = NULL; 1629 1630 return 0; 1631 } 1632 1633 /* Parse next byte. */ 1634 slave_reg_tmp >>= 8; 1635 } 1636 } 1637 1638 return -ENXIO; 1639 } 1640 1641 static int mlxbf_i2c_init_coalesce(struct platform_device *pdev, 1642 struct mlxbf_i2c_priv *priv) 1643 { 1644 struct mlxbf_i2c_resource *coalesce_res; 1645 struct resource *params; 1646 resource_size_t size; 1647 int ret = 0; 1648 1649 /* 1650 * Unlike BlueField-1 platform, the coalesce registers is a dedicated 1651 * resource in the next generations of BlueField. 1652 */ 1653 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) { 1654 coalesce_res = mlxbf_i2c_get_shared_resource(priv, 1655 MLXBF_I2C_COALESCE_RES); 1656 if (!coalesce_res) 1657 return -EPERM; 1658 1659 /* 1660 * The Cause Coalesce group in TYU space is shared among 1661 * I2C busses. This function MUST be serialized to avoid 1662 * racing when claiming the memory region. 1663 */ 1664 lockdep_assert_held(mlxbf_i2c_gpio_res->lock); 1665 1666 /* Check whether the memory map exist. */ 1667 if (coalesce_res->io) { 1668 priv->coalesce = coalesce_res; 1669 return 0; 1670 } 1671 1672 params = coalesce_res->params; 1673 size = resource_size(params); 1674 1675 if (!request_mem_region(params->start, size, params->name)) 1676 return -EFAULT; 1677 1678 coalesce_res->io = ioremap(params->start, size); 1679 if (!coalesce_res->io) { 1680 release_mem_region(params->start, size); 1681 return -ENOMEM; 1682 } 1683 1684 priv->coalesce = coalesce_res; 1685 1686 } else { 1687 ret = mlxbf_i2c_init_resource(pdev, &priv->coalesce, 1688 MLXBF_I2C_COALESCE_RES); 1689 } 1690 1691 return ret; 1692 } 1693 1694 static int mlxbf_i2c_release_coalesce(struct platform_device *pdev, 1695 struct mlxbf_i2c_priv *priv) 1696 { 1697 struct mlxbf_i2c_resource *coalesce_res; 1698 struct device *dev = &pdev->dev; 1699 struct resource *params; 1700 resource_size_t size; 1701 1702 coalesce_res = priv->coalesce; 1703 1704 if (coalesce_res->io) { 1705 params = coalesce_res->params; 1706 size = resource_size(params); 1707 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) { 1708 mutex_lock(coalesce_res->lock); 1709 iounmap(coalesce_res->io); 1710 release_mem_region(params->start, size); 1711 mutex_unlock(coalesce_res->lock); 1712 } else { 1713 devm_release_mem_region(dev, params->start, size); 1714 } 1715 } 1716 1717 return 0; 1718 } 1719 1720 static int mlxbf_i2c_init_slave(struct platform_device *pdev, 1721 struct mlxbf_i2c_priv *priv) 1722 { 1723 struct device *dev = &pdev->dev; 1724 u32 int_reg; 1725 int ret; 1726 1727 /* Reset FSM. */ 1728 writel(0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_FSM); 1729 1730 /* 1731 * Enable slave cause interrupt bits. Drive 1732 * MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE and 1733 * MLXBF_I2C_CAUSE_WRITE_SUCCESS, these are enabled when an external 1734 * masters issue a Read and Write, respectively. But, clear all 1735 * interrupts first. 1736 */ 1737 writel(~0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR); 1738 int_reg = MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE; 1739 int_reg |= MLXBF_I2C_CAUSE_WRITE_SUCCESS; 1740 writel(int_reg, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_EVTEN0); 1741 1742 /* Finally, set the 'ready' bit to start handling transactions. */ 1743 writel(0x1, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1744 1745 /* Initialize the cause coalesce resource. */ 1746 ret = mlxbf_i2c_init_coalesce(pdev, priv); 1747 if (ret < 0) { 1748 dev_err(dev, "failed to initialize cause coalesce\n"); 1749 return ret; 1750 } 1751 1752 return 0; 1753 } 1754 1755 static bool mlxbf_i2c_has_coalesce(struct mlxbf_i2c_priv *priv, bool *read, 1756 bool *write) 1757 { 1758 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1759 u32 coalesce0_reg, cause_reg; 1760 u8 slave_shift, is_set; 1761 1762 *write = false; 1763 *read = false; 1764 1765 slave_shift = chip->type != MLXBF_I2C_CHIP_TYPE_1 ? 1766 MLXBF_I2C_CAUSE_YU_SLAVE_BIT : 1767 priv->bus + MLXBF_I2C_CAUSE_TYU_SLAVE_BIT; 1768 1769 coalesce0_reg = readl(priv->coalesce->io + MLXBF_I2C_CAUSE_COALESCE_0); 1770 is_set = coalesce0_reg & (1 << slave_shift); 1771 1772 if (!is_set) 1773 return false; 1774 1775 /* Check the source of the interrupt, i.e. whether a Read or Write. */ 1776 cause_reg = readl(priv->slv_cause->io + MLXBF_I2C_CAUSE_ARBITER); 1777 if (cause_reg & MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE) 1778 *read = true; 1779 else if (cause_reg & MLXBF_I2C_CAUSE_WRITE_SUCCESS) 1780 *write = true; 1781 1782 /* Clear cause bits. */ 1783 writel(~0x0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR); 1784 1785 return true; 1786 } 1787 1788 static struct i2c_client *mlxbf_i2c_get_slave_from_addr( 1789 struct mlxbf_i2c_priv *priv, u8 addr) 1790 { 1791 int i; 1792 1793 for (i = 0; i < MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT; i++) { 1794 if (!priv->slave[i]) 1795 continue; 1796 1797 if (priv->slave[i]->addr == addr) 1798 return priv->slave[i]; 1799 } 1800 1801 return NULL; 1802 } 1803 1804 /* 1805 * Send byte to 'external' smbus master. This function is executed when 1806 * an external smbus master wants to read data from the BlueField. 1807 */ 1808 static int mlxbf_i2c_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes) 1809 { 1810 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 }; 1811 u8 write_size, pec_en, addr, value, byte_cnt; 1812 struct i2c_client *slave; 1813 u32 control32, data32; 1814 int ret = 0; 1815 1816 /* 1817 * Read the first byte received from the external master to 1818 * determine the slave address. This byte is located in the 1819 * first data descriptor register of the slave GW. 1820 */ 1821 data32 = ioread32be(priv->slv->io + 1822 MLXBF_I2C_SLAVE_DATA_DESC_ADDR); 1823 addr = (data32 & GENMASK(7, 0)) >> 1; 1824 1825 /* 1826 * Check if the slave address received in the data descriptor register 1827 * matches any of the slave addresses registered. If there is a match, 1828 * set the slave. 1829 */ 1830 slave = mlxbf_i2c_get_slave_from_addr(priv, addr); 1831 if (!slave) { 1832 ret = -ENXIO; 1833 goto clear_csr; 1834 } 1835 1836 /* 1837 * An I2C read can consist of a WRITE bit transaction followed by 1838 * a READ bit transaction. Indeed, slave devices often expect 1839 * the slave address to be followed by the internal address. 1840 * So, write the internal address byte first, and then, send the 1841 * requested data to the master. 1842 */ 1843 if (recv_bytes > 1) { 1844 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1845 value = (data32 >> 8) & GENMASK(7, 0); 1846 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, 1847 &value); 1848 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1849 1850 if (ret < 0) 1851 goto clear_csr; 1852 } 1853 1854 /* 1855 * Send data to the master. Currently, the driver supports 1856 * READ_BYTE, READ_WORD and BLOCK READ protocols. The 1857 * hardware can send up to 128 bytes per transfer which is 1858 * the total size of the data registers. 1859 */ 1860 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); 1861 1862 for (byte_cnt = 0; byte_cnt < MLXBF_I2C_SLAVE_DATA_DESC_SIZE; byte_cnt++) { 1863 data_desc[byte_cnt] = value; 1864 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value); 1865 } 1866 1867 /* Send a stop condition to the backend. */ 1868 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1869 1870 /* Set the number of bytes to write to master. */ 1871 write_size = (byte_cnt - 1) & 0x7f; 1872 1873 /* Write data to Slave GW data descriptor. */ 1874 mlxbf_i2c_smbus_write_data(priv, data_desc, byte_cnt, 1875 MLXBF_I2C_SLAVE_DATA_DESC_ADDR, false); 1876 1877 pec_en = 0; /* Disable PEC since it is not supported. */ 1878 1879 /* Prepare control word. */ 1880 control32 = MLXBF_I2C_SLAVE_ENABLE; 1881 control32 |= rol32(write_size, MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT); 1882 control32 |= rol32(pec_en, MLXBF_I2C_SLAVE_SEND_PEC_SHIFT); 1883 1884 writel(control32, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_GW); 1885 1886 /* 1887 * Wait until the transfer is completed; the driver will wait 1888 * until the GW is idle, a cause will rise on fall of GW busy. 1889 */ 1890 readl_poll_timeout_atomic(priv->slv_cause->io + MLXBF_I2C_CAUSE_ARBITER, 1891 data32, data32 & MLXBF_I2C_CAUSE_S_GW_BUSY_FALL, 1892 MLXBF_I2C_POLL_FREQ_IN_USEC, MLXBF_I2C_SMBUS_TIMEOUT); 1893 1894 clear_csr: 1895 /* Release the Slave GW. */ 1896 writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 1897 writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_PEC); 1898 writel(0x1, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1899 1900 return ret; 1901 } 1902 1903 /* 1904 * Receive bytes from 'external' smbus master. This function is executed when 1905 * an external smbus master wants to write data to the BlueField. 1906 */ 1907 static int mlxbf_i2c_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes) 1908 { 1909 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 }; 1910 struct i2c_client *slave; 1911 u8 value, byte, addr; 1912 int ret = 0; 1913 1914 /* Read data from Slave GW data descriptor. */ 1915 mlxbf_i2c_smbus_read_data(priv, data_desc, recv_bytes, 1916 MLXBF_I2C_SLAVE_DATA_DESC_ADDR, false); 1917 addr = data_desc[0] >> 1; 1918 1919 /* 1920 * Check if the slave address received in the data descriptor register 1921 * matches any of the slave addresses registered. 1922 */ 1923 slave = mlxbf_i2c_get_slave_from_addr(priv, addr); 1924 if (!slave) { 1925 ret = -EINVAL; 1926 goto clear_csr; 1927 } 1928 1929 /* 1930 * Notify the slave backend that an smbus master wants to write data 1931 * to the BlueField. 1932 */ 1933 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1934 1935 /* Send the received data to the slave backend. */ 1936 for (byte = 1; byte < recv_bytes; byte++) { 1937 value = data_desc[byte]; 1938 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, 1939 &value); 1940 if (ret < 0) 1941 break; 1942 } 1943 1944 /* 1945 * Send a stop event to the slave backend, to signal 1946 * the end of the write transactions. 1947 */ 1948 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1949 1950 clear_csr: 1951 /* Release the Slave GW. */ 1952 writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 1953 writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_PEC); 1954 writel(0x1, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1955 1956 return ret; 1957 } 1958 1959 static irqreturn_t mlxbf_i2c_irq(int irq, void *ptr) 1960 { 1961 struct mlxbf_i2c_priv *priv = ptr; 1962 bool read, write, irq_is_set; 1963 u32 rw_bytes_reg; 1964 u8 recv_bytes; 1965 1966 /* 1967 * Read TYU interrupt register and determine the source of the 1968 * interrupt. Based on the source of the interrupt one of the 1969 * following actions are performed: 1970 * - Receive data and send response to master. 1971 * - Send data and release slave GW. 1972 * 1973 * Handle read/write transaction only. CRmaster and Iarp requests 1974 * are ignored for now. 1975 */ 1976 irq_is_set = mlxbf_i2c_has_coalesce(priv, &read, &write); 1977 if (!irq_is_set || (!read && !write)) { 1978 /* Nothing to do here, interrupt was not from this device. */ 1979 return IRQ_NONE; 1980 } 1981 1982 /* 1983 * The MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES includes the number of 1984 * bytes from/to master. These are defined by 8-bits each. If the lower 1985 * 8 bits are set, then the master expect to read N bytes from the 1986 * slave, if the higher 8 bits are sent then the slave expect N bytes 1987 * from the master. 1988 */ 1989 rw_bytes_reg = readl(priv->slv->io + 1990 MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 1991 recv_bytes = (rw_bytes_reg >> 8) & GENMASK(7, 0); 1992 1993 /* 1994 * For now, the slave supports 128 bytes transfer. Discard remaining 1995 * data bytes if the master wrote more than 1996 * MLXBF_I2C_SLAVE_DATA_DESC_SIZE, i.e, the actual size of the slave 1997 * data descriptor. 1998 * 1999 * Note that we will never expect to transfer more than 128 bytes; as 2000 * specified in the SMBus standard, block transactions cannot exceed 2001 * 32 bytes. 2002 */ 2003 recv_bytes = recv_bytes > MLXBF_I2C_SLAVE_DATA_DESC_SIZE ? 2004 MLXBF_I2C_SLAVE_DATA_DESC_SIZE : recv_bytes; 2005 2006 if (read) 2007 mlxbf_i2c_irq_send(priv, recv_bytes); 2008 else 2009 mlxbf_i2c_irq_recv(priv, recv_bytes); 2010 2011 return IRQ_HANDLED; 2012 } 2013 2014 /* Return negative errno on error. */ 2015 static s32 mlxbf_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr, 2016 unsigned short flags, char read_write, 2017 u8 command, int size, 2018 union i2c_smbus_data *data) 2019 { 2020 struct mlxbf_i2c_smbus_request request = { 0 }; 2021 struct mlxbf_i2c_priv *priv; 2022 bool read, pec; 2023 u8 byte_cnt; 2024 2025 request.slave = addr; 2026 2027 read = (read_write == I2C_SMBUS_READ); 2028 pec = flags & I2C_FUNC_SMBUS_PEC; 2029 2030 switch (size) { 2031 case I2C_SMBUS_QUICK: 2032 mlxbf_i2c_smbus_quick_command(&request, read); 2033 dev_dbg(&adap->dev, "smbus quick, slave 0x%02x\n", addr); 2034 break; 2035 2036 case I2C_SMBUS_BYTE: 2037 mlxbf_i2c_smbus_byte_func(&request, 2038 read ? &data->byte : &command, read, 2039 pec); 2040 dev_dbg(&adap->dev, "smbus %s byte, slave 0x%02x.\n", 2041 read ? "read" : "write", addr); 2042 break; 2043 2044 case I2C_SMBUS_BYTE_DATA: 2045 mlxbf_i2c_smbus_data_byte_func(&request, &command, &data->byte, 2046 read, pec); 2047 dev_dbg(&adap->dev, "smbus %s byte data at 0x%02x, slave 0x%02x.\n", 2048 read ? "read" : "write", command, addr); 2049 break; 2050 2051 case I2C_SMBUS_WORD_DATA: 2052 mlxbf_i2c_smbus_data_word_func(&request, &command, 2053 (u8 *)&data->word, read, pec); 2054 dev_dbg(&adap->dev, "smbus %s word data at 0x%02x, slave 0x%02x.\n", 2055 read ? "read" : "write", command, addr); 2056 break; 2057 2058 case I2C_SMBUS_I2C_BLOCK_DATA: 2059 byte_cnt = data->block[0]; 2060 mlxbf_i2c_smbus_i2c_block_func(&request, &command, data->block, 2061 &byte_cnt, read, pec); 2062 dev_dbg(&adap->dev, "i2c %s block data, %d bytes at 0x%02x, slave 0x%02x.\n", 2063 read ? "read" : "write", byte_cnt, command, addr); 2064 break; 2065 2066 case I2C_SMBUS_BLOCK_DATA: 2067 byte_cnt = read ? I2C_SMBUS_BLOCK_MAX : data->block[0]; 2068 mlxbf_i2c_smbus_block_func(&request, &command, data->block, 2069 &byte_cnt, read, pec); 2070 dev_dbg(&adap->dev, "smbus %s block data, %d bytes at 0x%02x, slave 0x%02x.\n", 2071 read ? "read" : "write", byte_cnt, command, addr); 2072 break; 2073 2074 case I2C_FUNC_SMBUS_PROC_CALL: 2075 mlxbf_i2c_smbus_process_call_func(&request, &command, 2076 (u8 *)&data->word, pec); 2077 dev_dbg(&adap->dev, "process call, wr/rd at 0x%02x, slave 0x%02x.\n", 2078 command, addr); 2079 break; 2080 2081 case I2C_FUNC_SMBUS_BLOCK_PROC_CALL: 2082 byte_cnt = data->block[0]; 2083 mlxbf_i2c_smbus_blk_process_call_func(&request, &command, 2084 data->block, &byte_cnt, 2085 pec); 2086 dev_dbg(&adap->dev, "block process call, wr/rd %d bytes, slave 0x%02x.\n", 2087 byte_cnt, addr); 2088 break; 2089 2090 default: 2091 dev_dbg(&adap->dev, "Unsupported I2C/SMBus command %d\n", 2092 size); 2093 return -EOPNOTSUPP; 2094 } 2095 2096 priv = i2c_get_adapdata(adap); 2097 2098 return mlxbf_i2c_smbus_start_transaction(priv, &request); 2099 } 2100 2101 static int mlxbf_i2c_reg_slave(struct i2c_client *slave) 2102 { 2103 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 2104 struct device *dev = &slave->dev; 2105 int ret; 2106 2107 /* 2108 * Do not support ten bit chip address and do not use Packet Error 2109 * Checking (PEC). 2110 */ 2111 if (slave->flags & (I2C_CLIENT_TEN | I2C_CLIENT_PEC)) { 2112 dev_err(dev, "SMBus PEC and 10 bit address not supported\n"); 2113 return -EAFNOSUPPORT; 2114 } 2115 2116 ret = mlxbf_i2c_slave_enable(priv, slave); 2117 if (ret) 2118 dev_err(dev, "Surpassed max number of registered slaves allowed\n"); 2119 2120 return 0; 2121 } 2122 2123 static int mlxbf_i2c_unreg_slave(struct i2c_client *slave) 2124 { 2125 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 2126 struct device *dev = &slave->dev; 2127 int ret; 2128 2129 /* 2130 * Unregister slave by: 2131 * 1) Disabling the slave address in hardware 2132 * 2) Freeing priv->slave at the corresponding index 2133 */ 2134 ret = mlxbf_i2c_slave_disable(priv, slave->addr); 2135 if (ret) 2136 dev_err(dev, "Unable to find slave 0x%x\n", slave->addr); 2137 2138 return ret; 2139 } 2140 2141 static u32 mlxbf_i2c_functionality(struct i2c_adapter *adap) 2142 { 2143 return MLXBF_I2C_FUNC_ALL; 2144 } 2145 2146 static struct mlxbf_i2c_chip_info mlxbf_i2c_chip[] = { 2147 [MLXBF_I2C_CHIP_TYPE_1] = { 2148 .type = MLXBF_I2C_CHIP_TYPE_1, 2149 .shared_res = { 2150 [0] = &mlxbf_i2c_coalesce_res[MLXBF_I2C_CHIP_TYPE_1], 2151 [1] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_1], 2152 [2] = &mlxbf_i2c_gpio_res[MLXBF_I2C_CHIP_TYPE_1] 2153 }, 2154 .calculate_freq = mlxbf_i2c_calculate_freq_from_tyu, 2155 .smbus_master_rs_bytes_off = MLXBF_I2C_YU_SMBUS_RS_BYTES, 2156 .smbus_master_fsm_off = MLXBF_I2C_YU_SMBUS_MASTER_FSM 2157 }, 2158 [MLXBF_I2C_CHIP_TYPE_2] = { 2159 .type = MLXBF_I2C_CHIP_TYPE_2, 2160 .shared_res = { 2161 [0] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_2] 2162 }, 2163 .calculate_freq = mlxbf_i2c_calculate_freq_from_yu, 2164 .smbus_master_rs_bytes_off = MLXBF_I2C_YU_SMBUS_RS_BYTES, 2165 .smbus_master_fsm_off = MLXBF_I2C_YU_SMBUS_MASTER_FSM 2166 }, 2167 [MLXBF_I2C_CHIP_TYPE_3] = { 2168 .type = MLXBF_I2C_CHIP_TYPE_3, 2169 .shared_res = { 2170 [0] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_3] 2171 }, 2172 .calculate_freq = mlxbf_i2c_calculate_freq_from_yu, 2173 .smbus_master_rs_bytes_off = MLXBF_I2C_RSH_YU_SMBUS_RS_BYTES, 2174 .smbus_master_fsm_off = MLXBF_I2C_RSH_YU_SMBUS_MASTER_FSM 2175 } 2176 }; 2177 2178 static const struct i2c_algorithm mlxbf_i2c_algo = { 2179 .smbus_xfer = mlxbf_i2c_smbus_xfer, 2180 .functionality = mlxbf_i2c_functionality, 2181 .reg_slave = mlxbf_i2c_reg_slave, 2182 .unreg_slave = mlxbf_i2c_unreg_slave, 2183 }; 2184 2185 static struct i2c_adapter_quirks mlxbf_i2c_quirks = { 2186 .max_read_len = MLXBF_I2C_MASTER_DATA_R_LENGTH, 2187 .max_write_len = MLXBF_I2C_MASTER_DATA_W_LENGTH, 2188 }; 2189 2190 static const struct acpi_device_id mlxbf_i2c_acpi_ids[] = { 2191 { "MLNXBF03", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1] }, 2192 { "MLNXBF23", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2] }, 2193 { "MLNXBF31", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_3] }, 2194 {}, 2195 }; 2196 2197 MODULE_DEVICE_TABLE(acpi, mlxbf_i2c_acpi_ids); 2198 2199 static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv) 2200 { 2201 const struct acpi_device_id *aid; 2202 u64 bus_id; 2203 int ret; 2204 2205 if (acpi_disabled) 2206 return -ENOENT; 2207 2208 aid = acpi_match_device(mlxbf_i2c_acpi_ids, dev); 2209 if (!aid) 2210 return -ENODEV; 2211 2212 priv->chip = (struct mlxbf_i2c_chip_info *)aid->driver_data; 2213 2214 ret = acpi_dev_uid_to_integer(ACPI_COMPANION(dev), &bus_id); 2215 if (ret) { 2216 dev_err(dev, "Cannot retrieve UID\n"); 2217 return ret; 2218 } 2219 2220 priv->bus = bus_id; 2221 2222 return 0; 2223 } 2224 2225 static int mlxbf_i2c_probe(struct platform_device *pdev) 2226 { 2227 struct device *dev = &pdev->dev; 2228 struct mlxbf_i2c_priv *priv; 2229 struct i2c_adapter *adap; 2230 u32 resource_version; 2231 int irq, ret; 2232 2233 priv = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_priv), GFP_KERNEL); 2234 if (!priv) 2235 return -ENOMEM; 2236 2237 ret = mlxbf_i2c_acpi_probe(dev, priv); 2238 if (ret < 0) 2239 return ret; 2240 2241 /* This property allows the driver to stay backward compatible with older 2242 * ACPI tables. 2243 * Starting BlueField-3 SoC, the "smbus" resource was broken down into 3 2244 * separate resources "timer", "master" and "slave". 2245 */ 2246 if (device_property_read_u32(dev, "resource_version", &resource_version)) 2247 resource_version = 0; 2248 2249 priv->resource_version = resource_version; 2250 2251 if (priv->chip->type < MLXBF_I2C_CHIP_TYPE_3 && resource_version == 0) { 2252 priv->timer = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), GFP_KERNEL); 2253 if (!priv->timer) 2254 return -ENOMEM; 2255 2256 priv->mst = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), GFP_KERNEL); 2257 if (!priv->mst) 2258 return -ENOMEM; 2259 2260 priv->slv = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), GFP_KERNEL); 2261 if (!priv->slv) 2262 return -ENOMEM; 2263 2264 ret = mlxbf_i2c_init_resource(pdev, &priv->smbus, 2265 MLXBF_I2C_SMBUS_RES); 2266 if (ret < 0) 2267 return dev_err_probe(dev, ret, "Cannot fetch smbus resource info"); 2268 2269 priv->timer->io = priv->smbus->io; 2270 priv->mst->io = priv->smbus->io + MLXBF_I2C_MST_ADDR_OFFSET; 2271 priv->slv->io = priv->smbus->io + MLXBF_I2C_SLV_ADDR_OFFSET; 2272 } else { 2273 ret = mlxbf_i2c_init_resource(pdev, &priv->timer, 2274 MLXBF_I2C_SMBUS_TIMER_RES); 2275 if (ret < 0) 2276 return dev_err_probe(dev, ret, "Cannot fetch timer resource info"); 2277 2278 ret = mlxbf_i2c_init_resource(pdev, &priv->mst, 2279 MLXBF_I2C_SMBUS_MST_RES); 2280 if (ret < 0) 2281 return dev_err_probe(dev, ret, "Cannot fetch master resource info"); 2282 2283 ret = mlxbf_i2c_init_resource(pdev, &priv->slv, 2284 MLXBF_I2C_SMBUS_SLV_RES); 2285 if (ret < 0) 2286 return dev_err_probe(dev, ret, "Cannot fetch slave resource info"); 2287 } 2288 2289 ret = mlxbf_i2c_init_resource(pdev, &priv->mst_cause, 2290 MLXBF_I2C_MST_CAUSE_RES); 2291 if (ret < 0) 2292 return dev_err_probe(dev, ret, "Cannot fetch cause master resource info"); 2293 2294 ret = mlxbf_i2c_init_resource(pdev, &priv->slv_cause, 2295 MLXBF_I2C_SLV_CAUSE_RES); 2296 if (ret < 0) 2297 return dev_err_probe(dev, ret, "Cannot fetch cause slave resource info"); 2298 2299 adap = &priv->adap; 2300 adap->owner = THIS_MODULE; 2301 adap->class = I2C_CLASS_HWMON; 2302 adap->algo = &mlxbf_i2c_algo; 2303 adap->quirks = &mlxbf_i2c_quirks; 2304 adap->dev.parent = dev; 2305 adap->dev.of_node = dev->of_node; 2306 adap->nr = priv->bus; 2307 2308 snprintf(adap->name, sizeof(adap->name), "i2c%d", adap->nr); 2309 i2c_set_adapdata(adap, priv); 2310 2311 /* Read Core PLL frequency. */ 2312 ret = mlxbf_i2c_calculate_corepll_freq(pdev, priv); 2313 if (ret < 0) { 2314 dev_err(dev, "cannot get core clock frequency\n"); 2315 /* Set to default value. */ 2316 priv->frequency = MLXBF_I2C_COREPLL_FREQ; 2317 } 2318 2319 /* 2320 * Initialize master. 2321 * Note that a physical bus might be shared among Linux and firmware 2322 * (e.g., ATF). Thus, the bus should be initialized and ready and 2323 * bus initialization would be unnecessary. This requires additional 2324 * knowledge about physical busses. But, since an extra initialization 2325 * does not really hurt, then keep the code as is. 2326 */ 2327 ret = mlxbf_i2c_init_master(pdev, priv); 2328 if (ret < 0) 2329 return dev_err_probe(dev, ret, "failed to initialize smbus master %d", 2330 priv->bus); 2331 2332 mlxbf_i2c_init_timings(pdev, priv); 2333 2334 mlxbf_i2c_init_slave(pdev, priv); 2335 2336 irq = platform_get_irq(pdev, 0); 2337 if (irq < 0) 2338 return irq; 2339 ret = devm_request_irq(dev, irq, mlxbf_i2c_irq, 2340 IRQF_SHARED | IRQF_PROBE_SHARED, 2341 dev_name(dev), priv); 2342 if (ret < 0) 2343 return dev_err_probe(dev, ret, "Cannot get irq %d\n", irq); 2344 2345 priv->irq = irq; 2346 2347 platform_set_drvdata(pdev, priv); 2348 2349 ret = i2c_add_numbered_adapter(adap); 2350 if (ret < 0) 2351 return ret; 2352 2353 mutex_lock(&mlxbf_i2c_bus_lock); 2354 mlxbf_i2c_bus_count++; 2355 mutex_unlock(&mlxbf_i2c_bus_lock); 2356 2357 return 0; 2358 } 2359 2360 static void mlxbf_i2c_remove(struct platform_device *pdev) 2361 { 2362 struct mlxbf_i2c_priv *priv = platform_get_drvdata(pdev); 2363 struct device *dev = &pdev->dev; 2364 struct resource *params; 2365 2366 if (priv->chip->type < MLXBF_I2C_CHIP_TYPE_3 && priv->resource_version == 0) { 2367 params = priv->smbus->params; 2368 devm_release_mem_region(dev, params->start, resource_size(params)); 2369 } else { 2370 params = priv->timer->params; 2371 devm_release_mem_region(dev, params->start, resource_size(params)); 2372 2373 params = priv->mst->params; 2374 devm_release_mem_region(dev, params->start, resource_size(params)); 2375 2376 params = priv->slv->params; 2377 devm_release_mem_region(dev, params->start, resource_size(params)); 2378 } 2379 2380 params = priv->mst_cause->params; 2381 devm_release_mem_region(dev, params->start, resource_size(params)); 2382 2383 params = priv->slv_cause->params; 2384 devm_release_mem_region(dev, params->start, resource_size(params)); 2385 2386 /* 2387 * Release shared resources. This should be done when releasing 2388 * the I2C controller. 2389 */ 2390 mutex_lock(&mlxbf_i2c_bus_lock); 2391 if (--mlxbf_i2c_bus_count == 0) { 2392 mlxbf_i2c_release_coalesce(pdev, priv); 2393 mlxbf_i2c_release_corepll(pdev, priv); 2394 mlxbf_i2c_release_gpio(pdev, priv); 2395 } 2396 mutex_unlock(&mlxbf_i2c_bus_lock); 2397 2398 devm_free_irq(dev, priv->irq, priv); 2399 2400 i2c_del_adapter(&priv->adap); 2401 } 2402 2403 static struct platform_driver mlxbf_i2c_driver = { 2404 .probe = mlxbf_i2c_probe, 2405 .remove = mlxbf_i2c_remove, 2406 .driver = { 2407 .name = "i2c-mlxbf", 2408 .acpi_match_table = ACPI_PTR(mlxbf_i2c_acpi_ids), 2409 }, 2410 }; 2411 2412 static int __init mlxbf_i2c_init(void) 2413 { 2414 mutex_init(&mlxbf_i2c_coalesce_lock); 2415 mutex_init(&mlxbf_i2c_corepll_lock); 2416 mutex_init(&mlxbf_i2c_gpio_lock); 2417 2418 mutex_init(&mlxbf_i2c_bus_lock); 2419 2420 return platform_driver_register(&mlxbf_i2c_driver); 2421 } 2422 module_init(mlxbf_i2c_init); 2423 2424 static void __exit mlxbf_i2c_exit(void) 2425 { 2426 platform_driver_unregister(&mlxbf_i2c_driver); 2427 2428 mutex_destroy(&mlxbf_i2c_bus_lock); 2429 2430 mutex_destroy(&mlxbf_i2c_gpio_lock); 2431 mutex_destroy(&mlxbf_i2c_corepll_lock); 2432 mutex_destroy(&mlxbf_i2c_coalesce_lock); 2433 } 2434 module_exit(mlxbf_i2c_exit); 2435 2436 MODULE_DESCRIPTION("Mellanox BlueField I2C bus driver"); 2437 MODULE_AUTHOR("Khalil Blaiech <kblaiech@nvidia.com>"); 2438 MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>"); 2439 MODULE_LICENSE("GPL v2"); 2440