1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Mellanox BlueField I2C bus driver 4 * 5 * Copyright (C) 2020 Mellanox Technologies, Ltd. 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/bitfield.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/interrupt.h> 13 #include <linux/i2c.h> 14 #include <linux/io.h> 15 #include <linux/iopoll.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/string.h> 22 #include <linux/string_choices.h> 23 #include <linux/units.h> 24 25 /* Defines what functionality is present. */ 26 #define MLXBF_I2C_FUNC_SMBUS_BLOCK \ 27 (I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL) 28 29 #define MLXBF_I2C_FUNC_SMBUS_DEFAULT \ 30 (I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | \ 31 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_I2C_BLOCK | \ 32 I2C_FUNC_SMBUS_PROC_CALL) 33 34 #define MLXBF_I2C_FUNC_ALL \ 35 (MLXBF_I2C_FUNC_SMBUS_DEFAULT | MLXBF_I2C_FUNC_SMBUS_BLOCK | \ 36 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SLAVE) 37 38 /* Shared resources info in BlueField platforms. */ 39 40 #define MLXBF_I2C_COALESCE_TYU_ADDR 0x02801300 41 #define MLXBF_I2C_COALESCE_TYU_SIZE 0x010 42 43 #define MLXBF_I2C_GPIO_TYU_ADDR 0x02802000 44 #define MLXBF_I2C_GPIO_TYU_SIZE 0x100 45 46 #define MLXBF_I2C_COREPLL_TYU_ADDR 0x02800358 47 #define MLXBF_I2C_COREPLL_TYU_SIZE 0x008 48 49 #define MLXBF_I2C_COREPLL_YU_ADDR 0x02800c30 50 #define MLXBF_I2C_COREPLL_YU_SIZE 0x00c 51 52 #define MLXBF_I2C_COREPLL_RSH_YU_ADDR 0x13409824 53 #define MLXBF_I2C_COREPLL_RSH_YU_SIZE 0x00c 54 55 #define MLXBF_I2C_SHARED_RES_MAX 3 56 57 /* 58 * Note that the following SMBus, CAUSE, GPIO and PLL register addresses 59 * refer to their respective offsets relative to the corresponding 60 * memory-mapped region whose addresses are specified in either the DT or 61 * the ACPI tables or above. 62 */ 63 64 /* 65 * SMBus Master core clock frequency. Timing configurations are 66 * strongly dependent on the core clock frequency of the SMBus 67 * Master. Default value is set to 400MHz. 68 */ 69 #define MLXBF_I2C_TYU_PLL_OUT_FREQ (400 * HZ_PER_MHZ) 70 /* Reference clock for Bluefield - 156 MHz. */ 71 #define MLXBF_I2C_PLL_IN_FREQ 156250000ULL 72 73 /* Constant used to determine the PLL frequency. */ 74 #define MLNXBF_I2C_COREPLL_CONST 16384ULL 75 76 /* PLL registers. */ 77 #define MLXBF_I2C_CORE_PLL_REG1 0x4 78 #define MLXBF_I2C_CORE_PLL_REG2 0x8 79 80 /* OR cause register. */ 81 #define MLXBF_I2C_CAUSE_OR_EVTEN0 0x14 82 #define MLXBF_I2C_CAUSE_OR_CLEAR 0x18 83 84 /* Arbiter Cause Register. */ 85 #define MLXBF_I2C_CAUSE_ARBITER 0x1c 86 87 /* 88 * Cause Status flags. Note that those bits might be considered 89 * as interrupt enabled bits. 90 */ 91 92 /* Transaction ended with STOP. */ 93 #define MLXBF_I2C_CAUSE_TRANSACTION_ENDED BIT(0) 94 /* Master arbitration lost. */ 95 #define MLXBF_I2C_CAUSE_M_ARBITRATION_LOST BIT(1) 96 /* Unexpected start detected. */ 97 #define MLXBF_I2C_CAUSE_UNEXPECTED_START BIT(2) 98 /* Unexpected stop detected. */ 99 #define MLXBF_I2C_CAUSE_UNEXPECTED_STOP BIT(3) 100 /* Wait for transfer continuation. */ 101 #define MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA BIT(4) 102 /* Failed to generate STOP. */ 103 #define MLXBF_I2C_CAUSE_PUT_STOP_FAILED BIT(5) 104 /* Failed to generate START. */ 105 #define MLXBF_I2C_CAUSE_PUT_START_FAILED BIT(6) 106 /* Clock toggle completed. */ 107 #define MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE BIT(7) 108 /* Transfer timeout occurred. */ 109 #define MLXBF_I2C_CAUSE_M_FW_TIMEOUT BIT(8) 110 /* Master busy bit reset. */ 111 #define MLXBF_I2C_CAUSE_M_GW_BUSY_FALL BIT(9) 112 113 #define MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK GENMASK(9, 0) 114 115 #define MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR \ 116 (MLXBF_I2C_CAUSE_M_ARBITRATION_LOST | \ 117 MLXBF_I2C_CAUSE_UNEXPECTED_START | \ 118 MLXBF_I2C_CAUSE_UNEXPECTED_STOP | \ 119 MLXBF_I2C_CAUSE_PUT_STOP_FAILED | \ 120 MLXBF_I2C_CAUSE_PUT_START_FAILED | \ 121 MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE | \ 122 MLXBF_I2C_CAUSE_M_FW_TIMEOUT) 123 124 /* 125 * Slave cause status flags. Note that those bits might be considered 126 * as interrupt enabled bits. 127 */ 128 129 /* Write transaction received successfully. */ 130 #define MLXBF_I2C_CAUSE_WRITE_SUCCESS BIT(0) 131 /* Read transaction received, waiting for response. */ 132 #define MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE BIT(13) 133 /* Slave busy bit reset. */ 134 #define MLXBF_I2C_CAUSE_S_GW_BUSY_FALL BIT(18) 135 136 /* Cause coalesce registers. */ 137 #define MLXBF_I2C_CAUSE_COALESCE_0 0x00 138 139 #define MLXBF_I2C_CAUSE_TYU_SLAVE_BIT 3 140 #define MLXBF_I2C_CAUSE_YU_SLAVE_BIT 1 141 142 /* Functional enable register. */ 143 #define MLXBF_I2C_GPIO_0_FUNC_EN_0 0x28 144 /* Force OE enable register. */ 145 #define MLXBF_I2C_GPIO_0_FORCE_OE_EN 0x30 146 /* 147 * Note that Smbus GWs are on GPIOs 30:25. Two pins are used to control 148 * SDA/SCL lines: 149 * 150 * SMBUS GW0 -> bits[26:25] 151 * SMBUS GW1 -> bits[28:27] 152 * SMBUS GW2 -> bits[30:29] 153 */ 154 #define MLXBF_I2C_GPIO_SMBUS_GW_PINS(num) (25 + ((num) << 1)) 155 156 /* Note that gw_id can be 0,1 or 2. */ 157 #define MLXBF_I2C_GPIO_SMBUS_GW_MASK(num) \ 158 (0xffffffff & (~(0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num)))) 159 160 #define MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(num, val) \ 161 ((val) & MLXBF_I2C_GPIO_SMBUS_GW_MASK(num)) 162 163 #define MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(num, val) \ 164 ((val) | (0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num))) 165 166 /* 167 * Defines SMBus operating frequency and core clock frequency. 168 * According to ADB files, default values are compliant to 100KHz SMBus 169 * @ 400MHz core clock. The driver should be able to calculate core 170 * frequency based on PLL parameters. 171 */ 172 #define MLXBF_I2C_COREPLL_FREQ MLXBF_I2C_TYU_PLL_OUT_FREQ 173 174 /* Core PLL TYU configuration. */ 175 #define MLXBF_I2C_COREPLL_CORE_F_TYU_MASK GENMASK(15, 3) 176 #define MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK GENMASK(19, 16) 177 #define MLXBF_I2C_COREPLL_CORE_R_TYU_MASK GENMASK(25, 20) 178 179 /* Core PLL YU configuration. */ 180 #define MLXBF_I2C_COREPLL_CORE_F_YU_MASK GENMASK(25, 0) 181 #define MLXBF_I2C_COREPLL_CORE_OD_YU_MASK GENMASK(3, 0) 182 #define MLXBF_I2C_COREPLL_CORE_R_YU_MASK GENMASK(31, 26) 183 184 /* SMBus timing parameters. */ 185 #define MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH 0x00 186 #define MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE 0x04 187 #define MLXBF_I2C_SMBUS_TIMER_THOLD 0x08 188 #define MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP 0x0c 189 #define MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA 0x10 190 #define MLXBF_I2C_SMBUS_THIGH_MAX_TBUF 0x14 191 #define MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT 0x18 192 193 #define MLXBF_I2C_SHIFT_0 0 194 #define MLXBF_I2C_SHIFT_8 8 195 #define MLXBF_I2C_SHIFT_16 16 196 #define MLXBF_I2C_SHIFT_24 24 197 198 #define MLXBF_I2C_MASK_8 GENMASK(7, 0) 199 #define MLXBF_I2C_MASK_16 GENMASK(15, 0) 200 #define MLXBF_I2C_MASK_32 GENMASK(31, 0) 201 202 #define MLXBF_I2C_MST_ADDR_OFFSET 0x200 203 204 /* SMBus Master GW. */ 205 #define MLXBF_I2C_SMBUS_MASTER_GW 0x0 206 /* Number of bytes received and sent. */ 207 #define MLXBF_I2C_YU_SMBUS_RS_BYTES 0x100 208 #define MLXBF_I2C_RSH_YU_SMBUS_RS_BYTES 0x10c 209 /* Packet error check (PEC) value. */ 210 #define MLXBF_I2C_SMBUS_MASTER_PEC 0x104 211 /* Status bits (ACK/NACK/FW Timeout). */ 212 #define MLXBF_I2C_SMBUS_MASTER_STATUS 0x108 213 /* SMbus Master Finite State Machine. */ 214 #define MLXBF_I2C_YU_SMBUS_MASTER_FSM 0x110 215 #define MLXBF_I2C_RSH_YU_SMBUS_MASTER_FSM 0x100 216 217 /* SMBus master GW control bits offset in MLXBF_I2C_SMBUS_MASTER_GW[31:3]. */ 218 #define MLXBF_I2C_MASTER_LOCK_BIT BIT(31) /* Lock bit. */ 219 #define MLXBF_I2C_MASTER_BUSY_BIT BIT(30) /* Busy bit. */ 220 #define MLXBF_I2C_MASTER_START_BIT BIT(29) /* Control start. */ 221 #define MLXBF_I2C_MASTER_CTL_WRITE_BIT BIT(28) /* Control write phase. */ 222 #define MLXBF_I2C_MASTER_CTL_READ_BIT BIT(19) /* Control read phase. */ 223 #define MLXBF_I2C_MASTER_STOP_BIT BIT(3) /* Control stop. */ 224 225 #define MLXBF_I2C_MASTER_ENABLE \ 226 (MLXBF_I2C_MASTER_LOCK_BIT | MLXBF_I2C_MASTER_BUSY_BIT | \ 227 MLXBF_I2C_MASTER_START_BIT) 228 229 #define MLXBF_I2C_MASTER_ENABLE_WRITE \ 230 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_WRITE_BIT) 231 232 #define MLXBF_I2C_MASTER_ENABLE_READ \ 233 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_READ_BIT) 234 235 #define MLXBF_I2C_MASTER_WRITE_SHIFT 21 /* Control write bytes */ 236 #define MLXBF_I2C_MASTER_SEND_PEC_SHIFT 20 /* Send PEC byte when set to 1 */ 237 #define MLXBF_I2C_MASTER_PARSE_EXP_SHIFT 11 /* Control parse expected bytes */ 238 #define MLXBF_I2C_MASTER_SLV_ADDR_SHIFT 12 /* Slave address */ 239 #define MLXBF_I2C_MASTER_READ_SHIFT 4 /* Control read bytes */ 240 241 /* SMBus master GW Data descriptor. */ 242 #define MLXBF_I2C_MASTER_DATA_DESC_ADDR 0x80 243 #define MLXBF_I2C_MASTER_DATA_DESC_SIZE 0x80 /* Size in bytes. */ 244 245 /* Maximum bytes to read/write per SMBus transaction. */ 246 #define MLXBF_I2C_MASTER_DATA_R_LENGTH MLXBF_I2C_MASTER_DATA_DESC_SIZE 247 #define MLXBF_I2C_MASTER_DATA_W_LENGTH (MLXBF_I2C_MASTER_DATA_DESC_SIZE - 1) 248 249 /* All bytes were transmitted. */ 250 #define MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE BIT(0) 251 /* NACK received. */ 252 #define MLXBF_I2C_SMBUS_STATUS_NACK_RCV BIT(1) 253 /* Slave's byte count >128 bytes. */ 254 #define MLXBF_I2C_SMBUS_STATUS_READ_ERR BIT(2) 255 /* Timeout occurred. */ 256 #define MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT BIT(3) 257 258 #define MLXBF_I2C_SMBUS_MASTER_STATUS_MASK GENMASK(3, 0) 259 260 #define MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR \ 261 (MLXBF_I2C_SMBUS_STATUS_NACK_RCV | \ 262 MLXBF_I2C_SMBUS_STATUS_READ_ERR | \ 263 MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT) 264 265 #define MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK BIT(31) 266 #define MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK BIT(15) 267 268 #define MLXBF_I2C_SLV_ADDR_OFFSET 0x400 269 270 /* SMBus slave GW. */ 271 #define MLXBF_I2C_SMBUS_SLAVE_GW 0x0 272 /* Number of bytes received and sent from/to master. */ 273 #define MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES 0x100 274 /* Packet error check (PEC) value. */ 275 #define MLXBF_I2C_SMBUS_SLAVE_PEC 0x104 276 /* SMBus slave Finite State Machine (FSM). */ 277 #define MLXBF_I2C_SMBUS_SLAVE_FSM 0x110 278 /* 279 * Should be set when all raised causes handled, and cleared by HW on 280 * every new cause. 281 */ 282 #define MLXBF_I2C_SMBUS_SLAVE_READY 0x12c 283 284 /* SMBus slave GW control bits offset in MLXBF_I2C_SMBUS_SLAVE_GW[31:19]. */ 285 #define MLXBF_I2C_SLAVE_BUSY_BIT BIT(30) /* Busy bit. */ 286 #define MLXBF_I2C_SLAVE_WRITE_BIT BIT(29) /* Control write enable. */ 287 288 #define MLXBF_I2C_SLAVE_ENABLE \ 289 (MLXBF_I2C_SLAVE_BUSY_BIT | MLXBF_I2C_SLAVE_WRITE_BIT) 290 291 #define MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT 22 /* Number of bytes to write. */ 292 #define MLXBF_I2C_SLAVE_SEND_PEC_SHIFT 21 /* Send PEC byte shift. */ 293 294 /* SMBus slave GW Data descriptor. */ 295 #define MLXBF_I2C_SLAVE_DATA_DESC_ADDR 0x80 296 #define MLXBF_I2C_SLAVE_DATA_DESC_SIZE 0x80 /* Size in bytes. */ 297 298 /* SMbus slave configuration registers. */ 299 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG 0x114 300 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT 16 301 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT BIT(7) 302 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK GENMASK(6, 0) 303 304 /* 305 * Timeout is given in microsends. Note also that timeout handling is not 306 * exact. 307 */ 308 #define MLXBF_I2C_SMBUS_TIMEOUT (300 * 1000) /* 300ms */ 309 #define MLXBF_I2C_SMBUS_LOCK_POLL_TIMEOUT (300 * 1000) /* 300ms */ 310 311 /* Polling frequency in microseconds. */ 312 #define MLXBF_I2C_POLL_FREQ_IN_USEC 200 313 314 #define MLXBF_I2C_SMBUS_OP_CNT_1 1 315 #define MLXBF_I2C_SMBUS_OP_CNT_2 2 316 #define MLXBF_I2C_SMBUS_OP_CNT_3 3 317 #define MLXBF_I2C_SMBUS_MAX_OP_CNT MLXBF_I2C_SMBUS_OP_CNT_3 318 319 /* Helper macro to define an I2C resource parameters. */ 320 #define MLXBF_I2C_RES_PARAMS(addr, size, str) \ 321 { \ 322 .start = (addr), \ 323 .end = (addr) + (size) - 1, \ 324 .name = (str) \ 325 } 326 327 enum { 328 MLXBF_I2C_F_READ = BIT(0), 329 MLXBF_I2C_F_WRITE = BIT(1), 330 MLXBF_I2C_F_NORESTART = BIT(3), 331 MLXBF_I2C_F_SMBUS_OPERATION = BIT(4), 332 MLXBF_I2C_F_SMBUS_BLOCK = BIT(5), 333 MLXBF_I2C_F_SMBUS_PEC = BIT(6), 334 MLXBF_I2C_F_SMBUS_PROCESS_CALL = BIT(7), 335 MLXBF_I2C_F_WRITE_WITHOUT_STOP = BIT(8), 336 }; 337 338 /* Mellanox BlueField chip type. */ 339 enum mlxbf_i2c_chip_type { 340 MLXBF_I2C_CHIP_TYPE_1, /* Mellanox BlueField-1 chip. */ 341 MLXBF_I2C_CHIP_TYPE_2, /* Mellanox BlueField-2 chip. */ 342 MLXBF_I2C_CHIP_TYPE_3 /* Mellanox BlueField-3 chip. */ 343 }; 344 345 /* List of chip resources that are being accessed by the driver. */ 346 enum { 347 MLXBF_I2C_SMBUS_RES, 348 MLXBF_I2C_MST_CAUSE_RES, 349 MLXBF_I2C_SLV_CAUSE_RES, 350 MLXBF_I2C_COALESCE_RES, 351 MLXBF_I2C_SMBUS_TIMER_RES, 352 MLXBF_I2C_SMBUS_MST_RES, 353 MLXBF_I2C_SMBUS_SLV_RES, 354 MLXBF_I2C_COREPLL_RES, 355 MLXBF_I2C_GPIO_RES, 356 MLXBF_I2C_END_RES 357 }; 358 359 /* Encapsulates timing parameters. */ 360 struct mlxbf_i2c_timings { 361 u16 scl_high; /* Clock high period. */ 362 u16 scl_low; /* Clock low period. */ 363 u8 sda_rise; /* Data rise time. */ 364 u8 sda_fall; /* Data fall time. */ 365 u8 scl_rise; /* Clock rise time. */ 366 u8 scl_fall; /* Clock fall time. */ 367 u16 hold_start; /* Hold time after (REPEATED) START. */ 368 u16 hold_data; /* Data hold time. */ 369 u16 setup_start; /* REPEATED START condition setup time. */ 370 u16 setup_stop; /* STOP condition setup time. */ 371 u16 setup_data; /* Data setup time. */ 372 u16 pad; /* Padding. */ 373 u16 buf; /* Bus free time between STOP and START. */ 374 u16 thigh_max; /* Thigh max. */ 375 u32 timeout; /* Detect clock low timeout. */ 376 }; 377 378 struct mlxbf_i2c_smbus_operation { 379 u32 flags; 380 u32 length; /* Buffer length in bytes. */ 381 u8 *buffer; 382 }; 383 384 struct mlxbf_i2c_smbus_request { 385 u8 slave; 386 u8 operation_cnt; 387 struct mlxbf_i2c_smbus_operation operation[MLXBF_I2C_SMBUS_MAX_OP_CNT]; 388 }; 389 390 struct mlxbf_i2c_resource { 391 void __iomem *io; 392 struct resource *params; 393 struct mutex *lock; /* Mutex to protect mlxbf_i2c_resource. */ 394 u8 type; 395 }; 396 397 struct mlxbf_i2c_chip_info { 398 enum mlxbf_i2c_chip_type type; 399 /* Chip shared resources that are being used by the I2C controller. */ 400 struct mlxbf_i2c_resource *shared_res[MLXBF_I2C_SHARED_RES_MAX]; 401 402 /* Callback to calculate the core PLL frequency. */ 403 u64 (*calculate_freq)(struct mlxbf_i2c_resource *corepll_res); 404 405 /* Registers' address offset */ 406 u32 smbus_master_rs_bytes_off; 407 u32 smbus_master_fsm_off; 408 }; 409 410 struct mlxbf_i2c_priv { 411 const struct mlxbf_i2c_chip_info *chip; 412 struct i2c_adapter adap; 413 struct mlxbf_i2c_resource *smbus; 414 struct mlxbf_i2c_resource *timer; 415 struct mlxbf_i2c_resource *mst; 416 struct mlxbf_i2c_resource *slv; 417 struct mlxbf_i2c_resource *mst_cause; 418 struct mlxbf_i2c_resource *slv_cause; 419 struct mlxbf_i2c_resource *coalesce; 420 u64 frequency; /* Core frequency in Hz. */ 421 int bus; /* Physical bus identifier. */ 422 int irq; 423 struct i2c_client *slave[MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT]; 424 u32 resource_version; 425 }; 426 427 /* Core PLL frequency. */ 428 static u64 mlxbf_i2c_corepll_frequency; 429 430 static struct resource mlxbf_i2c_coalesce_tyu_params = 431 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COALESCE_TYU_ADDR, 432 MLXBF_I2C_COALESCE_TYU_SIZE, 433 "COALESCE_MEM"); 434 static struct resource mlxbf_i2c_corepll_tyu_params = 435 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_TYU_ADDR, 436 MLXBF_I2C_COREPLL_TYU_SIZE, 437 "COREPLL_MEM"); 438 static struct resource mlxbf_i2c_corepll_yu_params = 439 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_YU_ADDR, 440 MLXBF_I2C_COREPLL_YU_SIZE, 441 "COREPLL_MEM"); 442 static struct resource mlxbf_i2c_corepll_rsh_yu_params = 443 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_RSH_YU_ADDR, 444 MLXBF_I2C_COREPLL_RSH_YU_SIZE, 445 "COREPLL_MEM"); 446 static struct resource mlxbf_i2c_gpio_tyu_params = 447 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_GPIO_TYU_ADDR, 448 MLXBF_I2C_GPIO_TYU_SIZE, 449 "GPIO_MEM"); 450 451 static struct mutex mlxbf_i2c_coalesce_lock; 452 static struct mutex mlxbf_i2c_corepll_lock; 453 static struct mutex mlxbf_i2c_gpio_lock; 454 455 static struct mlxbf_i2c_resource mlxbf_i2c_coalesce_res[] = { 456 [MLXBF_I2C_CHIP_TYPE_1] = { 457 .params = &mlxbf_i2c_coalesce_tyu_params, 458 .lock = &mlxbf_i2c_coalesce_lock, 459 .type = MLXBF_I2C_COALESCE_RES 460 }, 461 {} 462 }; 463 464 static struct mlxbf_i2c_resource mlxbf_i2c_corepll_res[] = { 465 [MLXBF_I2C_CHIP_TYPE_1] = { 466 .params = &mlxbf_i2c_corepll_tyu_params, 467 .lock = &mlxbf_i2c_corepll_lock, 468 .type = MLXBF_I2C_COREPLL_RES 469 }, 470 [MLXBF_I2C_CHIP_TYPE_2] = { 471 .params = &mlxbf_i2c_corepll_yu_params, 472 .lock = &mlxbf_i2c_corepll_lock, 473 .type = MLXBF_I2C_COREPLL_RES, 474 }, 475 [MLXBF_I2C_CHIP_TYPE_3] = { 476 .params = &mlxbf_i2c_corepll_rsh_yu_params, 477 .lock = &mlxbf_i2c_corepll_lock, 478 .type = MLXBF_I2C_COREPLL_RES, 479 } 480 }; 481 482 static struct mlxbf_i2c_resource mlxbf_i2c_gpio_res[] = { 483 [MLXBF_I2C_CHIP_TYPE_1] = { 484 .params = &mlxbf_i2c_gpio_tyu_params, 485 .lock = &mlxbf_i2c_gpio_lock, 486 .type = MLXBF_I2C_GPIO_RES 487 }, 488 {} 489 }; 490 491 static u8 mlxbf_i2c_bus_count; 492 493 static struct mutex mlxbf_i2c_bus_lock; 494 495 static bool mlxbf_i2c_smbus_transaction_success(u32 master_status, 496 u32 cause_status) 497 { 498 /* 499 * When transaction ended with STOP, all bytes were transmitted, 500 * and no NACK received, then the transaction ended successfully. 501 * On the other hand, when the GW is configured with the stop bit 502 * de-asserted then the SMBus expects the following GW configuration 503 * for transfer continuation. 504 */ 505 if ((cause_status & MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA) || 506 ((cause_status & MLXBF_I2C_CAUSE_TRANSACTION_ENDED) && 507 (master_status & MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE) && 508 !(master_status & MLXBF_I2C_SMBUS_STATUS_NACK_RCV))) 509 return true; 510 511 return false; 512 } 513 514 /* 515 * Poll SMBus master status and return transaction status, 516 * i.e. whether succeeded or failed. I2C and SMBus fault codes 517 * are returned as negative numbers from most calls, with zero 518 * or some positive number indicating a non-fault return. 519 */ 520 static int mlxbf_i2c_smbus_check_status(struct mlxbf_i2c_priv *priv) 521 { 522 u32 master_status_bits; 523 u32 cause_status_bits; 524 u32 bits; 525 526 /* 527 * GW busy bit is raised by the driver and cleared by the HW 528 * when the transaction is completed. The busy bit is a good 529 * indicator of transaction status. So poll the busy bit, and 530 * then read the cause and master status bits to determine if 531 * errors occurred during the transaction. 532 */ 533 readl_poll_timeout_atomic(priv->mst->io + MLXBF_I2C_SMBUS_MASTER_GW, 534 bits, !(bits & MLXBF_I2C_MASTER_BUSY_BIT), 535 MLXBF_I2C_POLL_FREQ_IN_USEC, MLXBF_I2C_SMBUS_TIMEOUT); 536 537 /* Read cause status bits. */ 538 cause_status_bits = readl(priv->mst_cause->io + 539 MLXBF_I2C_CAUSE_ARBITER); 540 cause_status_bits &= MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK; 541 542 /* 543 * Parse both Cause and Master GW bits, then return transaction status. 544 */ 545 546 master_status_bits = readl(priv->mst->io + 547 MLXBF_I2C_SMBUS_MASTER_STATUS); 548 master_status_bits &= MLXBF_I2C_SMBUS_MASTER_STATUS_MASK; 549 550 if (mlxbf_i2c_smbus_transaction_success(master_status_bits, 551 cause_status_bits)) 552 return 0; 553 554 /* 555 * In case of timeout on GW busy, the ISR will clear busy bit but 556 * transaction ended bits cause will not be set so the transaction 557 * fails. Then, we must check Master GW status bits. 558 */ 559 if ((master_status_bits & MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR) && 560 (cause_status_bits & (MLXBF_I2C_CAUSE_TRANSACTION_ENDED | 561 MLXBF_I2C_CAUSE_M_GW_BUSY_FALL))) 562 return -EIO; 563 564 if (cause_status_bits & MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR) 565 return -EAGAIN; 566 567 return -ETIMEDOUT; 568 } 569 570 static void mlxbf_i2c_smbus_write_data(struct mlxbf_i2c_priv *priv, 571 const u8 *data, u8 length, u32 addr, 572 bool is_master) 573 { 574 u8 offset, aligned_length; 575 u32 data32; 576 577 aligned_length = round_up(length, 4); 578 579 /* 580 * Copy data bytes from 4-byte aligned source buffer. 581 * Data copied to the Master GW Data Descriptor MUST be shifted 582 * left so the data starts at the MSB of the descriptor registers 583 * as required by the underlying hardware. Enable byte swapping 584 * when writing data bytes to the 32 * 32-bit HW Data registers 585 * a.k.a Master GW Data Descriptor. 586 */ 587 for (offset = 0; offset < aligned_length; offset += sizeof(u32)) { 588 data32 = *((u32 *)(data + offset)); 589 if (is_master) 590 iowrite32be(data32, priv->mst->io + addr + offset); 591 else 592 iowrite32be(data32, priv->slv->io + addr + offset); 593 } 594 } 595 596 static void mlxbf_i2c_smbus_read_data(struct mlxbf_i2c_priv *priv, 597 u8 *data, u8 length, u32 addr, 598 bool is_master) 599 { 600 u32 data32, mask; 601 u8 byte, offset; 602 603 mask = sizeof(u32) - 1; 604 605 /* 606 * Data bytes in the Master GW Data Descriptor are shifted left 607 * so the data starts at the MSB of the descriptor registers as 608 * set by the underlying hardware. Enable byte swapping while 609 * reading data bytes from the 32 * 32-bit HW Data registers 610 * a.k.a Master GW Data Descriptor. 611 */ 612 613 for (offset = 0; offset < (length & ~mask); offset += sizeof(u32)) { 614 if (is_master) 615 data32 = ioread32be(priv->mst->io + addr + offset); 616 else 617 data32 = ioread32be(priv->slv->io + addr + offset); 618 *((u32 *)(data + offset)) = data32; 619 } 620 621 if (!(length & mask)) 622 return; 623 624 if (is_master) 625 data32 = ioread32be(priv->mst->io + addr + offset); 626 else 627 data32 = ioread32be(priv->slv->io + addr + offset); 628 629 for (byte = 0; byte < (length & mask); byte++) { 630 data[offset + byte] = data32 & GENMASK(7, 0); 631 data32 = ror32(data32, MLXBF_I2C_SHIFT_8); 632 } 633 } 634 635 static int mlxbf_i2c_smbus_enable(struct mlxbf_i2c_priv *priv, u8 slave, 636 u8 len, u8 block_en, u8 pec_en, bool read, 637 bool stop) 638 { 639 u32 command = 0; 640 641 /* Set Master GW control word. */ 642 if (stop) 643 command |= MLXBF_I2C_MASTER_STOP_BIT; 644 if (read) { 645 command |= MLXBF_I2C_MASTER_ENABLE_READ; 646 command |= rol32(len, MLXBF_I2C_MASTER_READ_SHIFT); 647 } else { 648 command |= MLXBF_I2C_MASTER_ENABLE_WRITE; 649 command |= rol32(len, MLXBF_I2C_MASTER_WRITE_SHIFT); 650 } 651 command |= rol32(slave, MLXBF_I2C_MASTER_SLV_ADDR_SHIFT); 652 command |= rol32(block_en, MLXBF_I2C_MASTER_PARSE_EXP_SHIFT); 653 command |= rol32(pec_en, MLXBF_I2C_MASTER_SEND_PEC_SHIFT); 654 655 /* Clear status bits. */ 656 writel(0x0, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_STATUS); 657 /* Set the cause data. */ 658 writel(~0x0, priv->mst_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR); 659 /* Zero PEC byte. */ 660 writel(0x0, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_PEC); 661 /* Zero byte count. */ 662 writel(0x0, priv->mst->io + priv->chip->smbus_master_rs_bytes_off); 663 664 /* GW activation. */ 665 writel(command, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_GW); 666 667 /* 668 * Poll master status and check status bits. An ACK is sent when 669 * completing writing data to the bus (Master 'byte_count_done' bit 670 * is set to 1). 671 */ 672 return mlxbf_i2c_smbus_check_status(priv); 673 } 674 675 static int 676 mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv, 677 struct mlxbf_i2c_smbus_request *request) 678 { 679 u8 data_desc[MLXBF_I2C_MASTER_DATA_DESC_SIZE] = { 0 }; 680 u8 op_idx, data_idx, data_len, write_len, read_len; 681 struct mlxbf_i2c_smbus_operation *operation; 682 u8 read_en, write_en, block_en, pec_en; 683 bool stop_after_write = true; 684 u8 slave, addr; 685 u8 *read_buf; 686 u32 flags; 687 u32 bits; 688 int ret; 689 690 if (request->operation_cnt > MLXBF_I2C_SMBUS_MAX_OP_CNT) 691 return -EINVAL; 692 693 read_buf = NULL; 694 data_idx = 0; 695 read_en = 0; 696 write_en = 0; 697 write_len = 0; 698 read_len = 0; 699 block_en = 0; 700 pec_en = 0; 701 slave = request->slave & GENMASK(6, 0); 702 addr = slave << 1; 703 704 /* 705 * Try to acquire the smbus gw lock before any reads of the GW register since 706 * a read sets the lock. 707 */ 708 ret = readl_poll_timeout_atomic(priv->mst->io + MLXBF_I2C_SMBUS_MASTER_GW, 709 bits, !(bits & MLXBF_I2C_MASTER_LOCK_BIT), 710 MLXBF_I2C_POLL_FREQ_IN_USEC, 711 MLXBF_I2C_SMBUS_LOCK_POLL_TIMEOUT); 712 if (WARN_ON(ret)) 713 return -EBUSY; 714 715 /* 716 * SW must make sure that the SMBus Master GW is idle before starting 717 * a transaction. Accordingly, this call polls the Master FSM stop bit; 718 * it returns -ETIMEDOUT when the bit is asserted, 0 if not. 719 */ 720 ret = readl_poll_timeout_atomic(priv->mst->io + priv->chip->smbus_master_fsm_off, 721 bits, !(bits & MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK), 722 MLXBF_I2C_POLL_FREQ_IN_USEC, MLXBF_I2C_SMBUS_TIMEOUT); 723 if (WARN_ON(ret)) { 724 ret = -EBUSY; 725 goto out_unlock; 726 } 727 728 /* Set first byte. */ 729 data_desc[data_idx++] = addr; 730 731 for (op_idx = 0; op_idx < request->operation_cnt; op_idx++) { 732 operation = &request->operation[op_idx]; 733 flags = operation->flags; 734 735 /* 736 * Note that read and write operations might be handled by a 737 * single command. If the MLXBF_I2C_F_SMBUS_OPERATION is set 738 * then write command byte and set the optional SMBus specific 739 * bits such as block_en and pec_en. These bits MUST be 740 * submitted by the first operation only. 741 */ 742 if (op_idx == 0 && flags & MLXBF_I2C_F_SMBUS_OPERATION) { 743 block_en = flags & MLXBF_I2C_F_SMBUS_BLOCK; 744 pec_en = flags & MLXBF_I2C_F_SMBUS_PEC; 745 } 746 747 if (flags & MLXBF_I2C_F_WRITE) { 748 write_en = 1; 749 write_len += operation->length; 750 if (data_idx + operation->length > 751 MLXBF_I2C_MASTER_DATA_DESC_SIZE) { 752 ret = -ENOBUFS; 753 goto out_unlock; 754 } 755 memcpy(data_desc + data_idx, 756 operation->buffer, operation->length); 757 data_idx += operation->length; 758 759 /* 760 * The stop condition can be skipped when writing on the bus 761 * to implement a repeated start condition on the next read 762 * as required for several SMBus and I2C operations. 763 */ 764 if (flags & MLXBF_I2C_F_WRITE_WITHOUT_STOP) 765 stop_after_write = false; 766 } 767 768 /* 769 * We assume that read operations are performed only once per 770 * SMBus transaction. *TBD* protect this statement so it won't 771 * be executed twice? or return an error if we try to read more 772 * than once? 773 */ 774 if (flags & MLXBF_I2C_F_READ) { 775 read_en = 1; 776 /* Subtract 1 as required by HW. */ 777 read_len = operation->length - 1; 778 read_buf = operation->buffer; 779 } 780 } 781 782 /* Set Master GW data descriptor. */ 783 data_len = write_len + 1; /* Add one byte of the slave address. */ 784 /* 785 * Note that data_len cannot be 0. Indeed, the slave address byte 786 * must be written to the data registers. 787 */ 788 mlxbf_i2c_smbus_write_data(priv, (const u8 *)data_desc, data_len, 789 MLXBF_I2C_MASTER_DATA_DESC_ADDR, true); 790 791 if (write_en) { 792 ret = mlxbf_i2c_smbus_enable(priv, slave, write_len, block_en, 793 pec_en, 0, stop_after_write); 794 if (ret) 795 goto out_unlock; 796 } 797 798 if (read_en) { 799 /* Write slave address to Master GW data descriptor. */ 800 mlxbf_i2c_smbus_write_data(priv, (const u8 *)&addr, 1, 801 MLXBF_I2C_MASTER_DATA_DESC_ADDR, true); 802 ret = mlxbf_i2c_smbus_enable(priv, slave, read_len, block_en, 803 pec_en, 1, true); 804 if (!ret) { 805 /* Get Master GW data descriptor. */ 806 mlxbf_i2c_smbus_read_data(priv, data_desc, read_len + 1, 807 MLXBF_I2C_MASTER_DATA_DESC_ADDR, true); 808 809 /* Get data from Master GW data descriptor. */ 810 memcpy(read_buf, data_desc, read_len + 1); 811 } 812 813 /* 814 * After a read operation the SMBus FSM ps (present state) 815 * needs to be 'manually' reset. This should be removed in 816 * next tag integration. 817 */ 818 writel(MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK, 819 priv->mst->io + priv->chip->smbus_master_fsm_off); 820 } 821 822 out_unlock: 823 /* Clear the gw to clear the lock */ 824 writel(0, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_GW); 825 826 return ret; 827 } 828 829 /* I2C SMBus protocols. */ 830 831 static void 832 mlxbf_i2c_smbus_quick_command(struct mlxbf_i2c_smbus_request *request, 833 u8 read) 834 { 835 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1; 836 837 request->operation[0].length = 0; 838 request->operation[0].flags = MLXBF_I2C_F_WRITE; 839 request->operation[0].flags |= read ? MLXBF_I2C_F_READ : 0; 840 } 841 842 static void mlxbf_i2c_smbus_byte_func(struct mlxbf_i2c_smbus_request *request, 843 u8 *data, bool read, bool pec_check) 844 { 845 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1; 846 847 request->operation[0].length = 1; 848 request->operation[0].length += pec_check; 849 850 request->operation[0].flags = MLXBF_I2C_F_SMBUS_OPERATION; 851 request->operation[0].flags |= read ? 852 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 853 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 854 855 request->operation[0].buffer = data; 856 } 857 858 static void 859 mlxbf_i2c_smbus_data_byte_func(struct mlxbf_i2c_smbus_request *request, 860 u8 *command, u8 *data, bool read, bool pec_check) 861 { 862 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 863 864 request->operation[0].length = 1; 865 request->operation[0].flags = 866 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 867 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 868 request->operation[0].buffer = command; 869 870 request->operation[1].length = 1; 871 request->operation[1].length += pec_check; 872 request->operation[1].flags = read ? 873 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 874 request->operation[1].buffer = data; 875 } 876 877 static void 878 mlxbf_i2c_smbus_data_word_func(struct mlxbf_i2c_smbus_request *request, 879 u8 *command, u8 *data, bool read, bool pec_check) 880 { 881 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 882 883 request->operation[0].length = 1; 884 request->operation[0].flags = 885 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 886 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 887 request->operation[0].buffer = command; 888 889 request->operation[1].length = 2; 890 request->operation[1].length += pec_check; 891 request->operation[1].flags = read ? 892 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 893 request->operation[1].buffer = data; 894 } 895 896 static void 897 mlxbf_i2c_smbus_i2c_block_func(struct mlxbf_i2c_smbus_request *request, 898 u8 *command, u8 *data, u8 *data_len, bool read, 899 bool pec_check) 900 { 901 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 902 903 request->operation[0].length = 1; 904 request->operation[0].flags = 905 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 906 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 907 request->operation[0].buffer = command; 908 909 if (read) 910 request->operation[0].flags |= MLXBF_I2C_F_WRITE_WITHOUT_STOP; 911 912 /* 913 * As specified in the standard, the max number of bytes to read/write 914 * per block operation is 32 bytes. In Golan code, the controller can 915 * read up to 128 bytes and write up to 127 bytes. 916 */ 917 request->operation[1].length = 918 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 919 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 920 request->operation[1].flags = read ? 921 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 922 /* 923 * Skip the first data byte, which corresponds to the number of bytes 924 * to read/write. 925 */ 926 request->operation[1].buffer = data + 1; 927 928 *data_len = request->operation[1].length; 929 930 /* Set the number of byte to read. This will be used by userspace. */ 931 if (read) 932 data[0] = *data_len; 933 } 934 935 static void mlxbf_i2c_smbus_block_func(struct mlxbf_i2c_smbus_request *request, 936 u8 *command, u8 *data, u8 *data_len, 937 bool read, bool pec_check) 938 { 939 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 940 941 request->operation[0].length = 1; 942 request->operation[0].flags = 943 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 944 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 945 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 946 request->operation[0].buffer = command; 947 948 request->operation[1].length = 949 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 950 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 951 request->operation[1].flags = read ? 952 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 953 request->operation[1].buffer = data + 1; 954 955 *data_len = request->operation[1].length; 956 957 /* Set the number of bytes to read. This will be used by userspace. */ 958 if (read) 959 data[0] = *data_len; 960 } 961 962 static void 963 mlxbf_i2c_smbus_process_call_func(struct mlxbf_i2c_smbus_request *request, 964 u8 *command, u8 *data, bool pec_check) 965 { 966 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3; 967 968 request->operation[0].length = 1; 969 request->operation[0].flags = 970 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 971 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 972 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 973 request->operation[0].buffer = command; 974 975 request->operation[1].length = 2; 976 request->operation[1].flags = MLXBF_I2C_F_WRITE; 977 request->operation[1].buffer = data; 978 979 request->operation[2].length = 3; 980 request->operation[2].flags = MLXBF_I2C_F_READ; 981 request->operation[2].buffer = data; 982 } 983 984 static void 985 mlxbf_i2c_smbus_blk_process_call_func(struct mlxbf_i2c_smbus_request *request, 986 u8 *command, u8 *data, u8 *data_len, 987 bool pec_check) 988 { 989 u32 length; 990 991 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3; 992 993 request->operation[0].length = 1; 994 request->operation[0].flags = 995 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 996 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 997 request->operation[0].flags |= (pec_check) ? MLXBF_I2C_F_SMBUS_PEC : 0; 998 request->operation[0].buffer = command; 999 1000 length = (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 1001 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 1002 1003 request->operation[1].length = length - pec_check; 1004 request->operation[1].flags = MLXBF_I2C_F_WRITE; 1005 request->operation[1].buffer = data; 1006 1007 request->operation[2].length = length; 1008 request->operation[2].flags = MLXBF_I2C_F_READ; 1009 request->operation[2].buffer = data; 1010 1011 *data_len = length; /* including PEC byte. */ 1012 } 1013 1014 /* Initialization functions. */ 1015 1016 static bool mlxbf_i2c_has_chip_type(struct mlxbf_i2c_priv *priv, u8 type) 1017 { 1018 return priv->chip->type == type; 1019 } 1020 1021 static struct mlxbf_i2c_resource * 1022 mlxbf_i2c_get_shared_resource(struct mlxbf_i2c_priv *priv, u8 type) 1023 { 1024 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1025 struct mlxbf_i2c_resource *res; 1026 u8 res_idx = 0; 1027 1028 for (res_idx = 0; res_idx < MLXBF_I2C_SHARED_RES_MAX; res_idx++) { 1029 res = chip->shared_res[res_idx]; 1030 if (res && res->type == type) 1031 return res; 1032 } 1033 1034 return NULL; 1035 } 1036 1037 static int mlxbf_i2c_init_resource(struct platform_device *pdev, 1038 struct mlxbf_i2c_resource **res, 1039 u8 type) 1040 { 1041 struct mlxbf_i2c_resource *tmp_res; 1042 struct device *dev = &pdev->dev; 1043 1044 if (!res || *res || type >= MLXBF_I2C_END_RES) 1045 return -EINVAL; 1046 1047 tmp_res = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), 1048 GFP_KERNEL); 1049 if (!tmp_res) 1050 return -ENOMEM; 1051 1052 tmp_res->io = devm_platform_get_and_ioremap_resource(pdev, type, &tmp_res->params); 1053 if (IS_ERR(tmp_res->io)) { 1054 devm_kfree(dev, tmp_res); 1055 return PTR_ERR(tmp_res->io); 1056 } 1057 1058 tmp_res->type = type; 1059 1060 *res = tmp_res; 1061 1062 return 0; 1063 } 1064 1065 static u32 mlxbf_i2c_get_ticks(struct mlxbf_i2c_priv *priv, u64 nanoseconds, 1066 bool minimum) 1067 { 1068 u64 frequency; 1069 u32 ticks; 1070 1071 /* 1072 * Compute ticks as follow: 1073 * 1074 * Ticks 1075 * Time = --------- x 10^9 => Ticks = Time x Frequency x 10^-9 1076 * Frequency 1077 */ 1078 frequency = priv->frequency; 1079 ticks = div_u64(nanoseconds * frequency, HZ_PER_GHZ); 1080 /* 1081 * The number of ticks is rounded down and if minimum is equal to 1 1082 * then add one tick. 1083 */ 1084 if (minimum) 1085 ticks++; 1086 1087 return ticks; 1088 } 1089 1090 static u32 mlxbf_i2c_set_timer(struct mlxbf_i2c_priv *priv, u64 nsec, bool opt, 1091 u32 mask, u8 shift) 1092 { 1093 u32 val = (mlxbf_i2c_get_ticks(priv, nsec, opt) & mask) << shift; 1094 1095 return val; 1096 } 1097 1098 static void mlxbf_i2c_set_timings(struct mlxbf_i2c_priv *priv, 1099 const struct mlxbf_i2c_timings *timings) 1100 { 1101 u32 timer; 1102 1103 timer = mlxbf_i2c_set_timer(priv, timings->scl_high, 1104 false, MLXBF_I2C_MASK_16, 1105 MLXBF_I2C_SHIFT_0); 1106 timer |= mlxbf_i2c_set_timer(priv, timings->scl_low, 1107 false, MLXBF_I2C_MASK_16, 1108 MLXBF_I2C_SHIFT_16); 1109 writel(timer, priv->timer->io + 1110 MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH); 1111 1112 timer = mlxbf_i2c_set_timer(priv, timings->sda_rise, false, 1113 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_0); 1114 timer |= mlxbf_i2c_set_timer(priv, timings->sda_fall, false, 1115 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_8); 1116 timer |= mlxbf_i2c_set_timer(priv, timings->scl_rise, false, 1117 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_16); 1118 timer |= mlxbf_i2c_set_timer(priv, timings->scl_fall, false, 1119 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_24); 1120 writel(timer, priv->timer->io + 1121 MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE); 1122 1123 timer = mlxbf_i2c_set_timer(priv, timings->hold_start, true, 1124 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1125 timer |= mlxbf_i2c_set_timer(priv, timings->hold_data, true, 1126 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1127 writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_TIMER_THOLD); 1128 1129 timer = mlxbf_i2c_set_timer(priv, timings->setup_start, true, 1130 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1131 timer |= mlxbf_i2c_set_timer(priv, timings->setup_stop, true, 1132 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1133 writel(timer, priv->timer->io + 1134 MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP); 1135 1136 timer = mlxbf_i2c_set_timer(priv, timings->setup_data, true, 1137 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1138 writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA); 1139 1140 timer = mlxbf_i2c_set_timer(priv, timings->buf, false, 1141 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1142 timer |= mlxbf_i2c_set_timer(priv, timings->thigh_max, false, 1143 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1144 writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_THIGH_MAX_TBUF); 1145 1146 timer = mlxbf_i2c_set_timer(priv, timings->timeout, false, 1147 MLXBF_I2C_MASK_32, MLXBF_I2C_SHIFT_0); 1148 writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT); 1149 } 1150 1151 enum mlxbf_i2c_timings_config { 1152 MLXBF_I2C_TIMING_CONFIG_100KHZ, 1153 MLXBF_I2C_TIMING_CONFIG_400KHZ, 1154 MLXBF_I2C_TIMING_CONFIG_1000KHZ, 1155 }; 1156 1157 /* Timing values are in nanoseconds */ 1158 static const struct mlxbf_i2c_timings mlxbf_i2c_timings[] = { 1159 [MLXBF_I2C_TIMING_CONFIG_100KHZ] = { 1160 .scl_high = 4810, 1161 .scl_low = 5000, 1162 .hold_start = 4000, 1163 .setup_start = 4800, 1164 .setup_stop = 4000, 1165 .setup_data = 250, 1166 .sda_rise = 50, 1167 .sda_fall = 50, 1168 .scl_rise = 50, 1169 .scl_fall = 50, 1170 .hold_data = 300, 1171 .buf = 20000, 1172 .thigh_max = 50000, 1173 .timeout = 35000000 1174 }, 1175 [MLXBF_I2C_TIMING_CONFIG_400KHZ] = { 1176 .scl_high = 1011, 1177 .scl_low = 1300, 1178 .hold_start = 600, 1179 .setup_start = 700, 1180 .setup_stop = 600, 1181 .setup_data = 100, 1182 .sda_rise = 50, 1183 .sda_fall = 50, 1184 .scl_rise = 50, 1185 .scl_fall = 50, 1186 .hold_data = 300, 1187 .buf = 20000, 1188 .thigh_max = 50000, 1189 .timeout = 35000000 1190 }, 1191 [MLXBF_I2C_TIMING_CONFIG_1000KHZ] = { 1192 .scl_high = 383, 1193 .scl_low = 460, 1194 .hold_start = 600, 1195 .setup_start = 260, 1196 .setup_stop = 260, 1197 .setup_data = 50, 1198 .sda_rise = 50, 1199 .sda_fall = 50, 1200 .scl_rise = 50, 1201 .scl_fall = 50, 1202 .hold_data = 300, 1203 .buf = 500, 1204 .thigh_max = 50000, 1205 .timeout = 35000000 1206 } 1207 }; 1208 1209 static int mlxbf_i2c_init_timings(struct platform_device *pdev, 1210 struct mlxbf_i2c_priv *priv) 1211 { 1212 enum mlxbf_i2c_timings_config config_idx; 1213 struct device *dev = &pdev->dev; 1214 u32 config_khz; 1215 1216 int ret; 1217 1218 ret = device_property_read_u32(dev, "clock-frequency", &config_khz); 1219 if (ret < 0) 1220 config_khz = I2C_MAX_STANDARD_MODE_FREQ; 1221 1222 switch (config_khz) { 1223 default: 1224 /* Default settings is 100 KHz. */ 1225 pr_warn("Illegal value %d: defaulting to 100 KHz\n", 1226 config_khz); 1227 fallthrough; 1228 case I2C_MAX_STANDARD_MODE_FREQ: 1229 config_idx = MLXBF_I2C_TIMING_CONFIG_100KHZ; 1230 break; 1231 1232 case I2C_MAX_FAST_MODE_FREQ: 1233 config_idx = MLXBF_I2C_TIMING_CONFIG_400KHZ; 1234 break; 1235 1236 case I2C_MAX_FAST_MODE_PLUS_FREQ: 1237 config_idx = MLXBF_I2C_TIMING_CONFIG_1000KHZ; 1238 break; 1239 } 1240 1241 mlxbf_i2c_set_timings(priv, &mlxbf_i2c_timings[config_idx]); 1242 1243 return 0; 1244 } 1245 1246 static int mlxbf_i2c_get_gpio(struct platform_device *pdev, 1247 struct mlxbf_i2c_priv *priv) 1248 { 1249 struct mlxbf_i2c_resource *gpio_res; 1250 struct device *dev = &pdev->dev; 1251 struct resource *params; 1252 resource_size_t size; 1253 1254 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1255 if (!gpio_res) 1256 return -EPERM; 1257 1258 /* 1259 * The GPIO region in TYU space is shared among I2C busses. 1260 * This function MUST be serialized to avoid racing when 1261 * claiming the memory region and/or setting up the GPIO. 1262 */ 1263 lockdep_assert_held(gpio_res->lock); 1264 1265 /* Check whether the memory map exist. */ 1266 if (gpio_res->io) 1267 return 0; 1268 1269 params = gpio_res->params; 1270 size = resource_size(params); 1271 1272 if (!devm_request_mem_region(dev, params->start, size, params->name)) 1273 return -EFAULT; 1274 1275 gpio_res->io = devm_ioremap(dev, params->start, size); 1276 if (!gpio_res->io) { 1277 devm_release_mem_region(dev, params->start, size); 1278 return -ENOMEM; 1279 } 1280 1281 return 0; 1282 } 1283 1284 static int mlxbf_i2c_release_gpio(struct platform_device *pdev, 1285 struct mlxbf_i2c_priv *priv) 1286 { 1287 struct mlxbf_i2c_resource *gpio_res; 1288 struct device *dev = &pdev->dev; 1289 struct resource *params; 1290 1291 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1292 if (!gpio_res) 1293 return 0; 1294 1295 mutex_lock(gpio_res->lock); 1296 1297 if (gpio_res->io) { 1298 /* Release the GPIO resource. */ 1299 params = gpio_res->params; 1300 devm_iounmap(dev, gpio_res->io); 1301 devm_release_mem_region(dev, params->start, 1302 resource_size(params)); 1303 } 1304 1305 mutex_unlock(gpio_res->lock); 1306 1307 return 0; 1308 } 1309 1310 static int mlxbf_i2c_get_corepll(struct platform_device *pdev, 1311 struct mlxbf_i2c_priv *priv) 1312 { 1313 struct mlxbf_i2c_resource *corepll_res; 1314 struct device *dev = &pdev->dev; 1315 struct resource *params; 1316 resource_size_t size; 1317 1318 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1319 MLXBF_I2C_COREPLL_RES); 1320 if (!corepll_res) 1321 return -EPERM; 1322 1323 /* 1324 * The COREPLL region in TYU space is shared among I2C busses. 1325 * This function MUST be serialized to avoid racing when 1326 * claiming the memory region. 1327 */ 1328 lockdep_assert_held(corepll_res->lock); 1329 1330 /* Check whether the memory map exist. */ 1331 if (corepll_res->io) 1332 return 0; 1333 1334 params = corepll_res->params; 1335 size = resource_size(params); 1336 1337 if (!devm_request_mem_region(dev, params->start, size, params->name)) 1338 return -EFAULT; 1339 1340 corepll_res->io = devm_ioremap(dev, params->start, size); 1341 if (!corepll_res->io) { 1342 devm_release_mem_region(dev, params->start, size); 1343 return -ENOMEM; 1344 } 1345 1346 return 0; 1347 } 1348 1349 static int mlxbf_i2c_release_corepll(struct platform_device *pdev, 1350 struct mlxbf_i2c_priv *priv) 1351 { 1352 struct mlxbf_i2c_resource *corepll_res; 1353 struct device *dev = &pdev->dev; 1354 struct resource *params; 1355 1356 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1357 MLXBF_I2C_COREPLL_RES); 1358 1359 mutex_lock(corepll_res->lock); 1360 1361 if (corepll_res->io) { 1362 /* Release the CorePLL resource. */ 1363 params = corepll_res->params; 1364 devm_iounmap(dev, corepll_res->io); 1365 devm_release_mem_region(dev, params->start, 1366 resource_size(params)); 1367 } 1368 1369 mutex_unlock(corepll_res->lock); 1370 1371 return 0; 1372 } 1373 1374 static int mlxbf_i2c_init_master(struct platform_device *pdev, 1375 struct mlxbf_i2c_priv *priv) 1376 { 1377 struct mlxbf_i2c_resource *gpio_res; 1378 struct device *dev = &pdev->dev; 1379 u32 config_reg; 1380 int ret; 1381 1382 /* This configuration is only needed for BlueField 1. */ 1383 if (!mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) 1384 return 0; 1385 1386 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1387 if (!gpio_res) 1388 return -EPERM; 1389 1390 /* 1391 * The GPIO region in TYU space is shared among I2C busses. 1392 * This function MUST be serialized to avoid racing when 1393 * claiming the memory region and/or setting up the GPIO. 1394 */ 1395 1396 mutex_lock(gpio_res->lock); 1397 1398 ret = mlxbf_i2c_get_gpio(pdev, priv); 1399 if (ret < 0) { 1400 dev_err(dev, "Failed to get gpio resource"); 1401 mutex_unlock(gpio_res->lock); 1402 return ret; 1403 } 1404 1405 /* 1406 * TYU - Configuration for GPIO pins. Those pins must be asserted in 1407 * MLXBF_I2C_GPIO_0_FUNC_EN_0, i.e. GPIO 0 is controlled by HW, and must 1408 * be reset in MLXBF_I2C_GPIO_0_FORCE_OE_EN, i.e. GPIO_OE will be driven 1409 * instead of HW_OE. 1410 * For now, we do not reset the GPIO state when the driver is removed. 1411 * First, it is not necessary to disable the bus since we are using 1412 * the same busses. Then, some busses might be shared among Linux and 1413 * platform firmware; disabling the bus might compromise the system 1414 * functionality. 1415 */ 1416 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0); 1417 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(priv->bus, 1418 config_reg); 1419 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0); 1420 1421 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN); 1422 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(priv->bus, 1423 config_reg); 1424 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN); 1425 1426 mutex_unlock(gpio_res->lock); 1427 1428 return 0; 1429 } 1430 1431 static u64 mlxbf_i2c_calculate_freq_from_tyu(struct mlxbf_i2c_resource *corepll_res) 1432 { 1433 u64 core_frequency; 1434 u8 core_od, core_r; 1435 u32 corepll_val; 1436 u16 core_f; 1437 1438 corepll_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1); 1439 1440 /* Get Core PLL configuration bits. */ 1441 core_f = FIELD_GET(MLXBF_I2C_COREPLL_CORE_F_TYU_MASK, corepll_val); 1442 core_od = FIELD_GET(MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK, corepll_val); 1443 core_r = FIELD_GET(MLXBF_I2C_COREPLL_CORE_R_TYU_MASK, corepll_val); 1444 1445 /* 1446 * Compute PLL output frequency as follow: 1447 * 1448 * CORE_F + 1 1449 * PLL_OUT_FREQ = PLL_IN_FREQ * ---------------------------- 1450 * (CORE_R + 1) * (CORE_OD + 1) 1451 * 1452 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency 1453 * and PadFrequency, respectively. 1454 */ 1455 core_frequency = MLXBF_I2C_PLL_IN_FREQ * (++core_f); 1456 1457 return div_u64(core_frequency, (++core_r) * (++core_od)); 1458 } 1459 1460 static u64 mlxbf_i2c_calculate_freq_from_yu(struct mlxbf_i2c_resource *corepll_res) 1461 { 1462 u32 corepll_reg1_val, corepll_reg2_val; 1463 u64 corepll_frequency; 1464 u8 core_od, core_r; 1465 u32 core_f; 1466 1467 corepll_reg1_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1); 1468 corepll_reg2_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG2); 1469 1470 /* Get Core PLL configuration bits */ 1471 core_f = FIELD_GET(MLXBF_I2C_COREPLL_CORE_F_YU_MASK, corepll_reg1_val); 1472 core_r = FIELD_GET(MLXBF_I2C_COREPLL_CORE_R_YU_MASK, corepll_reg1_val); 1473 core_od = FIELD_GET(MLXBF_I2C_COREPLL_CORE_OD_YU_MASK, corepll_reg2_val); 1474 1475 /* 1476 * Compute PLL output frequency as follow: 1477 * 1478 * CORE_F / 16384 1479 * PLL_OUT_FREQ = PLL_IN_FREQ * ---------------------------- 1480 * (CORE_R + 1) * (CORE_OD + 1) 1481 * 1482 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency 1483 * and PadFrequency, respectively. 1484 */ 1485 corepll_frequency = (MLXBF_I2C_PLL_IN_FREQ * core_f) / MLNXBF_I2C_COREPLL_CONST; 1486 1487 return div_u64(corepll_frequency, (++core_r) * (++core_od)); 1488 } 1489 1490 static int mlxbf_i2c_calculate_corepll_freq(struct platform_device *pdev, 1491 struct mlxbf_i2c_priv *priv) 1492 { 1493 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1494 struct mlxbf_i2c_resource *corepll_res; 1495 struct device *dev = &pdev->dev; 1496 u64 *freq = &priv->frequency; 1497 int ret; 1498 1499 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1500 MLXBF_I2C_COREPLL_RES); 1501 if (!corepll_res) 1502 return -EPERM; 1503 1504 /* 1505 * First, check whether the TYU core Clock frequency is set. 1506 * The TYU core frequency is the same for all I2C busses; when 1507 * the first device gets probed the frequency is determined and 1508 * stored into a globally visible variable. So, first of all, 1509 * check whether the frequency is already set. Here, we assume 1510 * that the frequency is expected to be greater than 0. 1511 */ 1512 mutex_lock(corepll_res->lock); 1513 if (!mlxbf_i2c_corepll_frequency) { 1514 if (!chip->calculate_freq) { 1515 mutex_unlock(corepll_res->lock); 1516 return -EPERM; 1517 } 1518 1519 ret = mlxbf_i2c_get_corepll(pdev, priv); 1520 if (ret < 0) { 1521 dev_err(dev, "Failed to get corePLL resource"); 1522 mutex_unlock(corepll_res->lock); 1523 return ret; 1524 } 1525 1526 mlxbf_i2c_corepll_frequency = chip->calculate_freq(corepll_res); 1527 } 1528 mutex_unlock(corepll_res->lock); 1529 1530 *freq = mlxbf_i2c_corepll_frequency; 1531 1532 return 0; 1533 } 1534 1535 static int mlxbf_i2c_slave_enable(struct mlxbf_i2c_priv *priv, 1536 struct i2c_client *slave) 1537 { 1538 u8 reg, reg_cnt, byte, addr_tmp; 1539 u32 slave_reg, slave_reg_tmp; 1540 1541 if (!priv) 1542 return -EPERM; 1543 1544 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2; 1545 1546 /* 1547 * Read the slave registers. There are 4 * 32-bit slave registers. 1548 * Each slave register can hold up to 4 * 8-bit slave configuration: 1549 * 1) A 7-bit address 1550 * 2) And a status bit (1 if enabled, 0 if not). 1551 * Look for the next available slave register slot. 1552 */ 1553 for (reg = 0; reg < reg_cnt; reg++) { 1554 slave_reg = readl(priv->slv->io + 1555 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4); 1556 /* 1557 * Each register holds 4 slave addresses. So, we have to keep 1558 * the byte order consistent with the value read in order to 1559 * update the register correctly, if needed. 1560 */ 1561 slave_reg_tmp = slave_reg; 1562 for (byte = 0; byte < 4; byte++) { 1563 addr_tmp = slave_reg_tmp & GENMASK(7, 0); 1564 1565 /* 1566 * If an enable bit is not set in the 1567 * MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG register, then the 1568 * slave address slot associated with that bit is 1569 * free. So set the enable bit and write the 1570 * slave address bits. 1571 */ 1572 if (!(addr_tmp & MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT)) { 1573 slave_reg &= ~(MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK << (byte * 8)); 1574 slave_reg |= (slave->addr << (byte * 8)); 1575 slave_reg |= MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT << (byte * 8); 1576 writel(slave_reg, priv->slv->io + 1577 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + 1578 (reg * 0x4)); 1579 1580 /* 1581 * Set the slave at the corresponding index. 1582 */ 1583 priv->slave[(reg * 4) + byte] = slave; 1584 1585 return 0; 1586 } 1587 1588 /* Parse next byte. */ 1589 slave_reg_tmp >>= 8; 1590 } 1591 } 1592 1593 return -EBUSY; 1594 } 1595 1596 static int mlxbf_i2c_slave_disable(struct mlxbf_i2c_priv *priv, u8 addr) 1597 { 1598 u8 addr_tmp, reg, reg_cnt, byte; 1599 u32 slave_reg, slave_reg_tmp; 1600 1601 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2; 1602 1603 /* 1604 * Read the slave registers. There are 4 * 32-bit slave registers. 1605 * Each slave register can hold up to 4 * 8-bit slave configuration: 1606 * 1) A 7-bit address 1607 * 2) And a status bit (1 if enabled, 0 if not). 1608 * Check if addr is present in the registers. 1609 */ 1610 for (reg = 0; reg < reg_cnt; reg++) { 1611 slave_reg = readl(priv->slv->io + 1612 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4); 1613 1614 /* Check whether the address slots are empty. */ 1615 if (!slave_reg) 1616 continue; 1617 1618 /* 1619 * Check if addr matches any of the 4 slave addresses 1620 * in the register. 1621 */ 1622 slave_reg_tmp = slave_reg; 1623 for (byte = 0; byte < 4; byte++) { 1624 addr_tmp = slave_reg_tmp & MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK; 1625 /* 1626 * Parse slave address bytes and check whether the 1627 * slave address already exists. 1628 */ 1629 if (addr_tmp == addr) { 1630 /* Clear the slave address slot. */ 1631 slave_reg &= ~(GENMASK(7, 0) << (byte * 8)); 1632 writel(slave_reg, priv->slv->io + 1633 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + 1634 (reg * 0x4)); 1635 /* Free slave at the corresponding index */ 1636 priv->slave[(reg * 4) + byte] = NULL; 1637 1638 return 0; 1639 } 1640 1641 /* Parse next byte. */ 1642 slave_reg_tmp >>= 8; 1643 } 1644 } 1645 1646 return -ENXIO; 1647 } 1648 1649 static int mlxbf_i2c_init_coalesce(struct platform_device *pdev, 1650 struct mlxbf_i2c_priv *priv) 1651 { 1652 struct mlxbf_i2c_resource *coalesce_res; 1653 struct resource *params; 1654 resource_size_t size; 1655 int ret = 0; 1656 1657 /* 1658 * Unlike BlueField-1 platform, the coalesce registers is a dedicated 1659 * resource in the next generations of BlueField. 1660 */ 1661 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) { 1662 coalesce_res = mlxbf_i2c_get_shared_resource(priv, 1663 MLXBF_I2C_COALESCE_RES); 1664 if (!coalesce_res) 1665 return -EPERM; 1666 1667 /* 1668 * The Cause Coalesce group in TYU space is shared among 1669 * I2C busses. This function MUST be serialized to avoid 1670 * racing when claiming the memory region. 1671 */ 1672 lockdep_assert_held(mlxbf_i2c_gpio_res->lock); 1673 1674 /* Check whether the memory map exist. */ 1675 if (coalesce_res->io) { 1676 priv->coalesce = coalesce_res; 1677 return 0; 1678 } 1679 1680 params = coalesce_res->params; 1681 size = resource_size(params); 1682 1683 if (!request_mem_region(params->start, size, params->name)) 1684 return -EFAULT; 1685 1686 coalesce_res->io = ioremap(params->start, size); 1687 if (!coalesce_res->io) { 1688 release_mem_region(params->start, size); 1689 return -ENOMEM; 1690 } 1691 1692 priv->coalesce = coalesce_res; 1693 1694 } else { 1695 ret = mlxbf_i2c_init_resource(pdev, &priv->coalesce, 1696 MLXBF_I2C_COALESCE_RES); 1697 } 1698 1699 return ret; 1700 } 1701 1702 static int mlxbf_i2c_release_coalesce(struct platform_device *pdev, 1703 struct mlxbf_i2c_priv *priv) 1704 { 1705 struct mlxbf_i2c_resource *coalesce_res; 1706 struct device *dev = &pdev->dev; 1707 struct resource *params; 1708 resource_size_t size; 1709 1710 coalesce_res = priv->coalesce; 1711 1712 if (coalesce_res->io) { 1713 params = coalesce_res->params; 1714 size = resource_size(params); 1715 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) { 1716 mutex_lock(coalesce_res->lock); 1717 iounmap(coalesce_res->io); 1718 release_mem_region(params->start, size); 1719 mutex_unlock(coalesce_res->lock); 1720 } else { 1721 devm_release_mem_region(dev, params->start, size); 1722 } 1723 } 1724 1725 return 0; 1726 } 1727 1728 static int mlxbf_i2c_init_slave(struct platform_device *pdev, 1729 struct mlxbf_i2c_priv *priv) 1730 { 1731 struct device *dev = &pdev->dev; 1732 u32 int_reg; 1733 int ret; 1734 1735 /* Reset FSM. */ 1736 writel(0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_FSM); 1737 1738 /* 1739 * Enable slave cause interrupt bits. Drive 1740 * MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE and 1741 * MLXBF_I2C_CAUSE_WRITE_SUCCESS, these are enabled when an external 1742 * masters issue a Read and Write, respectively. But, clear all 1743 * interrupts first. 1744 */ 1745 writel(~0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR); 1746 int_reg = MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE; 1747 int_reg |= MLXBF_I2C_CAUSE_WRITE_SUCCESS; 1748 writel(int_reg, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_EVTEN0); 1749 1750 /* Finally, set the 'ready' bit to start handling transactions. */ 1751 writel(0x1, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1752 1753 /* Initialize the cause coalesce resource. */ 1754 ret = mlxbf_i2c_init_coalesce(pdev, priv); 1755 if (ret < 0) { 1756 dev_err(dev, "failed to initialize cause coalesce\n"); 1757 return ret; 1758 } 1759 1760 return 0; 1761 } 1762 1763 static bool mlxbf_i2c_has_coalesce(struct mlxbf_i2c_priv *priv, bool *read, 1764 bool *write) 1765 { 1766 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1767 u32 coalesce0_reg, cause_reg; 1768 u8 slave_shift, is_set; 1769 1770 *write = false; 1771 *read = false; 1772 1773 slave_shift = chip->type != MLXBF_I2C_CHIP_TYPE_1 ? 1774 MLXBF_I2C_CAUSE_YU_SLAVE_BIT : 1775 priv->bus + MLXBF_I2C_CAUSE_TYU_SLAVE_BIT; 1776 1777 coalesce0_reg = readl(priv->coalesce->io + MLXBF_I2C_CAUSE_COALESCE_0); 1778 is_set = coalesce0_reg & (1 << slave_shift); 1779 1780 if (!is_set) 1781 return false; 1782 1783 /* Check the source of the interrupt, i.e. whether a Read or Write. */ 1784 cause_reg = readl(priv->slv_cause->io + MLXBF_I2C_CAUSE_ARBITER); 1785 if (cause_reg & MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE) 1786 *read = true; 1787 else if (cause_reg & MLXBF_I2C_CAUSE_WRITE_SUCCESS) 1788 *write = true; 1789 1790 /* Clear cause bits. */ 1791 writel(~0x0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR); 1792 1793 return true; 1794 } 1795 1796 static struct i2c_client *mlxbf_i2c_get_slave_from_addr( 1797 struct mlxbf_i2c_priv *priv, u8 addr) 1798 { 1799 int i; 1800 1801 for (i = 0; i < MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT; i++) { 1802 if (!priv->slave[i]) 1803 continue; 1804 1805 if (priv->slave[i]->addr == addr) 1806 return priv->slave[i]; 1807 } 1808 1809 return NULL; 1810 } 1811 1812 /* 1813 * Send byte to 'external' smbus master. This function is executed when 1814 * an external smbus master wants to read data from the BlueField. 1815 */ 1816 static int mlxbf_i2c_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes) 1817 { 1818 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 }; 1819 u8 write_size, pec_en, addr, value, byte_cnt; 1820 struct i2c_client *slave; 1821 u32 control32, data32; 1822 int ret = 0; 1823 1824 /* 1825 * Read the first byte received from the external master to 1826 * determine the slave address. This byte is located in the 1827 * first data descriptor register of the slave GW. 1828 */ 1829 data32 = ioread32be(priv->slv->io + 1830 MLXBF_I2C_SLAVE_DATA_DESC_ADDR); 1831 addr = (data32 & GENMASK(7, 0)) >> 1; 1832 1833 /* 1834 * Check if the slave address received in the data descriptor register 1835 * matches any of the slave addresses registered. If there is a match, 1836 * set the slave. 1837 */ 1838 slave = mlxbf_i2c_get_slave_from_addr(priv, addr); 1839 if (!slave) { 1840 ret = -ENXIO; 1841 goto clear_csr; 1842 } 1843 1844 /* 1845 * An I2C read can consist of a WRITE bit transaction followed by 1846 * a READ bit transaction. Indeed, slave devices often expect 1847 * the slave address to be followed by the internal address. 1848 * So, write the internal address byte first, and then, send the 1849 * requested data to the master. 1850 */ 1851 if (recv_bytes > 1) { 1852 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1853 value = (data32 >> 8) & GENMASK(7, 0); 1854 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, 1855 &value); 1856 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1857 1858 if (ret < 0) 1859 goto clear_csr; 1860 } 1861 1862 /* 1863 * Send data to the master. Currently, the driver supports 1864 * READ_BYTE, READ_WORD and BLOCK READ protocols. The 1865 * hardware can send up to 128 bytes per transfer which is 1866 * the total size of the data registers. 1867 */ 1868 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); 1869 1870 for (byte_cnt = 0; byte_cnt < MLXBF_I2C_SLAVE_DATA_DESC_SIZE; byte_cnt++) { 1871 data_desc[byte_cnt] = value; 1872 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value); 1873 } 1874 1875 /* Send a stop condition to the backend. */ 1876 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1877 1878 /* Set the number of bytes to write to master. */ 1879 write_size = (byte_cnt - 1) & 0x7f; 1880 1881 /* Write data to Slave GW data descriptor. */ 1882 mlxbf_i2c_smbus_write_data(priv, data_desc, byte_cnt, 1883 MLXBF_I2C_SLAVE_DATA_DESC_ADDR, false); 1884 1885 pec_en = 0; /* Disable PEC since it is not supported. */ 1886 1887 /* Prepare control word. */ 1888 control32 = MLXBF_I2C_SLAVE_ENABLE; 1889 control32 |= rol32(write_size, MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT); 1890 control32 |= rol32(pec_en, MLXBF_I2C_SLAVE_SEND_PEC_SHIFT); 1891 1892 writel(control32, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_GW); 1893 1894 /* 1895 * Wait until the transfer is completed; the driver will wait 1896 * until the GW is idle, a cause will rise on fall of GW busy. 1897 */ 1898 readl_poll_timeout_atomic(priv->slv_cause->io + MLXBF_I2C_CAUSE_ARBITER, 1899 data32, data32 & MLXBF_I2C_CAUSE_S_GW_BUSY_FALL, 1900 MLXBF_I2C_POLL_FREQ_IN_USEC, MLXBF_I2C_SMBUS_TIMEOUT); 1901 1902 clear_csr: 1903 /* Release the Slave GW. */ 1904 writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 1905 writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_PEC); 1906 writel(0x1, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1907 1908 return ret; 1909 } 1910 1911 /* 1912 * Receive bytes from 'external' smbus master. This function is executed when 1913 * an external smbus master wants to write data to the BlueField. 1914 */ 1915 static int mlxbf_i2c_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes) 1916 { 1917 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 }; 1918 struct i2c_client *slave; 1919 u8 value, byte, addr; 1920 int ret = 0; 1921 1922 /* Read data from Slave GW data descriptor. */ 1923 mlxbf_i2c_smbus_read_data(priv, data_desc, recv_bytes, 1924 MLXBF_I2C_SLAVE_DATA_DESC_ADDR, false); 1925 addr = data_desc[0] >> 1; 1926 1927 /* 1928 * Check if the slave address received in the data descriptor register 1929 * matches any of the slave addresses registered. 1930 */ 1931 slave = mlxbf_i2c_get_slave_from_addr(priv, addr); 1932 if (!slave) { 1933 ret = -EINVAL; 1934 goto clear_csr; 1935 } 1936 1937 /* 1938 * Notify the slave backend that an smbus master wants to write data 1939 * to the BlueField. 1940 */ 1941 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1942 1943 /* Send the received data to the slave backend. */ 1944 for (byte = 1; byte < recv_bytes; byte++) { 1945 value = data_desc[byte]; 1946 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, 1947 &value); 1948 if (ret < 0) 1949 break; 1950 } 1951 1952 /* 1953 * Send a stop event to the slave backend, to signal 1954 * the end of the write transactions. 1955 */ 1956 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1957 1958 clear_csr: 1959 /* Release the Slave GW. */ 1960 writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 1961 writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_PEC); 1962 writel(0x1, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1963 1964 return ret; 1965 } 1966 1967 static irqreturn_t mlxbf_i2c_irq(int irq, void *ptr) 1968 { 1969 struct mlxbf_i2c_priv *priv = ptr; 1970 bool read, write, irq_is_set; 1971 u32 rw_bytes_reg; 1972 u8 recv_bytes; 1973 1974 /* 1975 * Read TYU interrupt register and determine the source of the 1976 * interrupt. Based on the source of the interrupt one of the 1977 * following actions are performed: 1978 * - Receive data and send response to master. 1979 * - Send data and release slave GW. 1980 * 1981 * Handle read/write transaction only. CRmaster and Iarp requests 1982 * are ignored for now. 1983 */ 1984 irq_is_set = mlxbf_i2c_has_coalesce(priv, &read, &write); 1985 if (!irq_is_set || (!read && !write)) { 1986 /* Nothing to do here, interrupt was not from this device. */ 1987 return IRQ_NONE; 1988 } 1989 1990 /* 1991 * The MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES includes the number of 1992 * bytes from/to master. These are defined by 8-bits each. If the lower 1993 * 8 bits are set, then the master expect to read N bytes from the 1994 * slave, if the higher 8 bits are sent then the slave expect N bytes 1995 * from the master. 1996 */ 1997 rw_bytes_reg = readl(priv->slv->io + 1998 MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 1999 recv_bytes = (rw_bytes_reg >> 8) & GENMASK(7, 0); 2000 2001 /* 2002 * For now, the slave supports 128 bytes transfer. Discard remaining 2003 * data bytes if the master wrote more than 2004 * MLXBF_I2C_SLAVE_DATA_DESC_SIZE, i.e, the actual size of the slave 2005 * data descriptor. 2006 * 2007 * Note that we will never expect to transfer more than 128 bytes; as 2008 * specified in the SMBus standard, block transactions cannot exceed 2009 * 32 bytes. 2010 */ 2011 recv_bytes = recv_bytes > MLXBF_I2C_SLAVE_DATA_DESC_SIZE ? 2012 MLXBF_I2C_SLAVE_DATA_DESC_SIZE : recv_bytes; 2013 2014 if (read) 2015 mlxbf_i2c_irq_send(priv, recv_bytes); 2016 else 2017 mlxbf_i2c_irq_recv(priv, recv_bytes); 2018 2019 return IRQ_HANDLED; 2020 } 2021 2022 /* Return negative errno on error. */ 2023 static s32 mlxbf_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr, 2024 unsigned short flags, char read_write, 2025 u8 command, int size, 2026 union i2c_smbus_data *data) 2027 { 2028 struct mlxbf_i2c_smbus_request request = { 0 }; 2029 struct mlxbf_i2c_priv *priv; 2030 bool read, pec; 2031 u8 byte_cnt; 2032 2033 request.slave = addr; 2034 2035 read = (read_write == I2C_SMBUS_READ); 2036 pec = flags & I2C_FUNC_SMBUS_PEC; 2037 2038 switch (size) { 2039 case I2C_SMBUS_QUICK: 2040 mlxbf_i2c_smbus_quick_command(&request, read); 2041 dev_dbg(&adap->dev, "smbus quick, slave 0x%02x\n", addr); 2042 break; 2043 2044 case I2C_SMBUS_BYTE: 2045 mlxbf_i2c_smbus_byte_func(&request, 2046 read ? &data->byte : &command, read, 2047 pec); 2048 dev_dbg(&adap->dev, "smbus %s byte, slave 0x%02x.\n", 2049 str_read_write(read), addr); 2050 break; 2051 2052 case I2C_SMBUS_BYTE_DATA: 2053 mlxbf_i2c_smbus_data_byte_func(&request, &command, &data->byte, 2054 read, pec); 2055 dev_dbg(&adap->dev, "smbus %s byte data at 0x%02x, slave 0x%02x.\n", 2056 str_read_write(read), command, addr); 2057 break; 2058 2059 case I2C_SMBUS_WORD_DATA: 2060 mlxbf_i2c_smbus_data_word_func(&request, &command, 2061 (u8 *)&data->word, read, pec); 2062 dev_dbg(&adap->dev, "smbus %s word data at 0x%02x, slave 0x%02x.\n", 2063 str_read_write(read), command, addr); 2064 break; 2065 2066 case I2C_SMBUS_I2C_BLOCK_DATA: 2067 byte_cnt = data->block[0]; 2068 mlxbf_i2c_smbus_i2c_block_func(&request, &command, data->block, 2069 &byte_cnt, read, pec); 2070 dev_dbg(&adap->dev, "i2c %s block data, %d bytes at 0x%02x, slave 0x%02x.\n", 2071 str_read_write(read), byte_cnt, command, addr); 2072 break; 2073 2074 case I2C_SMBUS_BLOCK_DATA: 2075 byte_cnt = read ? I2C_SMBUS_BLOCK_MAX : data->block[0]; 2076 mlxbf_i2c_smbus_block_func(&request, &command, data->block, 2077 &byte_cnt, read, pec); 2078 dev_dbg(&adap->dev, "smbus %s block data, %d bytes at 0x%02x, slave 0x%02x.\n", 2079 str_read_write(read), byte_cnt, command, addr); 2080 break; 2081 2082 case I2C_FUNC_SMBUS_PROC_CALL: 2083 mlxbf_i2c_smbus_process_call_func(&request, &command, 2084 (u8 *)&data->word, pec); 2085 dev_dbg(&adap->dev, "process call, wr/rd at 0x%02x, slave 0x%02x.\n", 2086 command, addr); 2087 break; 2088 2089 case I2C_FUNC_SMBUS_BLOCK_PROC_CALL: 2090 byte_cnt = data->block[0]; 2091 mlxbf_i2c_smbus_blk_process_call_func(&request, &command, 2092 data->block, &byte_cnt, 2093 pec); 2094 dev_dbg(&adap->dev, "block process call, wr/rd %d bytes, slave 0x%02x.\n", 2095 byte_cnt, addr); 2096 break; 2097 2098 default: 2099 dev_dbg(&adap->dev, "Unsupported I2C/SMBus command %d\n", 2100 size); 2101 return -EOPNOTSUPP; 2102 } 2103 2104 priv = i2c_get_adapdata(adap); 2105 2106 return mlxbf_i2c_smbus_start_transaction(priv, &request); 2107 } 2108 2109 static int mlxbf_i2c_reg_slave(struct i2c_client *slave) 2110 { 2111 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 2112 struct device *dev = &slave->dev; 2113 int ret; 2114 2115 /* 2116 * Do not support ten bit chip address and do not use Packet Error 2117 * Checking (PEC). 2118 */ 2119 if (slave->flags & (I2C_CLIENT_TEN | I2C_CLIENT_PEC)) { 2120 dev_err(dev, "SMBus PEC and 10 bit address not supported\n"); 2121 return -EAFNOSUPPORT; 2122 } 2123 2124 ret = mlxbf_i2c_slave_enable(priv, slave); 2125 if (ret) 2126 dev_err(dev, "Surpassed max number of registered slaves allowed\n"); 2127 2128 return 0; 2129 } 2130 2131 static int mlxbf_i2c_unreg_slave(struct i2c_client *slave) 2132 { 2133 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 2134 struct device *dev = &slave->dev; 2135 int ret; 2136 2137 /* 2138 * Unregister slave by: 2139 * 1) Disabling the slave address in hardware 2140 * 2) Freeing priv->slave at the corresponding index 2141 */ 2142 ret = mlxbf_i2c_slave_disable(priv, slave->addr); 2143 if (ret) 2144 dev_err(dev, "Unable to find slave 0x%x\n", slave->addr); 2145 2146 return ret; 2147 } 2148 2149 static u32 mlxbf_i2c_functionality(struct i2c_adapter *adap) 2150 { 2151 return MLXBF_I2C_FUNC_ALL; 2152 } 2153 2154 static struct mlxbf_i2c_chip_info mlxbf_i2c_chip[] = { 2155 [MLXBF_I2C_CHIP_TYPE_1] = { 2156 .type = MLXBF_I2C_CHIP_TYPE_1, 2157 .shared_res = { 2158 [0] = &mlxbf_i2c_coalesce_res[MLXBF_I2C_CHIP_TYPE_1], 2159 [1] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_1], 2160 [2] = &mlxbf_i2c_gpio_res[MLXBF_I2C_CHIP_TYPE_1] 2161 }, 2162 .calculate_freq = mlxbf_i2c_calculate_freq_from_tyu, 2163 .smbus_master_rs_bytes_off = MLXBF_I2C_YU_SMBUS_RS_BYTES, 2164 .smbus_master_fsm_off = MLXBF_I2C_YU_SMBUS_MASTER_FSM 2165 }, 2166 [MLXBF_I2C_CHIP_TYPE_2] = { 2167 .type = MLXBF_I2C_CHIP_TYPE_2, 2168 .shared_res = { 2169 [0] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_2] 2170 }, 2171 .calculate_freq = mlxbf_i2c_calculate_freq_from_yu, 2172 .smbus_master_rs_bytes_off = MLXBF_I2C_YU_SMBUS_RS_BYTES, 2173 .smbus_master_fsm_off = MLXBF_I2C_YU_SMBUS_MASTER_FSM 2174 }, 2175 [MLXBF_I2C_CHIP_TYPE_3] = { 2176 .type = MLXBF_I2C_CHIP_TYPE_3, 2177 .shared_res = { 2178 [0] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_3] 2179 }, 2180 .calculate_freq = mlxbf_i2c_calculate_freq_from_yu, 2181 .smbus_master_rs_bytes_off = MLXBF_I2C_RSH_YU_SMBUS_RS_BYTES, 2182 .smbus_master_fsm_off = MLXBF_I2C_RSH_YU_SMBUS_MASTER_FSM 2183 } 2184 }; 2185 2186 static const struct i2c_algorithm mlxbf_i2c_algo = { 2187 .smbus_xfer = mlxbf_i2c_smbus_xfer, 2188 .functionality = mlxbf_i2c_functionality, 2189 .reg_slave = mlxbf_i2c_reg_slave, 2190 .unreg_slave = mlxbf_i2c_unreg_slave, 2191 }; 2192 2193 static struct i2c_adapter_quirks mlxbf_i2c_quirks = { 2194 .max_read_len = MLXBF_I2C_MASTER_DATA_R_LENGTH, 2195 .max_write_len = MLXBF_I2C_MASTER_DATA_W_LENGTH, 2196 }; 2197 2198 static const struct acpi_device_id mlxbf_i2c_acpi_ids[] = { 2199 { "MLNXBF03", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1] }, 2200 { "MLNXBF23", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2] }, 2201 { "MLNXBF31", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_3] }, 2202 {}, 2203 }; 2204 2205 MODULE_DEVICE_TABLE(acpi, mlxbf_i2c_acpi_ids); 2206 2207 static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv) 2208 { 2209 const struct acpi_device_id *aid; 2210 u64 bus_id; 2211 int ret; 2212 2213 if (acpi_disabled) 2214 return -ENOENT; 2215 2216 aid = acpi_match_device(mlxbf_i2c_acpi_ids, dev); 2217 if (!aid) 2218 return -ENODEV; 2219 2220 priv->chip = (struct mlxbf_i2c_chip_info *)aid->driver_data; 2221 2222 ret = acpi_dev_uid_to_integer(ACPI_COMPANION(dev), &bus_id); 2223 if (ret) { 2224 dev_err(dev, "Cannot retrieve UID\n"); 2225 return ret; 2226 } 2227 2228 priv->bus = bus_id; 2229 2230 return 0; 2231 } 2232 2233 static int mlxbf_i2c_probe(struct platform_device *pdev) 2234 { 2235 struct device *dev = &pdev->dev; 2236 struct mlxbf_i2c_priv *priv; 2237 struct i2c_adapter *adap; 2238 u32 resource_version; 2239 int irq, ret; 2240 2241 priv = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_priv), GFP_KERNEL); 2242 if (!priv) 2243 return -ENOMEM; 2244 2245 ret = mlxbf_i2c_acpi_probe(dev, priv); 2246 if (ret < 0) 2247 return ret; 2248 2249 /* This property allows the driver to stay backward compatible with older 2250 * ACPI tables. 2251 * Starting BlueField-3 SoC, the "smbus" resource was broken down into 3 2252 * separate resources "timer", "master" and "slave". 2253 */ 2254 if (device_property_read_u32(dev, "resource_version", &resource_version)) 2255 resource_version = 0; 2256 2257 priv->resource_version = resource_version; 2258 2259 if (priv->chip->type < MLXBF_I2C_CHIP_TYPE_3 && resource_version == 0) { 2260 priv->timer = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), GFP_KERNEL); 2261 if (!priv->timer) 2262 return -ENOMEM; 2263 2264 priv->mst = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), GFP_KERNEL); 2265 if (!priv->mst) 2266 return -ENOMEM; 2267 2268 priv->slv = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), GFP_KERNEL); 2269 if (!priv->slv) 2270 return -ENOMEM; 2271 2272 ret = mlxbf_i2c_init_resource(pdev, &priv->smbus, 2273 MLXBF_I2C_SMBUS_RES); 2274 if (ret < 0) 2275 return dev_err_probe(dev, ret, "Cannot fetch smbus resource info"); 2276 2277 priv->timer->io = priv->smbus->io; 2278 priv->mst->io = priv->smbus->io + MLXBF_I2C_MST_ADDR_OFFSET; 2279 priv->slv->io = priv->smbus->io + MLXBF_I2C_SLV_ADDR_OFFSET; 2280 } else { 2281 ret = mlxbf_i2c_init_resource(pdev, &priv->timer, 2282 MLXBF_I2C_SMBUS_TIMER_RES); 2283 if (ret < 0) 2284 return dev_err_probe(dev, ret, "Cannot fetch timer resource info"); 2285 2286 ret = mlxbf_i2c_init_resource(pdev, &priv->mst, 2287 MLXBF_I2C_SMBUS_MST_RES); 2288 if (ret < 0) 2289 return dev_err_probe(dev, ret, "Cannot fetch master resource info"); 2290 2291 ret = mlxbf_i2c_init_resource(pdev, &priv->slv, 2292 MLXBF_I2C_SMBUS_SLV_RES); 2293 if (ret < 0) 2294 return dev_err_probe(dev, ret, "Cannot fetch slave resource info"); 2295 } 2296 2297 ret = mlxbf_i2c_init_resource(pdev, &priv->mst_cause, 2298 MLXBF_I2C_MST_CAUSE_RES); 2299 if (ret < 0) 2300 return dev_err_probe(dev, ret, "Cannot fetch cause master resource info"); 2301 2302 ret = mlxbf_i2c_init_resource(pdev, &priv->slv_cause, 2303 MLXBF_I2C_SLV_CAUSE_RES); 2304 if (ret < 0) 2305 return dev_err_probe(dev, ret, "Cannot fetch cause slave resource info"); 2306 2307 adap = &priv->adap; 2308 adap->owner = THIS_MODULE; 2309 adap->class = I2C_CLASS_HWMON; 2310 adap->algo = &mlxbf_i2c_algo; 2311 adap->quirks = &mlxbf_i2c_quirks; 2312 adap->dev.parent = dev; 2313 adap->dev.of_node = dev->of_node; 2314 adap->nr = priv->bus; 2315 2316 snprintf(adap->name, sizeof(adap->name), "i2c%d", adap->nr); 2317 i2c_set_adapdata(adap, priv); 2318 2319 /* Read Core PLL frequency. */ 2320 ret = mlxbf_i2c_calculate_corepll_freq(pdev, priv); 2321 if (ret < 0) { 2322 dev_err(dev, "cannot get core clock frequency\n"); 2323 /* Set to default value. */ 2324 priv->frequency = MLXBF_I2C_COREPLL_FREQ; 2325 } 2326 2327 /* 2328 * Initialize master. 2329 * Note that a physical bus might be shared among Linux and firmware 2330 * (e.g., ATF). Thus, the bus should be initialized and ready and 2331 * bus initialization would be unnecessary. This requires additional 2332 * knowledge about physical busses. But, since an extra initialization 2333 * does not really hurt, then keep the code as is. 2334 */ 2335 ret = mlxbf_i2c_init_master(pdev, priv); 2336 if (ret < 0) 2337 return dev_err_probe(dev, ret, "failed to initialize smbus master %d", 2338 priv->bus); 2339 2340 mlxbf_i2c_init_timings(pdev, priv); 2341 2342 mlxbf_i2c_init_slave(pdev, priv); 2343 2344 irq = platform_get_irq(pdev, 0); 2345 if (irq < 0) 2346 return irq; 2347 ret = devm_request_irq(dev, irq, mlxbf_i2c_irq, 2348 IRQF_SHARED | IRQF_PROBE_SHARED, 2349 dev_name(dev), priv); 2350 if (ret < 0) 2351 return dev_err_probe(dev, ret, "Cannot get irq %d\n", irq); 2352 2353 priv->irq = irq; 2354 2355 platform_set_drvdata(pdev, priv); 2356 2357 ret = i2c_add_numbered_adapter(adap); 2358 if (ret < 0) 2359 return ret; 2360 2361 mutex_lock(&mlxbf_i2c_bus_lock); 2362 mlxbf_i2c_bus_count++; 2363 mutex_unlock(&mlxbf_i2c_bus_lock); 2364 2365 return 0; 2366 } 2367 2368 static void mlxbf_i2c_remove(struct platform_device *pdev) 2369 { 2370 struct mlxbf_i2c_priv *priv = platform_get_drvdata(pdev); 2371 struct device *dev = &pdev->dev; 2372 struct resource *params; 2373 2374 if (priv->chip->type < MLXBF_I2C_CHIP_TYPE_3 && priv->resource_version == 0) { 2375 params = priv->smbus->params; 2376 devm_release_mem_region(dev, params->start, resource_size(params)); 2377 } else { 2378 params = priv->timer->params; 2379 devm_release_mem_region(dev, params->start, resource_size(params)); 2380 2381 params = priv->mst->params; 2382 devm_release_mem_region(dev, params->start, resource_size(params)); 2383 2384 params = priv->slv->params; 2385 devm_release_mem_region(dev, params->start, resource_size(params)); 2386 } 2387 2388 params = priv->mst_cause->params; 2389 devm_release_mem_region(dev, params->start, resource_size(params)); 2390 2391 params = priv->slv_cause->params; 2392 devm_release_mem_region(dev, params->start, resource_size(params)); 2393 2394 /* 2395 * Release shared resources. This should be done when releasing 2396 * the I2C controller. 2397 */ 2398 mutex_lock(&mlxbf_i2c_bus_lock); 2399 if (--mlxbf_i2c_bus_count == 0) { 2400 mlxbf_i2c_release_coalesce(pdev, priv); 2401 mlxbf_i2c_release_corepll(pdev, priv); 2402 mlxbf_i2c_release_gpio(pdev, priv); 2403 } 2404 mutex_unlock(&mlxbf_i2c_bus_lock); 2405 2406 devm_free_irq(dev, priv->irq, priv); 2407 2408 i2c_del_adapter(&priv->adap); 2409 } 2410 2411 static struct platform_driver mlxbf_i2c_driver = { 2412 .probe = mlxbf_i2c_probe, 2413 .remove = mlxbf_i2c_remove, 2414 .driver = { 2415 .name = "i2c-mlxbf", 2416 .acpi_match_table = ACPI_PTR(mlxbf_i2c_acpi_ids), 2417 }, 2418 }; 2419 2420 static int __init mlxbf_i2c_init(void) 2421 { 2422 mutex_init(&mlxbf_i2c_coalesce_lock); 2423 mutex_init(&mlxbf_i2c_corepll_lock); 2424 mutex_init(&mlxbf_i2c_gpio_lock); 2425 2426 mutex_init(&mlxbf_i2c_bus_lock); 2427 2428 return platform_driver_register(&mlxbf_i2c_driver); 2429 } 2430 module_init(mlxbf_i2c_init); 2431 2432 static void __exit mlxbf_i2c_exit(void) 2433 { 2434 platform_driver_unregister(&mlxbf_i2c_driver); 2435 2436 mutex_destroy(&mlxbf_i2c_bus_lock); 2437 2438 mutex_destroy(&mlxbf_i2c_gpio_lock); 2439 mutex_destroy(&mlxbf_i2c_corepll_lock); 2440 mutex_destroy(&mlxbf_i2c_coalesce_lock); 2441 } 2442 module_exit(mlxbf_i2c_exit); 2443 2444 MODULE_DESCRIPTION("Mellanox BlueField I2C bus driver"); 2445 MODULE_AUTHOR("Khalil Blaiech <kblaiech@nvidia.com>"); 2446 MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>"); 2447 MODULE_LICENSE("GPL v2"); 2448