1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Loongson-2K0300 I2C controller driver 4 * 5 * Copyright (C) 2025-2026 Loongson Technology Corporation Limited 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/clk.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/i2c.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/property.h> 18 #include <linux/regmap.h> 19 #include <linux/time.h> 20 #include <linux/types.h> 21 #include <linux/units.h> 22 23 /* Loongson-2 fast I2C offset registers */ 24 #define LOONGSON2_I2C_CR1 0x00 /* I2C control 1 register */ 25 #define LOONGSON2_I2C_CR2 0x04 /* I2C control 2 register */ 26 #define LOONGSON2_I2C_OAR 0x08 /* I2C slave address register */ 27 #define LOONGSON2_I2C_DR 0x10 /* I2C data register */ 28 #define LOONGSON2_I2C_SR1 0x14 /* I2C status 1 register */ 29 #define LOONGSON2_I2C_SR2 0x18 /* I2C status 2 register */ 30 #define LOONGSON2_I2C_CCR 0x1c /* I2C clock control register */ 31 #define LOONGSON2_I2C_TRISE 0x20 /* I2C trise register */ 32 #define LOONGSON2_I2C_FLTR 0x24 33 34 /* Bitfields of I2C control 1 register */ 35 #define LOONGSON2_I2C_CR1_PE BIT(0) /* Peripheral enable */ 36 #define LOONGSON2_I2C_CR1_START BIT(8) /* Start generation */ 37 #define LOONGSON2_I2C_CR1_STOP BIT(9) /* Stop generation */ 38 #define LOONGSON2_I2C_CR1_ACK BIT(10) /* Acknowledge enable */ 39 #define LOONGSON2_I2C_CR1_POS BIT(11) /* Acknowledge/PEC Position (for data reception) */ 40 41 #define LOONGSON2_I2C_CR1_OP_MASK (LOONGSON2_I2C_CR1_START | LOONGSON2_I2C_CR1_STOP) 42 43 /* Bitfields of I2C control 2 register */ 44 #define LOONGSON2_I2C_CR2_FREQ GENMASK(5, 0) /* APB Clock Frequency in MHz */ 45 #define LOONGSON2_I2C_CR2_ITERREN BIT(8) /* Fault-Class Interrupt Enable */ 46 #define LOONGSON2_I2C_CR2_ITEVTEN BIT(9) /* Event-Based Interrupt Enable */ 47 #define LOONGSON2_I2C_CR2_ITBUFEN BIT(10) /* Cache-Class Interrupt Enable */ 48 49 #define LOONGSON2_I2C_CR2_INT_MASK \ 50 (LOONGSON2_I2C_CR2_ITBUFEN | LOONGSON2_I2C_CR2_ITEVTEN | LOONGSON2_I2C_CR2_ITERREN) 51 52 /* Bitfields of I2C status 1 register */ 53 #define LOONGSON2_I2C_SR1_SB BIT(0) /* Start bit (Master mode) */ 54 #define LOONGSON2_I2C_SR1_ADDR BIT(1) /* Address sent (master mode) */ 55 #define LOONGSON2_I2C_SR1_BTF BIT(2) /* Byte transfer finished */ 56 #define LOONGSON2_I2C_SR1_RXNE BIT(6) /* Data register not empty (receivers) */ 57 #define LOONGSON2_I2C_SR1_TXE BIT(7) /* Data register empty (transmitters) */ 58 #define LOONGSON2_I2C_SR1_BERR BIT(8) /* Bus error */ 59 #define LOONGSON2_I2C_SR1_ARLO BIT(9) /* Arbitration lost (master mode) */ 60 #define LOONGSON2_I2C_SR1_AF BIT(10) /* Acknowledge failure */ 61 62 #define LOONGSON2_I2C_SR1_ITEVTEN_MASK \ 63 (LOONGSON2_I2C_SR1_BTF | LOONGSON2_I2C_SR1_ADDR | LOONGSON2_I2C_SR1_SB) 64 #define LOONGSON2_I2C_SR1_ITBUFEN_MASK (LOONGSON2_I2C_SR1_TXE | LOONGSON2_I2C_SR1_RXNE) 65 #define LOONGSON2_I2C_SR1_ITERREN_MASK \ 66 (LOONGSON2_I2C_SR1_AF | LOONGSON2_I2C_SR1_ARLO | LOONGSON2_I2C_SR1_BERR) 67 68 /* Bitfields of I2C status 2 register */ 69 #define LOONGSON2_I2C_SR2_MSL BIT(0) /* Master/slave */ 70 #define LOONGSON2_I2C_SR2_BUSY BIT(1) /* Bus busy */ 71 #define LOONGSON2_I2C_SR2_TRA BIT(2) /* Transmitter/receiver */ 72 #define LOONGSON2_I2C_SR2_GENCALL BIT(4) /* General call address (Slave mode) */ 73 74 /* Bitfields of I2C clock control register */ 75 #define LOONGSON2_I2C_CCR_CCR GENMASK(11, 0) 76 #define LOONGSON2_I2C_CCR_DUTY BIT(14) 77 #define LOONGSON2_I2C_CCR_FS BIT(15) 78 79 /* Bitfields of I2C trise register */ 80 #define LOONGSON2_I2C_TRISE_SCL GENMASK(5, 0) 81 82 #define LOONGSON2_I2C_FREE_SLEEP_US 10 83 #define LOONGSON2_I2C_FREE_TIMEOUT_US (2 * USEC_PER_MSEC) 84 85 /** 86 * struct loongson2_i2c_msg - client specific data 87 * @buf: data buffer 88 * @count: number of bytes to be transferred 89 * @result: result of the transfer 90 * @addr: 8-bit slave addr, including r/w bit 91 * @stop: last I2C msg to be sent, i.e. STOP to be generated 92 */ 93 struct loongson2_i2c_msg { 94 u8 *buf; 95 u32 count; 96 int result; 97 u8 addr; 98 bool stop; 99 }; 100 101 /** 102 * struct loongson2_i2c_priv - private data of the controller 103 * @adapter: I2C adapter for this controller 104 * @complete: completion of I2C message 105 * @clk: hw i2c clock 106 * @regmap: regmap of the I2C device 107 * @parent_rate_MHz: I2C clock parent rate 108 * @msg: I2C transfer information 109 */ 110 struct loongson2_i2c_priv { 111 struct i2c_adapter adapter; 112 struct completion complete; 113 struct clk *clk; 114 struct regmap *regmap; 115 unsigned long parent_rate_MHz; 116 struct loongson2_i2c_msg msg; 117 }; 118 119 static void loongson2_i2c_disable_irq(struct loongson2_i2c_priv *priv) 120 { 121 regmap_update_bits(priv->regmap, LOONGSON2_I2C_CR2, LOONGSON2_I2C_CR2_INT_MASK, 0); 122 } 123 124 static void loongson2_i2c_read_msg(struct loongson2_i2c_priv *priv) 125 { 126 struct loongson2_i2c_msg *msg = &priv->msg; 127 u32 rbuf; 128 129 regmap_read(priv->regmap, LOONGSON2_I2C_DR, &rbuf); 130 *msg->buf++ = rbuf; 131 msg->count--; 132 } 133 134 static void loongson2_i2c_write_msg(struct loongson2_i2c_priv *priv, u8 byte) 135 { 136 regmap_write(priv->regmap, LOONGSON2_I2C_DR, byte); 137 } 138 139 static void loongson2_i2c_terminate_xfer(struct loongson2_i2c_priv *priv) 140 { 141 struct loongson2_i2c_msg *msg = &priv->msg; 142 143 loongson2_i2c_disable_irq(priv); 144 regmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_OP_MASK, 145 msg->stop ? LOONGSON2_I2C_CR1_STOP : LOONGSON2_I2C_CR1_START); 146 complete(&priv->complete); 147 } 148 149 static void loongson2_i2c_handle_write(struct loongson2_i2c_priv *priv) 150 { 151 struct loongson2_i2c_msg *msg = &priv->msg; 152 153 if (msg->count) { 154 loongson2_i2c_write_msg(priv, *msg->buf++); 155 if (!--msg->count) 156 regmap_update_bits(priv->regmap, LOONGSON2_I2C_CR2, 157 LOONGSON2_I2C_CR2_ITBUFEN, 0); 158 } else { 159 loongson2_i2c_terminate_xfer(priv); 160 } 161 } 162 163 static void loongson2_i2c_handle_rx_addr(struct loongson2_i2c_priv *priv) 164 { 165 struct loongson2_i2c_msg *msg = &priv->msg; 166 167 switch (msg->count) { 168 case 0: 169 loongson2_i2c_terminate_xfer(priv); 170 break; 171 case 1: 172 /* Enable NACK and reset POS (Acknowledge position) */ 173 regmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, 174 LOONGSON2_I2C_CR1_ACK | LOONGSON2_I2C_CR1_POS, 0); 175 /* Set STOP or RepSTART */ 176 regmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_OP_MASK, 177 msg->stop ? LOONGSON2_I2C_CR1_STOP : LOONGSON2_I2C_CR1_START); 178 break; 179 case 2: 180 /* Enable NACK */ 181 regmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_ACK, 0); 182 /* Set POS (NACK position) */ 183 regmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_POS, 184 LOONGSON2_I2C_CR1_POS); 185 break; 186 187 default: 188 /* Enable ACK */ 189 regmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_ACK, 190 LOONGSON2_I2C_CR1_ACK); 191 /* Reset POS (ACK position) */ 192 regmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_POS, 0); 193 break; 194 } 195 } 196 197 static void loongson2_i2c_isr_error(u32 status, void *data) 198 { 199 struct loongson2_i2c_priv *priv = data; 200 struct loongson2_i2c_msg *msg = &priv->msg; 201 202 /* Arbitration lost */ 203 if (status & LOONGSON2_I2C_SR1_ARLO) { 204 regmap_update_bits(priv->regmap, LOONGSON2_I2C_SR1, LOONGSON2_I2C_SR1_ARLO, 0); 205 msg->result = -EAGAIN; 206 goto out; 207 } 208 209 /* 210 * Acknowledge failure: 211 * In master transmitter mode a Stop must be generated by software. 212 */ 213 if (status & LOONGSON2_I2C_SR1_AF) { 214 regmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_STOP, 215 LOONGSON2_I2C_CR1_STOP); 216 regmap_update_bits(priv->regmap, LOONGSON2_I2C_SR1, LOONGSON2_I2C_SR1_AF, 0); 217 msg->result = -EIO; 218 goto out; 219 } 220 221 /* Bus error */ 222 if (status & LOONGSON2_I2C_SR1_BERR) { 223 regmap_update_bits(priv->regmap, LOONGSON2_I2C_SR1, LOONGSON2_I2C_SR1_BERR, 0); 224 msg->result = -EIO; 225 goto out; 226 } 227 228 out: 229 loongson2_i2c_disable_irq(priv); 230 complete(&priv->complete); 231 } 232 233 static void loongson2_i2c_handle_read(struct loongson2_i2c_priv *priv) 234 { 235 struct loongson2_i2c_msg *msg = &priv->msg; 236 237 switch (msg->count) { 238 case 1: 239 loongson2_i2c_disable_irq(priv); 240 loongson2_i2c_read_msg(priv); 241 complete(&priv->complete); 242 break; 243 case 2: 244 case 3: 245 /* 246 * For 2-byte/3-byte reception and for N-byte reception with N > 3, we have to 247 * wait for byte transferred finished event before reading data. 248 * Just disable buffer interrupt in order to avoid another system preemption due 249 * to RX not empty event. 250 */ 251 regmap_update_bits(priv->regmap, LOONGSON2_I2C_CR2, LOONGSON2_I2C_CR2_ITBUFEN, 0); 252 break; 253 default: 254 /* 255 * For N byte reception with N > 3 we directly read data register 256 * until N-2 data. 257 */ 258 loongson2_i2c_read_msg(priv); 259 break; 260 } 261 } 262 263 static void loongson2_i2c_handle_rx_done(struct loongson2_i2c_priv *priv) 264 { 265 struct loongson2_i2c_msg *msg = &priv->msg; 266 267 switch (msg->count) { 268 case 2: 269 /* 270 * The STOP/START bit has to be set before reading the last two bytes. 271 * After that, we could read the last two bytes. 272 */ 273 regmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_OP_MASK, 274 msg->stop ? LOONGSON2_I2C_CR1_STOP : LOONGSON2_I2C_CR1_START); 275 276 for (unsigned int i = msg->count; i > 0; i--) 277 loongson2_i2c_read_msg(priv); 278 279 loongson2_i2c_disable_irq(priv); 280 281 complete(&priv->complete); 282 break; 283 case 3: 284 /* 285 * In order to generate the NACK after the last received data byte, enable NACK 286 * before reading N-2 data. 287 */ 288 regmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_ACK, 0); 289 loongson2_i2c_read_msg(priv); 290 break; 291 default: 292 loongson2_i2c_read_msg(priv); 293 break; 294 } 295 } 296 297 static irqreturn_t loongson2_i2c_isr_event(int irq, void *data) 298 { 299 struct loongson2_i2c_priv *priv = data; 300 struct device *dev = regmap_get_device(priv->regmap); 301 struct loongson2_i2c_msg *msg = &priv->msg; 302 u32 status, ien, event, cr2, possible_status; 303 304 regmap_read(priv->regmap, LOONGSON2_I2C_SR1, &status); 305 if (status & LOONGSON2_I2C_SR1_ITERREN_MASK) { 306 loongson2_i2c_isr_error(status, data); 307 return IRQ_HANDLED; 308 } 309 310 regmap_read(priv->regmap, LOONGSON2_I2C_CR2, &cr2); 311 ien = cr2 & LOONGSON2_I2C_CR2_INT_MASK; 312 313 /* Update possible_status if buffer interrupt is enabled */ 314 possible_status = LOONGSON2_I2C_SR1_ITEVTEN_MASK; 315 if (ien & LOONGSON2_I2C_CR2_ITBUFEN) 316 possible_status |= LOONGSON2_I2C_SR1_ITBUFEN_MASK; 317 318 event = status & possible_status; 319 if (!event) { 320 dev_dbg(dev, "spurious evt IRQ (status=0x%08x, ien=0x%08x)\n", status, ien); 321 return IRQ_NONE; 322 } 323 324 /* Start condition generated */ 325 if (event & LOONGSON2_I2C_SR1_SB) 326 loongson2_i2c_write_msg(priv, msg->addr); 327 328 /* I2C Address sent */ 329 if (event & LOONGSON2_I2C_SR1_ADDR) { 330 if (msg->addr & I2C_M_RD) 331 loongson2_i2c_handle_rx_addr(priv); 332 /* Clear ADDR flag */ 333 regmap_read(priv->regmap, LOONGSON2_I2C_SR2, &status); 334 /* Enable buffer interrupts for RX/TX not empty events */ 335 regmap_update_bits(priv->regmap, LOONGSON2_I2C_CR2, LOONGSON2_I2C_CR2_ITBUFEN, 336 LOONGSON2_I2C_CR2_ITBUFEN); 337 } 338 339 /* TX empty */ 340 if ((event & LOONGSON2_I2C_SR1_TXE) && !(msg->addr & I2C_M_RD)) 341 loongson2_i2c_handle_write(priv); 342 343 /* RX not empty */ 344 if ((event & LOONGSON2_I2C_SR1_RXNE) && (msg->addr & I2C_M_RD)) 345 loongson2_i2c_handle_read(priv); 346 347 /* 348 * The BTF (Byte Transfer finished) event occurs when: 349 * - in reception: a new byte is received in the shift register 350 * but the previous byte has not been read yet from data register 351 * - in transmission: a new byte should be sent but the data register 352 * has not been written yet 353 */ 354 if (event & LOONGSON2_I2C_SR1_BTF) { 355 if (msg->addr & I2C_M_RD) 356 loongson2_i2c_handle_rx_done(priv); 357 else 358 loongson2_i2c_handle_write(priv); 359 } 360 361 return IRQ_HANDLED; 362 } 363 364 static int loongson2_i2c_xfer_msg(struct loongson2_i2c_priv *priv, struct i2c_msg *msg, 365 bool is_stop) 366 { 367 struct loongson2_i2c_msg *l_msg = &priv->msg; 368 unsigned long timeout; 369 370 l_msg->addr = i2c_8bit_addr_from_msg(msg); 371 l_msg->buf = msg->buf; 372 l_msg->count = msg->len; 373 l_msg->stop = is_stop; 374 l_msg->result = 0; 375 376 reinit_completion(&priv->complete); 377 378 /* Enable events and errors interrupts */ 379 regmap_update_bits(priv->regmap, LOONGSON2_I2C_CR2, 380 LOONGSON2_I2C_CR2_ITEVTEN | LOONGSON2_I2C_CR2_ITERREN, 381 LOONGSON2_I2C_CR2_ITEVTEN | LOONGSON2_I2C_CR2_ITERREN); 382 383 timeout = wait_for_completion_timeout(&priv->complete, priv->adapter.timeout); 384 if (!timeout) 385 return -ETIMEDOUT; 386 387 return l_msg->result; 388 } 389 390 static int loongson2_i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], int num) 391 { 392 struct loongson2_i2c_priv *priv = i2c_get_adapdata(i2c_adap); 393 struct device *dev = regmap_get_device(priv->regmap); 394 unsigned int status; 395 int ret; 396 397 /* Wait I2C bus free */ 398 ret = regmap_read_poll_timeout(priv->regmap, LOONGSON2_I2C_SR2, status, 399 !(status & LOONGSON2_I2C_SR2_BUSY), 400 LOONGSON2_I2C_FREE_SLEEP_US, 401 LOONGSON2_I2C_FREE_TIMEOUT_US); 402 if (ret) { 403 dev_dbg(dev, "The I2C bus is busy now.\n"); 404 return ret; 405 } 406 407 /* Start generation */ 408 regmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_START, 409 LOONGSON2_I2C_CR1_START); 410 411 for (unsigned int i = 0; i < num; i++) { 412 ret = loongson2_i2c_xfer_msg(priv, &msgs[i], i == num - 1); 413 if (ret < 0) 414 return ret; 415 } 416 417 return num; 418 } 419 420 static u32 loongson2_i2c_func(struct i2c_adapter *adap) 421 { 422 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 423 } 424 425 static const struct i2c_algorithm loongson2_i2c_algo = { 426 .xfer = loongson2_i2c_xfer, 427 .functionality = loongson2_i2c_func, 428 }; 429 430 static int loongson2_i2c_adjust_bus_speed(struct loongson2_i2c_priv *priv) 431 { 432 struct device *dev = regmap_get_device(priv->regmap); 433 struct i2c_timings i2c_t; 434 u32 val, freq_MHz, ccr; 435 436 i2c_parse_fw_timings(dev, &i2c_t, true); 437 priv->parent_rate_MHz = clk_get_rate(priv->clk); 438 439 if (i2c_t.bus_freq_hz == I2C_MAX_STANDARD_MODE_FREQ) { 440 /* Select Standard mode */ 441 ccr = 0; 442 val = DIV_ROUND_UP(priv->parent_rate_MHz, i2c_t.bus_freq_hz * 2); 443 } else if (i2c_t.bus_freq_hz == I2C_MAX_FAST_MODE_FREQ) { 444 /* Select Fast mode */ 445 ccr = LOONGSON2_I2C_CCR_FS; 446 val = DIV_ROUND_UP(priv->parent_rate_MHz, i2c_t.bus_freq_hz * 3); 447 } else { 448 return dev_err_probe(dev, -EINVAL, "Unsupported speed (%uHz)\n", i2c_t.bus_freq_hz); 449 } 450 451 FIELD_MODIFY(LOONGSON2_I2C_CCR_CCR, &ccr, val); 452 regmap_write(priv->regmap, LOONGSON2_I2C_CCR, ccr); 453 454 freq_MHz = DIV_ROUND_UP(priv->parent_rate_MHz, HZ_PER_MHZ); 455 regmap_update_bits(priv->regmap, LOONGSON2_I2C_CR2, LOONGSON2_I2C_CR2_FREQ, 456 FIELD_GET(LOONGSON2_I2C_CR2_FREQ, freq_MHz)); 457 458 regmap_update_bits(priv->regmap, LOONGSON2_I2C_TRISE, LOONGSON2_I2C_TRISE_SCL, 459 LOONGSON2_I2C_TRISE_SCL); 460 461 /* Enable I2C */ 462 regmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_PE, 463 LOONGSON2_I2C_CR1_PE); 464 465 return 0; 466 } 467 468 static const struct regmap_config loongson2_i2c_regmap_config = { 469 .reg_bits = 32, 470 .val_bits = 32, 471 .reg_stride = 4, 472 .max_register = LOONGSON2_I2C_TRISE, 473 }; 474 475 static int loongson2_i2c_probe(struct platform_device *pdev) 476 { 477 struct device *dev = &pdev->dev; 478 struct loongson2_i2c_priv *priv; 479 struct i2c_adapter *adap; 480 void __iomem *base; 481 int irq, ret; 482 483 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 484 if (!priv) 485 return -ENOMEM; 486 487 base = devm_platform_ioremap_resource(pdev, 0); 488 if (IS_ERR(base)) 489 return PTR_ERR(base); 490 491 priv->regmap = devm_regmap_init_mmio(dev, base, &loongson2_i2c_regmap_config); 492 if (IS_ERR(priv->regmap)) 493 return dev_err_probe(dev, PTR_ERR(priv->regmap), "Failed to init regmap.\n"); 494 495 priv->clk = devm_clk_get_enabled(dev, NULL); 496 if (IS_ERR(priv->clk)) 497 return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to enable clock.\n"); 498 499 irq = platform_get_irq(pdev, 0); 500 if (irq < 0) 501 return irq; 502 503 adap = &priv->adapter; 504 adap->retries = 5; 505 adap->nr = pdev->id; 506 adap->dev.parent = dev; 507 adap->owner = THIS_MODULE; 508 adap->algo = &loongson2_i2c_algo; 509 adap->timeout = 2 * HZ; 510 device_set_node(&adap->dev, dev_fwnode(dev)); 511 i2c_set_adapdata(adap, priv); 512 strscpy(adap->name, pdev->name); 513 init_completion(&priv->complete); 514 platform_set_drvdata(pdev, priv); 515 516 ret = loongson2_i2c_adjust_bus_speed(priv); 517 if (ret) 518 return ret; 519 520 ret = devm_request_irq(dev, irq, loongson2_i2c_isr_event, IRQF_SHARED, pdev->name, priv); 521 if (ret) 522 return ret; 523 524 return devm_i2c_add_adapter(dev, adap); 525 } 526 527 static const struct of_device_id loongson2_i2c_id_table[] = { 528 { .compatible = "loongson,ls2k0300-i2c" }, 529 { /* sentinel */ } 530 }; 531 MODULE_DEVICE_TABLE(of, loongson2_i2c_id_table); 532 533 static struct platform_driver loongson2_i2c_driver = { 534 .driver = { 535 .name = "loongson2-i2c-v2", 536 .of_match_table = loongson2_i2c_id_table, 537 }, 538 .probe = loongson2_i2c_probe, 539 }; 540 module_platform_driver(loongson2_i2c_driver); 541 542 MODULE_DESCRIPTION("Loongson-2K0300 I2C bus driver"); 543 MODULE_AUTHOR("Loongson Technology Corporation Limited"); 544 MODULE_LICENSE("GPL"); 545