1 /* 2 * Copyright (C) 2011 NXP Semiconductors 3 * 4 * Code portions referenced from the i2x-pxa and i2c-pnx drivers 5 * 6 * Make SMBus byte and word transactions work on LPC178x/7x 7 * Copyright (c) 2012 8 * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com 9 * Anton Protopopov, Emcraft Systems, antonp@emcraft.com 10 * 11 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com> 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 */ 19 20 #include <linux/clk.h> 21 #include <linux/errno.h> 22 #include <linux/i2c.h> 23 #include <linux/interrupt.h> 24 #include <linux/io.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/of.h> 28 #include <linux/of_device.h> 29 #include <linux/platform_device.h> 30 #include <linux/sched.h> 31 #include <linux/time.h> 32 33 /* LPC24xx register offsets and bits */ 34 #define LPC24XX_I2CONSET 0x00 35 #define LPC24XX_I2STAT 0x04 36 #define LPC24XX_I2DAT 0x08 37 #define LPC24XX_I2ADDR 0x0c 38 #define LPC24XX_I2SCLH 0x10 39 #define LPC24XX_I2SCLL 0x14 40 #define LPC24XX_I2CONCLR 0x18 41 42 #define LPC24XX_AA BIT(2) 43 #define LPC24XX_SI BIT(3) 44 #define LPC24XX_STO BIT(4) 45 #define LPC24XX_STA BIT(5) 46 #define LPC24XX_I2EN BIT(6) 47 48 #define LPC24XX_STO_AA (LPC24XX_STO | LPC24XX_AA) 49 #define LPC24XX_CLEAR_ALL (LPC24XX_AA | LPC24XX_SI | LPC24XX_STO | \ 50 LPC24XX_STA | LPC24XX_I2EN) 51 52 /* I2C SCL clock has different duty cycle depending on mode */ 53 #define I2C_STD_MODE_DUTY 46 54 #define I2C_FAST_MODE_DUTY 36 55 #define I2C_FAST_MODE_PLUS_DUTY 38 56 57 /* 58 * 26 possible I2C status codes, but codes applicable only 59 * to master are listed here and used in this driver 60 */ 61 enum { 62 M_BUS_ERROR = 0x00, 63 M_START = 0x08, 64 M_REPSTART = 0x10, 65 MX_ADDR_W_ACK = 0x18, 66 MX_ADDR_W_NACK = 0x20, 67 MX_DATA_W_ACK = 0x28, 68 MX_DATA_W_NACK = 0x30, 69 M_DATA_ARB_LOST = 0x38, 70 MR_ADDR_R_ACK = 0x40, 71 MR_ADDR_R_NACK = 0x48, 72 MR_DATA_R_ACK = 0x50, 73 MR_DATA_R_NACK = 0x58, 74 M_I2C_IDLE = 0xf8, 75 }; 76 77 struct lpc2k_i2c { 78 void __iomem *base; 79 struct clk *clk; 80 int irq; 81 wait_queue_head_t wait; 82 struct i2c_adapter adap; 83 struct i2c_msg *msg; 84 int msg_idx; 85 int msg_status; 86 int is_last; 87 }; 88 89 static void i2c_lpc2k_reset(struct lpc2k_i2c *i2c) 90 { 91 /* Will force clear all statuses */ 92 writel(LPC24XX_CLEAR_ALL, i2c->base + LPC24XX_I2CONCLR); 93 writel(0, i2c->base + LPC24XX_I2ADDR); 94 writel(LPC24XX_I2EN, i2c->base + LPC24XX_I2CONSET); 95 } 96 97 static int i2c_lpc2k_clear_arb(struct lpc2k_i2c *i2c) 98 { 99 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 100 101 /* 102 * If the transfer needs to abort for some reason, we'll try to 103 * force a stop condition to clear any pending bus conditions 104 */ 105 writel(LPC24XX_STO, i2c->base + LPC24XX_I2CONSET); 106 107 /* Wait for status change */ 108 while (readl(i2c->base + LPC24XX_I2STAT) != M_I2C_IDLE) { 109 if (time_after(jiffies, timeout)) { 110 /* Bus was not idle, try to reset adapter */ 111 i2c_lpc2k_reset(i2c); 112 return -EBUSY; 113 } 114 115 cpu_relax(); 116 } 117 118 return 0; 119 } 120 121 static void i2c_lpc2k_pump_msg(struct lpc2k_i2c *i2c) 122 { 123 unsigned char data; 124 u32 status; 125 126 /* 127 * I2C in the LPC2xxx series is basically a state machine. 128 * Just run through the steps based on the current status. 129 */ 130 status = readl(i2c->base + LPC24XX_I2STAT); 131 132 switch (status) { 133 case M_START: 134 case M_REPSTART: 135 /* Start bit was just sent out, send out addr and dir */ 136 data = i2c_8bit_addr_from_msg(i2c->msg); 137 138 writel(data, i2c->base + LPC24XX_I2DAT); 139 writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR); 140 break; 141 142 case MX_ADDR_W_ACK: 143 case MX_DATA_W_ACK: 144 /* 145 * Address or data was sent out with an ACK. If there is more 146 * data to send, send it now 147 */ 148 if (i2c->msg_idx < i2c->msg->len) { 149 writel(i2c->msg->buf[i2c->msg_idx], 150 i2c->base + LPC24XX_I2DAT); 151 } else if (i2c->is_last) { 152 /* Last message, send stop */ 153 writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET); 154 writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR); 155 i2c->msg_status = 0; 156 disable_irq_nosync(i2c->irq); 157 } else { 158 i2c->msg_status = 0; 159 disable_irq_nosync(i2c->irq); 160 } 161 162 i2c->msg_idx++; 163 break; 164 165 case MR_ADDR_R_ACK: 166 /* Receive first byte from slave */ 167 if (i2c->msg->len == 1) { 168 /* Last byte, return NACK */ 169 writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR); 170 } else { 171 /* Not last byte, return ACK */ 172 writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET); 173 } 174 175 writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR); 176 break; 177 178 case MR_DATA_R_NACK: 179 /* 180 * The I2C shows NACK status on reads, so we need to accept 181 * the NACK as an ACK here. This should be ok, as the real 182 * BACK would of been caught on the address write. 183 */ 184 case MR_DATA_R_ACK: 185 /* Data was received */ 186 if (i2c->msg_idx < i2c->msg->len) { 187 i2c->msg->buf[i2c->msg_idx] = 188 readl(i2c->base + LPC24XX_I2DAT); 189 } 190 191 /* If transfer is done, send STOP */ 192 if (i2c->msg_idx >= i2c->msg->len - 1 && i2c->is_last) { 193 writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET); 194 writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR); 195 i2c->msg_status = 0; 196 } 197 198 /* Message is done */ 199 if (i2c->msg_idx >= i2c->msg->len - 1) { 200 i2c->msg_status = 0; 201 disable_irq_nosync(i2c->irq); 202 } 203 204 /* 205 * One pre-last data input, send NACK to tell the slave that 206 * this is going to be the last data byte to be transferred. 207 */ 208 if (i2c->msg_idx >= i2c->msg->len - 2) { 209 /* One byte left to receive - NACK */ 210 writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR); 211 } else { 212 /* More than one byte left to receive - ACK */ 213 writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET); 214 } 215 216 writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR); 217 i2c->msg_idx++; 218 break; 219 220 case MX_ADDR_W_NACK: 221 case MX_DATA_W_NACK: 222 case MR_ADDR_R_NACK: 223 /* NACK processing is done */ 224 writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET); 225 i2c->msg_status = -ENXIO; 226 disable_irq_nosync(i2c->irq); 227 break; 228 229 case M_DATA_ARB_LOST: 230 /* Arbitration lost */ 231 i2c->msg_status = -EAGAIN; 232 233 /* Release the I2C bus */ 234 writel(LPC24XX_STA | LPC24XX_STO, i2c->base + LPC24XX_I2CONCLR); 235 disable_irq_nosync(i2c->irq); 236 break; 237 238 default: 239 /* Unexpected statuses */ 240 i2c->msg_status = -EIO; 241 disable_irq_nosync(i2c->irq); 242 break; 243 } 244 245 /* Exit on failure or all bytes transferred */ 246 if (i2c->msg_status != -EBUSY) 247 wake_up(&i2c->wait); 248 249 /* 250 * If `msg_status` is zero, then `lpc2k_process_msg()` 251 * is responsible for clearing the SI flag. 252 */ 253 if (i2c->msg_status != 0) 254 writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR); 255 } 256 257 static int lpc2k_process_msg(struct lpc2k_i2c *i2c, int msgidx) 258 { 259 /* A new transfer is kicked off by initiating a start condition */ 260 if (!msgidx) { 261 writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET); 262 } else { 263 /* 264 * A multi-message I2C transfer continues where the 265 * previous I2C transfer left off and uses the 266 * current condition of the I2C adapter. 267 */ 268 if (unlikely(i2c->msg->flags & I2C_M_NOSTART)) { 269 WARN_ON(i2c->msg->len == 0); 270 271 if (!(i2c->msg->flags & I2C_M_RD)) { 272 /* Start transmit of data */ 273 writel(i2c->msg->buf[0], 274 i2c->base + LPC24XX_I2DAT); 275 i2c->msg_idx++; 276 } 277 } else { 278 /* Start or repeated start */ 279 writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET); 280 } 281 282 writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR); 283 } 284 285 enable_irq(i2c->irq); 286 287 /* Wait for transfer completion */ 288 if (wait_event_timeout(i2c->wait, i2c->msg_status != -EBUSY, 289 msecs_to_jiffies(1000)) == 0) { 290 disable_irq_nosync(i2c->irq); 291 292 return -ETIMEDOUT; 293 } 294 295 return i2c->msg_status; 296 } 297 298 static int i2c_lpc2k_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 299 int msg_num) 300 { 301 struct lpc2k_i2c *i2c = i2c_get_adapdata(adap); 302 int ret, i; 303 u32 stat; 304 305 /* Check for bus idle condition */ 306 stat = readl(i2c->base + LPC24XX_I2STAT); 307 if (stat != M_I2C_IDLE) { 308 /* Something is holding the bus, try to clear it */ 309 return i2c_lpc2k_clear_arb(i2c); 310 } 311 312 /* Process a single message at a time */ 313 for (i = 0; i < msg_num; i++) { 314 /* Save message pointer and current message data index */ 315 i2c->msg = &msgs[i]; 316 i2c->msg_idx = 0; 317 i2c->msg_status = -EBUSY; 318 i2c->is_last = (i == (msg_num - 1)); 319 320 ret = lpc2k_process_msg(i2c, i); 321 if (ret) 322 return ret; 323 } 324 325 return msg_num; 326 } 327 328 static irqreturn_t i2c_lpc2k_handler(int irq, void *dev_id) 329 { 330 struct lpc2k_i2c *i2c = dev_id; 331 332 if (readl(i2c->base + LPC24XX_I2CONSET) & LPC24XX_SI) { 333 i2c_lpc2k_pump_msg(i2c); 334 return IRQ_HANDLED; 335 } 336 337 return IRQ_NONE; 338 } 339 340 static u32 i2c_lpc2k_functionality(struct i2c_adapter *adap) 341 { 342 /* Only emulated SMBus for now */ 343 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 344 } 345 346 static const struct i2c_algorithm i2c_lpc2k_algorithm = { 347 .master_xfer = i2c_lpc2k_xfer, 348 .functionality = i2c_lpc2k_functionality, 349 }; 350 351 static int i2c_lpc2k_probe(struct platform_device *pdev) 352 { 353 struct lpc2k_i2c *i2c; 354 struct resource *res; 355 u32 bus_clk_rate; 356 u32 scl_high; 357 u32 clkrate; 358 int ret; 359 360 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 361 if (!i2c) 362 return -ENOMEM; 363 364 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 365 i2c->base = devm_ioremap_resource(&pdev->dev, res); 366 if (IS_ERR(i2c->base)) 367 return PTR_ERR(i2c->base); 368 369 i2c->irq = platform_get_irq(pdev, 0); 370 if (i2c->irq < 0) { 371 dev_err(&pdev->dev, "can't get interrupt resource\n"); 372 return i2c->irq; 373 } 374 375 init_waitqueue_head(&i2c->wait); 376 377 i2c->clk = devm_clk_get(&pdev->dev, NULL); 378 if (IS_ERR(i2c->clk)) { 379 dev_err(&pdev->dev, "error getting clock\n"); 380 return PTR_ERR(i2c->clk); 381 } 382 383 ret = clk_prepare_enable(i2c->clk); 384 if (ret) { 385 dev_err(&pdev->dev, "unable to enable clock.\n"); 386 return ret; 387 } 388 389 ret = devm_request_irq(&pdev->dev, i2c->irq, i2c_lpc2k_handler, 0, 390 dev_name(&pdev->dev), i2c); 391 if (ret < 0) { 392 dev_err(&pdev->dev, "can't request interrupt.\n"); 393 goto fail_clk; 394 } 395 396 disable_irq_nosync(i2c->irq); 397 398 /* Place controller is a known state */ 399 i2c_lpc2k_reset(i2c); 400 401 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", 402 &bus_clk_rate); 403 if (ret) 404 bus_clk_rate = 100000; /* 100 kHz default clock rate */ 405 406 clkrate = clk_get_rate(i2c->clk); 407 if (clkrate == 0) { 408 dev_err(&pdev->dev, "can't get I2C base clock\n"); 409 ret = -EINVAL; 410 goto fail_clk; 411 } 412 413 /* Setup I2C dividers to generate clock with proper duty cycle */ 414 clkrate = clkrate / bus_clk_rate; 415 if (bus_clk_rate <= 100000) 416 scl_high = (clkrate * I2C_STD_MODE_DUTY) / 100; 417 else if (bus_clk_rate <= 400000) 418 scl_high = (clkrate * I2C_FAST_MODE_DUTY) / 100; 419 else 420 scl_high = (clkrate * I2C_FAST_MODE_PLUS_DUTY) / 100; 421 422 writel(scl_high, i2c->base + LPC24XX_I2SCLH); 423 writel(clkrate - scl_high, i2c->base + LPC24XX_I2SCLL); 424 425 platform_set_drvdata(pdev, i2c); 426 427 i2c_set_adapdata(&i2c->adap, i2c); 428 i2c->adap.owner = THIS_MODULE; 429 strlcpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name)); 430 i2c->adap.algo = &i2c_lpc2k_algorithm; 431 i2c->adap.dev.parent = &pdev->dev; 432 i2c->adap.dev.of_node = pdev->dev.of_node; 433 434 ret = i2c_add_adapter(&i2c->adap); 435 if (ret < 0) 436 goto fail_clk; 437 438 dev_info(&pdev->dev, "LPC2K I2C adapter\n"); 439 440 return 0; 441 442 fail_clk: 443 clk_disable_unprepare(i2c->clk); 444 return ret; 445 } 446 447 static int i2c_lpc2k_remove(struct platform_device *dev) 448 { 449 struct lpc2k_i2c *i2c = platform_get_drvdata(dev); 450 451 i2c_del_adapter(&i2c->adap); 452 clk_disable_unprepare(i2c->clk); 453 454 return 0; 455 } 456 457 #ifdef CONFIG_PM 458 static int i2c_lpc2k_suspend(struct device *dev) 459 { 460 struct platform_device *pdev = to_platform_device(dev); 461 struct lpc2k_i2c *i2c = platform_get_drvdata(pdev); 462 463 clk_disable(i2c->clk); 464 465 return 0; 466 } 467 468 static int i2c_lpc2k_resume(struct device *dev) 469 { 470 struct platform_device *pdev = to_platform_device(dev); 471 struct lpc2k_i2c *i2c = platform_get_drvdata(pdev); 472 473 clk_enable(i2c->clk); 474 i2c_lpc2k_reset(i2c); 475 476 return 0; 477 } 478 479 static const struct dev_pm_ops i2c_lpc2k_dev_pm_ops = { 480 .suspend_noirq = i2c_lpc2k_suspend, 481 .resume_noirq = i2c_lpc2k_resume, 482 }; 483 484 #define I2C_LPC2K_DEV_PM_OPS (&i2c_lpc2k_dev_pm_ops) 485 #else 486 #define I2C_LPC2K_DEV_PM_OPS NULL 487 #endif 488 489 static const struct of_device_id lpc2k_i2c_match[] = { 490 { .compatible = "nxp,lpc1788-i2c" }, 491 {}, 492 }; 493 MODULE_DEVICE_TABLE(of, lpc2k_i2c_match); 494 495 static struct platform_driver i2c_lpc2k_driver = { 496 .probe = i2c_lpc2k_probe, 497 .remove = i2c_lpc2k_remove, 498 .driver = { 499 .name = "lpc2k-i2c", 500 .pm = I2C_LPC2K_DEV_PM_OPS, 501 .of_match_table = lpc2k_i2c_match, 502 }, 503 }; 504 module_platform_driver(i2c_lpc2k_driver); 505 506 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); 507 MODULE_DESCRIPTION("I2C driver for LPC2xxx devices"); 508 MODULE_LICENSE("GPL"); 509 MODULE_ALIAS("platform:lpc2k-i2c"); 510