xref: /linux/drivers/i2c/busses/i2c-lpc2k.c (revision ca55b2fef3a9373fcfc30f82fd26bc7fccbda732) 
1 /*
2  * Copyright (C) 2011 NXP Semiconductors
3  *
4  * Code portions referenced from the i2x-pxa and i2c-pnx drivers
5  *
6  * Make SMBus byte and word transactions work on LPC178x/7x
7  * Copyright (c) 2012
8  * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
9  * Anton Protopopov, Emcraft Systems, antonp@emcraft.com
10  *
11  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
12  *
13  * This program is free software; you can redistribute it and/or modify
14  * it under the terms of the GNU General Public License as published by
15  * the Free Software Foundation; either version 2 of the License, or
16  * (at your option) any later version.
17  *
18  */
19 
20 #include <linux/clk.h>
21 #include <linux/errno.h>
22 #include <linux/i2c.h>
23 #include <linux/interrupt.h>
24 #include <linux/io.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/of.h>
28 #include <linux/of_device.h>
29 #include <linux/platform_device.h>
30 #include <linux/sched.h>
31 #include <linux/time.h>
32 
33 /* LPC24xx register offsets and bits */
34 #define LPC24XX_I2CONSET	0x00
35 #define LPC24XX_I2STAT		0x04
36 #define LPC24XX_I2DAT		0x08
37 #define LPC24XX_I2ADDR		0x0c
38 #define LPC24XX_I2SCLH		0x10
39 #define LPC24XX_I2SCLL		0x14
40 #define LPC24XX_I2CONCLR	0x18
41 
42 #define LPC24XX_AA		BIT(2)
43 #define LPC24XX_SI		BIT(3)
44 #define LPC24XX_STO		BIT(4)
45 #define LPC24XX_STA		BIT(5)
46 #define LPC24XX_I2EN		BIT(6)
47 
48 #define LPC24XX_STO_AA		(LPC24XX_STO | LPC24XX_AA)
49 #define LPC24XX_CLEAR_ALL	(LPC24XX_AA | LPC24XX_SI | LPC24XX_STO | \
50 				 LPC24XX_STA | LPC24XX_I2EN)
51 
52 /* I2C SCL clock has different duty cycle depending on mode */
53 #define I2C_STD_MODE_DUTY		46
54 #define I2C_FAST_MODE_DUTY		36
55 #define I2C_FAST_MODE_PLUS_DUTY		38
56 
57 /*
58  * 26 possible I2C status codes, but codes applicable only
59  * to master are listed here and used in this driver
60  */
61 enum {
62 	M_BUS_ERROR		= 0x00,
63 	M_START			= 0x08,
64 	M_REPSTART		= 0x10,
65 	MX_ADDR_W_ACK		= 0x18,
66 	MX_ADDR_W_NACK		= 0x20,
67 	MX_DATA_W_ACK		= 0x28,
68 	MX_DATA_W_NACK		= 0x30,
69 	M_DATA_ARB_LOST		= 0x38,
70 	MR_ADDR_R_ACK		= 0x40,
71 	MR_ADDR_R_NACK		= 0x48,
72 	MR_DATA_R_ACK		= 0x50,
73 	MR_DATA_R_NACK		= 0x58,
74 	M_I2C_IDLE		= 0xf8,
75 };
76 
77 struct lpc2k_i2c {
78 	void __iomem		*base;
79 	struct clk		*clk;
80 	int			irq;
81 	wait_queue_head_t	wait;
82 	struct i2c_adapter	adap;
83 	struct i2c_msg		*msg;
84 	int			msg_idx;
85 	int			msg_status;
86 	int			is_last;
87 };
88 
89 static void i2c_lpc2k_reset(struct lpc2k_i2c *i2c)
90 {
91 	/* Will force clear all statuses */
92 	writel(LPC24XX_CLEAR_ALL, i2c->base + LPC24XX_I2CONCLR);
93 	writel(0, i2c->base + LPC24XX_I2ADDR);
94 	writel(LPC24XX_I2EN, i2c->base + LPC24XX_I2CONSET);
95 }
96 
97 static int i2c_lpc2k_clear_arb(struct lpc2k_i2c *i2c)
98 {
99 	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
100 
101 	/*
102 	 * If the transfer needs to abort for some reason, we'll try to
103 	 * force a stop condition to clear any pending bus conditions
104 	 */
105 	writel(LPC24XX_STO, i2c->base + LPC24XX_I2CONSET);
106 
107 	/* Wait for status change */
108 	while (readl(i2c->base + LPC24XX_I2STAT) != M_I2C_IDLE) {
109 		if (time_after(jiffies, timeout)) {
110 			/* Bus was not idle, try to reset adapter */
111 			i2c_lpc2k_reset(i2c);
112 			return -EBUSY;
113 		}
114 
115 		cpu_relax();
116 	}
117 
118 	return 0;
119 }
120 
121 static void i2c_lpc2k_pump_msg(struct lpc2k_i2c *i2c)
122 {
123 	unsigned char data;
124 	u32 status;
125 
126 	/*
127 	 * I2C in the LPC2xxx series is basically a state machine.
128 	 * Just run through the steps based on the current status.
129 	 */
130 	status = readl(i2c->base + LPC24XX_I2STAT);
131 
132 	switch (status) {
133 	case M_START:
134 	case M_REPSTART:
135 		/* Start bit was just sent out, send out addr and dir */
136 		data = i2c->msg->addr << 1;
137 		if (i2c->msg->flags & I2C_M_RD)
138 			data |= 1;
139 
140 		writel(data, i2c->base + LPC24XX_I2DAT);
141 		writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
142 		break;
143 
144 	case MX_ADDR_W_ACK:
145 	case MX_DATA_W_ACK:
146 		/*
147 		 * Address or data was sent out with an ACK. If there is more
148 		 * data to send, send it now
149 		 */
150 		if (i2c->msg_idx < i2c->msg->len) {
151 			writel(i2c->msg->buf[i2c->msg_idx],
152 			       i2c->base + LPC24XX_I2DAT);
153 		} else if (i2c->is_last) {
154 			/* Last message, send stop */
155 			writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
156 			writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
157 			i2c->msg_status = 0;
158 			disable_irq_nosync(i2c->irq);
159 		} else {
160 			i2c->msg_status = 0;
161 			disable_irq_nosync(i2c->irq);
162 		}
163 
164 		i2c->msg_idx++;
165 		break;
166 
167 	case MR_ADDR_R_ACK:
168 		/* Receive first byte from slave */
169 		if (i2c->msg->len == 1) {
170 			/* Last byte, return NACK */
171 			writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR);
172 		} else {
173 			/* Not last byte, return ACK */
174 			writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET);
175 		}
176 
177 		writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
178 		break;
179 
180 	case MR_DATA_R_NACK:
181 		/*
182 		 * The I2C shows NACK status on reads, so we need to accept
183 		 * the NACK as an ACK here. This should be ok, as the real
184 		 * BACK would of been caught on the address write.
185 		 */
186 	case MR_DATA_R_ACK:
187 		/* Data was received */
188 		if (i2c->msg_idx < i2c->msg->len) {
189 			i2c->msg->buf[i2c->msg_idx] =
190 					readl(i2c->base + LPC24XX_I2DAT);
191 		}
192 
193 		/* If transfer is done, send STOP */
194 		if (i2c->msg_idx >= i2c->msg->len - 1 && i2c->is_last) {
195 			writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
196 			writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
197 			i2c->msg_status = 0;
198 		}
199 
200 		/* Message is done */
201 		if (i2c->msg_idx >= i2c->msg->len - 1) {
202 			i2c->msg_status = 0;
203 			disable_irq_nosync(i2c->irq);
204 		}
205 
206 		/*
207 		 * One pre-last data input, send NACK to tell the slave that
208 		 * this is going to be the last data byte to be transferred.
209 		 */
210 		if (i2c->msg_idx >= i2c->msg->len - 2) {
211 			/* One byte left to receive - NACK */
212 			writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR);
213 		} else {
214 			/* More than one byte left to receive - ACK */
215 			writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET);
216 		}
217 
218 		writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
219 		i2c->msg_idx++;
220 		break;
221 
222 	case MX_ADDR_W_NACK:
223 	case MX_DATA_W_NACK:
224 	case MR_ADDR_R_NACK:
225 		/* NACK processing is done */
226 		writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
227 		i2c->msg_status = -ENXIO;
228 		disable_irq_nosync(i2c->irq);
229 		break;
230 
231 	case M_DATA_ARB_LOST:
232 		/* Arbitration lost */
233 		i2c->msg_status = -EAGAIN;
234 
235 		/* Release the I2C bus */
236 		writel(LPC24XX_STA | LPC24XX_STO, i2c->base + LPC24XX_I2CONCLR);
237 		disable_irq_nosync(i2c->irq);
238 		break;
239 
240 	default:
241 		/* Unexpected statuses */
242 		i2c->msg_status = -EIO;
243 		disable_irq_nosync(i2c->irq);
244 		break;
245 	}
246 
247 	/* Exit on failure or all bytes transferred */
248 	if (i2c->msg_status != -EBUSY)
249 		wake_up(&i2c->wait);
250 
251 	/*
252 	 * If `msg_status` is zero, then `lpc2k_process_msg()`
253 	 * is responsible for clearing the SI flag.
254 	 */
255 	if (i2c->msg_status != 0)
256 		writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
257 }
258 
259 static int lpc2k_process_msg(struct lpc2k_i2c *i2c, int msgidx)
260 {
261 	/* A new transfer is kicked off by initiating a start condition */
262 	if (!msgidx) {
263 		writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET);
264 	} else {
265 		/*
266 		 * A multi-message I2C transfer continues where the
267 		 * previous I2C transfer left off and uses the
268 		 * current condition of the I2C adapter.
269 		 */
270 		if (unlikely(i2c->msg->flags & I2C_M_NOSTART)) {
271 			WARN_ON(i2c->msg->len == 0);
272 
273 			if (!(i2c->msg->flags & I2C_M_RD)) {
274 				/* Start transmit of data */
275 				writel(i2c->msg->buf[0],
276 				       i2c->base + LPC24XX_I2DAT);
277 				i2c->msg_idx++;
278 			}
279 		} else {
280 			/* Start or repeated start */
281 			writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET);
282 		}
283 
284 		writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
285 	}
286 
287 	enable_irq(i2c->irq);
288 
289 	/* Wait for transfer completion */
290 	if (wait_event_timeout(i2c->wait, i2c->msg_status != -EBUSY,
291 			       msecs_to_jiffies(1000)) == 0) {
292 		disable_irq_nosync(i2c->irq);
293 
294 		return -ETIMEDOUT;
295 	}
296 
297 	return i2c->msg_status;
298 }
299 
300 static int i2c_lpc2k_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
301 			  int msg_num)
302 {
303 	struct lpc2k_i2c *i2c = i2c_get_adapdata(adap);
304 	int ret, i;
305 	u32 stat;
306 
307 	/* Check for bus idle condition */
308 	stat = readl(i2c->base + LPC24XX_I2STAT);
309 	if (stat != M_I2C_IDLE) {
310 		/* Something is holding the bus, try to clear it */
311 		return i2c_lpc2k_clear_arb(i2c);
312 	}
313 
314 	/* Process a single message at a time */
315 	for (i = 0; i < msg_num; i++) {
316 		/* Save message pointer and current message data index */
317 		i2c->msg = &msgs[i];
318 		i2c->msg_idx = 0;
319 		i2c->msg_status = -EBUSY;
320 		i2c->is_last = (i == (msg_num - 1));
321 
322 		ret = lpc2k_process_msg(i2c, i);
323 		if (ret)
324 			return ret;
325 	}
326 
327 	return msg_num;
328 }
329 
330 static irqreturn_t i2c_lpc2k_handler(int irq, void *dev_id)
331 {
332 	struct lpc2k_i2c *i2c = dev_id;
333 
334 	if (readl(i2c->base + LPC24XX_I2CONSET) & LPC24XX_SI) {
335 		i2c_lpc2k_pump_msg(i2c);
336 		return IRQ_HANDLED;
337 	}
338 
339 	return IRQ_NONE;
340 }
341 
342 static u32 i2c_lpc2k_functionality(struct i2c_adapter *adap)
343 {
344 	/* Only emulated SMBus for now */
345 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
346 }
347 
348 static const struct i2c_algorithm i2c_lpc2k_algorithm = {
349 	.master_xfer	= i2c_lpc2k_xfer,
350 	.functionality	= i2c_lpc2k_functionality,
351 };
352 
353 static int i2c_lpc2k_probe(struct platform_device *pdev)
354 {
355 	struct lpc2k_i2c *i2c;
356 	struct resource *res;
357 	u32 bus_clk_rate;
358 	u32 scl_high;
359 	u32 clkrate;
360 	int ret;
361 
362 	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
363 	if (!i2c)
364 		return -ENOMEM;
365 
366 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
367 	i2c->base = devm_ioremap_resource(&pdev->dev, res);
368 	if (IS_ERR(i2c->base))
369 		return PTR_ERR(i2c->base);
370 
371 	i2c->irq = platform_get_irq(pdev, 0);
372 	if (i2c->irq < 0) {
373 		dev_err(&pdev->dev, "can't get interrupt resource\n");
374 		return i2c->irq;
375 	}
376 
377 	init_waitqueue_head(&i2c->wait);
378 
379 	i2c->clk = devm_clk_get(&pdev->dev, NULL);
380 	if (IS_ERR(i2c->clk)) {
381 		dev_err(&pdev->dev, "error getting clock\n");
382 		return PTR_ERR(i2c->clk);
383 	}
384 
385 	ret = clk_prepare_enable(i2c->clk);
386 	if (ret) {
387 		dev_err(&pdev->dev, "unable to enable clock.\n");
388 		return ret;
389 	}
390 
391 	ret = devm_request_irq(&pdev->dev, i2c->irq, i2c_lpc2k_handler, 0,
392 			       dev_name(&pdev->dev), i2c);
393 	if (ret < 0) {
394 		dev_err(&pdev->dev, "can't request interrupt.\n");
395 		goto fail_clk;
396 	}
397 
398 	disable_irq_nosync(i2c->irq);
399 
400 	/* Place controller is a known state */
401 	i2c_lpc2k_reset(i2c);
402 
403 	ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
404 				   &bus_clk_rate);
405 	if (ret)
406 		bus_clk_rate = 100000; /* 100 kHz default clock rate */
407 
408 	clkrate = clk_get_rate(i2c->clk);
409 	if (clkrate == 0) {
410 		dev_err(&pdev->dev, "can't get I2C base clock\n");
411 		ret = -EINVAL;
412 		goto fail_clk;
413 	}
414 
415 	/* Setup I2C dividers to generate clock with proper duty cycle */
416 	clkrate = clkrate / bus_clk_rate;
417 	if (bus_clk_rate <= 100000)
418 		scl_high = (clkrate * I2C_STD_MODE_DUTY) / 100;
419 	else if (bus_clk_rate <= 400000)
420 		scl_high = (clkrate * I2C_FAST_MODE_DUTY) / 100;
421 	else
422 		scl_high = (clkrate * I2C_FAST_MODE_PLUS_DUTY) / 100;
423 
424 	writel(scl_high, i2c->base + LPC24XX_I2SCLH);
425 	writel(clkrate - scl_high, i2c->base + LPC24XX_I2SCLL);
426 
427 	platform_set_drvdata(pdev, i2c);
428 
429 	i2c_set_adapdata(&i2c->adap, i2c);
430 	i2c->adap.owner = THIS_MODULE;
431 	strlcpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name));
432 	i2c->adap.algo = &i2c_lpc2k_algorithm;
433 	i2c->adap.dev.parent = &pdev->dev;
434 	i2c->adap.dev.of_node = pdev->dev.of_node;
435 
436 	ret = i2c_add_adapter(&i2c->adap);
437 	if (ret < 0) {
438 		dev_err(&pdev->dev, "failed to add adapter!\n");
439 		goto fail_clk;
440 	}
441 
442 	dev_info(&pdev->dev, "LPC2K I2C adapter\n");
443 
444 	return 0;
445 
446 fail_clk:
447 	clk_disable_unprepare(i2c->clk);
448 	return ret;
449 }
450 
451 static int i2c_lpc2k_remove(struct platform_device *dev)
452 {
453 	struct lpc2k_i2c *i2c = platform_get_drvdata(dev);
454 
455 	i2c_del_adapter(&i2c->adap);
456 	clk_disable_unprepare(i2c->clk);
457 
458 	return 0;
459 }
460 
461 #ifdef CONFIG_PM
462 static int i2c_lpc2k_suspend(struct device *dev)
463 {
464 	struct platform_device *pdev = to_platform_device(dev);
465 	struct lpc2k_i2c *i2c = platform_get_drvdata(pdev);
466 
467 	clk_disable(i2c->clk);
468 
469 	return 0;
470 }
471 
472 static int i2c_lpc2k_resume(struct device *dev)
473 {
474 	struct platform_device *pdev = to_platform_device(dev);
475 	struct lpc2k_i2c *i2c = platform_get_drvdata(pdev);
476 
477 	clk_enable(i2c->clk);
478 	i2c_lpc2k_reset(i2c);
479 
480 	return 0;
481 }
482 
483 static const struct dev_pm_ops i2c_lpc2k_dev_pm_ops = {
484 	.suspend_noirq = i2c_lpc2k_suspend,
485 	.resume_noirq = i2c_lpc2k_resume,
486 };
487 
488 #define I2C_LPC2K_DEV_PM_OPS (&i2c_lpc2k_dev_pm_ops)
489 #else
490 #define I2C_LPC2K_DEV_PM_OPS NULL
491 #endif
492 
493 static const struct of_device_id lpc2k_i2c_match[] = {
494 	{ .compatible = "nxp,lpc1788-i2c" },
495 	{},
496 };
497 MODULE_DEVICE_TABLE(of, lpc2k_i2c_match);
498 
499 static struct platform_driver i2c_lpc2k_driver = {
500 	.probe	= i2c_lpc2k_probe,
501 	.remove	= i2c_lpc2k_remove,
502 	.driver	= {
503 		.name		= "lpc2k-i2c",
504 		.pm		= I2C_LPC2K_DEV_PM_OPS,
505 		.of_match_table	= lpc2k_i2c_match,
506 	},
507 };
508 module_platform_driver(i2c_lpc2k_driver);
509 
510 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
511 MODULE_DESCRIPTION("I2C driver for LPC2xxx devices");
512 MODULE_LICENSE("GPL");
513 MODULE_ALIAS("platform:lpc2k-i2c");
514