1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2024-2025 Troy Mitchell <troymitchell988@gmail.com> 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/clk.h> 8 #include <linux/i2c.h> 9 #include <linux/iopoll.h> 10 #include <linux/module.h> 11 #include <linux/of_address.h> 12 #include <linux/platform_device.h> 13 #include <linux/reset.h> 14 15 /* spacemit i2c registers */ 16 #define SPACEMIT_ICR 0x0 /* Control register */ 17 #define SPACEMIT_ISR 0x4 /* Status register */ 18 #define SPACEMIT_IDBR 0xc /* Data buffer register */ 19 #define SPACEMIT_IRCR 0x18 /* Reset cycle counter */ 20 #define SPACEMIT_IBMR 0x1c /* Bus monitor register */ 21 22 /* SPACEMIT_ICR register fields */ 23 #define SPACEMIT_CR_START BIT(0) /* start bit */ 24 #define SPACEMIT_CR_STOP BIT(1) /* stop bit */ 25 #define SPACEMIT_CR_ACKNAK BIT(2) /* send ACK(0) or NAK(1) */ 26 #define SPACEMIT_CR_TB BIT(3) /* transfer byte bit */ 27 /* Bits 4-7 are reserved */ 28 #define SPACEMIT_CR_MODE_FAST BIT(8) /* bus mode (master operation) */ 29 /* Bit 9 is reserved */ 30 #define SPACEMIT_CR_UR BIT(10) /* unit reset */ 31 #define SPACEMIT_CR_RSTREQ BIT(11) /* i2c bus reset request */ 32 /* Bit 12 is reserved */ 33 #define SPACEMIT_CR_SCLE BIT(13) /* master clock enable */ 34 #define SPACEMIT_CR_IUE BIT(14) /* unit enable */ 35 /* Bits 15-17 are reserved */ 36 #define SPACEMIT_CR_ALDIE BIT(18) /* enable arbitration interrupt */ 37 #define SPACEMIT_CR_DTEIE BIT(19) /* enable TX interrupts */ 38 #define SPACEMIT_CR_DRFIE BIT(20) /* enable RX interrupts */ 39 #define SPACEMIT_CR_GCD BIT(21) /* general call disable */ 40 #define SPACEMIT_CR_BEIE BIT(22) /* enable bus error ints */ 41 /* Bits 23-24 are reserved */ 42 #define SPACEMIT_CR_MSDIE BIT(25) /* master STOP detected int enable */ 43 #define SPACEMIT_CR_MSDE BIT(26) /* master STOP detected enable */ 44 #define SPACEMIT_CR_TXDONEIE BIT(27) /* transaction done int enable */ 45 #define SPACEMIT_CR_TXEIE BIT(28) /* transmit FIFO empty int enable */ 46 #define SPACEMIT_CR_RXHFIE BIT(29) /* receive FIFO half-full int enable */ 47 #define SPACEMIT_CR_RXFIE BIT(30) /* receive FIFO full int enable */ 48 #define SPACEMIT_CR_RXOVIE BIT(31) /* receive FIFO overrun int enable */ 49 50 #define SPACEMIT_I2C_INT_CTRL_MASK (SPACEMIT_CR_ALDIE | SPACEMIT_CR_DTEIE | \ 51 SPACEMIT_CR_DRFIE | SPACEMIT_CR_BEIE | \ 52 SPACEMIT_CR_TXDONEIE | SPACEMIT_CR_TXEIE | \ 53 SPACEMIT_CR_RXHFIE | SPACEMIT_CR_RXFIE | \ 54 SPACEMIT_CR_RXOVIE | SPACEMIT_CR_MSDIE) 55 56 /* SPACEMIT_ISR register fields */ 57 /* Bits 0-13 are reserved */ 58 #define SPACEMIT_SR_ACKNAK BIT(14) /* ACK/NACK status */ 59 #define SPACEMIT_SR_UB BIT(15) /* unit busy */ 60 #define SPACEMIT_SR_IBB BIT(16) /* i2c bus busy */ 61 #define SPACEMIT_SR_EBB BIT(17) /* early bus busy */ 62 #define SPACEMIT_SR_ALD BIT(18) /* arbitration loss detected */ 63 #define SPACEMIT_SR_ITE BIT(19) /* TX buffer empty */ 64 #define SPACEMIT_SR_IRF BIT(20) /* RX buffer full */ 65 #define SPACEMIT_SR_GCAD BIT(21) /* general call address detected */ 66 #define SPACEMIT_SR_BED BIT(22) /* bus error no ACK/NAK */ 67 #define SPACEMIT_SR_SAD BIT(23) /* slave address detected */ 68 #define SPACEMIT_SR_SSD BIT(24) /* slave stop detected */ 69 /* Bit 25 is reserved */ 70 #define SPACEMIT_SR_MSD BIT(26) /* master stop detected */ 71 #define SPACEMIT_SR_TXDONE BIT(27) /* transaction done */ 72 #define SPACEMIT_SR_TXE BIT(28) /* TX FIFO empty */ 73 #define SPACEMIT_SR_RXHF BIT(29) /* RX FIFO half-full */ 74 #define SPACEMIT_SR_RXF BIT(30) /* RX FIFO full */ 75 #define SPACEMIT_SR_RXOV BIT(31) /* RX FIFO overrun */ 76 77 #define SPACEMIT_I2C_INT_STATUS_MASK (SPACEMIT_SR_RXOV | SPACEMIT_SR_RXF | SPACEMIT_SR_RXHF | \ 78 SPACEMIT_SR_TXE | SPACEMIT_SR_TXDONE | SPACEMIT_SR_MSD | \ 79 SPACEMIT_SR_SSD | SPACEMIT_SR_SAD | SPACEMIT_SR_BED | \ 80 SPACEMIT_SR_GCAD | SPACEMIT_SR_IRF | SPACEMIT_SR_ITE | \ 81 SPACEMIT_SR_ALD) 82 83 #define SPACEMIT_RCR_SDA_GLITCH_NOFIX BIT(7) /* bypass the SDA glitch fix */ 84 /* the cycles of SCL during bus reset */ 85 #define SPACEMIT_RCR_FIELD_RST_CYC GENMASK(3, 0) 86 87 /* SPACEMIT_IBMR register fields */ 88 #define SPACEMIT_BMR_SDA BIT(0) /* SDA line level */ 89 #define SPACEMIT_BMR_SCL BIT(1) /* SCL line level */ 90 91 /* i2c bus recover timeout: us */ 92 #define SPACEMIT_I2C_BUS_BUSY_TIMEOUT 100000 93 94 #define SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ 100000 /* Hz */ 95 #define SPACEMIT_I2C_MAX_FAST_MODE_FREQ 400000 /* Hz */ 96 97 #define SPACEMIT_SR_ERR (SPACEMIT_SR_BED | SPACEMIT_SR_RXOV | SPACEMIT_SR_ALD) 98 99 #define SPACEMIT_BUS_RESET_CLK_CNT_MAX 9 100 101 enum spacemit_i2c_state { 102 SPACEMIT_STATE_IDLE, 103 SPACEMIT_STATE_START, 104 SPACEMIT_STATE_READ, 105 SPACEMIT_STATE_WRITE, 106 }; 107 108 /* i2c-spacemit driver's main struct */ 109 struct spacemit_i2c_dev { 110 struct device *dev; 111 struct i2c_adapter adapt; 112 113 /* hardware resources */ 114 void __iomem *base; 115 int irq; 116 u32 clock_freq; 117 118 struct i2c_msg *msgs; 119 u32 msg_num; 120 121 /* index of the current message being processed */ 122 u32 msg_idx; 123 u8 *msg_buf; 124 /* the number of unprocessed bytes remaining in the current message */ 125 u32 unprocessed; 126 127 enum spacemit_i2c_state state; 128 bool read; 129 struct completion complete; 130 u32 status; 131 }; 132 133 static void spacemit_i2c_enable(struct spacemit_i2c_dev *i2c) 134 { 135 u32 val; 136 137 val = readl(i2c->base + SPACEMIT_ICR); 138 val |= SPACEMIT_CR_IUE; 139 writel(val, i2c->base + SPACEMIT_ICR); 140 } 141 142 static void spacemit_i2c_disable(struct spacemit_i2c_dev *i2c) 143 { 144 u32 val; 145 146 val = readl(i2c->base + SPACEMIT_ICR); 147 val &= ~SPACEMIT_CR_IUE; 148 writel(val, i2c->base + SPACEMIT_ICR); 149 } 150 151 static void spacemit_i2c_reset(struct spacemit_i2c_dev *i2c) 152 { 153 writel(SPACEMIT_CR_UR, i2c->base + SPACEMIT_ICR); 154 udelay(5); 155 writel(0, i2c->base + SPACEMIT_ICR); 156 } 157 158 static int spacemit_i2c_handle_err(struct spacemit_i2c_dev *i2c) 159 { 160 dev_dbg(i2c->dev, "i2c error status: 0x%08x\n", i2c->status); 161 162 /* Arbitration Loss Detected */ 163 if (i2c->status & SPACEMIT_SR_ALD) { 164 spacemit_i2c_reset(i2c); 165 return -EAGAIN; 166 } 167 168 /* Bus Error No ACK/NAK */ 169 if (i2c->status & SPACEMIT_SR_BED) 170 spacemit_i2c_reset(i2c); 171 172 return i2c->status & SPACEMIT_SR_ACKNAK ? -ENXIO : -EIO; 173 } 174 175 static void spacemit_i2c_conditionally_reset_bus(struct spacemit_i2c_dev *i2c) 176 { 177 u32 status; 178 u8 clk_cnt; 179 180 /* if bus is locked, reset unit. 0: locked */ 181 status = readl(i2c->base + SPACEMIT_IBMR); 182 if ((status & SPACEMIT_BMR_SDA) && (status & SPACEMIT_BMR_SCL)) 183 return; 184 185 spacemit_i2c_reset(i2c); 186 usleep_range(10, 20); 187 188 for (clk_cnt = 0; clk_cnt < SPACEMIT_BUS_RESET_CLK_CNT_MAX; clk_cnt++) { 189 status = readl(i2c->base + SPACEMIT_IBMR); 190 if (status & SPACEMIT_BMR_SDA) 191 return; 192 193 /* There's nothing left to save here, we are about to exit */ 194 writel(FIELD_PREP(SPACEMIT_RCR_FIELD_RST_CYC, 1), 195 i2c->base + SPACEMIT_IRCR); 196 writel(SPACEMIT_CR_RSTREQ, i2c->base + SPACEMIT_ICR); 197 usleep_range(20, 30); 198 } 199 200 /* check sda again here */ 201 status = readl(i2c->base + SPACEMIT_IBMR); 202 if (!(status & SPACEMIT_BMR_SDA)) 203 dev_warn_ratelimited(i2c->dev, "unit reset failed\n"); 204 } 205 206 static int spacemit_i2c_wait_bus_idle(struct spacemit_i2c_dev *i2c) 207 { 208 int ret; 209 u32 val; 210 211 val = readl(i2c->base + SPACEMIT_ISR); 212 if (!(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB))) 213 return 0; 214 215 ret = readl_poll_timeout(i2c->base + SPACEMIT_ISR, 216 val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)), 217 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT); 218 if (ret) 219 spacemit_i2c_reset(i2c); 220 221 return ret; 222 } 223 224 static void spacemit_i2c_check_bus_release(struct spacemit_i2c_dev *i2c) 225 { 226 /* in case bus is not released after transfer completes */ 227 if (readl(i2c->base + SPACEMIT_ISR) & SPACEMIT_SR_EBB) { 228 spacemit_i2c_conditionally_reset_bus(i2c); 229 usleep_range(90, 150); 230 } 231 } 232 233 static inline void 234 spacemit_i2c_clear_int_status(struct spacemit_i2c_dev *i2c, u32 mask) 235 { 236 writel(mask & SPACEMIT_I2C_INT_STATUS_MASK, i2c->base + SPACEMIT_ISR); 237 } 238 239 static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) 240 { 241 u32 val; 242 243 /* 244 * Unmask interrupt bits for all xfer mode: 245 * bus error, arbitration loss detected. 246 * For transaction complete signal, we use master stop 247 * interrupt, so we don't need to unmask SPACEMIT_CR_TXDONEIE. 248 */ 249 val = SPACEMIT_CR_BEIE | SPACEMIT_CR_ALDIE; 250 251 /* 252 * Unmask interrupt bits for interrupt xfer mode: 253 * When IDBR receives a byte, an interrupt is triggered. 254 * 255 * For the tx empty interrupt, it will be enabled in the 256 * i2c_start function. 257 * Otherwise, it will cause an erroneous empty interrupt before i2c_start. 258 */ 259 val |= SPACEMIT_CR_DRFIE; 260 261 if (i2c->clock_freq == SPACEMIT_I2C_MAX_FAST_MODE_FREQ) 262 val |= SPACEMIT_CR_MODE_FAST; 263 264 /* disable response to general call */ 265 val |= SPACEMIT_CR_GCD; 266 267 /* enable SCL clock output */ 268 val |= SPACEMIT_CR_SCLE; 269 270 /* enable master stop detected */ 271 val |= SPACEMIT_CR_MSDE | SPACEMIT_CR_MSDIE; 272 273 writel(val, i2c->base + SPACEMIT_ICR); 274 275 /* 276 * The glitch fix in the K1 I2C controller introduces a delay 277 * on restart signals, so we disable the fix here. 278 */ 279 val = readl(i2c->base + SPACEMIT_IRCR); 280 val |= SPACEMIT_RCR_SDA_GLITCH_NOFIX; 281 writel(val, i2c->base + SPACEMIT_IRCR); 282 283 spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK); 284 } 285 286 static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c) 287 { 288 u32 target_addr_rw, val; 289 struct i2c_msg *cur_msg = i2c->msgs + i2c->msg_idx; 290 291 i2c->read = !!(cur_msg->flags & I2C_M_RD); 292 293 i2c->state = SPACEMIT_STATE_START; 294 295 target_addr_rw = (cur_msg->addr & 0x7f) << 1; 296 if (cur_msg->flags & I2C_M_RD) 297 target_addr_rw |= 1; 298 299 writel(target_addr_rw, i2c->base + SPACEMIT_IDBR); 300 301 /* send start pulse */ 302 val = readl(i2c->base + SPACEMIT_ICR); 303 val &= ~SPACEMIT_CR_STOP; 304 val |= SPACEMIT_CR_START | SPACEMIT_CR_TB | SPACEMIT_CR_DTEIE; 305 writel(val, i2c->base + SPACEMIT_ICR); 306 } 307 308 static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) 309 { 310 unsigned long time_left; 311 struct i2c_msg *msg; 312 313 for (i2c->msg_idx = 0; i2c->msg_idx < i2c->msg_num; i2c->msg_idx++) { 314 msg = &i2c->msgs[i2c->msg_idx]; 315 i2c->msg_buf = msg->buf; 316 i2c->unprocessed = msg->len; 317 i2c->status = 0; 318 319 reinit_completion(&i2c->complete); 320 321 spacemit_i2c_start(i2c); 322 323 time_left = wait_for_completion_timeout(&i2c->complete, 324 i2c->adapt.timeout); 325 if (!time_left) { 326 dev_err(i2c->dev, "msg completion timeout\n"); 327 spacemit_i2c_conditionally_reset_bus(i2c); 328 spacemit_i2c_reset(i2c); 329 return -ETIMEDOUT; 330 } 331 332 if (i2c->status & SPACEMIT_SR_ERR) 333 return spacemit_i2c_handle_err(i2c); 334 } 335 336 return 0; 337 } 338 339 static bool spacemit_i2c_is_last_msg(struct spacemit_i2c_dev *i2c) 340 { 341 if (i2c->msg_idx != i2c->msg_num - 1) 342 return false; 343 344 if (i2c->read) 345 return i2c->unprocessed == 1; 346 347 return !i2c->unprocessed; 348 } 349 350 static void spacemit_i2c_handle_write(struct spacemit_i2c_dev *i2c) 351 { 352 /* if transfer completes, SPACEMIT_ISR will handle it */ 353 if (i2c->status & SPACEMIT_SR_MSD) 354 return; 355 356 if (i2c->unprocessed) { 357 writel(*i2c->msg_buf++, i2c->base + SPACEMIT_IDBR); 358 i2c->unprocessed--; 359 return; 360 } 361 362 /* SPACEMIT_STATE_IDLE avoids trigger next byte */ 363 i2c->state = SPACEMIT_STATE_IDLE; 364 complete(&i2c->complete); 365 } 366 367 static void spacemit_i2c_handle_read(struct spacemit_i2c_dev *i2c) 368 { 369 if (i2c->unprocessed) { 370 *i2c->msg_buf++ = readl(i2c->base + SPACEMIT_IDBR); 371 i2c->unprocessed--; 372 } 373 374 /* if transfer completes, SPACEMIT_ISR will handle it */ 375 if (i2c->status & (SPACEMIT_SR_MSD | SPACEMIT_SR_ACKNAK)) 376 return; 377 378 /* it has to append stop bit in icr that read last byte */ 379 if (i2c->unprocessed) 380 return; 381 382 /* SPACEMIT_STATE_IDLE avoids trigger next byte */ 383 i2c->state = SPACEMIT_STATE_IDLE; 384 complete(&i2c->complete); 385 } 386 387 static void spacemit_i2c_handle_start(struct spacemit_i2c_dev *i2c) 388 { 389 i2c->state = i2c->read ? SPACEMIT_STATE_READ : SPACEMIT_STATE_WRITE; 390 if (i2c->state == SPACEMIT_STATE_WRITE) 391 spacemit_i2c_handle_write(i2c); 392 } 393 394 static void spacemit_i2c_err_check(struct spacemit_i2c_dev *i2c) 395 { 396 u32 val; 397 398 /* 399 * Send transaction complete signal: 400 * error happens, detect master stop 401 */ 402 if (!(i2c->status & (SPACEMIT_SR_ERR | SPACEMIT_SR_MSD))) 403 return; 404 405 /* 406 * Here the transaction is already done, we don't need any 407 * other interrupt signals from now, in case any interrupt 408 * happens before spacemit_i2c_xfer to disable irq and i2c unit, 409 * we mask all the interrupt signals and clear the interrupt 410 * status. 411 */ 412 val = readl(i2c->base + SPACEMIT_ICR); 413 val &= ~SPACEMIT_I2C_INT_CTRL_MASK; 414 writel(val, i2c->base + SPACEMIT_ICR); 415 416 spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK); 417 418 i2c->state = SPACEMIT_STATE_IDLE; 419 complete(&i2c->complete); 420 } 421 422 static irqreturn_t spacemit_i2c_irq_handler(int irq, void *devid) 423 { 424 struct spacemit_i2c_dev *i2c = devid; 425 u32 status, val; 426 427 status = readl(i2c->base + SPACEMIT_ISR); 428 if (!status) 429 return IRQ_HANDLED; 430 431 i2c->status = status; 432 433 spacemit_i2c_clear_int_status(i2c, status); 434 435 if (i2c->status & SPACEMIT_SR_ERR) 436 goto err_out; 437 438 val = readl(i2c->base + SPACEMIT_ICR); 439 val &= ~(SPACEMIT_CR_TB | SPACEMIT_CR_ACKNAK | SPACEMIT_CR_STOP | SPACEMIT_CR_START); 440 441 switch (i2c->state) { 442 case SPACEMIT_STATE_START: 443 spacemit_i2c_handle_start(i2c); 444 break; 445 case SPACEMIT_STATE_READ: 446 spacemit_i2c_handle_read(i2c); 447 break; 448 case SPACEMIT_STATE_WRITE: 449 spacemit_i2c_handle_write(i2c); 450 break; 451 default: 452 break; 453 } 454 455 if (i2c->state != SPACEMIT_STATE_IDLE) { 456 val |= SPACEMIT_CR_TB | SPACEMIT_CR_ALDIE; 457 458 if (spacemit_i2c_is_last_msg(i2c)) { 459 /* trigger next byte with stop */ 460 val |= SPACEMIT_CR_STOP; 461 462 if (i2c->read) 463 val |= SPACEMIT_CR_ACKNAK; 464 } 465 writel(val, i2c->base + SPACEMIT_ICR); 466 } 467 468 err_out: 469 spacemit_i2c_err_check(i2c); 470 return IRQ_HANDLED; 471 } 472 473 static void spacemit_i2c_calc_timeout(struct spacemit_i2c_dev *i2c) 474 { 475 unsigned long timeout; 476 int idx = 0, cnt = 0; 477 478 for (; idx < i2c->msg_num; idx++) 479 cnt += (i2c->msgs + idx)->len + 1; 480 481 /* 482 * Multiply by 9 because each byte in I2C transmission requires 483 * 9 clock cycles: 8 bits of data plus 1 ACK/NACK bit. 484 */ 485 timeout = cnt * 9 * USEC_PER_SEC / i2c->clock_freq; 486 487 i2c->adapt.timeout = usecs_to_jiffies(timeout + USEC_PER_SEC / 10) / i2c->msg_num; 488 } 489 490 static int spacemit_i2c_xfer(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num) 491 { 492 struct spacemit_i2c_dev *i2c = i2c_get_adapdata(adapt); 493 int ret; 494 495 i2c->msgs = msgs; 496 i2c->msg_num = num; 497 498 spacemit_i2c_calc_timeout(i2c); 499 500 spacemit_i2c_init(i2c); 501 502 spacemit_i2c_enable(i2c); 503 504 ret = spacemit_i2c_wait_bus_idle(i2c); 505 if (!ret) { 506 ret = spacemit_i2c_xfer_msg(i2c); 507 if (ret < 0) 508 dev_dbg(i2c->dev, "i2c transfer error: %d\n", ret); 509 } else { 510 spacemit_i2c_check_bus_release(i2c); 511 } 512 513 spacemit_i2c_disable(i2c); 514 515 if (ret == -ETIMEDOUT || ret == -EAGAIN) 516 dev_err(i2c->dev, "i2c transfer failed, ret %d err 0x%lx\n", 517 ret, i2c->status & SPACEMIT_SR_ERR); 518 519 return ret < 0 ? ret : num; 520 } 521 522 static u32 spacemit_i2c_func(struct i2c_adapter *adap) 523 { 524 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 525 } 526 527 static const struct i2c_algorithm spacemit_i2c_algo = { 528 .xfer = spacemit_i2c_xfer, 529 .functionality = spacemit_i2c_func, 530 }; 531 532 static int spacemit_i2c_probe(struct platform_device *pdev) 533 { 534 struct clk *clk; 535 struct device *dev = &pdev->dev; 536 struct device_node *of_node = pdev->dev.of_node; 537 struct spacemit_i2c_dev *i2c; 538 struct reset_control *rst; 539 int ret; 540 541 i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL); 542 if (!i2c) 543 return -ENOMEM; 544 545 ret = of_property_read_u32(of_node, "clock-frequency", &i2c->clock_freq); 546 if (ret && ret != -EINVAL) 547 dev_warn(dev, "failed to read clock-frequency property: %d\n", ret); 548 549 /* For now, this driver doesn't support high-speed. */ 550 if (!i2c->clock_freq || i2c->clock_freq > SPACEMIT_I2C_MAX_FAST_MODE_FREQ) { 551 dev_warn(dev, "unsupported clock frequency %u; using %u\n", 552 i2c->clock_freq, SPACEMIT_I2C_MAX_FAST_MODE_FREQ); 553 i2c->clock_freq = SPACEMIT_I2C_MAX_FAST_MODE_FREQ; 554 } else if (i2c->clock_freq < SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) { 555 dev_warn(dev, "unsupported clock frequency %u; using %u\n", 556 i2c->clock_freq, SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ); 557 i2c->clock_freq = SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ; 558 } 559 560 i2c->dev = &pdev->dev; 561 562 i2c->base = devm_platform_ioremap_resource(pdev, 0); 563 if (IS_ERR(i2c->base)) 564 return dev_err_probe(dev, PTR_ERR(i2c->base), "failed to do ioremap"); 565 566 i2c->irq = platform_get_irq(pdev, 0); 567 if (i2c->irq < 0) 568 return dev_err_probe(dev, i2c->irq, "failed to get irq resource"); 569 570 ret = devm_request_irq(i2c->dev, i2c->irq, spacemit_i2c_irq_handler, 571 IRQF_NO_SUSPEND, dev_name(i2c->dev), i2c); 572 if (ret) 573 return dev_err_probe(dev, ret, "failed to request irq"); 574 575 clk = devm_clk_get_enabled(dev, "func"); 576 if (IS_ERR(clk)) 577 return dev_err_probe(dev, PTR_ERR(clk), "failed to enable func clock"); 578 579 clk = devm_clk_get_enabled(dev, "bus"); 580 if (IS_ERR(clk)) 581 return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock"); 582 583 rst = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL); 584 if (IS_ERR(rst)) 585 return dev_err_probe(dev, PTR_ERR(rst), 586 "failed to acquire deasserted reset\n"); 587 588 spacemit_i2c_reset(i2c); 589 590 i2c_set_adapdata(&i2c->adapt, i2c); 591 i2c->adapt.owner = THIS_MODULE; 592 i2c->adapt.algo = &spacemit_i2c_algo; 593 i2c->adapt.dev.parent = i2c->dev; 594 i2c->adapt.nr = pdev->id; 595 596 i2c->adapt.dev.of_node = of_node; 597 598 strscpy(i2c->adapt.name, "spacemit-i2c-adapter", sizeof(i2c->adapt.name)); 599 600 init_completion(&i2c->complete); 601 602 platform_set_drvdata(pdev, i2c); 603 604 ret = i2c_add_numbered_adapter(&i2c->adapt); 605 if (ret) 606 return dev_err_probe(&pdev->dev, ret, "failed to add i2c adapter"); 607 608 return 0; 609 } 610 611 static void spacemit_i2c_remove(struct platform_device *pdev) 612 { 613 struct spacemit_i2c_dev *i2c = platform_get_drvdata(pdev); 614 615 i2c_del_adapter(&i2c->adapt); 616 } 617 618 static const struct of_device_id spacemit_i2c_of_match[] = { 619 { .compatible = "spacemit,k1-i2c", }, 620 { /* sentinel */ } 621 }; 622 MODULE_DEVICE_TABLE(of, spacemit_i2c_of_match); 623 624 static struct platform_driver spacemit_i2c_driver = { 625 .probe = spacemit_i2c_probe, 626 .remove = spacemit_i2c_remove, 627 .driver = { 628 .name = "i2c-k1", 629 .of_match_table = spacemit_i2c_of_match, 630 }, 631 }; 632 module_platform_driver(spacemit_i2c_driver); 633 634 MODULE_LICENSE("GPL"); 635 MODULE_DESCRIPTION("I2C bus driver for SpacemiT K1 SoC"); 636