1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2024-2025 Troy Mitchell <troymitchell988@gmail.com> 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/clk.h> 8 #include <linux/i2c.h> 9 #include <linux/iopoll.h> 10 #include <linux/module.h> 11 #include <linux/of_address.h> 12 #include <linux/platform_device.h> 13 #include <linux/reset.h> 14 15 /* spacemit i2c registers */ 16 #define SPACEMIT_ICR 0x0 /* Control register */ 17 #define SPACEMIT_ISR 0x4 /* Status register */ 18 #define SPACEMIT_IDBR 0xc /* Data buffer register */ 19 #define SPACEMIT_IRCR 0x18 /* Reset cycle counter */ 20 #define SPACEMIT_IBMR 0x1c /* Bus monitor register */ 21 22 /* SPACEMIT_ICR register fields */ 23 #define SPACEMIT_CR_START BIT(0) /* start bit */ 24 #define SPACEMIT_CR_STOP BIT(1) /* stop bit */ 25 #define SPACEMIT_CR_ACKNAK BIT(2) /* send ACK(0) or NAK(1) */ 26 #define SPACEMIT_CR_TB BIT(3) /* transfer byte bit */ 27 /* Bits 4-7 are reserved */ 28 #define SPACEMIT_CR_MODE_FAST BIT(8) /* bus mode (master operation) */ 29 /* Bit 9 is reserved */ 30 #define SPACEMIT_CR_UR BIT(10) /* unit reset */ 31 #define SPACEMIT_CR_RSTREQ BIT(11) /* i2c bus reset request */ 32 /* Bit 12 is reserved */ 33 #define SPACEMIT_CR_SCLE BIT(13) /* master clock enable */ 34 #define SPACEMIT_CR_IUE BIT(14) /* unit enable */ 35 /* Bits 15-17 are reserved */ 36 #define SPACEMIT_CR_ALDIE BIT(18) /* enable arbitration interrupt */ 37 #define SPACEMIT_CR_DTEIE BIT(19) /* enable TX interrupts */ 38 #define SPACEMIT_CR_DRFIE BIT(20) /* enable RX interrupts */ 39 #define SPACEMIT_CR_GCD BIT(21) /* general call disable */ 40 #define SPACEMIT_CR_BEIE BIT(22) /* enable bus error ints */ 41 /* Bits 23-24 are reserved */ 42 #define SPACEMIT_CR_MSDIE BIT(25) /* master STOP detected int enable */ 43 #define SPACEMIT_CR_MSDE BIT(26) /* master STOP detected enable */ 44 #define SPACEMIT_CR_TXDONEIE BIT(27) /* transaction done int enable */ 45 #define SPACEMIT_CR_TXEIE BIT(28) /* transmit FIFO empty int enable */ 46 #define SPACEMIT_CR_RXHFIE BIT(29) /* receive FIFO half-full int enable */ 47 #define SPACEMIT_CR_RXFIE BIT(30) /* receive FIFO full int enable */ 48 #define SPACEMIT_CR_RXOVIE BIT(31) /* receive FIFO overrun int enable */ 49 50 #define SPACEMIT_I2C_INT_CTRL_MASK (SPACEMIT_CR_ALDIE | SPACEMIT_CR_DTEIE | \ 51 SPACEMIT_CR_DRFIE | SPACEMIT_CR_BEIE | \ 52 SPACEMIT_CR_TXDONEIE | SPACEMIT_CR_TXEIE | \ 53 SPACEMIT_CR_RXHFIE | SPACEMIT_CR_RXFIE | \ 54 SPACEMIT_CR_RXOVIE | SPACEMIT_CR_MSDIE) 55 56 /* SPACEMIT_ISR register fields */ 57 /* Bits 0-13 are reserved */ 58 #define SPACEMIT_SR_ACKNAK BIT(14) /* ACK/NACK status */ 59 #define SPACEMIT_SR_UB BIT(15) /* unit busy */ 60 #define SPACEMIT_SR_IBB BIT(16) /* i2c bus busy */ 61 #define SPACEMIT_SR_EBB BIT(17) /* early bus busy */ 62 #define SPACEMIT_SR_ALD BIT(18) /* arbitration loss detected */ 63 #define SPACEMIT_SR_ITE BIT(19) /* TX buffer empty */ 64 #define SPACEMIT_SR_IRF BIT(20) /* RX buffer full */ 65 #define SPACEMIT_SR_GCAD BIT(21) /* general call address detected */ 66 #define SPACEMIT_SR_BED BIT(22) /* bus error no ACK/NAK */ 67 #define SPACEMIT_SR_SAD BIT(23) /* slave address detected */ 68 #define SPACEMIT_SR_SSD BIT(24) /* slave stop detected */ 69 /* Bit 25 is reserved */ 70 #define SPACEMIT_SR_MSD BIT(26) /* master stop detected */ 71 #define SPACEMIT_SR_TXDONE BIT(27) /* transaction done */ 72 #define SPACEMIT_SR_TXE BIT(28) /* TX FIFO empty */ 73 #define SPACEMIT_SR_RXHF BIT(29) /* RX FIFO half-full */ 74 #define SPACEMIT_SR_RXF BIT(30) /* RX FIFO full */ 75 #define SPACEMIT_SR_RXOV BIT(31) /* RX FIFO overrun */ 76 77 #define SPACEMIT_I2C_INT_STATUS_MASK (SPACEMIT_SR_RXOV | SPACEMIT_SR_RXF | SPACEMIT_SR_RXHF | \ 78 SPACEMIT_SR_TXE | SPACEMIT_SR_TXDONE | SPACEMIT_SR_MSD | \ 79 SPACEMIT_SR_SSD | SPACEMIT_SR_SAD | SPACEMIT_SR_BED | \ 80 SPACEMIT_SR_GCAD | SPACEMIT_SR_IRF | SPACEMIT_SR_ITE | \ 81 SPACEMIT_SR_ALD) 82 83 #define SPACEMIT_RCR_SDA_GLITCH_NOFIX BIT(7) /* bypass the SDA glitch fix */ 84 /* the cycles of SCL during bus reset */ 85 #define SPACEMIT_RCR_FIELD_RST_CYC GENMASK(3, 0) 86 87 /* SPACEMIT_IBMR register fields */ 88 #define SPACEMIT_BMR_SDA BIT(0) /* SDA line level */ 89 #define SPACEMIT_BMR_SCL BIT(1) /* SCL line level */ 90 91 /* i2c bus recover timeout: us */ 92 #define SPACEMIT_I2C_BUS_BUSY_TIMEOUT 100000 93 94 #define SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ 100000 /* Hz */ 95 #define SPACEMIT_I2C_MAX_FAST_MODE_FREQ 400000 /* Hz */ 96 97 #define SPACEMIT_SR_ERR (SPACEMIT_SR_BED | SPACEMIT_SR_RXOV | SPACEMIT_SR_ALD) 98 99 #define SPACEMIT_BUS_RESET_CLK_CNT_MAX 9 100 101 #define SPACEMIT_WAIT_TIMEOUT 1000 /* ms */ 102 #define SPACEMIT_POLL_TIMEOUT 1000 /* us */ 103 #define SPACEMIT_POLL_INTERVAL 30 /* us */ 104 105 enum spacemit_i2c_state { 106 SPACEMIT_STATE_IDLE, 107 SPACEMIT_STATE_START, 108 SPACEMIT_STATE_READ, 109 SPACEMIT_STATE_WRITE, 110 }; 111 112 /* i2c-spacemit driver's main struct */ 113 struct spacemit_i2c_dev { 114 struct device *dev; 115 struct i2c_adapter adapt; 116 117 /* hardware resources */ 118 void __iomem *base; 119 int irq; 120 u32 clock_freq; 121 122 struct i2c_msg *msgs; 123 u32 msg_num; 124 125 /* index of the current message being processed */ 126 u32 msg_idx; 127 u8 *msg_buf; 128 /* the number of unprocessed bytes remaining in the current message */ 129 u32 unprocessed; 130 131 enum spacemit_i2c_state state; 132 bool read; 133 bool use_pio; 134 struct completion complete; 135 u32 status; 136 }; 137 138 static void spacemit_i2c_enable(struct spacemit_i2c_dev *i2c) 139 { 140 u32 val; 141 142 val = readl(i2c->base + SPACEMIT_ICR); 143 val |= SPACEMIT_CR_IUE; 144 writel(val, i2c->base + SPACEMIT_ICR); 145 } 146 147 static void spacemit_i2c_disable(struct spacemit_i2c_dev *i2c) 148 { 149 u32 val; 150 151 val = readl(i2c->base + SPACEMIT_ICR); 152 val &= ~SPACEMIT_CR_IUE; 153 writel(val, i2c->base + SPACEMIT_ICR); 154 } 155 156 static void spacemit_i2c_reset(struct spacemit_i2c_dev *i2c) 157 { 158 writel(SPACEMIT_CR_UR, i2c->base + SPACEMIT_ICR); 159 udelay(5); 160 writel(0, i2c->base + SPACEMIT_ICR); 161 } 162 163 static int spacemit_i2c_handle_err(struct spacemit_i2c_dev *i2c) 164 { 165 dev_dbg(i2c->dev, "i2c error status: 0x%08x\n", i2c->status); 166 167 /* Arbitration Loss Detected */ 168 if (i2c->status & SPACEMIT_SR_ALD) { 169 spacemit_i2c_reset(i2c); 170 return -EAGAIN; 171 } 172 173 /* Bus Error No ACK/NAK */ 174 if (i2c->status & SPACEMIT_SR_BED) 175 spacemit_i2c_reset(i2c); 176 177 return i2c->status & SPACEMIT_SR_ACKNAK ? -ENXIO : -EIO; 178 } 179 180 static inline void spacemit_i2c_delay(struct spacemit_i2c_dev *i2c, unsigned int us) 181 { 182 if (i2c->use_pio) 183 udelay(us); 184 else 185 fsleep(us); 186 } 187 188 static void spacemit_i2c_conditionally_reset_bus(struct spacemit_i2c_dev *i2c) 189 { 190 u32 status; 191 u8 clk_cnt; 192 193 /* if bus is locked, reset unit. 0: locked */ 194 status = readl(i2c->base + SPACEMIT_IBMR); 195 if ((status & SPACEMIT_BMR_SDA) && (status & SPACEMIT_BMR_SCL)) 196 return; 197 198 spacemit_i2c_reset(i2c); 199 200 spacemit_i2c_delay(i2c, 10); 201 202 for (clk_cnt = 0; clk_cnt < SPACEMIT_BUS_RESET_CLK_CNT_MAX; clk_cnt++) { 203 status = readl(i2c->base + SPACEMIT_IBMR); 204 if (status & SPACEMIT_BMR_SDA) 205 return; 206 207 /* There's nothing left to save here, we are about to exit */ 208 writel(FIELD_PREP(SPACEMIT_RCR_FIELD_RST_CYC, 1), 209 i2c->base + SPACEMIT_IRCR); 210 writel(SPACEMIT_CR_RSTREQ, i2c->base + SPACEMIT_ICR); 211 usleep_range(20, 30); 212 } 213 214 /* check sda again here */ 215 status = readl(i2c->base + SPACEMIT_IBMR); 216 if (!(status & SPACEMIT_BMR_SDA)) 217 dev_warn_ratelimited(i2c->dev, "unit reset failed\n"); 218 } 219 220 static int spacemit_i2c_wait_bus_idle(struct spacemit_i2c_dev *i2c) 221 { 222 int ret; 223 u32 val; 224 225 val = readl(i2c->base + SPACEMIT_ISR); 226 if (!(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB))) 227 return 0; 228 229 if (i2c->use_pio) 230 ret = readl_poll_timeout_atomic(i2c->base + SPACEMIT_ISR, 231 val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)), 232 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT); 233 else 234 ret = readl_poll_timeout(i2c->base + SPACEMIT_ISR, 235 val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)), 236 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT); 237 238 if (ret) 239 spacemit_i2c_reset(i2c); 240 241 return ret; 242 } 243 244 static void spacemit_i2c_check_bus_release(struct spacemit_i2c_dev *i2c) 245 { 246 /* in case bus is not released after transfer completes */ 247 if (readl(i2c->base + SPACEMIT_ISR) & SPACEMIT_SR_EBB) { 248 spacemit_i2c_conditionally_reset_bus(i2c); 249 spacemit_i2c_delay(i2c, 90); 250 } 251 } 252 253 static inline void 254 spacemit_i2c_clear_int_status(struct spacemit_i2c_dev *i2c, u32 mask) 255 { 256 writel(mask & SPACEMIT_I2C_INT_STATUS_MASK, i2c->base + SPACEMIT_ISR); 257 } 258 259 static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) 260 { 261 u32 val = 0; 262 263 if (!i2c->use_pio) { 264 /* 265 * Enable interrupt bits for all xfer mode: 266 * bus error, arbitration loss detected. 267 */ 268 val |= SPACEMIT_CR_BEIE | SPACEMIT_CR_ALDIE; 269 270 /* 271 * Unmask interrupt bits for interrupt xfer mode: 272 * When IDBR receives a byte, an interrupt is triggered. 273 * 274 * For the tx empty interrupt, it will be enabled in the 275 * i2c_start(). 276 * We don't want a TX empty interrupt until we start 277 * a transfer in i2c_start(). 278 */ 279 val |= SPACEMIT_CR_DRFIE; 280 281 /* 282 * Enable master stop interrupt bit. 283 * For transaction complete signal, we use master stop 284 * interrupt, so we don't need to unmask SPACEMIT_CR_TXDONEIE. 285 */ 286 val |= SPACEMIT_CR_MSDIE; 287 } 288 289 if (i2c->clock_freq == SPACEMIT_I2C_MAX_FAST_MODE_FREQ) 290 val |= SPACEMIT_CR_MODE_FAST; 291 292 /* disable response to general call */ 293 val |= SPACEMIT_CR_GCD; 294 295 /* enable SCL clock output */ 296 val |= SPACEMIT_CR_SCLE; 297 298 /* enable master stop detected */ 299 val |= SPACEMIT_CR_MSDE; 300 301 writel(val, i2c->base + SPACEMIT_ICR); 302 303 /* 304 * The glitch fix in the K1 I2C controller introduces a delay 305 * on restart signals, so we disable the fix here. 306 */ 307 val = readl(i2c->base + SPACEMIT_IRCR); 308 val |= SPACEMIT_RCR_SDA_GLITCH_NOFIX; 309 writel(val, i2c->base + SPACEMIT_IRCR); 310 311 spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK); 312 } 313 314 static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c) 315 { 316 u32 target_addr_rw, val; 317 struct i2c_msg *cur_msg = i2c->msgs + i2c->msg_idx; 318 319 i2c->read = !!(cur_msg->flags & I2C_M_RD); 320 321 i2c->state = SPACEMIT_STATE_START; 322 323 target_addr_rw = (cur_msg->addr & 0x7f) << 1; 324 if (cur_msg->flags & I2C_M_RD) 325 target_addr_rw |= 1; 326 327 writel(target_addr_rw, i2c->base + SPACEMIT_IDBR); 328 329 /* send start pulse */ 330 val = readl(i2c->base + SPACEMIT_ICR); 331 val &= ~SPACEMIT_CR_STOP; 332 val |= SPACEMIT_CR_START | SPACEMIT_CR_TB; 333 334 /* Enable the TX empty interrupt */ 335 if (!i2c->use_pio) 336 val |= SPACEMIT_CR_DTEIE; 337 338 writel(val, i2c->base + SPACEMIT_ICR); 339 } 340 341 static bool spacemit_i2c_is_last_msg(struct spacemit_i2c_dev *i2c) 342 { 343 if (i2c->msg_idx != i2c->msg_num - 1) 344 return false; 345 346 if (i2c->read) 347 return i2c->unprocessed == 1; 348 349 return !i2c->unprocessed; 350 } 351 352 static inline void spacemit_i2c_complete(struct spacemit_i2c_dev *i2c) 353 { 354 /* SPACEMIT_STATE_IDLE avoids triggering the next byte */ 355 i2c->state = SPACEMIT_STATE_IDLE; 356 357 if (i2c->use_pio) 358 return; 359 360 complete(&i2c->complete); 361 } 362 363 static void spacemit_i2c_handle_write(struct spacemit_i2c_dev *i2c) 364 { 365 /* If there's no space in the IDBR, we're done */ 366 if (!(i2c->status & SPACEMIT_SR_ITE)) 367 return; 368 369 /* if transfer completes, SPACEMIT_ISR will handle it */ 370 if (i2c->status & SPACEMIT_SR_MSD) 371 return; 372 373 if (i2c->unprocessed) { 374 writel(*i2c->msg_buf++, i2c->base + SPACEMIT_IDBR); 375 i2c->unprocessed--; 376 return; 377 } 378 379 spacemit_i2c_complete(i2c); 380 } 381 382 static void spacemit_i2c_handle_read(struct spacemit_i2c_dev *i2c) 383 { 384 /* If there's nothing in the IDBR, we're done */ 385 if (!(i2c->status & SPACEMIT_SR_IRF)) 386 return; 387 388 if (i2c->unprocessed) { 389 *i2c->msg_buf++ = readl(i2c->base + SPACEMIT_IDBR); 390 i2c->unprocessed--; 391 return; 392 } 393 394 /* if transfer completes, SPACEMIT_ISR will handle it */ 395 if (i2c->status & (SPACEMIT_SR_MSD | SPACEMIT_SR_ACKNAK)) 396 return; 397 398 /* it has to append stop bit in icr that read last byte */ 399 if (i2c->unprocessed) 400 return; 401 402 spacemit_i2c_complete(i2c); 403 } 404 405 static void spacemit_i2c_handle_start(struct spacemit_i2c_dev *i2c) 406 { 407 i2c->state = i2c->read ? SPACEMIT_STATE_READ : SPACEMIT_STATE_WRITE; 408 if (i2c->state == SPACEMIT_STATE_WRITE) 409 spacemit_i2c_handle_write(i2c); 410 } 411 412 static void spacemit_i2c_err_check(struct spacemit_i2c_dev *i2c) 413 { 414 u32 val; 415 416 /* 417 * Send transaction complete signal: 418 * error happens, detect master stop 419 */ 420 if (!(i2c->status & (SPACEMIT_SR_ERR | SPACEMIT_SR_MSD))) 421 return; 422 423 /* 424 * Here the transaction is already done, we don't need any 425 * other interrupt signals from now, in case any interrupt 426 * happens before spacemit_i2c_xfer to disable irq and i2c unit, 427 * we mask all the interrupt signals and clear the interrupt 428 * status. 429 */ 430 val = readl(i2c->base + SPACEMIT_ICR); 431 val &= ~SPACEMIT_I2C_INT_CTRL_MASK; 432 writel(val, i2c->base + SPACEMIT_ICR); 433 434 spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK); 435 436 spacemit_i2c_complete(i2c); 437 } 438 439 static void spacemit_i2c_handle_state(struct spacemit_i2c_dev *i2c) 440 { 441 u32 val; 442 443 if (i2c->status & SPACEMIT_SR_ERR) 444 goto err_out; 445 446 switch (i2c->state) { 447 case SPACEMIT_STATE_START: 448 spacemit_i2c_handle_start(i2c); 449 break; 450 case SPACEMIT_STATE_READ: 451 spacemit_i2c_handle_read(i2c); 452 break; 453 case SPACEMIT_STATE_WRITE: 454 spacemit_i2c_handle_write(i2c); 455 break; 456 default: 457 break; 458 } 459 460 if (i2c->state != SPACEMIT_STATE_IDLE) { 461 val = readl(i2c->base + SPACEMIT_ICR); 462 val &= ~(SPACEMIT_CR_TB | SPACEMIT_CR_ACKNAK | 463 SPACEMIT_CR_STOP | SPACEMIT_CR_START); 464 val |= SPACEMIT_CR_TB; 465 if (!i2c->use_pio) 466 val |= SPACEMIT_CR_ALDIE; 467 468 if (spacemit_i2c_is_last_msg(i2c)) { 469 /* trigger next byte with stop */ 470 val |= SPACEMIT_CR_STOP; 471 472 if (i2c->read) 473 val |= SPACEMIT_CR_ACKNAK; 474 } 475 writel(val, i2c->base + SPACEMIT_ICR); 476 } 477 478 err_out: 479 spacemit_i2c_err_check(i2c); 480 } 481 482 /* 483 * In PIO mode, this function is used as a replacement for 484 * wait_for_completion_timeout(), whose return value indicates 485 * the remaining time. 486 * 487 * We do not have a meaningful remaining-time value here, so 488 * return a non-zero value on success to indicate "not timed out". 489 * Returning 1 ensures callers treating the return value as 490 * time_left will not incorrectly report a timeout. 491 */ 492 static int spacemit_i2c_wait_pio_xfer(struct spacemit_i2c_dev *i2c) 493 { 494 u32 mask, msec = jiffies_to_msecs(i2c->adapt.timeout); 495 ktime_t timeout = ktime_add_ms(ktime_get(), msec); 496 int ret; 497 498 mask = SPACEMIT_SR_IRF | SPACEMIT_SR_ITE; 499 500 do { 501 i2c->status = readl(i2c->base + SPACEMIT_ISR); 502 503 spacemit_i2c_clear_int_status(i2c, i2c->status); 504 505 if (i2c->status & mask) 506 spacemit_i2c_handle_state(i2c); 507 else 508 udelay(SPACEMIT_POLL_INTERVAL); 509 } while (i2c->unprocessed && ktime_compare(ktime_get(), timeout) < 0); 510 511 if (i2c->unprocessed) 512 return 0; 513 514 if (i2c->read) 515 return 1; 516 517 /* 518 * If this is the last byte to write of the current message, 519 * we have to wait here. Otherwise, control will proceed directly 520 * to start(), which would overwrite the current data. 521 */ 522 ret = readl_poll_timeout_atomic(i2c->base + SPACEMIT_ISR, 523 i2c->status, i2c->status & SPACEMIT_SR_ITE, 524 SPACEMIT_POLL_INTERVAL, SPACEMIT_POLL_TIMEOUT); 525 if (ret) 526 return 0; 527 528 /* 529 * For writes: in interrupt mode, an ITE (write-empty) interrupt is triggered 530 * after the last byte, and the MSD-related handling takes place there. 531 * In PIO mode, however, we need to explicitly call err_check() to emulate this 532 * step, otherwise the next transfer will fail. 533 */ 534 if (i2c->msg_idx == i2c->msg_num - 1) { 535 mask = SPACEMIT_SR_MSD | SPACEMIT_SR_ERR; 536 /* 537 * In some cases, MSD may not arrive immediately; 538 * wait here to handle that. 539 */ 540 ret = readl_poll_timeout_atomic(i2c->base + SPACEMIT_ISR, 541 i2c->status, i2c->status & mask, 542 SPACEMIT_POLL_INTERVAL, SPACEMIT_POLL_TIMEOUT); 543 if (ret) 544 return 0; 545 546 spacemit_i2c_err_check(i2c); 547 } 548 549 return 1; 550 } 551 552 static int spacemit_i2c_wait_xfer_complete(struct spacemit_i2c_dev *i2c) 553 { 554 if (i2c->use_pio) 555 return spacemit_i2c_wait_pio_xfer(i2c); 556 557 return wait_for_completion_timeout(&i2c->complete, 558 i2c->adapt.timeout); 559 } 560 561 static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) 562 { 563 unsigned long time_left; 564 struct i2c_msg *msg; 565 566 for (i2c->msg_idx = 0; i2c->msg_idx < i2c->msg_num; i2c->msg_idx++) { 567 msg = &i2c->msgs[i2c->msg_idx]; 568 i2c->msg_buf = msg->buf; 569 i2c->unprocessed = msg->len; 570 i2c->status = 0; 571 572 reinit_completion(&i2c->complete); 573 574 spacemit_i2c_start(i2c); 575 576 time_left = spacemit_i2c_wait_xfer_complete(i2c); 577 578 if (!time_left) { 579 dev_err(i2c->dev, "msg completion timeout\n"); 580 spacemit_i2c_conditionally_reset_bus(i2c); 581 spacemit_i2c_reset(i2c); 582 return -ETIMEDOUT; 583 } 584 585 if (i2c->status & SPACEMIT_SR_ERR) 586 return spacemit_i2c_handle_err(i2c); 587 } 588 589 return 0; 590 } 591 592 static irqreturn_t spacemit_i2c_irq_handler(int irq, void *devid) 593 { 594 struct spacemit_i2c_dev *i2c = devid; 595 u32 status; 596 597 status = readl(i2c->base + SPACEMIT_ISR); 598 if (!status) 599 return IRQ_HANDLED; 600 601 i2c->status = status; 602 603 spacemit_i2c_clear_int_status(i2c, status); 604 605 spacemit_i2c_handle_state(i2c); 606 607 return IRQ_HANDLED; 608 } 609 610 static void spacemit_i2c_calc_timeout(struct spacemit_i2c_dev *i2c) 611 { 612 unsigned long timeout; 613 int idx = 0, cnt = 0; 614 615 if (i2c->use_pio) { 616 i2c->adapt.timeout = msecs_to_jiffies(SPACEMIT_WAIT_TIMEOUT); 617 return; 618 } 619 620 for (; idx < i2c->msg_num; idx++) 621 cnt += (i2c->msgs + idx)->len + 1; 622 623 /* 624 * Multiply by 9 because each byte in I2C transmission requires 625 * 9 clock cycles: 8 bits of data plus 1 ACK/NACK bit. 626 */ 627 timeout = cnt * 9 * USEC_PER_SEC / i2c->clock_freq; 628 629 i2c->adapt.timeout = usecs_to_jiffies(timeout + USEC_PER_SEC / 10) / i2c->msg_num; 630 } 631 632 static inline int 633 spacemit_i2c_xfer_common(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num, bool use_pio) 634 { 635 struct spacemit_i2c_dev *i2c = i2c_get_adapdata(adapt); 636 int ret; 637 638 i2c->use_pio = use_pio; 639 640 i2c->msgs = msgs; 641 i2c->msg_num = num; 642 643 spacemit_i2c_calc_timeout(i2c); 644 645 spacemit_i2c_init(i2c); 646 647 spacemit_i2c_enable(i2c); 648 649 ret = spacemit_i2c_wait_bus_idle(i2c); 650 if (!ret) { 651 ret = spacemit_i2c_xfer_msg(i2c); 652 if (ret < 0) 653 dev_dbg(i2c->dev, "i2c transfer error: %d\n", ret); 654 } else { 655 spacemit_i2c_check_bus_release(i2c); 656 } 657 658 spacemit_i2c_disable(i2c); 659 660 if (ret == -ETIMEDOUT || ret == -EAGAIN) 661 dev_err(i2c->dev, "i2c transfer failed, ret %d err 0x%lx\n", 662 ret, i2c->status & SPACEMIT_SR_ERR); 663 664 return ret < 0 ? ret : num; 665 } 666 667 static int spacemit_i2c_xfer(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num) 668 { 669 return spacemit_i2c_xfer_common(adapt, msgs, num, false); 670 } 671 672 static int spacemit_i2c_pio_xfer_atomic(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num) 673 { 674 return spacemit_i2c_xfer_common(adapt, msgs, num, true); 675 } 676 677 static u32 spacemit_i2c_func(struct i2c_adapter *adap) 678 { 679 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 680 } 681 682 static const struct i2c_algorithm spacemit_i2c_algo = { 683 .xfer = spacemit_i2c_xfer, 684 .xfer_atomic = spacemit_i2c_pio_xfer_atomic, 685 .functionality = spacemit_i2c_func, 686 }; 687 688 static int spacemit_i2c_probe(struct platform_device *pdev) 689 { 690 struct clk *clk; 691 struct device *dev = &pdev->dev; 692 struct device_node *of_node = pdev->dev.of_node; 693 struct spacemit_i2c_dev *i2c; 694 struct reset_control *rst; 695 int ret; 696 697 i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL); 698 if (!i2c) 699 return -ENOMEM; 700 701 ret = of_property_read_u32(of_node, "clock-frequency", &i2c->clock_freq); 702 if (ret && ret != -EINVAL) 703 dev_warn(dev, "failed to read clock-frequency property: %d\n", ret); 704 705 /* For now, this driver doesn't support high-speed. */ 706 if (!i2c->clock_freq || i2c->clock_freq > SPACEMIT_I2C_MAX_FAST_MODE_FREQ) { 707 dev_warn(dev, "unsupported clock frequency %u; using %u\n", 708 i2c->clock_freq, SPACEMIT_I2C_MAX_FAST_MODE_FREQ); 709 i2c->clock_freq = SPACEMIT_I2C_MAX_FAST_MODE_FREQ; 710 } else if (i2c->clock_freq < SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) { 711 dev_warn(dev, "unsupported clock frequency %u; using %u\n", 712 i2c->clock_freq, SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ); 713 i2c->clock_freq = SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ; 714 } 715 716 i2c->dev = &pdev->dev; 717 718 i2c->base = devm_platform_ioremap_resource(pdev, 0); 719 if (IS_ERR(i2c->base)) 720 return dev_err_probe(dev, PTR_ERR(i2c->base), "failed to do ioremap"); 721 722 i2c->irq = platform_get_irq(pdev, 0); 723 if (i2c->irq < 0) 724 return dev_err_probe(dev, i2c->irq, "failed to get irq resource"); 725 726 ret = devm_request_irq(i2c->dev, i2c->irq, spacemit_i2c_irq_handler, 727 IRQF_NO_SUSPEND, dev_name(i2c->dev), i2c); 728 if (ret) 729 return dev_err_probe(dev, ret, "failed to request irq"); 730 731 clk = devm_clk_get_enabled(dev, "func"); 732 if (IS_ERR(clk)) 733 return dev_err_probe(dev, PTR_ERR(clk), "failed to enable func clock"); 734 735 clk = devm_clk_get_enabled(dev, "bus"); 736 if (IS_ERR(clk)) 737 return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock"); 738 739 rst = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL); 740 if (IS_ERR(rst)) 741 return dev_err_probe(dev, PTR_ERR(rst), 742 "failed to acquire deasserted reset\n"); 743 744 spacemit_i2c_reset(i2c); 745 746 i2c_set_adapdata(&i2c->adapt, i2c); 747 i2c->adapt.owner = THIS_MODULE; 748 i2c->adapt.algo = &spacemit_i2c_algo; 749 i2c->adapt.dev.parent = i2c->dev; 750 i2c->adapt.nr = pdev->id; 751 752 i2c->adapt.dev.of_node = of_node; 753 754 strscpy(i2c->adapt.name, "spacemit-i2c-adapter", sizeof(i2c->adapt.name)); 755 756 init_completion(&i2c->complete); 757 758 platform_set_drvdata(pdev, i2c); 759 760 ret = i2c_add_numbered_adapter(&i2c->adapt); 761 if (ret) 762 return dev_err_probe(&pdev->dev, ret, "failed to add i2c adapter"); 763 764 return 0; 765 } 766 767 static void spacemit_i2c_remove(struct platform_device *pdev) 768 { 769 struct spacemit_i2c_dev *i2c = platform_get_drvdata(pdev); 770 771 i2c_del_adapter(&i2c->adapt); 772 } 773 774 static const struct of_device_id spacemit_i2c_of_match[] = { 775 { .compatible = "spacemit,k1-i2c", }, 776 { /* sentinel */ } 777 }; 778 MODULE_DEVICE_TABLE(of, spacemit_i2c_of_match); 779 780 static struct platform_driver spacemit_i2c_driver = { 781 .probe = spacemit_i2c_probe, 782 .remove = spacemit_i2c_remove, 783 .driver = { 784 .name = "i2c-k1", 785 .of_match_table = spacemit_i2c_of_match, 786 }, 787 }; 788 module_platform_driver(spacemit_i2c_driver); 789 790 MODULE_LICENSE("GPL"); 791 MODULE_DESCRIPTION("I2C bus driver for SpacemiT K1 SoC"); 792