1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2024-2025 Troy Mitchell <troymitchell988@gmail.com> 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/clk.h> 8 #include <linux/i2c.h> 9 #include <linux/iopoll.h> 10 #include <linux/module.h> 11 #include <linux/of_address.h> 12 #include <linux/platform_device.h> 13 14 /* spacemit i2c registers */ 15 #define SPACEMIT_ICR 0x0 /* Control register */ 16 #define SPACEMIT_ISR 0x4 /* Status register */ 17 #define SPACEMIT_IDBR 0xc /* Data buffer register */ 18 #define SPACEMIT_IRCR 0x18 /* Reset cycle counter */ 19 #define SPACEMIT_IBMR 0x1c /* Bus monitor register */ 20 21 /* SPACEMIT_ICR register fields */ 22 #define SPACEMIT_CR_START BIT(0) /* start bit */ 23 #define SPACEMIT_CR_STOP BIT(1) /* stop bit */ 24 #define SPACEMIT_CR_ACKNAK BIT(2) /* send ACK(0) or NAK(1) */ 25 #define SPACEMIT_CR_TB BIT(3) /* transfer byte bit */ 26 /* Bits 4-7 are reserved */ 27 #define SPACEMIT_CR_MODE_FAST BIT(8) /* bus mode (master operation) */ 28 /* Bit 9 is reserved */ 29 #define SPACEMIT_CR_UR BIT(10) /* unit reset */ 30 #define SPACEMIT_CR_RSTREQ BIT(11) /* i2c bus reset request */ 31 /* Bit 12 is reserved */ 32 #define SPACEMIT_CR_SCLE BIT(13) /* master clock enable */ 33 #define SPACEMIT_CR_IUE BIT(14) /* unit enable */ 34 /* Bits 15-17 are reserved */ 35 #define SPACEMIT_CR_ALDIE BIT(18) /* enable arbitration interrupt */ 36 #define SPACEMIT_CR_DTEIE BIT(19) /* enable TX interrupts */ 37 #define SPACEMIT_CR_DRFIE BIT(20) /* enable RX interrupts */ 38 #define SPACEMIT_CR_GCD BIT(21) /* general call disable */ 39 #define SPACEMIT_CR_BEIE BIT(22) /* enable bus error ints */ 40 /* Bits 23-24 are reserved */ 41 #define SPACEMIT_CR_MSDIE BIT(25) /* master STOP detected int enable */ 42 #define SPACEMIT_CR_MSDE BIT(26) /* master STOP detected enable */ 43 #define SPACEMIT_CR_TXDONEIE BIT(27) /* transaction done int enable */ 44 #define SPACEMIT_CR_TXEIE BIT(28) /* transmit FIFO empty int enable */ 45 #define SPACEMIT_CR_RXHFIE BIT(29) /* receive FIFO half-full int enable */ 46 #define SPACEMIT_CR_RXFIE BIT(30) /* receive FIFO full int enable */ 47 #define SPACEMIT_CR_RXOVIE BIT(31) /* receive FIFO overrun int enable */ 48 49 #define SPACEMIT_I2C_INT_CTRL_MASK (SPACEMIT_CR_ALDIE | SPACEMIT_CR_DTEIE | \ 50 SPACEMIT_CR_DRFIE | SPACEMIT_CR_BEIE | \ 51 SPACEMIT_CR_TXDONEIE | SPACEMIT_CR_TXEIE | \ 52 SPACEMIT_CR_RXHFIE | SPACEMIT_CR_RXFIE | \ 53 SPACEMIT_CR_RXOVIE | SPACEMIT_CR_MSDIE) 54 55 /* SPACEMIT_ISR register fields */ 56 /* Bits 0-13 are reserved */ 57 #define SPACEMIT_SR_ACKNAK BIT(14) /* ACK/NACK status */ 58 #define SPACEMIT_SR_UB BIT(15) /* unit busy */ 59 #define SPACEMIT_SR_IBB BIT(16) /* i2c bus busy */ 60 #define SPACEMIT_SR_EBB BIT(17) /* early bus busy */ 61 #define SPACEMIT_SR_ALD BIT(18) /* arbitration loss detected */ 62 #define SPACEMIT_SR_ITE BIT(19) /* TX buffer empty */ 63 #define SPACEMIT_SR_IRF BIT(20) /* RX buffer full */ 64 #define SPACEMIT_SR_GCAD BIT(21) /* general call address detected */ 65 #define SPACEMIT_SR_BED BIT(22) /* bus error no ACK/NAK */ 66 #define SPACEMIT_SR_SAD BIT(23) /* slave address detected */ 67 #define SPACEMIT_SR_SSD BIT(24) /* slave stop detected */ 68 /* Bit 25 is reserved */ 69 #define SPACEMIT_SR_MSD BIT(26) /* master stop detected */ 70 #define SPACEMIT_SR_TXDONE BIT(27) /* transaction done */ 71 #define SPACEMIT_SR_TXE BIT(28) /* TX FIFO empty */ 72 #define SPACEMIT_SR_RXHF BIT(29) /* RX FIFO half-full */ 73 #define SPACEMIT_SR_RXF BIT(30) /* RX FIFO full */ 74 #define SPACEMIT_SR_RXOV BIT(31) /* RX FIFO overrun */ 75 76 #define SPACEMIT_I2C_INT_STATUS_MASK (SPACEMIT_SR_RXOV | SPACEMIT_SR_RXF | SPACEMIT_SR_RXHF | \ 77 SPACEMIT_SR_TXE | SPACEMIT_SR_TXDONE | SPACEMIT_SR_MSD | \ 78 SPACEMIT_SR_SSD | SPACEMIT_SR_SAD | SPACEMIT_SR_BED | \ 79 SPACEMIT_SR_GCAD | SPACEMIT_SR_IRF | SPACEMIT_SR_ITE | \ 80 SPACEMIT_SR_ALD) 81 82 #define SPACEMIT_RCR_SDA_GLITCH_NOFIX BIT(7) /* bypass the SDA glitch fix */ 83 /* the cycles of SCL during bus reset */ 84 #define SPACEMIT_RCR_FIELD_RST_CYC GENMASK(3, 0) 85 86 /* SPACEMIT_IBMR register fields */ 87 #define SPACEMIT_BMR_SDA BIT(0) /* SDA line level */ 88 #define SPACEMIT_BMR_SCL BIT(1) /* SCL line level */ 89 90 /* i2c bus recover timeout: us */ 91 #define SPACEMIT_I2C_BUS_BUSY_TIMEOUT 100000 92 93 #define SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ 100000 /* Hz */ 94 #define SPACEMIT_I2C_MAX_FAST_MODE_FREQ 400000 /* Hz */ 95 96 #define SPACEMIT_SR_ERR (SPACEMIT_SR_BED | SPACEMIT_SR_RXOV | SPACEMIT_SR_ALD) 97 98 #define SPACEMIT_BUS_RESET_CLK_CNT_MAX 9 99 100 enum spacemit_i2c_state { 101 SPACEMIT_STATE_IDLE, 102 SPACEMIT_STATE_START, 103 SPACEMIT_STATE_READ, 104 SPACEMIT_STATE_WRITE, 105 }; 106 107 /* i2c-spacemit driver's main struct */ 108 struct spacemit_i2c_dev { 109 struct device *dev; 110 struct i2c_adapter adapt; 111 112 /* hardware resources */ 113 void __iomem *base; 114 int irq; 115 u32 clock_freq; 116 117 struct i2c_msg *msgs; 118 u32 msg_num; 119 120 /* index of the current message being processed */ 121 u32 msg_idx; 122 u8 *msg_buf; 123 /* the number of unprocessed bytes remaining in the current message */ 124 u32 unprocessed; 125 126 enum spacemit_i2c_state state; 127 bool read; 128 struct completion complete; 129 u32 status; 130 }; 131 132 static void spacemit_i2c_enable(struct spacemit_i2c_dev *i2c) 133 { 134 u32 val; 135 136 val = readl(i2c->base + SPACEMIT_ICR); 137 val |= SPACEMIT_CR_IUE; 138 writel(val, i2c->base + SPACEMIT_ICR); 139 } 140 141 static void spacemit_i2c_disable(struct spacemit_i2c_dev *i2c) 142 { 143 u32 val; 144 145 val = readl(i2c->base + SPACEMIT_ICR); 146 val &= ~SPACEMIT_CR_IUE; 147 writel(val, i2c->base + SPACEMIT_ICR); 148 } 149 150 static void spacemit_i2c_reset(struct spacemit_i2c_dev *i2c) 151 { 152 writel(SPACEMIT_CR_UR, i2c->base + SPACEMIT_ICR); 153 udelay(5); 154 writel(0, i2c->base + SPACEMIT_ICR); 155 } 156 157 static int spacemit_i2c_handle_err(struct spacemit_i2c_dev *i2c) 158 { 159 dev_dbg(i2c->dev, "i2c error status: 0x%08x\n", i2c->status); 160 161 if (i2c->status & (SPACEMIT_SR_BED | SPACEMIT_SR_ALD)) { 162 spacemit_i2c_reset(i2c); 163 return -EAGAIN; 164 } 165 166 return i2c->status & SPACEMIT_SR_ACKNAK ? -ENXIO : -EIO; 167 } 168 169 static void spacemit_i2c_conditionally_reset_bus(struct spacemit_i2c_dev *i2c) 170 { 171 u32 status; 172 u8 clk_cnt; 173 174 /* if bus is locked, reset unit. 0: locked */ 175 status = readl(i2c->base + SPACEMIT_IBMR); 176 if ((status & SPACEMIT_BMR_SDA) && (status & SPACEMIT_BMR_SCL)) 177 return; 178 179 spacemit_i2c_reset(i2c); 180 usleep_range(10, 20); 181 182 for (clk_cnt = 0; clk_cnt < SPACEMIT_BUS_RESET_CLK_CNT_MAX; clk_cnt++) { 183 status = readl(i2c->base + SPACEMIT_IBMR); 184 if (status & SPACEMIT_BMR_SDA) 185 return; 186 187 /* There's nothing left to save here, we are about to exit */ 188 writel(FIELD_PREP(SPACEMIT_RCR_FIELD_RST_CYC, 1), 189 i2c->base + SPACEMIT_IRCR); 190 writel(SPACEMIT_CR_RSTREQ, i2c->base + SPACEMIT_ICR); 191 usleep_range(20, 30); 192 } 193 194 /* check sda again here */ 195 status = readl(i2c->base + SPACEMIT_IBMR); 196 if (!(status & SPACEMIT_BMR_SDA)) 197 dev_warn_ratelimited(i2c->dev, "unit reset failed\n"); 198 } 199 200 static int spacemit_i2c_wait_bus_idle(struct spacemit_i2c_dev *i2c) 201 { 202 int ret; 203 u32 val; 204 205 val = readl(i2c->base + SPACEMIT_ISR); 206 if (!(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB))) 207 return 0; 208 209 ret = readl_poll_timeout(i2c->base + SPACEMIT_ISR, 210 val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)), 211 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT); 212 if (ret) 213 spacemit_i2c_reset(i2c); 214 215 return ret; 216 } 217 218 static void spacemit_i2c_check_bus_release(struct spacemit_i2c_dev *i2c) 219 { 220 /* in case bus is not released after transfer completes */ 221 if (readl(i2c->base + SPACEMIT_ISR) & SPACEMIT_SR_EBB) { 222 spacemit_i2c_conditionally_reset_bus(i2c); 223 usleep_range(90, 150); 224 } 225 } 226 227 static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) 228 { 229 u32 val; 230 231 /* 232 * Unmask interrupt bits for all xfer mode: 233 * bus error, arbitration loss detected. 234 * For transaction complete signal, we use master stop 235 * interrupt, so we don't need to unmask SPACEMIT_CR_TXDONEIE. 236 */ 237 val = SPACEMIT_CR_BEIE | SPACEMIT_CR_ALDIE; 238 239 /* 240 * Unmask interrupt bits for interrupt xfer mode: 241 * When IDBR receives a byte, an interrupt is triggered. 242 * 243 * For the tx empty interrupt, it will be enabled in the 244 * i2c_start function. 245 * Otherwise, it will cause an erroneous empty interrupt before i2c_start. 246 */ 247 val |= SPACEMIT_CR_DRFIE; 248 249 if (i2c->clock_freq == SPACEMIT_I2C_MAX_FAST_MODE_FREQ) 250 val |= SPACEMIT_CR_MODE_FAST; 251 252 /* disable response to general call */ 253 val |= SPACEMIT_CR_GCD; 254 255 /* enable SCL clock output */ 256 val |= SPACEMIT_CR_SCLE; 257 258 /* enable master stop detected */ 259 val |= SPACEMIT_CR_MSDE | SPACEMIT_CR_MSDIE; 260 261 writel(val, i2c->base + SPACEMIT_ICR); 262 263 /* 264 * The glitch fix in the K1 I2C controller introduces a delay 265 * on restart signals, so we disable the fix here. 266 */ 267 val = readl(i2c->base + SPACEMIT_IRCR); 268 val |= SPACEMIT_RCR_SDA_GLITCH_NOFIX; 269 writel(val, i2c->base + SPACEMIT_IRCR); 270 } 271 272 static inline void 273 spacemit_i2c_clear_int_status(struct spacemit_i2c_dev *i2c, u32 mask) 274 { 275 writel(mask & SPACEMIT_I2C_INT_STATUS_MASK, i2c->base + SPACEMIT_ISR); 276 } 277 278 static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c) 279 { 280 u32 target_addr_rw, val; 281 struct i2c_msg *cur_msg = i2c->msgs + i2c->msg_idx; 282 283 i2c->read = !!(cur_msg->flags & I2C_M_RD); 284 285 i2c->state = SPACEMIT_STATE_START; 286 287 target_addr_rw = (cur_msg->addr & 0x7f) << 1; 288 if (cur_msg->flags & I2C_M_RD) 289 target_addr_rw |= 1; 290 291 writel(target_addr_rw, i2c->base + SPACEMIT_IDBR); 292 293 /* send start pulse */ 294 val = readl(i2c->base + SPACEMIT_ICR); 295 val &= ~SPACEMIT_CR_STOP; 296 val |= SPACEMIT_CR_START | SPACEMIT_CR_TB | SPACEMIT_CR_DTEIE; 297 writel(val, i2c->base + SPACEMIT_ICR); 298 } 299 300 static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) 301 { 302 unsigned long time_left; 303 struct i2c_msg *msg; 304 305 for (i2c->msg_idx = 0; i2c->msg_idx < i2c->msg_num; i2c->msg_idx++) { 306 msg = &i2c->msgs[i2c->msg_idx]; 307 i2c->msg_buf = msg->buf; 308 i2c->unprocessed = msg->len; 309 i2c->status = 0; 310 311 reinit_completion(&i2c->complete); 312 313 spacemit_i2c_start(i2c); 314 315 time_left = wait_for_completion_timeout(&i2c->complete, 316 i2c->adapt.timeout); 317 if (!time_left) { 318 dev_err(i2c->dev, "msg completion timeout\n"); 319 spacemit_i2c_conditionally_reset_bus(i2c); 320 spacemit_i2c_reset(i2c); 321 return -ETIMEDOUT; 322 } 323 324 if (i2c->status & SPACEMIT_SR_ERR) 325 return spacemit_i2c_handle_err(i2c); 326 } 327 328 return 0; 329 } 330 331 static bool spacemit_i2c_is_last_msg(struct spacemit_i2c_dev *i2c) 332 { 333 if (i2c->msg_idx != i2c->msg_num - 1) 334 return false; 335 336 if (i2c->read) 337 return i2c->unprocessed == 1; 338 339 return !i2c->unprocessed; 340 } 341 342 static void spacemit_i2c_handle_write(struct spacemit_i2c_dev *i2c) 343 { 344 /* if transfer completes, SPACEMIT_ISR will handle it */ 345 if (i2c->status & SPACEMIT_SR_MSD) 346 return; 347 348 if (i2c->unprocessed) { 349 writel(*i2c->msg_buf++, i2c->base + SPACEMIT_IDBR); 350 i2c->unprocessed--; 351 return; 352 } 353 354 /* SPACEMIT_STATE_IDLE avoids trigger next byte */ 355 i2c->state = SPACEMIT_STATE_IDLE; 356 complete(&i2c->complete); 357 } 358 359 static void spacemit_i2c_handle_read(struct spacemit_i2c_dev *i2c) 360 { 361 if (i2c->unprocessed) { 362 *i2c->msg_buf++ = readl(i2c->base + SPACEMIT_IDBR); 363 i2c->unprocessed--; 364 } 365 366 /* if transfer completes, SPACEMIT_ISR will handle it */ 367 if (i2c->status & (SPACEMIT_SR_MSD | SPACEMIT_SR_ACKNAK)) 368 return; 369 370 /* it has to append stop bit in icr that read last byte */ 371 if (i2c->unprocessed) 372 return; 373 374 /* SPACEMIT_STATE_IDLE avoids trigger next byte */ 375 i2c->state = SPACEMIT_STATE_IDLE; 376 complete(&i2c->complete); 377 } 378 379 static void spacemit_i2c_handle_start(struct spacemit_i2c_dev *i2c) 380 { 381 i2c->state = i2c->read ? SPACEMIT_STATE_READ : SPACEMIT_STATE_WRITE; 382 if (i2c->state == SPACEMIT_STATE_WRITE) 383 spacemit_i2c_handle_write(i2c); 384 } 385 386 static void spacemit_i2c_err_check(struct spacemit_i2c_dev *i2c) 387 { 388 u32 val; 389 390 /* 391 * Send transaction complete signal: 392 * error happens, detect master stop 393 */ 394 if (!(i2c->status & (SPACEMIT_SR_ERR | SPACEMIT_SR_MSD))) 395 return; 396 397 /* 398 * Here the transaction is already done, we don't need any 399 * other interrupt signals from now, in case any interrupt 400 * happens before spacemit_i2c_xfer to disable irq and i2c unit, 401 * we mask all the interrupt signals and clear the interrupt 402 * status. 403 */ 404 val = readl(i2c->base + SPACEMIT_ICR); 405 val &= ~SPACEMIT_I2C_INT_CTRL_MASK; 406 writel(val, i2c->base + SPACEMIT_ICR); 407 408 spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK); 409 410 i2c->state = SPACEMIT_STATE_IDLE; 411 complete(&i2c->complete); 412 } 413 414 static irqreturn_t spacemit_i2c_irq_handler(int irq, void *devid) 415 { 416 struct spacemit_i2c_dev *i2c = devid; 417 u32 status, val; 418 419 status = readl(i2c->base + SPACEMIT_ISR); 420 if (!status) 421 return IRQ_HANDLED; 422 423 i2c->status = status; 424 425 spacemit_i2c_clear_int_status(i2c, status); 426 427 if (i2c->status & SPACEMIT_SR_ERR) 428 goto err_out; 429 430 val = readl(i2c->base + SPACEMIT_ICR); 431 val &= ~(SPACEMIT_CR_TB | SPACEMIT_CR_ACKNAK | SPACEMIT_CR_STOP | SPACEMIT_CR_START); 432 433 switch (i2c->state) { 434 case SPACEMIT_STATE_START: 435 spacemit_i2c_handle_start(i2c); 436 break; 437 case SPACEMIT_STATE_READ: 438 spacemit_i2c_handle_read(i2c); 439 break; 440 case SPACEMIT_STATE_WRITE: 441 spacemit_i2c_handle_write(i2c); 442 break; 443 default: 444 break; 445 } 446 447 if (i2c->state != SPACEMIT_STATE_IDLE) { 448 val |= SPACEMIT_CR_TB | SPACEMIT_CR_ALDIE; 449 450 if (spacemit_i2c_is_last_msg(i2c)) { 451 /* trigger next byte with stop */ 452 val |= SPACEMIT_CR_STOP; 453 454 if (i2c->read) 455 val |= SPACEMIT_CR_ACKNAK; 456 } 457 writel(val, i2c->base + SPACEMIT_ICR); 458 } 459 460 err_out: 461 spacemit_i2c_err_check(i2c); 462 return IRQ_HANDLED; 463 } 464 465 static void spacemit_i2c_calc_timeout(struct spacemit_i2c_dev *i2c) 466 { 467 unsigned long timeout; 468 int idx = 0, cnt = 0; 469 470 for (; idx < i2c->msg_num; idx++) 471 cnt += (i2c->msgs + idx)->len + 1; 472 473 /* 474 * Multiply by 9 because each byte in I2C transmission requires 475 * 9 clock cycles: 8 bits of data plus 1 ACK/NACK bit. 476 */ 477 timeout = cnt * 9 * USEC_PER_SEC / i2c->clock_freq; 478 479 i2c->adapt.timeout = usecs_to_jiffies(timeout + USEC_PER_SEC / 10) / i2c->msg_num; 480 } 481 482 static int spacemit_i2c_xfer(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num) 483 { 484 struct spacemit_i2c_dev *i2c = i2c_get_adapdata(adapt); 485 int ret; 486 487 i2c->msgs = msgs; 488 i2c->msg_num = num; 489 490 spacemit_i2c_calc_timeout(i2c); 491 492 spacemit_i2c_init(i2c); 493 494 spacemit_i2c_enable(i2c); 495 496 ret = spacemit_i2c_wait_bus_idle(i2c); 497 if (!ret) { 498 ret = spacemit_i2c_xfer_msg(i2c); 499 if (ret < 0) 500 dev_dbg(i2c->dev, "i2c transfer error: %d\n", ret); 501 } else { 502 spacemit_i2c_check_bus_release(i2c); 503 } 504 505 spacemit_i2c_disable(i2c); 506 507 if (ret == -ETIMEDOUT || ret == -EAGAIN) 508 dev_err(i2c->dev, "i2c transfer failed, ret %d err 0x%lx\n", 509 ret, i2c->status & SPACEMIT_SR_ERR); 510 511 return ret < 0 ? ret : num; 512 } 513 514 static u32 spacemit_i2c_func(struct i2c_adapter *adap) 515 { 516 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 517 } 518 519 static const struct i2c_algorithm spacemit_i2c_algo = { 520 .xfer = spacemit_i2c_xfer, 521 .functionality = spacemit_i2c_func, 522 }; 523 524 static int spacemit_i2c_probe(struct platform_device *pdev) 525 { 526 struct clk *clk; 527 struct device *dev = &pdev->dev; 528 struct device_node *of_node = pdev->dev.of_node; 529 struct spacemit_i2c_dev *i2c; 530 int ret; 531 532 i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL); 533 if (!i2c) 534 return -ENOMEM; 535 536 ret = of_property_read_u32(of_node, "clock-frequency", &i2c->clock_freq); 537 if (ret && ret != -EINVAL) 538 dev_warn(dev, "failed to read clock-frequency property: %d\n", ret); 539 540 /* For now, this driver doesn't support high-speed. */ 541 if (!i2c->clock_freq || i2c->clock_freq > SPACEMIT_I2C_MAX_FAST_MODE_FREQ) { 542 dev_warn(dev, "unsupported clock frequency %u; using %u\n", 543 i2c->clock_freq, SPACEMIT_I2C_MAX_FAST_MODE_FREQ); 544 i2c->clock_freq = SPACEMIT_I2C_MAX_FAST_MODE_FREQ; 545 } else if (i2c->clock_freq < SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) { 546 dev_warn(dev, "unsupported clock frequency %u; using %u\n", 547 i2c->clock_freq, SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ); 548 i2c->clock_freq = SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ; 549 } 550 551 i2c->dev = &pdev->dev; 552 553 i2c->base = devm_platform_ioremap_resource(pdev, 0); 554 if (IS_ERR(i2c->base)) 555 return dev_err_probe(dev, PTR_ERR(i2c->base), "failed to do ioremap"); 556 557 i2c->irq = platform_get_irq(pdev, 0); 558 if (i2c->irq < 0) 559 return dev_err_probe(dev, i2c->irq, "failed to get irq resource"); 560 561 ret = devm_request_irq(i2c->dev, i2c->irq, spacemit_i2c_irq_handler, 562 IRQF_NO_SUSPEND | IRQF_ONESHOT, dev_name(i2c->dev), i2c); 563 if (ret) 564 return dev_err_probe(dev, ret, "failed to request irq"); 565 566 clk = devm_clk_get_enabled(dev, "func"); 567 if (IS_ERR(clk)) 568 return dev_err_probe(dev, PTR_ERR(clk), "failed to enable func clock"); 569 570 clk = devm_clk_get_enabled(dev, "bus"); 571 if (IS_ERR(clk)) 572 return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock"); 573 574 spacemit_i2c_reset(i2c); 575 576 i2c_set_adapdata(&i2c->adapt, i2c); 577 i2c->adapt.owner = THIS_MODULE; 578 i2c->adapt.algo = &spacemit_i2c_algo; 579 i2c->adapt.dev.parent = i2c->dev; 580 i2c->adapt.nr = pdev->id; 581 582 i2c->adapt.dev.of_node = of_node; 583 584 strscpy(i2c->adapt.name, "spacemit-i2c-adapter", sizeof(i2c->adapt.name)); 585 586 init_completion(&i2c->complete); 587 588 platform_set_drvdata(pdev, i2c); 589 590 ret = i2c_add_numbered_adapter(&i2c->adapt); 591 if (ret) 592 return dev_err_probe(&pdev->dev, ret, "failed to add i2c adapter"); 593 594 return 0; 595 } 596 597 static void spacemit_i2c_remove(struct platform_device *pdev) 598 { 599 struct spacemit_i2c_dev *i2c = platform_get_drvdata(pdev); 600 601 i2c_del_adapter(&i2c->adapt); 602 } 603 604 static const struct of_device_id spacemit_i2c_of_match[] = { 605 { .compatible = "spacemit,k1-i2c", }, 606 { /* sentinel */ } 607 }; 608 MODULE_DEVICE_TABLE(of, spacemit_i2c_of_match); 609 610 static struct platform_driver spacemit_i2c_driver = { 611 .probe = spacemit_i2c_probe, 612 .remove = spacemit_i2c_remove, 613 .driver = { 614 .name = "i2c-k1", 615 .of_match_table = spacemit_i2c_of_match, 616 }, 617 }; 618 module_platform_driver(spacemit_i2c_driver); 619 620 MODULE_LICENSE("GPL"); 621 MODULE_DESCRIPTION("I2C bus driver for SpacemiT K1 SoC"); 622