1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Linux kernel driver for Intel SCH chipset SMBus 4 * - Based on i2c-piix4.c 5 * Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and 6 * Philip Edelbrock <phil@netroedge.com> 7 * - Intel SCH support 8 * Copyright (c) 2007 - 2008 Jacob Jun Pan <jacob.jun.pan@intel.com> 9 */ 10 11 /* Supports: Intel SCH chipsets (AF82US15W, AF82US15L, AF82UL11L) */ 12 13 #include <linux/container_of.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/errno.h> 17 #include <linux/gfp_types.h> 18 #include <linux/i2c.h> 19 #include <linux/iopoll.h> 20 #include <linux/ioport.h> 21 #include <linux/module.h> 22 #include <linux/platform_device.h> 23 #include <linux/sprintf.h> 24 #include <linux/stddef.h> 25 #include <linux/string_choices.h> 26 #include <linux/types.h> 27 28 /* SCH SMBus address offsets */ 29 #define SMBHSTCNT 0x00 30 #define SMBHSTSTS 0x01 31 #define SMBHSTCLK 0x02 32 #define SMBHSTADD 0x04 /* TSA */ 33 #define SMBHSTCMD 0x05 34 #define SMBHSTDAT0 0x06 35 #define SMBHSTDAT1 0x07 36 #define SMBBLKDAT 0x20 37 38 /* I2C constants */ 39 #define SCH_QUICK 0x00 40 #define SCH_BYTE 0x01 41 #define SCH_BYTE_DATA 0x02 42 #define SCH_WORD_DATA 0x03 43 #define SCH_BLOCK_DATA 0x05 44 45 struct sch_i2c { 46 struct i2c_adapter adapter; 47 void __iomem *smba; 48 }; 49 50 static int backbone_speed = 33000; /* backbone speed in kHz */ 51 module_param(backbone_speed, int, 0600); 52 MODULE_PARM_DESC(backbone_speed, "Backbone speed in kHz, (default = 33000)"); 53 54 static inline u8 sch_io_rd8(struct sch_i2c *priv, unsigned int offset) 55 { 56 return ioread8(priv->smba + offset); 57 } 58 59 static inline void sch_io_wr8(struct sch_i2c *priv, unsigned int offset, u8 value) 60 { 61 iowrite8(value, priv->smba + offset); 62 } 63 64 static inline u16 sch_io_rd16(struct sch_i2c *priv, unsigned int offset) 65 { 66 return ioread16(priv->smba + offset); 67 } 68 69 static inline void sch_io_wr16(struct sch_i2c *priv, unsigned int offset, u16 value) 70 { 71 iowrite16(value, priv->smba + offset); 72 } 73 74 /** 75 * sch_transaction - Start the i2c transaction 76 * @adap: the i2c adapter pointer 77 * 78 * The sch_access() will prepare the transaction and 79 * this function will execute it. 80 * 81 * Return: 0 for success and others for failure. 82 */ 83 static int sch_transaction(struct i2c_adapter *adap) 84 { 85 struct sch_i2c *priv = container_of(adap, struct sch_i2c, adapter); 86 int temp; 87 int rc; 88 89 dev_dbg(&adap->dev, 90 "Transaction (pre): CNT=%02x, CMD=%02x, ADD=%02x, DAT0=%02x, DAT1=%02x\n", 91 sch_io_rd8(priv, SMBHSTCNT), sch_io_rd8(priv, SMBHSTCMD), 92 sch_io_rd8(priv, SMBHSTADD), 93 sch_io_rd8(priv, SMBHSTDAT0), sch_io_rd8(priv, SMBHSTDAT1)); 94 95 /* Make sure the SMBus host is ready to start transmitting */ 96 temp = sch_io_rd8(priv, SMBHSTSTS) & 0x0f; 97 if (temp) { 98 /* Can not be busy since we checked it in sch_access */ 99 if (temp & 0x01) 100 dev_dbg(&adap->dev, "Completion (%02x). Clear...\n", temp); 101 if (temp & 0x06) 102 dev_dbg(&adap->dev, "SMBus error (%02x). Resetting...\n", temp); 103 sch_io_wr8(priv, SMBHSTSTS, temp); 104 temp = sch_io_rd8(priv, SMBHSTSTS) & 0x0f; 105 if (temp) { 106 dev_err(&adap->dev, "SMBus is not ready: (%02x)\n", temp); 107 return -EAGAIN; 108 } 109 } 110 111 /* Start the transaction by setting bit 4 */ 112 temp = sch_io_rd8(priv, SMBHSTCNT); 113 temp |= 0x10; 114 sch_io_wr8(priv, SMBHSTCNT, temp); 115 116 rc = read_poll_timeout(sch_io_rd8, temp, !(temp & 0x08), 200, 500000, true, priv, SMBHSTSTS); 117 /* If the SMBus is still busy, we give up */ 118 if (rc) { 119 dev_err(&adap->dev, "SMBus Timeout!\n"); 120 } else if (temp & 0x04) { 121 rc = -EIO; 122 dev_dbg(&adap->dev, "Bus collision! SMBus may be locked until next hard reset. (sorry!)\n"); 123 /* Clock stops and target is stuck in mid-transmission */ 124 } else if (temp & 0x02) { 125 rc = -EIO; 126 dev_err(&adap->dev, "Error: no response!\n"); 127 } else if (temp & 0x01) { 128 dev_dbg(&adap->dev, "Post complete!\n"); 129 sch_io_wr8(priv, SMBHSTSTS, temp & 0x0f); 130 temp = sch_io_rd8(priv, SMBHSTSTS) & 0x07; 131 if (temp & 0x06) { 132 /* Completion clear failed */ 133 dev_dbg(&adap->dev, 134 "Failed reset at end of transaction (%02x), Bus error!\n", temp); 135 } 136 } else { 137 rc = -ENXIO; 138 dev_dbg(&adap->dev, "No such address.\n"); 139 } 140 dev_dbg(&adap->dev, "Transaction (post): CNT=%02x, CMD=%02x, ADD=%02x, DAT0=%02x, DAT1=%02x\n", 141 sch_io_rd8(priv, SMBHSTCNT), sch_io_rd8(priv, SMBHSTCMD), 142 sch_io_rd8(priv, SMBHSTADD), 143 sch_io_rd8(priv, SMBHSTDAT0), sch_io_rd8(priv, SMBHSTDAT1)); 144 return rc; 145 } 146 147 /** 148 * sch_access - the main access entry for i2c-sch access 149 * @adap: the i2c adapter pointer 150 * @addr: the i2c device bus address 151 * @flags: I2C_CLIENT_* flags (usually zero or I2C_CLIENT_PEC) 152 * @read_write: 0 for read and 1 for write 153 * @command: Byte interpreted by slave, for protocols which use such bytes 154 * @size: the i2c transaction type 155 * @data: the union of transaction for data to be transferred or data read from bus 156 * 157 * Return: 0 for success and others for failure. 158 */ 159 static s32 sch_access(struct i2c_adapter *adap, u16 addr, 160 unsigned short flags, char read_write, 161 u8 command, int size, union i2c_smbus_data *data) 162 { 163 struct sch_i2c *priv = container_of(adap, struct sch_i2c, adapter); 164 int i, len, temp, rc; 165 166 /* Make sure the SMBus host is not busy */ 167 temp = sch_io_rd8(priv, SMBHSTSTS) & 0x0f; 168 if (temp & 0x08) { 169 dev_dbg(&adap->dev, "SMBus busy (%02x)\n", temp); 170 return -EAGAIN; 171 } 172 temp = sch_io_rd16(priv, SMBHSTCLK); 173 if (!temp) { 174 /* 175 * We can't determine if we have 33 or 25 MHz clock for 176 * SMBus, so expect 33 MHz and calculate a bus clock of 177 * 100 kHz. If we actually run at 25 MHz the bus will be 178 * run ~75 kHz instead which should do no harm. 179 */ 180 dev_notice(&adap->dev, "Clock divider uninitialized. Setting defaults\n"); 181 sch_io_wr16(priv, SMBHSTCLK, backbone_speed / (4 * 100)); 182 } 183 184 dev_dbg(&adap->dev, "access size: %d %s\n", size, str_read_write(read_write)); 185 switch (size) { 186 case I2C_SMBUS_QUICK: 187 sch_io_wr8(priv, SMBHSTADD, (addr << 1) | read_write); 188 size = SCH_QUICK; 189 break; 190 case I2C_SMBUS_BYTE: 191 sch_io_wr8(priv, SMBHSTADD, (addr << 1) | read_write); 192 if (read_write == I2C_SMBUS_WRITE) 193 sch_io_wr8(priv, SMBHSTCMD, command); 194 size = SCH_BYTE; 195 break; 196 case I2C_SMBUS_BYTE_DATA: 197 sch_io_wr8(priv, SMBHSTADD, (addr << 1) | read_write); 198 sch_io_wr8(priv, SMBHSTCMD, command); 199 if (read_write == I2C_SMBUS_WRITE) 200 sch_io_wr8(priv, SMBHSTDAT0, data->byte); 201 size = SCH_BYTE_DATA; 202 break; 203 case I2C_SMBUS_WORD_DATA: 204 sch_io_wr8(priv, SMBHSTADD, (addr << 1) | read_write); 205 sch_io_wr8(priv, SMBHSTCMD, command); 206 if (read_write == I2C_SMBUS_WRITE) { 207 sch_io_wr8(priv, SMBHSTDAT0, data->word >> 0); 208 sch_io_wr8(priv, SMBHSTDAT1, data->word >> 8); 209 } 210 size = SCH_WORD_DATA; 211 break; 212 case I2C_SMBUS_BLOCK_DATA: 213 sch_io_wr8(priv, SMBHSTADD, (addr << 1) | read_write); 214 sch_io_wr8(priv, SMBHSTCMD, command); 215 if (read_write == I2C_SMBUS_WRITE) { 216 len = data->block[0]; 217 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) 218 return -EINVAL; 219 sch_io_wr8(priv, SMBHSTDAT0, len); 220 for (i = 1; i <= len; i++) 221 sch_io_wr8(priv, SMBBLKDAT + i - 1, data->block[i]); 222 } 223 size = SCH_BLOCK_DATA; 224 break; 225 default: 226 dev_warn(&adap->dev, "Unsupported transaction %d\n", size); 227 return -EOPNOTSUPP; 228 } 229 dev_dbg(&adap->dev, "write size %d to 0x%04x\n", size, SMBHSTCNT); 230 231 temp = sch_io_rd8(priv, SMBHSTCNT); 232 temp = (temp & 0xb0) | (size & 0x7); 233 sch_io_wr8(priv, SMBHSTCNT, temp); 234 235 rc = sch_transaction(adap); 236 if (rc) /* Error in transaction */ 237 return rc; 238 239 if ((read_write == I2C_SMBUS_WRITE) || (size == SCH_QUICK)) 240 return 0; 241 242 switch (size) { 243 case SCH_BYTE: 244 case SCH_BYTE_DATA: 245 data->byte = sch_io_rd8(priv, SMBHSTDAT0); 246 break; 247 case SCH_WORD_DATA: 248 data->word = (sch_io_rd8(priv, SMBHSTDAT0) << 0) + 249 (sch_io_rd8(priv, SMBHSTDAT1) << 8); 250 break; 251 case SCH_BLOCK_DATA: 252 data->block[0] = sch_io_rd8(priv, SMBHSTDAT0); 253 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 254 return -EPROTO; 255 for (i = 1; i <= data->block[0]; i++) 256 data->block[i] = sch_io_rd8(priv, SMBBLKDAT + i - 1); 257 break; 258 } 259 return 0; 260 } 261 262 static u32 sch_func(struct i2c_adapter *adapter) 263 { 264 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 265 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 266 I2C_FUNC_SMBUS_BLOCK_DATA; 267 } 268 269 static const struct i2c_algorithm smbus_algorithm = { 270 .smbus_xfer = sch_access, 271 .functionality = sch_func, 272 }; 273 274 static int smbus_sch_probe(struct platform_device *pdev) 275 { 276 struct device *dev = &pdev->dev; 277 struct sch_i2c *priv; 278 struct resource *res; 279 280 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 281 if (!priv) 282 return -ENOMEM; 283 284 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 285 if (!res) 286 return -EBUSY; 287 288 priv->smba = devm_ioport_map(dev, res->start, resource_size(res)); 289 if (!priv->smba) 290 return dev_err_probe(dev, -EBUSY, "SMBus region %pR already in use!\n", res); 291 292 /* Set up the sysfs linkage to our parent device */ 293 priv->adapter.dev.parent = dev; 294 priv->adapter.owner = THIS_MODULE, 295 priv->adapter.class = I2C_CLASS_HWMON, 296 priv->adapter.algo = &smbus_algorithm, 297 298 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 299 "SMBus SCH adapter at %04x", (unsigned short)res->start); 300 301 return devm_i2c_add_adapter(dev, &priv->adapter); 302 } 303 304 static struct platform_driver smbus_sch_driver = { 305 .driver = { 306 .name = "isch_smbus", 307 }, 308 .probe = smbus_sch_probe, 309 }; 310 311 module_platform_driver(smbus_sch_driver); 312 313 MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>"); 314 MODULE_DESCRIPTION("Intel SCH SMBus driver"); 315 MODULE_LICENSE("GPL"); 316 MODULE_ALIAS("platform:isch_smbus"); 317