1 // SPDX-License-Identifier: GPL-2.0-only 2 /* ------------------------------------------------------------------------- */ 3 /* i2c-iop3xx.c i2c driver algorithms for Intel XScale IOP3xx & IXP46x */ 4 /* ------------------------------------------------------------------------- */ 5 /* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd 6 * <Peter dot Milne at D hyphen TACQ dot com> 7 * 8 * With acknowledgements to i2c-algo-ibm_ocp.c by 9 * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com 10 * 11 * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund: 12 * 13 * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund 14 * 15 * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>, 16 * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com> 17 * 18 * Major cleanup by Deepak Saxena <dsaxena@plexity.net>, 01/2005: 19 * 20 * - Use driver model to pass per-chip info instead of hardcoding and #ifdefs 21 * - Use ioremap/__raw_readl/__raw_writel instead of direct dereference 22 * - Make it work with IXP46x chips 23 * - Cleanup function names, coding style, etc 24 * 25 * - writing to slave address causes latchup on iop331. 26 * fix: driver refuses to address self. 27 */ 28 29 #include <linux/interrupt.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/delay.h> 33 #include <linux/slab.h> 34 #include <linux/errno.h> 35 #include <linux/platform_device.h> 36 #include <linux/i2c.h> 37 #include <linux/io.h> 38 #include <linux/gpio.h> 39 40 #include "i2c-iop3xx.h" 41 42 /* global unit counter */ 43 static int i2c_id; 44 45 static inline unsigned char 46 iic_cook_addr(struct i2c_msg *msg) 47 { 48 unsigned char addr; 49 50 addr = i2c_8bit_addr_from_msg(msg); 51 52 return addr; 53 } 54 55 static void 56 iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap) 57 { 58 /* Follows devman 9.3 */ 59 __raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET); 60 __raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET); 61 __raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET); 62 } 63 64 static void 65 iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap) 66 { 67 u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE; 68 69 /* 70 * Every time unit enable is asserted, GPOD needs to be cleared 71 * on IOP3XX to avoid data corruption on the bus. 72 */ 73 #if defined(CONFIG_ARCH_IOP32X) || defined(CONFIG_ARCH_IOP33X) 74 if (iop3xx_adap->id == 0) { 75 gpio_set_value(7, 0); 76 gpio_set_value(6, 0); 77 } else { 78 gpio_set_value(5, 0); 79 gpio_set_value(4, 0); 80 } 81 #endif 82 /* NB SR bits not same position as CR IE bits :-( */ 83 iop3xx_adap->SR_enabled = 84 IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD | 85 IOP3XX_ISR_RXFULL | IOP3XX_ISR_TXEMPTY; 86 87 cr |= IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE | 88 IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE; 89 90 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); 91 } 92 93 static void 94 iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap) 95 { 96 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); 97 98 cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE | 99 IOP3XX_ICR_MSTOP | IOP3XX_ICR_SCLEN); 100 101 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); 102 } 103 104 /* 105 * NB: the handler has to clear the source of the interrupt! 106 * Then it passes the SR flags of interest to BH via adap data 107 */ 108 static irqreturn_t 109 iop3xx_i2c_irq_handler(int this_irq, void *dev_id) 110 { 111 struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id; 112 u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET); 113 114 if ((sr &= iop3xx_adap->SR_enabled)) { 115 __raw_writel(sr, iop3xx_adap->ioaddr + SR_OFFSET); 116 iop3xx_adap->SR_received |= sr; 117 wake_up_interruptible(&iop3xx_adap->waitq); 118 } 119 return IRQ_HANDLED; 120 } 121 122 /* check all error conditions, clear them , report most important */ 123 static int 124 iop3xx_i2c_error(u32 sr) 125 { 126 int rc = 0; 127 128 if ((sr & IOP3XX_ISR_BERRD)) { 129 if ( !rc ) rc = -I2C_ERR_BERR; 130 } 131 if ((sr & IOP3XX_ISR_ALD)) { 132 if ( !rc ) rc = -I2C_ERR_ALD; 133 } 134 return rc; 135 } 136 137 static inline u32 138 iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap) 139 { 140 unsigned long flags; 141 u32 sr; 142 143 spin_lock_irqsave(&iop3xx_adap->lock, flags); 144 sr = iop3xx_adap->SR_received; 145 iop3xx_adap->SR_received = 0; 146 spin_unlock_irqrestore(&iop3xx_adap->lock, flags); 147 148 return sr; 149 } 150 151 /* 152 * sleep until interrupted, then recover and analyse the SR 153 * saved by handler 154 */ 155 typedef int (* compare_func)(unsigned test, unsigned mask); 156 /* returns 1 on correct comparison */ 157 158 static int 159 iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap, 160 unsigned flags, unsigned* status, 161 compare_func compare) 162 { 163 unsigned sr = 0; 164 int interrupted; 165 int done; 166 int rc = 0; 167 168 do { 169 interrupted = wait_event_interruptible_timeout ( 170 iop3xx_adap->waitq, 171 (done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap) ,flags )), 172 1 * HZ 173 ); 174 if ((rc = iop3xx_i2c_error(sr)) < 0) { 175 *status = sr; 176 return rc; 177 } else if (!interrupted) { 178 *status = sr; 179 return -ETIMEDOUT; 180 } 181 } while(!done); 182 183 *status = sr; 184 185 return 0; 186 } 187 188 /* 189 * Concrete compare_funcs 190 */ 191 static int 192 all_bits_clear(unsigned test, unsigned mask) 193 { 194 return (test & mask) == 0; 195 } 196 197 static int 198 any_bits_set(unsigned test, unsigned mask) 199 { 200 return (test & mask) != 0; 201 } 202 203 static int 204 iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status) 205 { 206 return iop3xx_i2c_wait_event( 207 iop3xx_adap, 208 IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD, 209 status, any_bits_set); 210 } 211 212 static int 213 iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status) 214 { 215 return iop3xx_i2c_wait_event( 216 iop3xx_adap, 217 IOP3XX_ISR_RXFULL | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD, 218 status, any_bits_set); 219 } 220 221 static int 222 iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status) 223 { 224 return iop3xx_i2c_wait_event( 225 iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear); 226 } 227 228 static int 229 iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap, 230 struct i2c_msg* msg) 231 { 232 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); 233 int status; 234 int rc; 235 236 /* avoid writing to my slave address (hangs on 80331), 237 * forbidden in Intel developer manual 238 */ 239 if (msg->addr == MYSAR) { 240 return -EBUSY; 241 } 242 243 __raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET); 244 245 cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK); 246 cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE; 247 248 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); 249 rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status); 250 251 return rc; 252 } 253 254 static int 255 iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte, 256 int stop) 257 { 258 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); 259 int status; 260 int rc = 0; 261 262 __raw_writel(byte, iop3xx_adap->ioaddr + DBR_OFFSET); 263 cr &= ~IOP3XX_ICR_MSTART; 264 if (stop) { 265 cr |= IOP3XX_ICR_MSTOP; 266 } else { 267 cr &= ~IOP3XX_ICR_MSTOP; 268 } 269 cr |= IOP3XX_ICR_TBYTE; 270 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); 271 rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status); 272 273 return rc; 274 } 275 276 static int 277 iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte, 278 int stop) 279 { 280 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); 281 int status; 282 int rc = 0; 283 284 cr &= ~IOP3XX_ICR_MSTART; 285 286 if (stop) { 287 cr |= IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK; 288 } else { 289 cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK); 290 } 291 cr |= IOP3XX_ICR_TBYTE; 292 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); 293 294 rc = iop3xx_i2c_wait_rx_done(iop3xx_adap, &status); 295 296 *byte = __raw_readl(iop3xx_adap->ioaddr + DBR_OFFSET); 297 298 return rc; 299 } 300 301 static int 302 iop3xx_i2c_writebytes(struct i2c_adapter *i2c_adap, const char *buf, int count) 303 { 304 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data; 305 int ii; 306 int rc = 0; 307 308 for (ii = 0; rc == 0 && ii != count; ++ii) 309 rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1); 310 return rc; 311 } 312 313 static int 314 iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count) 315 { 316 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data; 317 int ii; 318 int rc = 0; 319 320 for (ii = 0; rc == 0 && ii != count; ++ii) 321 rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1); 322 323 return rc; 324 } 325 326 /* 327 * Description: This function implements combined transactions. Combined 328 * transactions consist of combinations of reading and writing blocks of data. 329 * FROM THE SAME ADDRESS 330 * Each transfer (i.e. a read or a write) is separated by a repeated start 331 * condition. 332 */ 333 static int 334 iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg) 335 { 336 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data; 337 int rc; 338 339 rc = iop3xx_i2c_send_target_addr(iop3xx_adap, pmsg); 340 if (rc < 0) { 341 return rc; 342 } 343 344 if ((pmsg->flags&I2C_M_RD)) { 345 return iop3xx_i2c_readbytes(i2c_adap, pmsg->buf, pmsg->len); 346 } else { 347 return iop3xx_i2c_writebytes(i2c_adap, pmsg->buf, pmsg->len); 348 } 349 } 350 351 /* 352 * master_xfer() - main read/write entry 353 */ 354 static int 355 iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, 356 int num) 357 { 358 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data; 359 int im = 0; 360 int ret = 0; 361 int status; 362 363 iop3xx_i2c_wait_idle(iop3xx_adap, &status); 364 iop3xx_i2c_reset(iop3xx_adap); 365 iop3xx_i2c_enable(iop3xx_adap); 366 367 for (im = 0; ret == 0 && im != num; im++) { 368 ret = iop3xx_i2c_handle_msg(i2c_adap, &msgs[im]); 369 } 370 371 iop3xx_i2c_transaction_cleanup(iop3xx_adap); 372 373 if(ret) 374 return ret; 375 376 return im; 377 } 378 379 static u32 380 iop3xx_i2c_func(struct i2c_adapter *adap) 381 { 382 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 383 } 384 385 static const struct i2c_algorithm iop3xx_i2c_algo = { 386 .master_xfer = iop3xx_i2c_master_xfer, 387 .functionality = iop3xx_i2c_func, 388 }; 389 390 static int 391 iop3xx_i2c_remove(struct platform_device *pdev) 392 { 393 struct i2c_adapter *padapter = platform_get_drvdata(pdev); 394 struct i2c_algo_iop3xx_data *adapter_data = 395 (struct i2c_algo_iop3xx_data *)padapter->algo_data; 396 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 397 unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET); 398 399 /* 400 * Disable the actual HW unit 401 */ 402 cr &= ~(IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE | 403 IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE); 404 __raw_writel(cr, adapter_data->ioaddr + CR_OFFSET); 405 406 iounmap(adapter_data->ioaddr); 407 release_mem_region(res->start, IOP3XX_I2C_IO_SIZE); 408 kfree(adapter_data); 409 kfree(padapter); 410 411 return 0; 412 } 413 414 static int 415 iop3xx_i2c_probe(struct platform_device *pdev) 416 { 417 struct resource *res; 418 int ret, irq; 419 struct i2c_adapter *new_adapter; 420 struct i2c_algo_iop3xx_data *adapter_data; 421 422 new_adapter = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL); 423 if (!new_adapter) { 424 ret = -ENOMEM; 425 goto out; 426 } 427 428 adapter_data = kzalloc(sizeof(struct i2c_algo_iop3xx_data), GFP_KERNEL); 429 if (!adapter_data) { 430 ret = -ENOMEM; 431 goto free_adapter; 432 } 433 434 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 435 if (!res) { 436 ret = -ENODEV; 437 goto free_both; 438 } 439 440 if (!request_mem_region(res->start, IOP3XX_I2C_IO_SIZE, pdev->name)) { 441 ret = -EBUSY; 442 goto free_both; 443 } 444 445 /* set the adapter enumeration # */ 446 adapter_data->id = i2c_id++; 447 448 adapter_data->ioaddr = ioremap(res->start, IOP3XX_I2C_IO_SIZE); 449 if (!adapter_data->ioaddr) { 450 ret = -ENOMEM; 451 goto release_region; 452 } 453 454 irq = platform_get_irq(pdev, 0); 455 if (irq < 0) { 456 ret = -ENXIO; 457 goto unmap; 458 } 459 ret = request_irq(irq, iop3xx_i2c_irq_handler, 0, 460 pdev->name, adapter_data); 461 462 if (ret) { 463 ret = -EIO; 464 goto unmap; 465 } 466 467 memcpy(new_adapter->name, pdev->name, strlen(pdev->name)); 468 new_adapter->owner = THIS_MODULE; 469 new_adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 470 new_adapter->dev.parent = &pdev->dev; 471 new_adapter->dev.of_node = pdev->dev.of_node; 472 new_adapter->nr = pdev->id; 473 474 /* 475 * Default values...should these come in from board code? 476 */ 477 new_adapter->timeout = HZ; 478 new_adapter->algo = &iop3xx_i2c_algo; 479 480 init_waitqueue_head(&adapter_data->waitq); 481 spin_lock_init(&adapter_data->lock); 482 483 iop3xx_i2c_reset(adapter_data); 484 iop3xx_i2c_enable(adapter_data); 485 486 platform_set_drvdata(pdev, new_adapter); 487 new_adapter->algo_data = adapter_data; 488 489 i2c_add_numbered_adapter(new_adapter); 490 491 return 0; 492 493 unmap: 494 iounmap(adapter_data->ioaddr); 495 496 release_region: 497 release_mem_region(res->start, IOP3XX_I2C_IO_SIZE); 498 499 free_both: 500 kfree(adapter_data); 501 502 free_adapter: 503 kfree(new_adapter); 504 505 out: 506 return ret; 507 } 508 509 static const struct of_device_id i2c_iop3xx_match[] = { 510 { .compatible = "intel,iop3xx-i2c", }, 511 { .compatible = "intel,ixp4xx-i2c", }, 512 {}, 513 }; 514 MODULE_DEVICE_TABLE(of, i2c_iop3xx_match); 515 516 static struct platform_driver iop3xx_i2c_driver = { 517 .probe = iop3xx_i2c_probe, 518 .remove = iop3xx_i2c_remove, 519 .driver = { 520 .name = "IOP3xx-I2C", 521 .of_match_table = i2c_iop3xx_match, 522 }, 523 }; 524 525 module_platform_driver(iop3xx_i2c_driver); 526 527 MODULE_AUTHOR("D-TACQ Solutions Ltd <www.d-tacq.com>"); 528 MODULE_DESCRIPTION("IOP3xx iic algorithm and driver"); 529 MODULE_LICENSE("GPL"); 530 MODULE_ALIAS("platform:IOP3xx-I2C"); 531