1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2002 Motorola GSG-China 4 * 5 * Author: 6 * Darius Augulis, Teltonika Inc. 7 * 8 * Desc.: 9 * Implementation of I2C Adapter/Algorithm Driver 10 * for I2C Bus integrated in Freescale i.MX/MXC processors 11 * 12 * Derived from Motorola GSG China I2C example driver 13 * 14 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de 15 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de 16 * Copyright (C) 2007 RightHand Technologies, Inc. 17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 18 * 19 * Copyright 2013 Freescale Semiconductor, Inc. 20 * 21 */ 22 23 #include <linux/clk.h> 24 #include <linux/completion.h> 25 #include <linux/delay.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/dmaengine.h> 28 #include <linux/dmapool.h> 29 #include <linux/err.h> 30 #include <linux/errno.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/i2c.h> 33 #include <linux/init.h> 34 #include <linux/interrupt.h> 35 #include <linux/io.h> 36 #include <linux/kernel.h> 37 #include <linux/module.h> 38 #include <linux/of.h> 39 #include <linux/of_device.h> 40 #include <linux/of_dma.h> 41 #include <linux/pinctrl/consumer.h> 42 #include <linux/platform_data/i2c-imx.h> 43 #include <linux/platform_device.h> 44 #include <linux/pm_runtime.h> 45 #include <linux/sched.h> 46 #include <linux/slab.h> 47 48 /* This will be the driver name the kernel reports */ 49 #define DRIVER_NAME "imx-i2c" 50 51 /* Default value */ 52 #define IMX_I2C_BIT_RATE 100000 /* 100kHz */ 53 54 /* 55 * Enable DMA if transfer byte size is bigger than this threshold. 56 * As the hardware request, it must bigger than 4 bytes.\ 57 * I have set '16' here, maybe it's not the best but I think it's 58 * the appropriate. 59 */ 60 #define DMA_THRESHOLD 16 61 #define DMA_TIMEOUT 1000 62 63 /* IMX I2C registers: 64 * the I2C register offset is different between SoCs, 65 * to provid support for all these chips, split the 66 * register offset into a fixed base address and a 67 * variable shift value, then the full register offset 68 * will be calculated by 69 * reg_off = ( reg_base_addr << reg_shift) 70 */ 71 #define IMX_I2C_IADR 0x00 /* i2c slave address */ 72 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ 73 #define IMX_I2C_I2CR 0x02 /* i2c control */ 74 #define IMX_I2C_I2SR 0x03 /* i2c status */ 75 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */ 76 77 #define IMX_I2C_REGSHIFT 2 78 #define VF610_I2C_REGSHIFT 0 79 80 /* Bits of IMX I2C registers */ 81 #define I2SR_RXAK 0x01 82 #define I2SR_IIF 0x02 83 #define I2SR_SRW 0x04 84 #define I2SR_IAL 0x10 85 #define I2SR_IBB 0x20 86 #define I2SR_IAAS 0x40 87 #define I2SR_ICF 0x80 88 #define I2CR_DMAEN 0x02 89 #define I2CR_RSTA 0x04 90 #define I2CR_TXAK 0x08 91 #define I2CR_MTX 0x10 92 #define I2CR_MSTA 0x20 93 #define I2CR_IIEN 0x40 94 #define I2CR_IEN 0x80 95 96 /* register bits different operating codes definition: 97 * 1) I2SR: Interrupt flags clear operation differ between SoCs: 98 * - write zero to clear(w0c) INT flag on i.MX, 99 * - but write one to clear(w1c) INT flag on Vybrid. 100 * 2) I2CR: I2C module enable operation also differ between SoCs: 101 * - set I2CR_IEN bit enable the module on i.MX, 102 * - but clear I2CR_IEN bit enable the module on Vybrid. 103 */ 104 #define I2SR_CLR_OPCODE_W0C 0x0 105 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) 106 #define I2CR_IEN_OPCODE_0 0x0 107 #define I2CR_IEN_OPCODE_1 I2CR_IEN 108 109 #define I2C_PM_TIMEOUT 10 /* ms */ 110 111 /* 112 * sorted list of clock divider, register value pairs 113 * taken from table 26-5, p.26-9, Freescale i.MX 114 * Integrated Portable System Processor Reference Manual 115 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 116 * 117 * Duplicated divider values removed from list 118 */ 119 struct imx_i2c_clk_pair { 120 u16 div; 121 u16 val; 122 }; 123 124 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = { 125 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 126 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 127 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 128 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 129 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 130 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 131 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 132 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 133 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 134 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 135 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 136 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 137 { 3072, 0x1E }, { 3840, 0x1F } 138 }; 139 140 /* Vybrid VF610 clock divider, register value pairs */ 141 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = { 142 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 143 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 144 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 145 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 146 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 147 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 148 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 149 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 150 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 151 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 152 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 153 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 154 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 155 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 156 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 157 }; 158 159 enum imx_i2c_type { 160 IMX1_I2C, 161 IMX21_I2C, 162 VF610_I2C, 163 }; 164 165 struct imx_i2c_hwdata { 166 enum imx_i2c_type devtype; 167 unsigned regshift; 168 struct imx_i2c_clk_pair *clk_div; 169 unsigned ndivs; 170 unsigned i2sr_clr_opcode; 171 unsigned i2cr_ien_opcode; 172 }; 173 174 struct imx_i2c_dma { 175 struct dma_chan *chan_tx; 176 struct dma_chan *chan_rx; 177 struct dma_chan *chan_using; 178 struct completion cmd_complete; 179 dma_addr_t dma_buf; 180 unsigned int dma_len; 181 enum dma_transfer_direction dma_transfer_dir; 182 enum dma_data_direction dma_data_dir; 183 }; 184 185 struct imx_i2c_struct { 186 struct i2c_adapter adapter; 187 struct clk *clk; 188 struct notifier_block clk_change_nb; 189 void __iomem *base; 190 wait_queue_head_t queue; 191 unsigned long i2csr; 192 unsigned int disable_delay; 193 int stopped; 194 unsigned int ifdr; /* IMX_I2C_IFDR */ 195 unsigned int cur_clk; 196 unsigned int bitrate; 197 const struct imx_i2c_hwdata *hwdata; 198 struct i2c_bus_recovery_info rinfo; 199 200 struct pinctrl *pinctrl; 201 struct pinctrl_state *pinctrl_pins_default; 202 struct pinctrl_state *pinctrl_pins_gpio; 203 204 struct imx_i2c_dma *dma; 205 }; 206 207 static const struct imx_i2c_hwdata imx1_i2c_hwdata = { 208 .devtype = IMX1_I2C, 209 .regshift = IMX_I2C_REGSHIFT, 210 .clk_div = imx_i2c_clk_div, 211 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 212 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 213 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 214 215 }; 216 217 static const struct imx_i2c_hwdata imx21_i2c_hwdata = { 218 .devtype = IMX21_I2C, 219 .regshift = IMX_I2C_REGSHIFT, 220 .clk_div = imx_i2c_clk_div, 221 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 222 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 223 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 224 225 }; 226 227 static struct imx_i2c_hwdata vf610_i2c_hwdata = { 228 .devtype = VF610_I2C, 229 .regshift = VF610_I2C_REGSHIFT, 230 .clk_div = vf610_i2c_clk_div, 231 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div), 232 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 233 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 234 235 }; 236 237 static const struct platform_device_id imx_i2c_devtype[] = { 238 { 239 .name = "imx1-i2c", 240 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata, 241 }, { 242 .name = "imx21-i2c", 243 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata, 244 }, { 245 /* sentinel */ 246 } 247 }; 248 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); 249 250 static const struct of_device_id i2c_imx_dt_ids[] = { 251 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, }, 252 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, }, 253 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, }, 254 { /* sentinel */ } 255 }; 256 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); 257 258 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) 259 { 260 return i2c_imx->hwdata->devtype == IMX1_I2C; 261 } 262 263 static inline void imx_i2c_write_reg(unsigned int val, 264 struct imx_i2c_struct *i2c_imx, unsigned int reg) 265 { 266 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 267 } 268 269 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, 270 unsigned int reg) 271 { 272 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 273 } 274 275 /* Functions for DMA support */ 276 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, 277 dma_addr_t phy_addr) 278 { 279 struct imx_i2c_dma *dma; 280 struct dma_slave_config dma_sconfig; 281 struct device *dev = &i2c_imx->adapter.dev; 282 int ret; 283 284 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 285 if (!dma) 286 return; 287 288 dma->chan_tx = dma_request_slave_channel(dev, "tx"); 289 if (!dma->chan_tx) { 290 dev_dbg(dev, "can't request DMA tx channel\n"); 291 goto fail_al; 292 } 293 294 dma_sconfig.dst_addr = phy_addr + 295 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 296 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 297 dma_sconfig.dst_maxburst = 1; 298 dma_sconfig.direction = DMA_MEM_TO_DEV; 299 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig); 300 if (ret < 0) { 301 dev_dbg(dev, "can't configure tx channel\n"); 302 goto fail_tx; 303 } 304 305 dma->chan_rx = dma_request_slave_channel(dev, "rx"); 306 if (!dma->chan_rx) { 307 dev_dbg(dev, "can't request DMA rx channel\n"); 308 goto fail_tx; 309 } 310 311 dma_sconfig.src_addr = phy_addr + 312 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 313 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 314 dma_sconfig.src_maxburst = 1; 315 dma_sconfig.direction = DMA_DEV_TO_MEM; 316 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig); 317 if (ret < 0) { 318 dev_dbg(dev, "can't configure rx channel\n"); 319 goto fail_rx; 320 } 321 322 i2c_imx->dma = dma; 323 init_completion(&dma->cmd_complete); 324 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n", 325 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); 326 327 return; 328 329 fail_rx: 330 dma_release_channel(dma->chan_rx); 331 fail_tx: 332 dma_release_channel(dma->chan_tx); 333 fail_al: 334 devm_kfree(dev, dma); 335 dev_info(dev, "can't use DMA, using PIO instead.\n"); 336 } 337 338 static void i2c_imx_dma_callback(void *arg) 339 { 340 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg; 341 struct imx_i2c_dma *dma = i2c_imx->dma; 342 343 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf, 344 dma->dma_len, dma->dma_data_dir); 345 complete(&dma->cmd_complete); 346 } 347 348 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx, 349 struct i2c_msg *msgs) 350 { 351 struct imx_i2c_dma *dma = i2c_imx->dma; 352 struct dma_async_tx_descriptor *txdesc; 353 struct device *dev = &i2c_imx->adapter.dev; 354 struct device *chan_dev = dma->chan_using->device->dev; 355 356 dma->dma_buf = dma_map_single(chan_dev, msgs->buf, 357 dma->dma_len, dma->dma_data_dir); 358 if (dma_mapping_error(chan_dev, dma->dma_buf)) { 359 dev_err(dev, "DMA mapping failed\n"); 360 goto err_map; 361 } 362 363 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf, 364 dma->dma_len, dma->dma_transfer_dir, 365 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 366 if (!txdesc) { 367 dev_err(dev, "Not able to get desc for DMA xfer\n"); 368 goto err_desc; 369 } 370 371 reinit_completion(&dma->cmd_complete); 372 txdesc->callback = i2c_imx_dma_callback; 373 txdesc->callback_param = i2c_imx; 374 if (dma_submit_error(dmaengine_submit(txdesc))) { 375 dev_err(dev, "DMA submit failed\n"); 376 goto err_submit; 377 } 378 379 dma_async_issue_pending(dma->chan_using); 380 return 0; 381 382 err_submit: 383 dmaengine_terminate_all(dma->chan_using); 384 err_desc: 385 dma_unmap_single(chan_dev, dma->dma_buf, 386 dma->dma_len, dma->dma_data_dir); 387 err_map: 388 return -EINVAL; 389 } 390 391 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx) 392 { 393 struct imx_i2c_dma *dma = i2c_imx->dma; 394 395 dma->dma_buf = 0; 396 dma->dma_len = 0; 397 398 dma_release_channel(dma->chan_tx); 399 dma->chan_tx = NULL; 400 401 dma_release_channel(dma->chan_rx); 402 dma->chan_rx = NULL; 403 404 dma->chan_using = NULL; 405 } 406 407 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy) 408 { 409 unsigned long orig_jiffies = jiffies; 410 unsigned int temp; 411 412 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 413 414 while (1) { 415 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 416 417 /* check for arbitration lost */ 418 if (temp & I2SR_IAL) { 419 temp &= ~I2SR_IAL; 420 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 421 return -EAGAIN; 422 } 423 424 if (for_busy && (temp & I2SR_IBB)) { 425 i2c_imx->stopped = 0; 426 break; 427 } 428 if (!for_busy && !(temp & I2SR_IBB)) { 429 i2c_imx->stopped = 1; 430 break; 431 } 432 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 433 dev_dbg(&i2c_imx->adapter.dev, 434 "<%s> I2C bus is busy\n", __func__); 435 return -ETIMEDOUT; 436 } 437 schedule(); 438 } 439 440 return 0; 441 } 442 443 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx) 444 { 445 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); 446 447 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { 448 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); 449 return -ETIMEDOUT; 450 } 451 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); 452 i2c_imx->i2csr = 0; 453 return 0; 454 } 455 456 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) 457 { 458 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 459 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); 460 return -ENXIO; /* No ACK */ 461 } 462 463 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); 464 return 0; 465 } 466 467 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 468 unsigned int i2c_clk_rate) 469 { 470 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; 471 unsigned int div; 472 int i; 473 474 /* Divider value calculation */ 475 if (i2c_imx->cur_clk == i2c_clk_rate) 476 return; 477 478 i2c_imx->cur_clk = i2c_clk_rate; 479 480 div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate; 481 if (div < i2c_clk_div[0].div) 482 i = 0; 483 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) 484 i = i2c_imx->hwdata->ndivs - 1; 485 else 486 for (i = 0; i2c_clk_div[i].div < div; i++) 487 ; 488 489 /* Store divider value */ 490 i2c_imx->ifdr = i2c_clk_div[i].val; 491 492 /* 493 * There dummy delay is calculated. 494 * It should be about one I2C clock period long. 495 * This delay is used in I2C bus disable function 496 * to fix chip hardware bug. 497 */ 498 i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div 499 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2); 500 501 #ifdef CONFIG_I2C_DEBUG_BUS 502 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n", 503 i2c_clk_rate, div); 504 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n", 505 i2c_clk_div[i].val, i2c_clk_div[i].div); 506 #endif 507 } 508 509 static int i2c_imx_clk_notifier_call(struct notifier_block *nb, 510 unsigned long action, void *data) 511 { 512 struct clk_notifier_data *ndata = data; 513 struct imx_i2c_struct *i2c_imx = container_of(&ndata->clk, 514 struct imx_i2c_struct, 515 clk); 516 517 if (action & POST_RATE_CHANGE) 518 i2c_imx_set_clk(i2c_imx, ndata->new_rate); 519 520 return NOTIFY_OK; 521 } 522 523 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx) 524 { 525 unsigned int temp = 0; 526 int result; 527 528 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 529 530 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); 531 /* Enable I2C controller */ 532 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 533 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR); 534 535 /* Wait controller to be stable */ 536 usleep_range(50, 150); 537 538 /* Start I2C transaction */ 539 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 540 temp |= I2CR_MSTA; 541 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 542 result = i2c_imx_bus_busy(i2c_imx, 1); 543 if (result) 544 return result; 545 546 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; 547 temp &= ~I2CR_DMAEN; 548 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 549 return result; 550 } 551 552 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx) 553 { 554 unsigned int temp = 0; 555 556 if (!i2c_imx->stopped) { 557 /* Stop I2C transaction */ 558 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 559 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 560 temp &= ~(I2CR_MSTA | I2CR_MTX); 561 if (i2c_imx->dma) 562 temp &= ~I2CR_DMAEN; 563 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 564 } 565 if (is_imx1_i2c(i2c_imx)) { 566 /* 567 * This delay caused by an i.MXL hardware bug. 568 * If no (or too short) delay, no "STOP" bit will be generated. 569 */ 570 udelay(i2c_imx->disable_delay); 571 } 572 573 if (!i2c_imx->stopped) 574 i2c_imx_bus_busy(i2c_imx, 0); 575 576 /* Disable I2C controller */ 577 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 578 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 579 } 580 581 static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 582 { 583 struct imx_i2c_struct *i2c_imx = dev_id; 584 unsigned int temp; 585 586 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 587 if (temp & I2SR_IIF) { 588 /* save status register */ 589 i2c_imx->i2csr = temp; 590 temp &= ~I2SR_IIF; 591 temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF); 592 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 593 wake_up(&i2c_imx->queue); 594 return IRQ_HANDLED; 595 } 596 597 return IRQ_NONE; 598 } 599 600 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx, 601 struct i2c_msg *msgs) 602 { 603 int result; 604 unsigned long time_left; 605 unsigned int temp = 0; 606 unsigned long orig_jiffies = jiffies; 607 struct imx_i2c_dma *dma = i2c_imx->dma; 608 struct device *dev = &i2c_imx->adapter.dev; 609 610 dma->chan_using = dma->chan_tx; 611 dma->dma_transfer_dir = DMA_MEM_TO_DEV; 612 dma->dma_data_dir = DMA_TO_DEVICE; 613 dma->dma_len = msgs->len - 1; 614 result = i2c_imx_dma_xfer(i2c_imx, msgs); 615 if (result) 616 return result; 617 618 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 619 temp |= I2CR_DMAEN; 620 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 621 622 /* 623 * Write slave address. 624 * The first byte must be transmitted by the CPU. 625 */ 626 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 627 time_left = wait_for_completion_timeout( 628 &i2c_imx->dma->cmd_complete, 629 msecs_to_jiffies(DMA_TIMEOUT)); 630 if (time_left == 0) { 631 dmaengine_terminate_all(dma->chan_using); 632 return -ETIMEDOUT; 633 } 634 635 /* Waiting for transfer complete. */ 636 while (1) { 637 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 638 if (temp & I2SR_ICF) 639 break; 640 if (time_after(jiffies, orig_jiffies + 641 msecs_to_jiffies(DMA_TIMEOUT))) { 642 dev_dbg(dev, "<%s> Timeout\n", __func__); 643 return -ETIMEDOUT; 644 } 645 schedule(); 646 } 647 648 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 649 temp &= ~I2CR_DMAEN; 650 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 651 652 /* The last data byte must be transferred by the CPU. */ 653 imx_i2c_write_reg(msgs->buf[msgs->len-1], 654 i2c_imx, IMX_I2C_I2DR); 655 result = i2c_imx_trx_complete(i2c_imx); 656 if (result) 657 return result; 658 659 return i2c_imx_acked(i2c_imx); 660 } 661 662 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx, 663 struct i2c_msg *msgs, bool is_lastmsg) 664 { 665 int result; 666 unsigned long time_left; 667 unsigned int temp; 668 unsigned long orig_jiffies = jiffies; 669 struct imx_i2c_dma *dma = i2c_imx->dma; 670 struct device *dev = &i2c_imx->adapter.dev; 671 672 673 dma->chan_using = dma->chan_rx; 674 dma->dma_transfer_dir = DMA_DEV_TO_MEM; 675 dma->dma_data_dir = DMA_FROM_DEVICE; 676 /* The last two data bytes must be transferred by the CPU. */ 677 dma->dma_len = msgs->len - 2; 678 result = i2c_imx_dma_xfer(i2c_imx, msgs); 679 if (result) 680 return result; 681 682 time_left = wait_for_completion_timeout( 683 &i2c_imx->dma->cmd_complete, 684 msecs_to_jiffies(DMA_TIMEOUT)); 685 if (time_left == 0) { 686 dmaengine_terminate_all(dma->chan_using); 687 return -ETIMEDOUT; 688 } 689 690 /* waiting for transfer complete. */ 691 while (1) { 692 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 693 if (temp & I2SR_ICF) 694 break; 695 if (time_after(jiffies, orig_jiffies + 696 msecs_to_jiffies(DMA_TIMEOUT))) { 697 dev_dbg(dev, "<%s> Timeout\n", __func__); 698 return -ETIMEDOUT; 699 } 700 schedule(); 701 } 702 703 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 704 temp &= ~I2CR_DMAEN; 705 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 706 707 /* read n-1 byte data */ 708 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 709 temp |= I2CR_TXAK; 710 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 711 712 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 713 /* read n byte data */ 714 result = i2c_imx_trx_complete(i2c_imx); 715 if (result) 716 return result; 717 718 if (is_lastmsg) { 719 /* 720 * It must generate STOP before read I2DR to prevent 721 * controller from generating another clock cycle 722 */ 723 dev_dbg(dev, "<%s> clear MSTA\n", __func__); 724 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 725 temp &= ~(I2CR_MSTA | I2CR_MTX); 726 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 727 i2c_imx_bus_busy(i2c_imx, 0); 728 } else { 729 /* 730 * For i2c master receiver repeat restart operation like: 731 * read -> repeat MSTA -> read/write 732 * The controller must set MTX before read the last byte in 733 * the first read operation, otherwise the first read cost 734 * one extra clock cycle. 735 */ 736 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 737 temp |= I2CR_MTX; 738 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 739 } 740 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 741 742 return 0; 743 } 744 745 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) 746 { 747 int i, result; 748 749 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 750 __func__, i2c_8bit_addr_from_msg(msgs)); 751 752 /* write slave address */ 753 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 754 result = i2c_imx_trx_complete(i2c_imx); 755 if (result) 756 return result; 757 result = i2c_imx_acked(i2c_imx); 758 if (result) 759 return result; 760 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); 761 762 /* write data */ 763 for (i = 0; i < msgs->len; i++) { 764 dev_dbg(&i2c_imx->adapter.dev, 765 "<%s> write byte: B%d=0x%X\n", 766 __func__, i, msgs->buf[i]); 767 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); 768 result = i2c_imx_trx_complete(i2c_imx); 769 if (result) 770 return result; 771 result = i2c_imx_acked(i2c_imx); 772 if (result) 773 return result; 774 } 775 return 0; 776 } 777 778 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg) 779 { 780 int i, result; 781 unsigned int temp; 782 int block_data = msgs->flags & I2C_M_RECV_LEN; 783 int use_dma = i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data; 784 785 dev_dbg(&i2c_imx->adapter.dev, 786 "<%s> write slave address: addr=0x%x\n", 787 __func__, i2c_8bit_addr_from_msg(msgs)); 788 789 /* write slave address */ 790 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 791 result = i2c_imx_trx_complete(i2c_imx); 792 if (result) 793 return result; 794 result = i2c_imx_acked(i2c_imx); 795 if (result) 796 return result; 797 798 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); 799 800 /* setup bus to read data */ 801 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 802 temp &= ~I2CR_MTX; 803 804 /* 805 * Reset the I2CR_TXAK flag initially for SMBus block read since the 806 * length is unknown 807 */ 808 if ((msgs->len - 1) || block_data) 809 temp &= ~I2CR_TXAK; 810 if (use_dma) 811 temp |= I2CR_DMAEN; 812 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 813 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 814 815 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 816 817 if (use_dma) 818 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg); 819 820 /* read data */ 821 for (i = 0; i < msgs->len; i++) { 822 u8 len = 0; 823 824 result = i2c_imx_trx_complete(i2c_imx); 825 if (result) 826 return result; 827 /* 828 * First byte is the length of remaining packet 829 * in the SMBus block data read. Add it to 830 * msgs->len. 831 */ 832 if ((!i) && block_data) { 833 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 834 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) 835 return -EPROTO; 836 dev_dbg(&i2c_imx->adapter.dev, 837 "<%s> read length: 0x%X\n", 838 __func__, len); 839 msgs->len += len; 840 } 841 if (i == (msgs->len - 1)) { 842 if (is_lastmsg) { 843 /* 844 * It must generate STOP before read I2DR to prevent 845 * controller from generating another clock cycle 846 */ 847 dev_dbg(&i2c_imx->adapter.dev, 848 "<%s> clear MSTA\n", __func__); 849 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 850 temp &= ~(I2CR_MSTA | I2CR_MTX); 851 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 852 i2c_imx_bus_busy(i2c_imx, 0); 853 } else { 854 /* 855 * For i2c master receiver repeat restart operation like: 856 * read -> repeat MSTA -> read/write 857 * The controller must set MTX before read the last byte in 858 * the first read operation, otherwise the first read cost 859 * one extra clock cycle. 860 */ 861 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 862 temp |= I2CR_MTX; 863 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 864 } 865 } else if (i == (msgs->len - 2)) { 866 dev_dbg(&i2c_imx->adapter.dev, 867 "<%s> set TXAK\n", __func__); 868 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 869 temp |= I2CR_TXAK; 870 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 871 } 872 if ((!i) && block_data) 873 msgs->buf[0] = len; 874 else 875 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 876 dev_dbg(&i2c_imx->adapter.dev, 877 "<%s> read byte: B%d=0x%X\n", 878 __func__, i, msgs->buf[i]); 879 } 880 return 0; 881 } 882 883 static int i2c_imx_xfer(struct i2c_adapter *adapter, 884 struct i2c_msg *msgs, int num) 885 { 886 unsigned int i, temp; 887 int result; 888 bool is_lastmsg = false; 889 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 890 891 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 892 893 result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent); 894 if (result < 0) 895 goto out; 896 897 /* Start I2C transfer */ 898 result = i2c_imx_start(i2c_imx); 899 if (result) { 900 if (i2c_imx->adapter.bus_recovery_info) { 901 i2c_recover_bus(&i2c_imx->adapter); 902 result = i2c_imx_start(i2c_imx); 903 } 904 } 905 906 if (result) 907 goto fail0; 908 909 /* read/write data */ 910 for (i = 0; i < num; i++) { 911 if (i == num - 1) 912 is_lastmsg = true; 913 914 if (i) { 915 dev_dbg(&i2c_imx->adapter.dev, 916 "<%s> repeated start\n", __func__); 917 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 918 temp |= I2CR_RSTA; 919 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 920 result = i2c_imx_bus_busy(i2c_imx, 1); 921 if (result) 922 goto fail0; 923 } 924 dev_dbg(&i2c_imx->adapter.dev, 925 "<%s> transfer message: %d\n", __func__, i); 926 /* write/read data */ 927 #ifdef CONFIG_I2C_DEBUG_BUS 928 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 929 dev_dbg(&i2c_imx->adapter.dev, 930 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", 931 __func__, 932 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), 933 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), 934 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); 935 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 936 dev_dbg(&i2c_imx->adapter.dev, 937 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", 938 __func__, 939 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), 940 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), 941 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), 942 (temp & I2SR_RXAK ? 1 : 0)); 943 #endif 944 if (msgs[i].flags & I2C_M_RD) 945 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg); 946 else { 947 if (i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD) 948 result = i2c_imx_dma_write(i2c_imx, &msgs[i]); 949 else 950 result = i2c_imx_write(i2c_imx, &msgs[i]); 951 } 952 if (result) 953 goto fail0; 954 } 955 956 fail0: 957 /* Stop I2C transfer */ 958 i2c_imx_stop(i2c_imx); 959 960 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent); 961 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent); 962 963 out: 964 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 965 (result < 0) ? "error" : "success msg", 966 (result < 0) ? result : num); 967 return (result < 0) ? result : num; 968 } 969 970 static void i2c_imx_prepare_recovery(struct i2c_adapter *adap) 971 { 972 struct imx_i2c_struct *i2c_imx; 973 974 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); 975 976 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio); 977 } 978 979 static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap) 980 { 981 struct imx_i2c_struct *i2c_imx; 982 983 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); 984 985 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default); 986 } 987 988 /* 989 * We switch SCL and SDA to their GPIO function and do some bitbanging 990 * for bus recovery. These alternative pinmux settings can be 991 * described in the device tree by a separate pinctrl state "gpio". If 992 * this is missing this is not a big problem, the only implication is 993 * that we can't do bus recovery. 994 */ 995 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx, 996 struct platform_device *pdev) 997 { 998 struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo; 999 1000 i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev); 1001 if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) { 1002 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n"); 1003 return PTR_ERR(i2c_imx->pinctrl); 1004 } 1005 1006 i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl, 1007 PINCTRL_STATE_DEFAULT); 1008 i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl, 1009 "gpio"); 1010 rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN); 1011 rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN); 1012 1013 if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER || 1014 PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) { 1015 return -EPROBE_DEFER; 1016 } else if (IS_ERR(rinfo->sda_gpiod) || 1017 IS_ERR(rinfo->scl_gpiod) || 1018 IS_ERR(i2c_imx->pinctrl_pins_default) || 1019 IS_ERR(i2c_imx->pinctrl_pins_gpio)) { 1020 dev_dbg(&pdev->dev, "recovery information incomplete\n"); 1021 return 0; 1022 } 1023 1024 dev_dbg(&pdev->dev, "using scl%s for recovery\n", 1025 rinfo->sda_gpiod ? ",sda" : ""); 1026 1027 rinfo->prepare_recovery = i2c_imx_prepare_recovery; 1028 rinfo->unprepare_recovery = i2c_imx_unprepare_recovery; 1029 rinfo->recover_bus = i2c_generic_scl_recovery; 1030 i2c_imx->adapter.bus_recovery_info = rinfo; 1031 1032 return 0; 1033 } 1034 1035 static u32 i2c_imx_func(struct i2c_adapter *adapter) 1036 { 1037 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 1038 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1039 } 1040 1041 static const struct i2c_algorithm i2c_imx_algo = { 1042 .master_xfer = i2c_imx_xfer, 1043 .functionality = i2c_imx_func, 1044 }; 1045 1046 static int i2c_imx_probe(struct platform_device *pdev) 1047 { 1048 const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids, 1049 &pdev->dev); 1050 struct imx_i2c_struct *i2c_imx; 1051 struct resource *res; 1052 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev); 1053 void __iomem *base; 1054 int irq, ret; 1055 dma_addr_t phy_addr; 1056 1057 dev_dbg(&pdev->dev, "<%s>\n", __func__); 1058 1059 irq = platform_get_irq(pdev, 0); 1060 if (irq < 0) { 1061 dev_err(&pdev->dev, "can't get irq number\n"); 1062 return irq; 1063 } 1064 1065 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1066 base = devm_ioremap_resource(&pdev->dev, res); 1067 if (IS_ERR(base)) 1068 return PTR_ERR(base); 1069 1070 phy_addr = (dma_addr_t)res->start; 1071 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL); 1072 if (!i2c_imx) 1073 return -ENOMEM; 1074 1075 if (of_id) 1076 i2c_imx->hwdata = of_id->data; 1077 else 1078 i2c_imx->hwdata = (struct imx_i2c_hwdata *) 1079 platform_get_device_id(pdev)->driver_data; 1080 1081 /* Setup i2c_imx driver structure */ 1082 strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); 1083 i2c_imx->adapter.owner = THIS_MODULE; 1084 i2c_imx->adapter.algo = &i2c_imx_algo; 1085 i2c_imx->adapter.dev.parent = &pdev->dev; 1086 i2c_imx->adapter.nr = pdev->id; 1087 i2c_imx->adapter.dev.of_node = pdev->dev.of_node; 1088 i2c_imx->base = base; 1089 1090 /* Get I2C clock */ 1091 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL); 1092 if (IS_ERR(i2c_imx->clk)) { 1093 dev_err(&pdev->dev, "can't get I2C clock\n"); 1094 return PTR_ERR(i2c_imx->clk); 1095 } 1096 1097 ret = clk_prepare_enable(i2c_imx->clk); 1098 if (ret) { 1099 dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret); 1100 return ret; 1101 } 1102 1103 /* Request IRQ */ 1104 ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, IRQF_SHARED, 1105 pdev->name, i2c_imx); 1106 if (ret) { 1107 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 1108 goto clk_disable; 1109 } 1110 1111 /* Init queue */ 1112 init_waitqueue_head(&i2c_imx->queue); 1113 1114 /* Set up adapter data */ 1115 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); 1116 1117 /* Set up platform driver data */ 1118 platform_set_drvdata(pdev, i2c_imx); 1119 1120 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT); 1121 pm_runtime_use_autosuspend(&pdev->dev); 1122 pm_runtime_set_active(&pdev->dev); 1123 pm_runtime_enable(&pdev->dev); 1124 1125 ret = pm_runtime_get_sync(&pdev->dev); 1126 if (ret < 0) 1127 goto rpm_disable; 1128 1129 /* Set up clock divider */ 1130 i2c_imx->bitrate = IMX_I2C_BIT_RATE; 1131 ret = of_property_read_u32(pdev->dev.of_node, 1132 "clock-frequency", &i2c_imx->bitrate); 1133 if (ret < 0 && pdata && pdata->bitrate) 1134 i2c_imx->bitrate = pdata->bitrate; 1135 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call; 1136 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb); 1137 i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk)); 1138 1139 /* Set up chip registers to defaults */ 1140 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 1141 i2c_imx, IMX_I2C_I2CR); 1142 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 1143 1144 /* Init optional bus recovery function */ 1145 ret = i2c_imx_init_recovery_info(i2c_imx, pdev); 1146 /* Give it another chance if pinctrl used is not ready yet */ 1147 if (ret == -EPROBE_DEFER) 1148 goto clk_notifier_unregister; 1149 1150 /* Add I2C adapter */ 1151 ret = i2c_add_numbered_adapter(&i2c_imx->adapter); 1152 if (ret < 0) 1153 goto clk_notifier_unregister; 1154 1155 pm_runtime_mark_last_busy(&pdev->dev); 1156 pm_runtime_put_autosuspend(&pdev->dev); 1157 1158 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq); 1159 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res); 1160 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 1161 i2c_imx->adapter.name); 1162 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 1163 1164 /* Init DMA config if supported */ 1165 i2c_imx_dma_request(i2c_imx, phy_addr); 1166 1167 return 0; /* Return OK */ 1168 1169 clk_notifier_unregister: 1170 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1171 rpm_disable: 1172 pm_runtime_put_noidle(&pdev->dev); 1173 pm_runtime_disable(&pdev->dev); 1174 pm_runtime_set_suspended(&pdev->dev); 1175 pm_runtime_dont_use_autosuspend(&pdev->dev); 1176 1177 clk_disable: 1178 clk_disable_unprepare(i2c_imx->clk); 1179 return ret; 1180 } 1181 1182 static int i2c_imx_remove(struct platform_device *pdev) 1183 { 1184 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 1185 int ret; 1186 1187 ret = pm_runtime_get_sync(&pdev->dev); 1188 if (ret < 0) 1189 return ret; 1190 1191 /* remove adapter */ 1192 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 1193 i2c_del_adapter(&i2c_imx->adapter); 1194 1195 if (i2c_imx->dma) 1196 i2c_imx_dma_free(i2c_imx); 1197 1198 /* setup chip registers to defaults */ 1199 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 1200 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); 1201 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); 1202 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); 1203 1204 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1205 clk_disable_unprepare(i2c_imx->clk); 1206 1207 pm_runtime_put_noidle(&pdev->dev); 1208 pm_runtime_disable(&pdev->dev); 1209 1210 return 0; 1211 } 1212 1213 #ifdef CONFIG_PM 1214 static int i2c_imx_runtime_suspend(struct device *dev) 1215 { 1216 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1217 1218 clk_disable(i2c_imx->clk); 1219 1220 return 0; 1221 } 1222 1223 static int i2c_imx_runtime_resume(struct device *dev) 1224 { 1225 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1226 int ret; 1227 1228 ret = clk_enable(i2c_imx->clk); 1229 if (ret) 1230 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret); 1231 1232 return ret; 1233 } 1234 1235 static const struct dev_pm_ops i2c_imx_pm_ops = { 1236 SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend, 1237 i2c_imx_runtime_resume, NULL) 1238 }; 1239 #define I2C_IMX_PM_OPS (&i2c_imx_pm_ops) 1240 #else 1241 #define I2C_IMX_PM_OPS NULL 1242 #endif /* CONFIG_PM */ 1243 1244 static struct platform_driver i2c_imx_driver = { 1245 .probe = i2c_imx_probe, 1246 .remove = i2c_imx_remove, 1247 .driver = { 1248 .name = DRIVER_NAME, 1249 .pm = I2C_IMX_PM_OPS, 1250 .of_match_table = i2c_imx_dt_ids, 1251 }, 1252 .id_table = imx_i2c_devtype, 1253 }; 1254 1255 static int __init i2c_adap_imx_init(void) 1256 { 1257 return platform_driver_register(&i2c_imx_driver); 1258 } 1259 subsys_initcall(i2c_adap_imx_init); 1260 1261 static void __exit i2c_adap_imx_exit(void) 1262 { 1263 platform_driver_unregister(&i2c_imx_driver); 1264 } 1265 module_exit(i2c_adap_imx_exit); 1266 1267 MODULE_LICENSE("GPL"); 1268 MODULE_AUTHOR("Darius Augulis"); 1269 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); 1270 MODULE_ALIAS("platform:" DRIVER_NAME); 1271