1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2002 Motorola GSG-China 4 * 5 * Author: 6 * Darius Augulis, Teltonika Inc. 7 * 8 * Desc.: 9 * Implementation of I2C Adapter/Algorithm Driver 10 * for I2C Bus integrated in Freescale i.MX/MXC processors 11 * 12 * Derived from Motorola GSG China I2C example driver 13 * 14 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de 15 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de 16 * Copyright (C) 2007 RightHand Technologies, Inc. 17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 18 * 19 * Copyright 2013 Freescale Semiconductor, Inc. 20 * Copyright 2020, 2024 NXP 21 * 22 */ 23 24 #include <linux/acpi.h> 25 #include <linux/clk.h> 26 #include <linux/completion.h> 27 #include <linux/delay.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/dmaengine.h> 30 #include <linux/dmapool.h> 31 #include <linux/err.h> 32 #include <linux/errno.h> 33 #include <linux/gpio/consumer.h> 34 #include <linux/i2c.h> 35 #include <linux/init.h> 36 #include <linux/interrupt.h> 37 #include <linux/io.h> 38 #include <linux/iopoll.h> 39 #include <linux/kernel.h> 40 #include <linux/spinlock.h> 41 #include <linux/hrtimer.h> 42 #include <linux/module.h> 43 #include <linux/of.h> 44 #include <linux/of_dma.h> 45 #include <linux/pinctrl/consumer.h> 46 #include <linux/platform_data/i2c-imx.h> 47 #include <linux/platform_device.h> 48 #include <linux/pm_runtime.h> 49 #include <linux/sched.h> 50 #include <linux/slab.h> 51 52 /* This will be the driver name the kernel reports */ 53 #define DRIVER_NAME "imx-i2c" 54 55 #define I2C_IMX_CHECK_DELAY 30000 /* Time to check for bus idle, in NS */ 56 57 /* 58 * Enable DMA if transfer byte size is bigger than this threshold. 59 * As the hardware request, it must bigger than 4 bytes.\ 60 * I have set '16' here, maybe it's not the best but I think it's 61 * the appropriate. 62 */ 63 #define DMA_THRESHOLD 16 64 #define DMA_TIMEOUT 1000 65 66 /* IMX I2C registers: 67 * the I2C register offset is different between SoCs, 68 * to provide support for all these chips, split the 69 * register offset into a fixed base address and a 70 * variable shift value, then the full register offset 71 * will be calculated by 72 * reg_off = ( reg_base_addr << reg_shift) 73 */ 74 #define IMX_I2C_IADR 0x00 /* i2c slave address */ 75 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ 76 #define IMX_I2C_I2CR 0x02 /* i2c control */ 77 #define IMX_I2C_I2SR 0x03 /* i2c status */ 78 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */ 79 80 /* 81 * All of the layerscape series SoCs support IBIC register. 82 */ 83 #define IMX_I2C_IBIC 0x05 /* i2c bus interrupt config */ 84 85 #define IMX_I2C_REGSHIFT 2 86 #define VF610_I2C_REGSHIFT 0 87 #define S32G_I2C_REGSHIFT 0 88 89 /* Bits of IMX I2C registers */ 90 #define I2SR_RXAK 0x01 91 #define I2SR_IIF 0x02 92 #define I2SR_SRW 0x04 93 #define I2SR_IAL 0x10 94 #define I2SR_IBB 0x20 95 #define I2SR_IAAS 0x40 96 #define I2SR_ICF 0x80 97 #define I2CR_DMAEN 0x02 98 #define I2CR_RSTA 0x04 99 #define I2CR_TXAK 0x08 100 #define I2CR_MTX 0x10 101 #define I2CR_MSTA 0x20 102 #define I2CR_IIEN 0x40 103 #define I2CR_IEN 0x80 104 #define IBIC_BIIE 0x80 /* Bus idle interrupt enable */ 105 106 /* register bits different operating codes definition: 107 * 1) I2SR: Interrupt flags clear operation differ between SoCs: 108 * - write zero to clear(w0c) INT flag on i.MX, 109 * - but write one to clear(w1c) INT flag on Vybrid. 110 * 2) I2CR: I2C module enable operation also differ between SoCs: 111 * - set I2CR_IEN bit enable the module on i.MX, 112 * - but clear I2CR_IEN bit enable the module on Vybrid. 113 */ 114 #define I2SR_CLR_OPCODE_W0C 0x0 115 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) 116 #define I2CR_IEN_OPCODE_0 0x0 117 #define I2CR_IEN_OPCODE_1 I2CR_IEN 118 119 #define I2C_PM_TIMEOUT 10 /* ms */ 120 121 /* 122 * sorted list of clock divider, register value pairs 123 * taken from table 26-5, p.26-9, Freescale i.MX 124 * Integrated Portable System Processor Reference Manual 125 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 126 * 127 * Duplicated divider values removed from list 128 */ 129 struct imx_i2c_clk_pair { 130 u16 div; 131 u16 val; 132 }; 133 134 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = { 135 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 136 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 137 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 138 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 139 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 140 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 141 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 142 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 143 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 144 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 145 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 146 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 147 { 3072, 0x1E }, { 3840, 0x1F } 148 }; 149 150 /* Vybrid VF610 clock divider, register value pairs */ 151 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = { 152 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 153 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 154 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 155 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 156 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 157 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 158 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 159 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 160 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 161 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 162 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 163 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 164 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 165 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 166 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 167 }; 168 169 /* S32G2/S32G3 clock divider, register value pairs */ 170 static struct imx_i2c_clk_pair s32g2_i2c_clk_div[] = { 171 { 34, 0x00 }, { 36, 0x01 }, { 38, 0x02 }, { 40, 0x03 }, 172 { 42, 0x04 }, { 44, 0x05 }, { 46, 0x06 }, { 48, 0x09 }, 173 { 52, 0x0A }, { 54, 0x07 }, { 56, 0x0B }, { 60, 0x0C }, 174 { 64, 0x0D }, { 68, 0x40 }, { 72, 0x0E }, { 76, 0x42 }, 175 { 80, 0x12 }, { 84, 0x0F }, { 88, 0x13 }, { 96, 0x14 }, 176 { 104, 0x15 }, { 108, 0x47 }, { 112, 0x19 }, { 120, 0x16 }, 177 { 128, 0x1A }, { 136, 0x80 }, { 144, 0x17 }, { 152, 0x82 }, 178 { 160, 0x1C }, { 168, 0x84 }, { 176, 0x1D }, { 192, 0x21 }, 179 { 208, 0x1E }, { 216, 0x87 }, { 224, 0x22 }, { 240, 0x56 }, 180 { 256, 0x1F }, { 288, 0x24 }, { 320, 0x25 }, { 336, 0x8F }, 181 { 352, 0x93 }, { 356, 0x5D }, { 358, 0x98 }, { 384, 0x26 }, 182 { 416, 0x56 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 183 { 576, 0x2C }, { 640, 0x2D }, { 704, 0x9D }, { 768, 0x2E }, 184 { 832, 0x9D }, { 896, 0x32 }, { 960, 0x2F }, { 1024, 0x33 }, 185 { 1152, 0x34 }, { 1280, 0x35 }, { 1536, 0x36 }, { 1792, 0x3A }, 186 { 1920, 0x37 }, { 2048, 0x3B }, { 2304, 0x74 }, { 2560, 0x3D }, 187 { 3072, 0x3E }, { 3584, 0x7A }, { 3840, 0x3F }, { 4096, 0x7B }, 188 { 4608, 0x7C }, { 5120, 0x7D }, { 6144, 0x7E }, { 7168, 0xBA }, 189 { 7680, 0x7F }, { 8192, 0xBB }, { 9216, 0xBC }, { 10240, 0xBD }, 190 { 12288, 0xBE }, { 15360, 0xBF }, 191 }; 192 193 enum imx_i2c_type { 194 IMX1_I2C, 195 IMX21_I2C, 196 S32G_I2C, 197 VF610_I2C, 198 }; 199 200 struct imx_i2c_hwdata { 201 enum imx_i2c_type devtype; 202 unsigned int regshift; 203 struct imx_i2c_clk_pair *clk_div; 204 unsigned int ndivs; 205 unsigned int i2sr_clr_opcode; 206 unsigned int i2cr_ien_opcode; 207 /* 208 * Errata ERR007805 or e7805: 209 * I2C: When the I2C clock speed is configured for 400 kHz, 210 * the SCL low period violates the I2C spec of 1.3 uS min. 211 */ 212 bool has_err007805; 213 }; 214 215 struct imx_i2c_dma { 216 struct dma_chan *chan_tx; 217 struct dma_chan *chan_rx; 218 struct dma_chan *chan_using; 219 struct completion cmd_complete; 220 dma_addr_t dma_buf; 221 unsigned int dma_len; 222 enum dma_transfer_direction dma_transfer_dir; 223 enum dma_data_direction dma_data_dir; 224 }; 225 226 enum imx_i2c_state { 227 IMX_I2C_STATE_DONE, 228 IMX_I2C_STATE_FAILED, 229 IMX_I2C_STATE_WRITE, 230 IMX_I2C_STATE_DMA, 231 IMX_I2C_STATE_READ, 232 IMX_I2C_STATE_READ_CONTINUE, 233 IMX_I2C_STATE_READ_BLOCK_DATA, 234 IMX_I2C_STATE_READ_BLOCK_DATA_LEN, 235 }; 236 237 struct imx_i2c_struct { 238 struct i2c_adapter adapter; 239 struct clk *clk; 240 struct notifier_block clk_change_nb; 241 void __iomem *base; 242 wait_queue_head_t queue; 243 unsigned long i2csr; 244 unsigned int disable_delay; 245 int stopped; 246 unsigned int ifdr; /* IMX_I2C_IFDR */ 247 unsigned int cur_clk; 248 unsigned int bitrate; 249 const struct imx_i2c_hwdata *hwdata; 250 struct i2c_bus_recovery_info rinfo; 251 252 struct imx_i2c_dma *dma; 253 struct i2c_client *slave; 254 enum i2c_slave_event last_slave_event; 255 256 struct i2c_msg *msg; 257 unsigned int msg_buf_idx; 258 int isr_result; 259 bool is_lastmsg; 260 enum imx_i2c_state state; 261 262 bool multi_master; 263 264 /* For checking slave events. */ 265 spinlock_t slave_lock; 266 struct hrtimer slave_timer; 267 }; 268 269 static const struct imx_i2c_hwdata imx1_i2c_hwdata = { 270 .devtype = IMX1_I2C, 271 .regshift = IMX_I2C_REGSHIFT, 272 .clk_div = imx_i2c_clk_div, 273 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 274 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 275 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 276 277 }; 278 279 static const struct imx_i2c_hwdata imx21_i2c_hwdata = { 280 .devtype = IMX21_I2C, 281 .regshift = IMX_I2C_REGSHIFT, 282 .clk_div = imx_i2c_clk_div, 283 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 284 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 285 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 286 287 }; 288 289 static const struct imx_i2c_hwdata imx6_i2c_hwdata = { 290 .devtype = IMX21_I2C, 291 .regshift = IMX_I2C_REGSHIFT, 292 .clk_div = imx_i2c_clk_div, 293 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 294 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 295 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 296 .has_err007805 = true, 297 }; 298 299 static struct imx_i2c_hwdata vf610_i2c_hwdata = { 300 .devtype = VF610_I2C, 301 .regshift = VF610_I2C_REGSHIFT, 302 .clk_div = vf610_i2c_clk_div, 303 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div), 304 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 305 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 306 }; 307 308 static const struct imx_i2c_hwdata s32g2_i2c_hwdata = { 309 .devtype = S32G_I2C, 310 .regshift = S32G_I2C_REGSHIFT, 311 .clk_div = s32g2_i2c_clk_div, 312 .ndivs = ARRAY_SIZE(s32g2_i2c_clk_div), 313 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 314 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 315 }; 316 317 static const struct platform_device_id imx_i2c_devtype[] = { 318 { 319 .name = "imx1-i2c", 320 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata, 321 }, { 322 .name = "imx21-i2c", 323 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata, 324 }, { 325 /* sentinel */ 326 } 327 }; 328 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); 329 330 static const struct of_device_id i2c_imx_dt_ids[] = { 331 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, }, 332 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, }, 333 { .compatible = "fsl,imx6q-i2c", .data = &imx6_i2c_hwdata, }, 334 { .compatible = "fsl,imx6sl-i2c", .data = &imx6_i2c_hwdata, }, 335 { .compatible = "fsl,imx6sll-i2c", .data = &imx6_i2c_hwdata, }, 336 { .compatible = "fsl,imx6sx-i2c", .data = &imx6_i2c_hwdata, }, 337 { .compatible = "fsl,imx6ul-i2c", .data = &imx6_i2c_hwdata, }, 338 { .compatible = "fsl,imx7s-i2c", .data = &imx6_i2c_hwdata, }, 339 { .compatible = "fsl,imx8mm-i2c", .data = &imx6_i2c_hwdata, }, 340 { .compatible = "fsl,imx8mn-i2c", .data = &imx6_i2c_hwdata, }, 341 { .compatible = "fsl,imx8mp-i2c", .data = &imx6_i2c_hwdata, }, 342 { .compatible = "fsl,imx8mq-i2c", .data = &imx6_i2c_hwdata, }, 343 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, }, 344 { .compatible = "nxp,s32g2-i2c", .data = &s32g2_i2c_hwdata, }, 345 { /* sentinel */ } 346 }; 347 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); 348 349 static const struct acpi_device_id i2c_imx_acpi_ids[] = { 350 {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata}, 351 { } 352 }; 353 MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids); 354 355 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) 356 { 357 return i2c_imx->hwdata->devtype == IMX1_I2C; 358 } 359 360 static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx) 361 { 362 return i2c_imx->hwdata->devtype == VF610_I2C; 363 } 364 365 static inline void imx_i2c_write_reg(unsigned int val, 366 struct imx_i2c_struct *i2c_imx, unsigned int reg) 367 { 368 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 369 } 370 371 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, 372 unsigned int reg) 373 { 374 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 375 } 376 377 static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits) 378 { 379 unsigned int temp; 380 381 /* 382 * i2sr_clr_opcode is the value to clear all interrupts. Here we want to 383 * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits> 384 * toggled. This is required because i.MX needs W0C and Vybrid uses W1C. 385 */ 386 temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits; 387 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 388 } 389 390 /* Set up i2c controller register and i2c status register to default value. */ 391 static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx) 392 { 393 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 394 i2c_imx, IMX_I2C_I2CR); 395 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 396 } 397 398 /* Functions for DMA support */ 399 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, 400 dma_addr_t phy_addr) 401 { 402 struct imx_i2c_dma *dma; 403 struct dma_slave_config dma_sconfig; 404 struct device *dev = &i2c_imx->adapter.dev; 405 int ret; 406 407 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 408 if (!dma) 409 return; 410 411 dma->chan_tx = dma_request_chan(dev, "tx"); 412 if (IS_ERR(dma->chan_tx)) { 413 ret = PTR_ERR(dma->chan_tx); 414 if (ret != -ENODEV && ret != -EPROBE_DEFER) 415 dev_err(dev, "can't request DMA tx channel (%d)\n", ret); 416 goto fail_al; 417 } 418 419 dma_sconfig.dst_addr = phy_addr + 420 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 421 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 422 dma_sconfig.dst_maxburst = 1; 423 dma_sconfig.direction = DMA_MEM_TO_DEV; 424 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig); 425 if (ret < 0) { 426 dev_err(dev, "can't configure tx channel (%d)\n", ret); 427 goto fail_tx; 428 } 429 430 dma->chan_rx = dma_request_chan(dev, "rx"); 431 if (IS_ERR(dma->chan_rx)) { 432 ret = PTR_ERR(dma->chan_rx); 433 if (ret != -ENODEV && ret != -EPROBE_DEFER) 434 dev_err(dev, "can't request DMA rx channel (%d)\n", ret); 435 goto fail_tx; 436 } 437 438 dma_sconfig.src_addr = phy_addr + 439 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 440 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 441 dma_sconfig.src_maxburst = 1; 442 dma_sconfig.direction = DMA_DEV_TO_MEM; 443 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig); 444 if (ret < 0) { 445 dev_err(dev, "can't configure rx channel (%d)\n", ret); 446 goto fail_rx; 447 } 448 449 i2c_imx->dma = dma; 450 init_completion(&dma->cmd_complete); 451 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n", 452 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); 453 454 return; 455 456 fail_rx: 457 dma_release_channel(dma->chan_rx); 458 fail_tx: 459 dma_release_channel(dma->chan_tx); 460 fail_al: 461 devm_kfree(dev, dma); 462 } 463 464 static void i2c_imx_dma_callback(void *arg) 465 { 466 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg; 467 struct imx_i2c_dma *dma = i2c_imx->dma; 468 469 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf, 470 dma->dma_len, dma->dma_data_dir); 471 complete(&dma->cmd_complete); 472 } 473 474 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx, 475 struct i2c_msg *msgs) 476 { 477 struct imx_i2c_dma *dma = i2c_imx->dma; 478 struct dma_async_tx_descriptor *txdesc; 479 struct device *dev = &i2c_imx->adapter.dev; 480 struct device *chan_dev = dma->chan_using->device->dev; 481 482 dma->dma_buf = dma_map_single(chan_dev, msgs->buf, 483 dma->dma_len, dma->dma_data_dir); 484 if (dma_mapping_error(chan_dev, dma->dma_buf)) { 485 dev_err(dev, "DMA mapping failed\n"); 486 goto err_map; 487 } 488 489 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf, 490 dma->dma_len, dma->dma_transfer_dir, 491 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 492 if (!txdesc) { 493 dev_err(dev, "Not able to get desc for DMA xfer\n"); 494 goto err_desc; 495 } 496 497 reinit_completion(&dma->cmd_complete); 498 txdesc->callback = i2c_imx_dma_callback; 499 txdesc->callback_param = i2c_imx; 500 if (dma_submit_error(dmaengine_submit(txdesc))) { 501 dev_err(dev, "DMA submit failed\n"); 502 goto err_submit; 503 } 504 505 dma_async_issue_pending(dma->chan_using); 506 return 0; 507 508 err_submit: 509 dmaengine_terminate_sync(dma->chan_using); 510 err_desc: 511 dma_unmap_single(chan_dev, dma->dma_buf, 512 dma->dma_len, dma->dma_data_dir); 513 err_map: 514 return -EINVAL; 515 } 516 517 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx) 518 { 519 struct imx_i2c_dma *dma = i2c_imx->dma; 520 521 dma->dma_buf = 0; 522 dma->dma_len = 0; 523 524 dma_release_channel(dma->chan_tx); 525 dma->chan_tx = NULL; 526 527 dma_release_channel(dma->chan_rx); 528 dma->chan_rx = NULL; 529 530 dma->chan_using = NULL; 531 } 532 533 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic) 534 { 535 unsigned long orig_jiffies = jiffies; 536 unsigned int temp; 537 538 if (!i2c_imx->multi_master) 539 return 0; 540 541 while (1) { 542 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 543 544 /* check for arbitration lost */ 545 if (temp & I2SR_IAL) { 546 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 547 return -EAGAIN; 548 } 549 550 if (for_busy && (temp & I2SR_IBB)) { 551 i2c_imx->stopped = 0; 552 break; 553 } 554 if (!for_busy && !(temp & I2SR_IBB)) { 555 i2c_imx->stopped = 1; 556 break; 557 } 558 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 559 dev_dbg(&i2c_imx->adapter.dev, 560 "<%s> I2C bus is busy\n", __func__); 561 return -ETIMEDOUT; 562 } 563 if (atomic) 564 udelay(100); 565 else 566 schedule(); 567 } 568 569 return 0; 570 } 571 572 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic) 573 { 574 if (atomic) { 575 void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift); 576 unsigned int regval; 577 578 /* 579 * The formula for the poll timeout is documented in the RM 580 * Rev.5 on page 1878: 581 * T_min = 10/F_scl 582 * Set the value hard as it is done for the non-atomic use-case. 583 * Use 10 kHz for the calculation since this is the minimum 584 * allowed SMBus frequency. Also add an offset of 100us since it 585 * turned out that the I2SR_IIF bit isn't set correctly within 586 * the minimum timeout in polling mode. 587 */ 588 readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100); 589 i2c_imx->i2csr = regval; 590 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 591 } else { 592 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); 593 } 594 595 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { 596 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); 597 return -ETIMEDOUT; 598 } 599 600 /* In multi-master mode check for arbitration lost */ 601 if (i2c_imx->multi_master && (i2c_imx->i2csr & I2SR_IAL)) { 602 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__); 603 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 604 605 i2c_imx->i2csr = 0; 606 return -EAGAIN; 607 } 608 609 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); 610 i2c_imx->i2csr = 0; 611 return 0; 612 } 613 614 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) 615 { 616 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 617 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); 618 return -ENXIO; /* No ACK */ 619 } 620 621 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); 622 return 0; 623 } 624 625 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 626 unsigned int i2c_clk_rate) 627 { 628 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; 629 unsigned int div; 630 int i; 631 632 if (i2c_imx->hwdata->has_err007805 && i2c_imx->bitrate > 384000) { 633 dev_dbg(&i2c_imx->adapter.dev, 634 "SoC errata ERR007805 or e7805 applies, bus frequency limited from %d Hz to 384000 Hz.\n", 635 i2c_imx->bitrate); 636 i2c_imx->bitrate = 384000; 637 } 638 639 /* Divider value calculation */ 640 if (i2c_imx->cur_clk == i2c_clk_rate) 641 return; 642 643 i2c_imx->cur_clk = i2c_clk_rate; 644 645 div = DIV_ROUND_UP(i2c_clk_rate, i2c_imx->bitrate); 646 if (div < i2c_clk_div[0].div) 647 i = 0; 648 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) 649 i = i2c_imx->hwdata->ndivs - 1; 650 else 651 for (i = 0; i2c_clk_div[i].div < div; i++) 652 ; 653 654 /* Store divider value */ 655 i2c_imx->ifdr = i2c_clk_div[i].val; 656 657 /* 658 * There dummy delay is calculated. 659 * It should be about one I2C clock period long. 660 * This delay is used in I2C bus disable function 661 * to fix chip hardware bug. 662 */ 663 i2c_imx->disable_delay = DIV_ROUND_UP(500000U * i2c_clk_div[i].div, 664 i2c_clk_rate / 2); 665 666 #ifdef CONFIG_I2C_DEBUG_BUS 667 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n", 668 i2c_clk_rate, div); 669 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n", 670 i2c_clk_div[i].val, i2c_clk_div[i].div); 671 #endif 672 } 673 674 static int i2c_imx_clk_notifier_call(struct notifier_block *nb, 675 unsigned long action, void *data) 676 { 677 struct clk_notifier_data *ndata = data; 678 struct imx_i2c_struct *i2c_imx = container_of(nb, 679 struct imx_i2c_struct, 680 clk_change_nb); 681 682 if (action & POST_RATE_CHANGE) 683 i2c_imx_set_clk(i2c_imx, ndata->new_rate); 684 685 return NOTIFY_OK; 686 } 687 688 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic) 689 { 690 unsigned int temp = 0; 691 int result; 692 693 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); 694 /* Enable I2C controller */ 695 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 696 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR); 697 698 /* Wait controller to be stable */ 699 if (atomic) 700 udelay(50); 701 else 702 usleep_range(50, 150); 703 704 /* Start I2C transaction */ 705 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 706 temp |= I2CR_MSTA; 707 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 708 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 709 if (result) 710 return result; 711 712 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; 713 if (atomic) 714 temp &= ~I2CR_IIEN; /* Disable interrupt */ 715 716 temp &= ~I2CR_DMAEN; 717 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 718 return result; 719 } 720 721 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic) 722 { 723 unsigned int temp = 0; 724 725 if (!i2c_imx->stopped) { 726 /* Stop I2C transaction */ 727 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 728 if (!(temp & I2CR_MSTA)) 729 i2c_imx->stopped = 1; 730 temp &= ~(I2CR_MSTA | I2CR_MTX); 731 if (i2c_imx->dma) 732 temp &= ~I2CR_DMAEN; 733 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 734 } 735 if (is_imx1_i2c(i2c_imx)) { 736 /* 737 * This delay caused by an i.MXL hardware bug. 738 * If no (or too short) delay, no "STOP" bit will be generated. 739 */ 740 udelay(i2c_imx->disable_delay); 741 } 742 743 if (!i2c_imx->stopped) 744 i2c_imx_bus_busy(i2c_imx, 0, atomic); 745 746 /* Disable I2C controller */ 747 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN; 748 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 749 } 750 751 /* 752 * Enable bus idle interrupts 753 * Note: IBIC register will be cleared after disabled i2c module. 754 * All of layerscape series SoCs support IBIC register. 755 */ 756 static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx) 757 { 758 if (is_vf610_i2c(i2c_imx)) { 759 unsigned int temp; 760 761 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC); 762 temp |= IBIC_BIIE; 763 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC); 764 } 765 } 766 767 static void i2c_imx_slave_event(struct imx_i2c_struct *i2c_imx, 768 enum i2c_slave_event event, u8 *val) 769 { 770 i2c_slave_event(i2c_imx->slave, event, val); 771 i2c_imx->last_slave_event = event; 772 } 773 774 static void i2c_imx_slave_finish_op(struct imx_i2c_struct *i2c_imx) 775 { 776 u8 val = 0; 777 778 while (i2c_imx->last_slave_event != I2C_SLAVE_STOP) { 779 switch (i2c_imx->last_slave_event) { 780 case I2C_SLAVE_READ_REQUESTED: 781 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_READ_PROCESSED, 782 &val); 783 break; 784 785 case I2C_SLAVE_WRITE_REQUESTED: 786 case I2C_SLAVE_READ_PROCESSED: 787 case I2C_SLAVE_WRITE_RECEIVED: 788 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_STOP, &val); 789 break; 790 791 case I2C_SLAVE_STOP: 792 break; 793 } 794 } 795 } 796 797 /* Returns true if the timer should be restarted, false if not. */ 798 static irqreturn_t i2c_imx_slave_handle(struct imx_i2c_struct *i2c_imx, 799 unsigned int status, unsigned int ctl) 800 { 801 u8 value = 0; 802 803 if (status & I2SR_IAL) { /* Arbitration lost */ 804 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 805 if (!(status & I2SR_IAAS)) 806 return IRQ_HANDLED; 807 } 808 809 if (!(status & I2SR_IBB)) { 810 /* No master on the bus, that could mean a stop condition. */ 811 i2c_imx_slave_finish_op(i2c_imx); 812 return IRQ_HANDLED; 813 } 814 815 if (!(status & I2SR_ICF)) 816 /* Data transfer still in progress, ignore this. */ 817 goto out; 818 819 if (status & I2SR_IAAS) { /* Addressed as a slave */ 820 i2c_imx_slave_finish_op(i2c_imx); 821 if (status & I2SR_SRW) { /* Master wants to read from us*/ 822 dev_dbg(&i2c_imx->adapter.dev, "read requested"); 823 i2c_imx_slave_event(i2c_imx, 824 I2C_SLAVE_READ_REQUESTED, &value); 825 826 /* Slave transmit */ 827 ctl |= I2CR_MTX; 828 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 829 830 /* Send data */ 831 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 832 } else { /* Master wants to write to us */ 833 dev_dbg(&i2c_imx->adapter.dev, "write requested"); 834 i2c_imx_slave_event(i2c_imx, 835 I2C_SLAVE_WRITE_REQUESTED, &value); 836 837 /* Slave receive */ 838 ctl &= ~I2CR_MTX; 839 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 840 /* Dummy read */ 841 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 842 } 843 } else if (!(ctl & I2CR_MTX)) { /* Receive mode */ 844 value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 845 i2c_imx_slave_event(i2c_imx, 846 I2C_SLAVE_WRITE_RECEIVED, &value); 847 } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */ 848 ctl |= I2CR_MTX; 849 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 850 851 i2c_imx_slave_event(i2c_imx, 852 I2C_SLAVE_READ_PROCESSED, &value); 853 854 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 855 } else { /* Transmit mode received NAK, operation is done */ 856 ctl &= ~I2CR_MTX; 857 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 858 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 859 860 /* flag the last byte as processed */ 861 i2c_imx_slave_event(i2c_imx, 862 I2C_SLAVE_READ_PROCESSED, &value); 863 864 i2c_imx_slave_finish_op(i2c_imx); 865 return IRQ_HANDLED; 866 } 867 868 out: 869 /* 870 * No need to check the return value here. If it returns 0 or 871 * 1, then everything is fine. If it returns -1, then the 872 * timer is running in the handler. This will still work, 873 * though it may be redone (or already have been done) by the 874 * timer function. 875 */ 876 hrtimer_try_to_cancel(&i2c_imx->slave_timer); 877 hrtimer_forward_now(&i2c_imx->slave_timer, I2C_IMX_CHECK_DELAY); 878 hrtimer_restart(&i2c_imx->slave_timer); 879 return IRQ_HANDLED; 880 } 881 882 static enum hrtimer_restart i2c_imx_slave_timeout(struct hrtimer *t) 883 { 884 struct imx_i2c_struct *i2c_imx = container_of(t, struct imx_i2c_struct, 885 slave_timer); 886 unsigned int ctl, status; 887 unsigned long flags; 888 889 spin_lock_irqsave(&i2c_imx->slave_lock, flags); 890 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 891 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 892 i2c_imx_slave_handle(i2c_imx, status, ctl); 893 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags); 894 return HRTIMER_NORESTART; 895 } 896 897 static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx) 898 { 899 int temp; 900 901 /* Set slave addr. */ 902 imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR); 903 904 i2c_imx_reset_regs(i2c_imx); 905 906 /* Enable module */ 907 temp = i2c_imx->hwdata->i2cr_ien_opcode; 908 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 909 910 /* Enable interrupt from i2c module */ 911 temp |= I2CR_IIEN; 912 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 913 914 i2c_imx_enable_bus_idle(i2c_imx); 915 } 916 917 static int i2c_imx_reg_slave(struct i2c_client *client) 918 { 919 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 920 int ret; 921 922 if (i2c_imx->slave) 923 return -EBUSY; 924 925 i2c_imx->slave = client; 926 i2c_imx->last_slave_event = I2C_SLAVE_STOP; 927 928 /* Resume */ 929 ret = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent); 930 if (ret < 0) { 931 dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller"); 932 return ret; 933 } 934 935 i2c_imx_slave_init(i2c_imx); 936 937 return 0; 938 } 939 940 static int i2c_imx_unreg_slave(struct i2c_client *client) 941 { 942 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 943 int ret; 944 945 if (!i2c_imx->slave) 946 return -EINVAL; 947 948 /* Reset slave address. */ 949 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 950 951 i2c_imx_reset_regs(i2c_imx); 952 953 i2c_imx->slave = NULL; 954 955 /* Suspend */ 956 ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent); 957 if (ret < 0) 958 dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller"); 959 960 return ret; 961 } 962 963 static inline int i2c_imx_isr_acked(struct imx_i2c_struct *i2c_imx) 964 { 965 i2c_imx->isr_result = 0; 966 967 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 968 i2c_imx->state = IMX_I2C_STATE_FAILED; 969 i2c_imx->isr_result = -ENXIO; 970 wake_up(&i2c_imx->queue); 971 } 972 973 return i2c_imx->isr_result; 974 } 975 976 static inline int i2c_imx_isr_write(struct imx_i2c_struct *i2c_imx) 977 { 978 int result; 979 980 result = i2c_imx_isr_acked(i2c_imx); 981 if (result) 982 return result; 983 984 if (i2c_imx->msg->len == i2c_imx->msg_buf_idx) 985 return 0; 986 987 imx_i2c_write_reg(i2c_imx->msg->buf[i2c_imx->msg_buf_idx++], i2c_imx, IMX_I2C_I2DR); 988 989 return 1; 990 } 991 992 static inline int i2c_imx_isr_read(struct imx_i2c_struct *i2c_imx) 993 { 994 int result; 995 unsigned int temp; 996 997 result = i2c_imx_isr_acked(i2c_imx); 998 if (result) 999 return result; 1000 1001 /* setup bus to read data */ 1002 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1003 temp &= ~I2CR_MTX; 1004 if (i2c_imx->msg->len - 1) 1005 temp &= ~I2CR_TXAK; 1006 1007 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1008 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 1009 1010 return 0; 1011 } 1012 1013 static inline void i2c_imx_isr_read_continue(struct imx_i2c_struct *i2c_imx) 1014 { 1015 unsigned int temp; 1016 1017 if ((i2c_imx->msg->len - 1) == i2c_imx->msg_buf_idx) { 1018 if (i2c_imx->is_lastmsg) { 1019 /* 1020 * It must generate STOP before read I2DR to prevent 1021 * controller from generating another clock cycle 1022 */ 1023 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1024 if (!(temp & I2CR_MSTA)) 1025 i2c_imx->stopped = 1; 1026 temp &= ~(I2CR_MSTA | I2CR_MTX); 1027 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1028 } else { 1029 /* 1030 * For i2c master receiver repeat restart operation like: 1031 * read -> repeat MSTA -> read/write 1032 * The controller must set MTX before read the last byte in 1033 * the first read operation, otherwise the first read cost 1034 * one extra clock cycle. 1035 */ 1036 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1037 temp |= I2CR_MTX; 1038 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1039 } 1040 } else if (i2c_imx->msg_buf_idx == (i2c_imx->msg->len - 2)) { 1041 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1042 temp |= I2CR_TXAK; 1043 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1044 } 1045 1046 i2c_imx->msg->buf[i2c_imx->msg_buf_idx++] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1047 } 1048 1049 static inline void i2c_imx_isr_read_block_data_len(struct imx_i2c_struct *i2c_imx) 1050 { 1051 u8 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1052 1053 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) { 1054 i2c_imx->isr_result = -EPROTO; 1055 i2c_imx->state = IMX_I2C_STATE_FAILED; 1056 wake_up(&i2c_imx->queue); 1057 } 1058 i2c_imx->msg->len += len; 1059 } 1060 1061 static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned int status) 1062 { 1063 /* 1064 * This state machine handles I2C reception and transmission in non-DMA 1065 * mode. We must process all the data in the ISR to reduce the delay 1066 * between two consecutive messages. If the data is not processed in 1067 * the ISR, SMBus devices may timeout, leading to a bus error. 1068 */ 1069 switch (i2c_imx->state) { 1070 case IMX_I2C_STATE_DMA: 1071 i2c_imx->i2csr = status; 1072 wake_up(&i2c_imx->queue); 1073 break; 1074 1075 case IMX_I2C_STATE_READ: 1076 if (i2c_imx_isr_read(i2c_imx)) 1077 break; 1078 i2c_imx->state = IMX_I2C_STATE_READ_CONTINUE; 1079 break; 1080 1081 case IMX_I2C_STATE_READ_CONTINUE: 1082 i2c_imx_isr_read_continue(i2c_imx); 1083 if (i2c_imx->msg_buf_idx == i2c_imx->msg->len) { 1084 i2c_imx->state = IMX_I2C_STATE_DONE; 1085 wake_up(&i2c_imx->queue); 1086 } 1087 break; 1088 1089 case IMX_I2C_STATE_READ_BLOCK_DATA: 1090 if (i2c_imx_isr_read(i2c_imx)) 1091 break; 1092 i2c_imx->state = IMX_I2C_STATE_READ_BLOCK_DATA_LEN; 1093 break; 1094 1095 case IMX_I2C_STATE_READ_BLOCK_DATA_LEN: 1096 i2c_imx_isr_read_block_data_len(i2c_imx); 1097 i2c_imx->state = IMX_I2C_STATE_READ_CONTINUE; 1098 break; 1099 1100 case IMX_I2C_STATE_WRITE: 1101 if (i2c_imx_isr_write(i2c_imx)) 1102 break; 1103 i2c_imx->state = IMX_I2C_STATE_DONE; 1104 wake_up(&i2c_imx->queue); 1105 break; 1106 1107 default: 1108 i2c_imx->i2csr = status; 1109 i2c_imx->state = IMX_I2C_STATE_FAILED; 1110 i2c_imx->isr_result = -EINVAL; 1111 wake_up(&i2c_imx->queue); 1112 } 1113 1114 return IRQ_HANDLED; 1115 } 1116 1117 static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 1118 { 1119 struct imx_i2c_struct *i2c_imx = dev_id; 1120 unsigned int ctl, status; 1121 unsigned long flags; 1122 1123 spin_lock_irqsave(&i2c_imx->slave_lock, flags); 1124 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1125 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1126 1127 if (status & I2SR_IIF) { 1128 i2c_imx_clear_irq(i2c_imx, I2SR_IIF); 1129 if (i2c_imx->slave) { 1130 if (!(ctl & I2CR_MSTA)) { 1131 irqreturn_t ret; 1132 1133 ret = i2c_imx_slave_handle(i2c_imx, 1134 status, ctl); 1135 spin_unlock_irqrestore(&i2c_imx->slave_lock, 1136 flags); 1137 return ret; 1138 } 1139 i2c_imx_slave_finish_op(i2c_imx); 1140 } 1141 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags); 1142 return i2c_imx_master_isr(i2c_imx, status); 1143 } 1144 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags); 1145 1146 return IRQ_NONE; 1147 } 1148 1149 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx, 1150 struct i2c_msg *msgs) 1151 { 1152 int result; 1153 unsigned long time_left; 1154 unsigned int temp = 0; 1155 unsigned long orig_jiffies = jiffies; 1156 struct imx_i2c_dma *dma = i2c_imx->dma; 1157 struct device *dev = &i2c_imx->adapter.dev; 1158 1159 i2c_imx->state = IMX_I2C_STATE_DMA; 1160 1161 dma->chan_using = dma->chan_tx; 1162 dma->dma_transfer_dir = DMA_MEM_TO_DEV; 1163 dma->dma_data_dir = DMA_TO_DEVICE; 1164 dma->dma_len = msgs->len - 1; 1165 result = i2c_imx_dma_xfer(i2c_imx, msgs); 1166 if (result) 1167 return result; 1168 1169 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1170 temp |= I2CR_DMAEN; 1171 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1172 1173 /* 1174 * Write slave address. 1175 * The first byte must be transmitted by the CPU. 1176 */ 1177 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1178 time_left = wait_for_completion_timeout( 1179 &i2c_imx->dma->cmd_complete, 1180 msecs_to_jiffies(DMA_TIMEOUT)); 1181 if (time_left == 0) { 1182 dmaengine_terminate_sync(dma->chan_using); 1183 return -ETIMEDOUT; 1184 } 1185 1186 /* Waiting for transfer complete. */ 1187 while (1) { 1188 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1189 if (temp & I2SR_ICF) 1190 break; 1191 if (time_after(jiffies, orig_jiffies + 1192 msecs_to_jiffies(DMA_TIMEOUT))) { 1193 dev_dbg(dev, "<%s> Timeout\n", __func__); 1194 return -ETIMEDOUT; 1195 } 1196 schedule(); 1197 } 1198 1199 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1200 temp &= ~I2CR_DMAEN; 1201 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1202 1203 /* The last data byte must be transferred by the CPU. */ 1204 imx_i2c_write_reg(msgs->buf[msgs->len-1], 1205 i2c_imx, IMX_I2C_I2DR); 1206 result = i2c_imx_trx_complete(i2c_imx, false); 1207 if (result) 1208 return result; 1209 1210 return i2c_imx_acked(i2c_imx); 1211 } 1212 1213 static int i2c_imx_prepare_read(struct imx_i2c_struct *i2c_imx, 1214 struct i2c_msg *msgs, bool use_dma) 1215 { 1216 int result; 1217 unsigned int temp = 0; 1218 1219 /* write slave address */ 1220 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1221 result = i2c_imx_trx_complete(i2c_imx, !use_dma); 1222 if (result) 1223 return result; 1224 result = i2c_imx_acked(i2c_imx); 1225 if (result) 1226 return result; 1227 1228 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); 1229 1230 /* setup bus to read data */ 1231 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1232 temp &= ~I2CR_MTX; 1233 1234 /* 1235 * Reset the I2CR_TXAK flag initially for SMBus block read since the 1236 * length is unknown 1237 */ 1238 if (msgs->len - 1) 1239 temp &= ~I2CR_TXAK; 1240 if (use_dma) 1241 temp |= I2CR_DMAEN; 1242 1243 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1244 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 1245 1246 return 0; 1247 } 1248 1249 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx, 1250 struct i2c_msg *msgs, bool is_lastmsg) 1251 { 1252 int result; 1253 unsigned long time_left; 1254 unsigned int temp; 1255 unsigned long orig_jiffies = jiffies; 1256 struct imx_i2c_dma *dma = i2c_imx->dma; 1257 struct device *dev = &i2c_imx->adapter.dev; 1258 1259 i2c_imx->state = IMX_I2C_STATE_DMA; 1260 1261 result = i2c_imx_prepare_read(i2c_imx, msgs, true); 1262 if (result) 1263 return result; 1264 1265 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 1266 1267 dma->chan_using = dma->chan_rx; 1268 dma->dma_transfer_dir = DMA_DEV_TO_MEM; 1269 dma->dma_data_dir = DMA_FROM_DEVICE; 1270 /* The last two data bytes must be transferred by the CPU. */ 1271 dma->dma_len = msgs->len - 2; 1272 result = i2c_imx_dma_xfer(i2c_imx, msgs); 1273 if (result) 1274 return result; 1275 1276 time_left = wait_for_completion_timeout( 1277 &i2c_imx->dma->cmd_complete, 1278 msecs_to_jiffies(DMA_TIMEOUT)); 1279 if (time_left == 0) { 1280 dmaengine_terminate_sync(dma->chan_using); 1281 return -ETIMEDOUT; 1282 } 1283 1284 /* waiting for transfer complete. */ 1285 while (1) { 1286 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1287 if (temp & I2SR_ICF) 1288 break; 1289 if (time_after(jiffies, orig_jiffies + 1290 msecs_to_jiffies(DMA_TIMEOUT))) { 1291 dev_dbg(dev, "<%s> Timeout\n", __func__); 1292 return -ETIMEDOUT; 1293 } 1294 schedule(); 1295 } 1296 1297 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1298 temp &= ~I2CR_DMAEN; 1299 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1300 1301 /* read n-1 byte data */ 1302 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1303 temp |= I2CR_TXAK; 1304 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1305 1306 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1307 /* read n byte data */ 1308 result = i2c_imx_trx_complete(i2c_imx, false); 1309 if (result) 1310 return result; 1311 1312 if (is_lastmsg) { 1313 /* 1314 * It must generate STOP before read I2DR to prevent 1315 * controller from generating another clock cycle 1316 */ 1317 dev_dbg(dev, "<%s> clear MSTA\n", __func__); 1318 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1319 if (!(temp & I2CR_MSTA)) 1320 i2c_imx->stopped = 1; 1321 temp &= ~(I2CR_MSTA | I2CR_MTX); 1322 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1323 if (!i2c_imx->stopped) 1324 i2c_imx_bus_busy(i2c_imx, 0, false); 1325 } else { 1326 /* 1327 * For i2c master receiver repeat restart operation like: 1328 * read -> repeat MSTA -> read/write 1329 * The controller must set MTX before read the last byte in 1330 * the first read operation, otherwise the first read cost 1331 * one extra clock cycle. 1332 */ 1333 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1334 temp |= I2CR_MTX; 1335 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1336 } 1337 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1338 1339 return 0; 1340 } 1341 1342 static int i2c_imx_atomic_write(struct imx_i2c_struct *i2c_imx, 1343 struct i2c_msg *msgs) 1344 { 1345 int i, result; 1346 1347 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 1348 __func__, i2c_8bit_addr_from_msg(msgs)); 1349 1350 /* write slave address */ 1351 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1352 result = i2c_imx_trx_complete(i2c_imx, true); 1353 if (result) 1354 return result; 1355 result = i2c_imx_acked(i2c_imx); 1356 if (result) 1357 return result; 1358 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); 1359 1360 /* write data */ 1361 for (i = 0; i < msgs->len; i++) { 1362 dev_dbg(&i2c_imx->adapter.dev, 1363 "<%s> write byte: B%d=0x%X\n", 1364 __func__, i, msgs->buf[i]); 1365 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); 1366 result = i2c_imx_trx_complete(i2c_imx, true); 1367 if (result) 1368 return result; 1369 result = i2c_imx_acked(i2c_imx); 1370 if (result) 1371 return result; 1372 } 1373 return 0; 1374 } 1375 1376 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) 1377 { 1378 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 1379 __func__, i2c_8bit_addr_from_msg(msgs)); 1380 1381 i2c_imx->state = IMX_I2C_STATE_WRITE; 1382 i2c_imx->msg = msgs; 1383 i2c_imx->msg_buf_idx = 0; 1384 1385 /* 1386 * By writing the device address we start the state machine in the ISR. 1387 * The ISR will report when it is done or when it fails. 1388 */ 1389 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1390 wait_event_timeout(i2c_imx->queue, 1391 i2c_imx->state == IMX_I2C_STATE_DONE || 1392 i2c_imx->state == IMX_I2C_STATE_FAILED, 1393 (msgs->len + 1) * HZ / 10); 1394 if (i2c_imx->state == IMX_I2C_STATE_FAILED) { 1395 dev_dbg(&i2c_imx->adapter.dev, "<%s> write failed with %d\n", 1396 __func__, i2c_imx->isr_result); 1397 return i2c_imx->isr_result; 1398 } 1399 if (i2c_imx->state != IMX_I2C_STATE_DONE) { 1400 dev_err(&i2c_imx->adapter.dev, "<%s> write timedout\n", __func__); 1401 return -ETIMEDOUT; 1402 } 1403 return 0; 1404 } 1405 1406 static int i2c_imx_atomic_read(struct imx_i2c_struct *i2c_imx, 1407 struct i2c_msg *msgs, bool is_lastmsg) 1408 { 1409 int i, result; 1410 unsigned int temp; 1411 int block_data = msgs->flags & I2C_M_RECV_LEN; 1412 1413 result = i2c_imx_prepare_read(i2c_imx, msgs, false); 1414 if (result) 1415 return result; 1416 1417 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 1418 1419 /* read data */ 1420 for (i = 0; i < msgs->len; i++) { 1421 u8 len = 0; 1422 1423 result = i2c_imx_trx_complete(i2c_imx, true); 1424 if (result) 1425 return result; 1426 /* 1427 * First byte is the length of remaining packet 1428 * in the SMBus block data read. Add it to 1429 * msgs->len. 1430 */ 1431 if ((!i) && block_data) { 1432 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1433 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) 1434 return -EPROTO; 1435 dev_dbg(&i2c_imx->adapter.dev, 1436 "<%s> read length: 0x%X\n", 1437 __func__, len); 1438 msgs->len += len; 1439 } 1440 if (i == (msgs->len - 1)) { 1441 if (is_lastmsg) { 1442 /* 1443 * It must generate STOP before read I2DR to prevent 1444 * controller from generating another clock cycle 1445 */ 1446 dev_dbg(&i2c_imx->adapter.dev, 1447 "<%s> clear MSTA\n", __func__); 1448 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1449 if (!(temp & I2CR_MSTA)) 1450 i2c_imx->stopped = 1; 1451 temp &= ~(I2CR_MSTA | I2CR_MTX); 1452 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1453 if (!i2c_imx->stopped) 1454 i2c_imx_bus_busy(i2c_imx, 0, true); 1455 } else { 1456 /* 1457 * For i2c master receiver repeat restart operation like: 1458 * read -> repeat MSTA -> read/write 1459 * The controller must set MTX before read the last byte in 1460 * the first read operation, otherwise the first read cost 1461 * one extra clock cycle. 1462 */ 1463 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1464 temp |= I2CR_MTX; 1465 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1466 } 1467 } else if (i == (msgs->len - 2)) { 1468 dev_dbg(&i2c_imx->adapter.dev, 1469 "<%s> set TXAK\n", __func__); 1470 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1471 temp |= I2CR_TXAK; 1472 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1473 } 1474 if ((!i) && block_data) 1475 msgs->buf[0] = len; 1476 else 1477 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1478 dev_dbg(&i2c_imx->adapter.dev, 1479 "<%s> read byte: B%d=0x%X\n", 1480 __func__, i, msgs->buf[i]); 1481 } 1482 return 0; 1483 } 1484 1485 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, 1486 bool is_lastmsg) 1487 { 1488 int block_data = msgs->flags & I2C_M_RECV_LEN; 1489 1490 dev_dbg(&i2c_imx->adapter.dev, 1491 "<%s> write slave address: addr=0x%x\n", 1492 __func__, i2c_8bit_addr_from_msg(msgs)); 1493 1494 i2c_imx->is_lastmsg = is_lastmsg; 1495 1496 if (block_data) 1497 i2c_imx->state = IMX_I2C_STATE_READ_BLOCK_DATA; 1498 else 1499 i2c_imx->state = IMX_I2C_STATE_READ; 1500 i2c_imx->msg = msgs; 1501 i2c_imx->msg_buf_idx = 0; 1502 1503 /* 1504 * By writing the device address we start the state machine in the ISR. 1505 * The ISR will report when it is done or when it fails. 1506 */ 1507 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1508 wait_event_timeout(i2c_imx->queue, 1509 i2c_imx->state == IMX_I2C_STATE_DONE || 1510 i2c_imx->state == IMX_I2C_STATE_FAILED, 1511 (msgs->len + 1) * HZ / 10); 1512 if (i2c_imx->state == IMX_I2C_STATE_FAILED) { 1513 dev_dbg(&i2c_imx->adapter.dev, "<%s> read failed with %d\n", 1514 __func__, i2c_imx->isr_result); 1515 return i2c_imx->isr_result; 1516 } 1517 if (i2c_imx->state != IMX_I2C_STATE_DONE) { 1518 dev_err(&i2c_imx->adapter.dev, "<%s> read timedout\n", __func__); 1519 return -ETIMEDOUT; 1520 } 1521 if (!i2c_imx->stopped) 1522 return i2c_imx_bus_busy(i2c_imx, 0, false); 1523 1524 return 0; 1525 } 1526 1527 static int i2c_imx_xfer_common(struct i2c_adapter *adapter, 1528 struct i2c_msg *msgs, int num, bool atomic) 1529 { 1530 unsigned int i, temp; 1531 int result; 1532 bool is_lastmsg = false; 1533 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1534 int use_dma = 0; 1535 1536 /* Start I2C transfer */ 1537 result = i2c_imx_start(i2c_imx, atomic); 1538 if (result) { 1539 /* 1540 * Bus recovery uses gpiod_get_value_cansleep() which is not 1541 * allowed within atomic context. 1542 */ 1543 if (!atomic && i2c_imx->adapter.bus_recovery_info) { 1544 i2c_recover_bus(&i2c_imx->adapter); 1545 result = i2c_imx_start(i2c_imx, atomic); 1546 } 1547 } 1548 1549 if (result) 1550 goto fail0; 1551 1552 /* read/write data */ 1553 for (i = 0; i < num; i++) { 1554 if (i == num - 1) 1555 is_lastmsg = true; 1556 1557 if (i) { 1558 dev_dbg(&i2c_imx->adapter.dev, 1559 "<%s> repeated start\n", __func__); 1560 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1561 temp |= I2CR_RSTA; 1562 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1563 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 1564 if (result) 1565 goto fail0; 1566 } 1567 dev_dbg(&i2c_imx->adapter.dev, 1568 "<%s> transfer message: %d\n", __func__, i); 1569 /* write/read data */ 1570 #ifdef CONFIG_I2C_DEBUG_BUS 1571 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1572 dev_dbg(&i2c_imx->adapter.dev, 1573 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", 1574 __func__, 1575 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), 1576 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), 1577 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); 1578 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1579 dev_dbg(&i2c_imx->adapter.dev, 1580 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", 1581 __func__, 1582 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), 1583 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), 1584 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), 1585 (temp & I2SR_RXAK ? 1 : 0)); 1586 #endif 1587 1588 use_dma = i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD && 1589 msgs[i].flags & I2C_M_DMA_SAFE; 1590 if (msgs[i].flags & I2C_M_RD) { 1591 int block_data = msgs->flags & I2C_M_RECV_LEN; 1592 1593 if (atomic) 1594 result = i2c_imx_atomic_read(i2c_imx, &msgs[i], is_lastmsg); 1595 else if (use_dma && !block_data) 1596 result = i2c_imx_dma_read(i2c_imx, &msgs[i], is_lastmsg); 1597 else 1598 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg); 1599 } else { 1600 if (atomic) 1601 result = i2c_imx_atomic_write(i2c_imx, &msgs[i]); 1602 else if (use_dma) 1603 result = i2c_imx_dma_write(i2c_imx, &msgs[i]); 1604 else 1605 result = i2c_imx_write(i2c_imx, &msgs[i]); 1606 } 1607 if (result) 1608 goto fail0; 1609 } 1610 1611 fail0: 1612 /* Stop I2C transfer */ 1613 i2c_imx_stop(i2c_imx, atomic); 1614 1615 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 1616 (result < 0) ? "error" : "success msg", 1617 (result < 0) ? result : num); 1618 /* After data is transferred, switch to slave mode(as a receiver) */ 1619 if (i2c_imx->slave) 1620 i2c_imx_slave_init(i2c_imx); 1621 1622 return (result < 0) ? result : num; 1623 } 1624 1625 static int i2c_imx_xfer(struct i2c_adapter *adapter, 1626 struct i2c_msg *msgs, int num) 1627 { 1628 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1629 int result; 1630 1631 result = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent); 1632 if (result < 0) 1633 return result; 1634 1635 result = i2c_imx_xfer_common(adapter, msgs, num, false); 1636 1637 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent); 1638 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent); 1639 1640 return result; 1641 } 1642 1643 static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter, 1644 struct i2c_msg *msgs, int num) 1645 { 1646 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1647 int result; 1648 1649 result = clk_enable(i2c_imx->clk); 1650 if (result) 1651 return result; 1652 1653 result = i2c_imx_xfer_common(adapter, msgs, num, true); 1654 1655 clk_disable(i2c_imx->clk); 1656 1657 return result; 1658 } 1659 1660 /* 1661 * We switch SCL and SDA to their GPIO function and do some bitbanging 1662 * for bus recovery. These alternative pinmux settings can be 1663 * described in the device tree by a separate pinctrl state "gpio". If 1664 * this is missing this is not a big problem, the only implication is 1665 * that we can't do bus recovery. 1666 */ 1667 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx, 1668 struct platform_device *pdev) 1669 { 1670 struct i2c_bus_recovery_info *bri = &i2c_imx->rinfo; 1671 1672 bri->pinctrl = devm_pinctrl_get(&pdev->dev); 1673 if (IS_ERR(bri->pinctrl)) 1674 return PTR_ERR(bri->pinctrl); 1675 1676 i2c_imx->adapter.bus_recovery_info = bri; 1677 1678 return 0; 1679 } 1680 1681 static u32 i2c_imx_func(struct i2c_adapter *adapter) 1682 { 1683 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 1684 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1685 } 1686 1687 static const struct i2c_algorithm i2c_imx_algo = { 1688 .master_xfer = i2c_imx_xfer, 1689 .master_xfer_atomic = i2c_imx_xfer_atomic, 1690 .functionality = i2c_imx_func, 1691 .reg_slave = i2c_imx_reg_slave, 1692 .unreg_slave = i2c_imx_unreg_slave, 1693 }; 1694 1695 static int i2c_imx_probe(struct platform_device *pdev) 1696 { 1697 struct imx_i2c_struct *i2c_imx; 1698 struct resource *res; 1699 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev); 1700 void __iomem *base; 1701 int irq, ret; 1702 dma_addr_t phy_addr; 1703 const struct imx_i2c_hwdata *match; 1704 1705 irq = platform_get_irq(pdev, 0); 1706 if (irq < 0) 1707 return irq; 1708 1709 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1710 if (IS_ERR(base)) 1711 return PTR_ERR(base); 1712 1713 phy_addr = (dma_addr_t)res->start; 1714 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL); 1715 if (!i2c_imx) 1716 return -ENOMEM; 1717 1718 spin_lock_init(&i2c_imx->slave_lock); 1719 hrtimer_init(&i2c_imx->slave_timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); 1720 i2c_imx->slave_timer.function = i2c_imx_slave_timeout; 1721 1722 match = device_get_match_data(&pdev->dev); 1723 if (match) 1724 i2c_imx->hwdata = match; 1725 else 1726 i2c_imx->hwdata = (struct imx_i2c_hwdata *) 1727 platform_get_device_id(pdev)->driver_data; 1728 1729 /* Setup i2c_imx driver structure */ 1730 strscpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); 1731 i2c_imx->adapter.owner = THIS_MODULE; 1732 i2c_imx->adapter.algo = &i2c_imx_algo; 1733 i2c_imx->adapter.dev.parent = &pdev->dev; 1734 i2c_imx->adapter.nr = pdev->id; 1735 i2c_imx->adapter.dev.of_node = pdev->dev.of_node; 1736 i2c_imx->base = base; 1737 ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev)); 1738 1739 /* Get I2C clock */ 1740 i2c_imx->clk = devm_clk_get_enabled(&pdev->dev, NULL); 1741 if (IS_ERR(i2c_imx->clk)) 1742 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_imx->clk), 1743 "can't get I2C clock\n"); 1744 1745 /* Init queue */ 1746 init_waitqueue_head(&i2c_imx->queue); 1747 1748 /* Set up adapter data */ 1749 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); 1750 1751 /* Set up platform driver data */ 1752 platform_set_drvdata(pdev, i2c_imx); 1753 1754 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT); 1755 pm_runtime_use_autosuspend(&pdev->dev); 1756 pm_runtime_set_active(&pdev->dev); 1757 pm_runtime_enable(&pdev->dev); 1758 1759 ret = pm_runtime_get_sync(&pdev->dev); 1760 if (ret < 0) 1761 goto rpm_disable; 1762 1763 /* Request IRQ */ 1764 ret = request_irq(irq, i2c_imx_isr, IRQF_SHARED, pdev->name, i2c_imx); 1765 if (ret) { 1766 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 1767 goto rpm_disable; 1768 } 1769 1770 /* 1771 * We use the single-master property for backward compatibility. 1772 * By default multi master mode is enabled. 1773 */ 1774 i2c_imx->multi_master = !of_property_read_bool(pdev->dev.of_node, "single-master"); 1775 1776 /* Set up clock divider */ 1777 i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ; 1778 ret = of_property_read_u32(pdev->dev.of_node, 1779 "clock-frequency", &i2c_imx->bitrate); 1780 if (ret < 0 && pdata && pdata->bitrate) 1781 i2c_imx->bitrate = pdata->bitrate; 1782 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call; 1783 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb); 1784 i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk)); 1785 1786 i2c_imx_reset_regs(i2c_imx); 1787 1788 /* Init optional bus recovery function */ 1789 ret = i2c_imx_init_recovery_info(i2c_imx, pdev); 1790 /* Give it another chance if pinctrl used is not ready yet */ 1791 if (ret == -EPROBE_DEFER) 1792 goto clk_notifier_unregister; 1793 1794 /* Add I2C adapter */ 1795 ret = i2c_add_numbered_adapter(&i2c_imx->adapter); 1796 if (ret < 0) 1797 goto clk_notifier_unregister; 1798 1799 pm_runtime_mark_last_busy(&pdev->dev); 1800 pm_runtime_put_autosuspend(&pdev->dev); 1801 1802 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq); 1803 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res); 1804 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 1805 i2c_imx->adapter.name); 1806 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 1807 1808 /* Init DMA config if supported */ 1809 i2c_imx_dma_request(i2c_imx, phy_addr); 1810 1811 return 0; /* Return OK */ 1812 1813 clk_notifier_unregister: 1814 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1815 free_irq(irq, i2c_imx); 1816 rpm_disable: 1817 pm_runtime_put_noidle(&pdev->dev); 1818 pm_runtime_disable(&pdev->dev); 1819 pm_runtime_set_suspended(&pdev->dev); 1820 pm_runtime_dont_use_autosuspend(&pdev->dev); 1821 return ret; 1822 } 1823 1824 static void i2c_imx_remove(struct platform_device *pdev) 1825 { 1826 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 1827 int irq, ret; 1828 1829 ret = pm_runtime_get_sync(&pdev->dev); 1830 1831 hrtimer_cancel(&i2c_imx->slave_timer); 1832 1833 /* remove adapter */ 1834 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 1835 i2c_del_adapter(&i2c_imx->adapter); 1836 1837 if (i2c_imx->dma) 1838 i2c_imx_dma_free(i2c_imx); 1839 1840 if (ret >= 0) { 1841 /* setup chip registers to defaults */ 1842 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 1843 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); 1844 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); 1845 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); 1846 } 1847 1848 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1849 irq = platform_get_irq(pdev, 0); 1850 if (irq >= 0) 1851 free_irq(irq, i2c_imx); 1852 1853 pm_runtime_put_noidle(&pdev->dev); 1854 pm_runtime_disable(&pdev->dev); 1855 } 1856 1857 static int i2c_imx_runtime_suspend(struct device *dev) 1858 { 1859 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1860 1861 clk_disable(i2c_imx->clk); 1862 1863 return 0; 1864 } 1865 1866 static int i2c_imx_runtime_resume(struct device *dev) 1867 { 1868 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1869 int ret; 1870 1871 ret = clk_enable(i2c_imx->clk); 1872 if (ret) 1873 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret); 1874 1875 return ret; 1876 } 1877 1878 static const struct dev_pm_ops i2c_imx_pm_ops = { 1879 RUNTIME_PM_OPS(i2c_imx_runtime_suspend, i2c_imx_runtime_resume, NULL) 1880 }; 1881 1882 static struct platform_driver i2c_imx_driver = { 1883 .probe = i2c_imx_probe, 1884 .remove = i2c_imx_remove, 1885 .driver = { 1886 .name = DRIVER_NAME, 1887 .pm = pm_ptr(&i2c_imx_pm_ops), 1888 .of_match_table = i2c_imx_dt_ids, 1889 .acpi_match_table = i2c_imx_acpi_ids, 1890 }, 1891 .id_table = imx_i2c_devtype, 1892 }; 1893 1894 static int __init i2c_adap_imx_init(void) 1895 { 1896 return platform_driver_register(&i2c_imx_driver); 1897 } 1898 subsys_initcall(i2c_adap_imx_init); 1899 1900 static void __exit i2c_adap_imx_exit(void) 1901 { 1902 platform_driver_unregister(&i2c_imx_driver); 1903 } 1904 module_exit(i2c_adap_imx_exit); 1905 1906 MODULE_LICENSE("GPL"); 1907 MODULE_AUTHOR("Darius Augulis"); 1908 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); 1909 MODULE_ALIAS("platform:" DRIVER_NAME); 1910