1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2002 Motorola GSG-China 4 * 5 * Author: 6 * Darius Augulis, Teltonika Inc. 7 * 8 * Desc.: 9 * Implementation of I2C Adapter/Algorithm Driver 10 * for I2C Bus integrated in Freescale i.MX/MXC processors 11 * 12 * Derived from Motorola GSG China I2C example driver 13 * 14 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de 15 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de 16 * Copyright (C) 2007 RightHand Technologies, Inc. 17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 18 * 19 * Copyright 2013 Freescale Semiconductor, Inc. 20 * Copyright 2020, 2024 NXP 21 * 22 */ 23 24 #include <linux/acpi.h> 25 #include <linux/clk.h> 26 #include <linux/completion.h> 27 #include <linux/delay.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/dmaengine.h> 30 #include <linux/dmapool.h> 31 #include <linux/err.h> 32 #include <linux/errno.h> 33 #include <linux/gpio/consumer.h> 34 #include <linux/i2c.h> 35 #include <linux/init.h> 36 #include <linux/interrupt.h> 37 #include <linux/io.h> 38 #include <linux/iopoll.h> 39 #include <linux/kernel.h> 40 #include <linux/spinlock.h> 41 #include <linux/hrtimer.h> 42 #include <linux/module.h> 43 #include <linux/of.h> 44 #include <linux/of_dma.h> 45 #include <linux/pinctrl/consumer.h> 46 #include <linux/platform_data/i2c-imx.h> 47 #include <linux/platform_device.h> 48 #include <linux/pm_runtime.h> 49 #include <linux/sched.h> 50 #include <linux/slab.h> 51 52 /* This will be the driver name the kernel reports */ 53 #define DRIVER_NAME "imx-i2c" 54 55 #define I2C_IMX_CHECK_DELAY 30000 /* Time to check for bus idle, in NS */ 56 57 /* 58 * Enable DMA if transfer byte size is bigger than this threshold. 59 * As the hardware request, it must bigger than 4 bytes.\ 60 * I have set '16' here, maybe it's not the best but I think it's 61 * the appropriate. 62 */ 63 #define DMA_THRESHOLD 16 64 #define DMA_TIMEOUT 1000 65 66 /* IMX I2C registers: 67 * the I2C register offset is different between SoCs, 68 * to provide support for all these chips, split the 69 * register offset into a fixed base address and a 70 * variable shift value, then the full register offset 71 * will be calculated by 72 * reg_off = ( reg_base_addr << reg_shift) 73 */ 74 #define IMX_I2C_IADR 0x00 /* i2c slave address */ 75 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ 76 #define IMX_I2C_I2CR 0x02 /* i2c control */ 77 #define IMX_I2C_I2SR 0x03 /* i2c status */ 78 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */ 79 80 /* 81 * All of the layerscape series SoCs support IBIC register. 82 */ 83 #define IMX_I2C_IBIC 0x05 /* i2c bus interrupt config */ 84 85 #define IMX_I2C_REGSHIFT 2 86 #define VF610_I2C_REGSHIFT 0 87 #define S32G_I2C_REGSHIFT 0 88 89 /* Bits of IMX I2C registers */ 90 #define I2SR_RXAK 0x01 91 #define I2SR_IIF 0x02 92 #define I2SR_SRW 0x04 93 #define I2SR_IAL 0x10 94 #define I2SR_IBB 0x20 95 #define I2SR_IAAS 0x40 96 #define I2SR_ICF 0x80 97 #define I2CR_DMAEN 0x02 98 #define I2CR_RSTA 0x04 99 #define I2CR_TXAK 0x08 100 #define I2CR_MTX 0x10 101 #define I2CR_MSTA 0x20 102 #define I2CR_IIEN 0x40 103 #define I2CR_IEN 0x80 104 #define IBIC_BIIE 0x80 /* Bus idle interrupt enable */ 105 106 /* register bits different operating codes definition: 107 * 1) I2SR: Interrupt flags clear operation differ between SoCs: 108 * - write zero to clear(w0c) INT flag on i.MX, 109 * - but write one to clear(w1c) INT flag on Vybrid. 110 * 2) I2CR: I2C module enable operation also differ between SoCs: 111 * - set I2CR_IEN bit enable the module on i.MX, 112 * - but clear I2CR_IEN bit enable the module on Vybrid. 113 */ 114 #define I2SR_CLR_OPCODE_W0C 0x0 115 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) 116 #define I2CR_IEN_OPCODE_0 0x0 117 #define I2CR_IEN_OPCODE_1 I2CR_IEN 118 119 #define I2C_PM_TIMEOUT 10 /* ms */ 120 121 /* 122 * sorted list of clock divider, register value pairs 123 * taken from table 26-5, p.26-9, Freescale i.MX 124 * Integrated Portable System Processor Reference Manual 125 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 126 * 127 * Duplicated divider values removed from list 128 */ 129 struct imx_i2c_clk_pair { 130 u16 div; 131 u16 val; 132 }; 133 134 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = { 135 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 136 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 137 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 138 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 139 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 140 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 141 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 142 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 143 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 144 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 145 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 146 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 147 { 3072, 0x1E }, { 3840, 0x1F } 148 }; 149 150 /* Vybrid VF610 clock divider, register value pairs */ 151 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = { 152 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 153 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 154 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 155 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 156 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 157 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 158 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 159 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 160 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 161 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 162 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 163 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 164 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 165 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 166 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 167 }; 168 169 /* S32G2/S32G3 clock divider, register value pairs */ 170 static struct imx_i2c_clk_pair s32g2_i2c_clk_div[] = { 171 { 34, 0x00 }, { 36, 0x01 }, { 38, 0x02 }, { 40, 0x03 }, 172 { 42, 0x04 }, { 44, 0x05 }, { 46, 0x06 }, { 48, 0x09 }, 173 { 52, 0x0A }, { 54, 0x07 }, { 56, 0x0B }, { 60, 0x0C }, 174 { 64, 0x0D }, { 68, 0x40 }, { 72, 0x0E }, { 76, 0x42 }, 175 { 80, 0x12 }, { 84, 0x0F }, { 88, 0x13 }, { 96, 0x14 }, 176 { 104, 0x15 }, { 108, 0x47 }, { 112, 0x19 }, { 120, 0x16 }, 177 { 128, 0x1A }, { 136, 0x80 }, { 144, 0x17 }, { 152, 0x82 }, 178 { 160, 0x1C }, { 168, 0x84 }, { 176, 0x1D }, { 192, 0x21 }, 179 { 208, 0x1E }, { 216, 0x87 }, { 224, 0x22 }, { 240, 0x56 }, 180 { 256, 0x1F }, { 288, 0x24 }, { 320, 0x25 }, { 336, 0x8F }, 181 { 352, 0x93 }, { 356, 0x5D }, { 358, 0x98 }, { 384, 0x26 }, 182 { 416, 0x56 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 183 { 576, 0x2C }, { 640, 0x2D }, { 704, 0x9D }, { 768, 0x2E }, 184 { 832, 0x9D }, { 896, 0x32 }, { 960, 0x2F }, { 1024, 0x33 }, 185 { 1152, 0x34 }, { 1280, 0x35 }, { 1536, 0x36 }, { 1792, 0x3A }, 186 { 1920, 0x37 }, { 2048, 0x3B }, { 2304, 0x74 }, { 2560, 0x3D }, 187 { 3072, 0x3E }, { 3584, 0x7A }, { 3840, 0x3F }, { 4096, 0x7B }, 188 { 4608, 0x7C }, { 5120, 0x7D }, { 6144, 0x7E }, { 7168, 0xBA }, 189 { 7680, 0x7F }, { 8192, 0xBB }, { 9216, 0xBC }, { 10240, 0xBD }, 190 { 12288, 0xBE }, { 15360, 0xBF }, 191 }; 192 193 enum imx_i2c_type { 194 IMX1_I2C, 195 IMX21_I2C, 196 S32G_I2C, 197 VF610_I2C, 198 }; 199 200 struct imx_i2c_hwdata { 201 enum imx_i2c_type devtype; 202 unsigned int regshift; 203 struct imx_i2c_clk_pair *clk_div; 204 unsigned int ndivs; 205 unsigned int i2sr_clr_opcode; 206 unsigned int i2cr_ien_opcode; 207 /* 208 * Errata ERR007805 or e7805: 209 * I2C: When the I2C clock speed is configured for 400 kHz, 210 * the SCL low period violates the I2C spec of 1.3 uS min. 211 */ 212 bool has_err007805; 213 }; 214 215 struct imx_i2c_dma { 216 struct dma_chan *chan_tx; 217 struct dma_chan *chan_rx; 218 struct dma_chan *chan_using; 219 struct completion cmd_complete; 220 dma_addr_t dma_buf; 221 unsigned int dma_len; 222 enum dma_transfer_direction dma_transfer_dir; 223 enum dma_data_direction dma_data_dir; 224 }; 225 226 enum imx_i2c_state { 227 IMX_I2C_STATE_DONE, 228 IMX_I2C_STATE_FAILED, 229 IMX_I2C_STATE_WRITE, 230 IMX_I2C_STATE_DMA, 231 IMX_I2C_STATE_READ, 232 IMX_I2C_STATE_READ_CONTINUE, 233 IMX_I2C_STATE_READ_BLOCK_DATA, 234 IMX_I2C_STATE_READ_BLOCK_DATA_LEN, 235 }; 236 237 struct imx_i2c_struct { 238 struct i2c_adapter adapter; 239 struct clk *clk; 240 struct notifier_block clk_change_nb; 241 void __iomem *base; 242 wait_queue_head_t queue; 243 unsigned long i2csr; 244 unsigned int disable_delay; 245 int stopped; 246 unsigned int ifdr; /* IMX_I2C_IFDR */ 247 unsigned int cur_clk; 248 unsigned int bitrate; 249 const struct imx_i2c_hwdata *hwdata; 250 struct i2c_bus_recovery_info rinfo; 251 252 struct imx_i2c_dma *dma; 253 struct i2c_client *slave; 254 enum i2c_slave_event last_slave_event; 255 256 struct i2c_msg *msg; 257 unsigned int msg_buf_idx; 258 int isr_result; 259 bool is_lastmsg; 260 enum imx_i2c_state state; 261 262 bool multi_master; 263 264 /* For checking slave events. */ 265 spinlock_t slave_lock; 266 struct hrtimer slave_timer; 267 }; 268 269 static const struct imx_i2c_hwdata imx1_i2c_hwdata = { 270 .devtype = IMX1_I2C, 271 .regshift = IMX_I2C_REGSHIFT, 272 .clk_div = imx_i2c_clk_div, 273 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 274 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 275 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 276 277 }; 278 279 static const struct imx_i2c_hwdata imx21_i2c_hwdata = { 280 .devtype = IMX21_I2C, 281 .regshift = IMX_I2C_REGSHIFT, 282 .clk_div = imx_i2c_clk_div, 283 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 284 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 285 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 286 287 }; 288 289 static const struct imx_i2c_hwdata imx6_i2c_hwdata = { 290 .devtype = IMX21_I2C, 291 .regshift = IMX_I2C_REGSHIFT, 292 .clk_div = imx_i2c_clk_div, 293 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 294 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 295 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 296 .has_err007805 = true, 297 }; 298 299 static struct imx_i2c_hwdata vf610_i2c_hwdata = { 300 .devtype = VF610_I2C, 301 .regshift = VF610_I2C_REGSHIFT, 302 .clk_div = vf610_i2c_clk_div, 303 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div), 304 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 305 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 306 }; 307 308 static const struct imx_i2c_hwdata s32g2_i2c_hwdata = { 309 .devtype = S32G_I2C, 310 .regshift = S32G_I2C_REGSHIFT, 311 .clk_div = s32g2_i2c_clk_div, 312 .ndivs = ARRAY_SIZE(s32g2_i2c_clk_div), 313 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 314 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 315 }; 316 317 static const struct platform_device_id imx_i2c_devtype[] = { 318 { 319 .name = "imx1-i2c", 320 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata, 321 }, { 322 .name = "imx21-i2c", 323 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata, 324 }, { 325 /* sentinel */ 326 } 327 }; 328 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); 329 330 static const struct of_device_id i2c_imx_dt_ids[] = { 331 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, }, 332 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, }, 333 { .compatible = "fsl,imx6q-i2c", .data = &imx6_i2c_hwdata, }, 334 { .compatible = "fsl,imx6sl-i2c", .data = &imx6_i2c_hwdata, }, 335 { .compatible = "fsl,imx6sll-i2c", .data = &imx6_i2c_hwdata, }, 336 { .compatible = "fsl,imx6sx-i2c", .data = &imx6_i2c_hwdata, }, 337 { .compatible = "fsl,imx6ul-i2c", .data = &imx6_i2c_hwdata, }, 338 { .compatible = "fsl,imx7d-i2c", .data = &imx6_i2c_hwdata, }, 339 { .compatible = "fsl,imx7s-i2c", .data = &imx6_i2c_hwdata, }, 340 { .compatible = "fsl,imx8mm-i2c", .data = &imx6_i2c_hwdata, }, 341 { .compatible = "fsl,imx8mn-i2c", .data = &imx6_i2c_hwdata, }, 342 { .compatible = "fsl,imx8mp-i2c", .data = &imx6_i2c_hwdata, }, 343 { .compatible = "fsl,imx8mq-i2c", .data = &imx6_i2c_hwdata, }, 344 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, }, 345 { .compatible = "nxp,s32g2-i2c", .data = &s32g2_i2c_hwdata, }, 346 { /* sentinel */ } 347 }; 348 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); 349 350 static const struct acpi_device_id i2c_imx_acpi_ids[] = { 351 {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata}, 352 { } 353 }; 354 MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids); 355 356 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) 357 { 358 return i2c_imx->hwdata->devtype == IMX1_I2C; 359 } 360 361 static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx) 362 { 363 return i2c_imx->hwdata->devtype == VF610_I2C; 364 } 365 366 static inline void imx_i2c_write_reg(unsigned int val, 367 struct imx_i2c_struct *i2c_imx, unsigned int reg) 368 { 369 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 370 } 371 372 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, 373 unsigned int reg) 374 { 375 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 376 } 377 378 static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits) 379 { 380 unsigned int temp; 381 382 /* 383 * i2sr_clr_opcode is the value to clear all interrupts. Here we want to 384 * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits> 385 * toggled. This is required because i.MX needs W0C and Vybrid uses W1C. 386 */ 387 temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits; 388 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 389 } 390 391 /* Set up i2c controller register and i2c status register to default value. */ 392 static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx) 393 { 394 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 395 i2c_imx, IMX_I2C_I2CR); 396 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 397 } 398 399 /* Functions for DMA support */ 400 static int i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, dma_addr_t phy_addr) 401 { 402 struct imx_i2c_dma *dma; 403 struct dma_slave_config dma_sconfig; 404 struct device *dev = i2c_imx->adapter.dev.parent; 405 int ret; 406 407 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 408 if (!dma) 409 return -ENOMEM; 410 411 dma->chan_tx = dma_request_chan(dev, "tx"); 412 if (IS_ERR(dma->chan_tx)) { 413 ret = PTR_ERR(dma->chan_tx); 414 if (ret != -ENODEV && ret != -EPROBE_DEFER) 415 dev_err(dev, "can't request DMA tx channel (%d)\n", ret); 416 goto fail_al; 417 } 418 419 dma_sconfig.dst_addr = phy_addr + 420 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 421 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 422 dma_sconfig.dst_maxburst = 1; 423 dma_sconfig.direction = DMA_MEM_TO_DEV; 424 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig); 425 if (ret < 0) { 426 dev_err(dev, "can't configure tx channel (%d)\n", ret); 427 goto fail_tx; 428 } 429 430 dma->chan_rx = dma_request_chan(dev, "rx"); 431 if (IS_ERR(dma->chan_rx)) { 432 ret = PTR_ERR(dma->chan_rx); 433 if (ret != -ENODEV && ret != -EPROBE_DEFER) 434 dev_err(dev, "can't request DMA rx channel (%d)\n", ret); 435 goto fail_tx; 436 } 437 438 dma_sconfig.src_addr = phy_addr + 439 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 440 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 441 dma_sconfig.src_maxburst = 1; 442 dma_sconfig.direction = DMA_DEV_TO_MEM; 443 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig); 444 if (ret < 0) { 445 dev_err(dev, "can't configure rx channel (%d)\n", ret); 446 goto fail_rx; 447 } 448 449 i2c_imx->dma = dma; 450 init_completion(&dma->cmd_complete); 451 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n", 452 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); 453 454 return 0; 455 456 fail_rx: 457 dma_release_channel(dma->chan_rx); 458 fail_tx: 459 dma_release_channel(dma->chan_tx); 460 fail_al: 461 devm_kfree(dev, dma); 462 463 return ret; 464 } 465 466 static void i2c_imx_dma_callback(void *arg) 467 { 468 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg; 469 struct imx_i2c_dma *dma = i2c_imx->dma; 470 471 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf, 472 dma->dma_len, dma->dma_data_dir); 473 complete(&dma->cmd_complete); 474 } 475 476 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx, 477 struct i2c_msg *msgs) 478 { 479 struct imx_i2c_dma *dma = i2c_imx->dma; 480 struct dma_async_tx_descriptor *txdesc; 481 struct device *dev = &i2c_imx->adapter.dev; 482 struct device *chan_dev = dma->chan_using->device->dev; 483 484 dma->dma_buf = dma_map_single(chan_dev, msgs->buf, 485 dma->dma_len, dma->dma_data_dir); 486 if (dma_mapping_error(chan_dev, dma->dma_buf)) { 487 dev_err(dev, "DMA mapping failed\n"); 488 goto err_map; 489 } 490 491 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf, 492 dma->dma_len, dma->dma_transfer_dir, 493 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 494 if (!txdesc) { 495 dev_err(dev, "Not able to get desc for DMA xfer\n"); 496 goto err_desc; 497 } 498 499 reinit_completion(&dma->cmd_complete); 500 txdesc->callback = i2c_imx_dma_callback; 501 txdesc->callback_param = i2c_imx; 502 if (dma_submit_error(dmaengine_submit(txdesc))) { 503 dev_err(dev, "DMA submit failed\n"); 504 goto err_submit; 505 } 506 507 dma_async_issue_pending(dma->chan_using); 508 return 0; 509 510 err_submit: 511 dmaengine_terminate_sync(dma->chan_using); 512 err_desc: 513 dma_unmap_single(chan_dev, dma->dma_buf, 514 dma->dma_len, dma->dma_data_dir); 515 err_map: 516 return -EINVAL; 517 } 518 519 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx) 520 { 521 struct imx_i2c_dma *dma = i2c_imx->dma; 522 523 dma->dma_buf = 0; 524 dma->dma_len = 0; 525 526 dma_release_channel(dma->chan_tx); 527 dma->chan_tx = NULL; 528 529 dma_release_channel(dma->chan_rx); 530 dma->chan_rx = NULL; 531 532 dma->chan_using = NULL; 533 } 534 535 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic) 536 { 537 bool multi_master = i2c_imx->multi_master; 538 unsigned long orig_jiffies = jiffies; 539 unsigned int temp; 540 541 while (1) { 542 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 543 544 /* check for arbitration lost */ 545 if (multi_master && (temp & I2SR_IAL)) { 546 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 547 return -EAGAIN; 548 } 549 550 if (for_busy && (!multi_master || (temp & I2SR_IBB))) { 551 i2c_imx->stopped = 0; 552 break; 553 } 554 if (!for_busy && !(temp & I2SR_IBB)) { 555 i2c_imx->stopped = 1; 556 break; 557 } 558 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 559 dev_dbg(&i2c_imx->adapter.dev, 560 "<%s> I2C bus is busy\n", __func__); 561 return -ETIMEDOUT; 562 } 563 if (atomic) 564 udelay(100); 565 else 566 schedule(); 567 } 568 569 return 0; 570 } 571 572 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic) 573 { 574 if (atomic) { 575 void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift); 576 unsigned int regval; 577 578 /* 579 * The formula for the poll timeout is documented in the RM 580 * Rev.5 on page 1878: 581 * T_min = 10/F_scl 582 * Set the value hard as it is done for the non-atomic use-case. 583 * Use 10 kHz for the calculation since this is the minimum 584 * allowed SMBus frequency. Also add an offset of 100us since it 585 * turned out that the I2SR_IIF bit isn't set correctly within 586 * the minimum timeout in polling mode. 587 */ 588 readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100); 589 i2c_imx->i2csr = regval; 590 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 591 } else { 592 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); 593 } 594 595 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { 596 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); 597 return -ETIMEDOUT; 598 } 599 600 /* In multi-master mode check for arbitration lost */ 601 if (i2c_imx->multi_master && (i2c_imx->i2csr & I2SR_IAL)) { 602 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__); 603 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 604 605 i2c_imx->i2csr = 0; 606 return -EAGAIN; 607 } 608 609 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); 610 i2c_imx->i2csr = 0; 611 return 0; 612 } 613 614 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) 615 { 616 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 617 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); 618 return -ENXIO; /* No ACK */ 619 } 620 621 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); 622 return 0; 623 } 624 625 static int i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 626 unsigned int i2c_clk_rate) 627 { 628 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; 629 unsigned int div; 630 int i; 631 632 if (i2c_imx->hwdata->has_err007805 && i2c_imx->bitrate > 384000) { 633 dev_dbg(&i2c_imx->adapter.dev, 634 "SoC errata ERR007805 or e7805 applies, bus frequency limited from %d Hz to 384000 Hz.\n", 635 i2c_imx->bitrate); 636 i2c_imx->bitrate = 384000; 637 } 638 639 /* Divider value calculation */ 640 if (i2c_imx->cur_clk == i2c_clk_rate) 641 return 0; 642 643 /* Keep the denominator of the following program always NOT equal to 0. */ 644 if (!(i2c_clk_rate / 2)) 645 return -EINVAL; 646 647 i2c_imx->cur_clk = i2c_clk_rate; 648 649 div = DIV_ROUND_UP(i2c_clk_rate, i2c_imx->bitrate); 650 if (div < i2c_clk_div[0].div) 651 i = 0; 652 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) 653 i = i2c_imx->hwdata->ndivs - 1; 654 else 655 for (i = 0; i2c_clk_div[i].div < div; i++) 656 ; 657 658 /* Store divider value */ 659 i2c_imx->ifdr = i2c_clk_div[i].val; 660 661 /* 662 * There dummy delay is calculated. 663 * It should be about one I2C clock period long. 664 * This delay is used in I2C bus disable function 665 * to fix chip hardware bug. 666 */ 667 i2c_imx->disable_delay = DIV_ROUND_UP(500000U * i2c_clk_div[i].div, 668 i2c_clk_rate / 2); 669 670 #ifdef CONFIG_I2C_DEBUG_BUS 671 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n", 672 i2c_clk_rate, div); 673 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n", 674 i2c_clk_div[i].val, i2c_clk_div[i].div); 675 #endif 676 677 return 0; 678 } 679 680 static int i2c_imx_clk_notifier_call(struct notifier_block *nb, 681 unsigned long action, void *data) 682 { 683 struct clk_notifier_data *ndata = data; 684 struct imx_i2c_struct *i2c_imx = container_of(nb, 685 struct imx_i2c_struct, 686 clk_change_nb); 687 int ret = 0; 688 689 if (action & POST_RATE_CHANGE) 690 ret = i2c_imx_set_clk(i2c_imx, ndata->new_rate); 691 692 return notifier_from_errno(ret); 693 } 694 695 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic) 696 { 697 unsigned int temp = 0; 698 int result; 699 700 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); 701 /* Enable I2C controller */ 702 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 703 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR); 704 705 /* Wait controller to be stable */ 706 if (atomic) 707 udelay(50); 708 else 709 usleep_range(50, 150); 710 711 /* Start I2C transaction */ 712 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 713 temp |= I2CR_MSTA; 714 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 715 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 716 if (result) 717 return result; 718 719 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; 720 if (atomic) 721 temp &= ~I2CR_IIEN; /* Disable interrupt */ 722 723 temp &= ~I2CR_DMAEN; 724 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 725 return result; 726 } 727 728 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic) 729 { 730 unsigned int temp = 0; 731 732 if (!i2c_imx->stopped) { 733 /* Stop I2C transaction */ 734 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 735 if (!(temp & I2CR_MSTA)) 736 i2c_imx->stopped = 1; 737 temp &= ~(I2CR_MSTA | I2CR_MTX); 738 if (i2c_imx->dma) 739 temp &= ~I2CR_DMAEN; 740 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 741 } 742 if (is_imx1_i2c(i2c_imx)) { 743 /* 744 * This delay caused by an i.MXL hardware bug. 745 * If no (or too short) delay, no "STOP" bit will be generated. 746 */ 747 udelay(i2c_imx->disable_delay); 748 } 749 750 if (!i2c_imx->stopped) 751 i2c_imx_bus_busy(i2c_imx, 0, atomic); 752 753 /* Disable I2C controller */ 754 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN; 755 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 756 } 757 758 /* 759 * Enable bus idle interrupts 760 * Note: IBIC register will be cleared after disabled i2c module. 761 * All of layerscape series SoCs support IBIC register. 762 */ 763 static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx) 764 { 765 if (is_vf610_i2c(i2c_imx)) { 766 unsigned int temp; 767 768 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC); 769 temp |= IBIC_BIIE; 770 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC); 771 } 772 } 773 774 static void i2c_imx_slave_event(struct imx_i2c_struct *i2c_imx, 775 enum i2c_slave_event event, u8 *val) 776 { 777 i2c_slave_event(i2c_imx->slave, event, val); 778 i2c_imx->last_slave_event = event; 779 } 780 781 static void i2c_imx_slave_finish_op(struct imx_i2c_struct *i2c_imx) 782 { 783 u8 val = 0; 784 785 while (i2c_imx->last_slave_event != I2C_SLAVE_STOP) { 786 switch (i2c_imx->last_slave_event) { 787 case I2C_SLAVE_READ_REQUESTED: 788 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_READ_PROCESSED, 789 &val); 790 break; 791 792 case I2C_SLAVE_WRITE_REQUESTED: 793 case I2C_SLAVE_READ_PROCESSED: 794 case I2C_SLAVE_WRITE_RECEIVED: 795 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_STOP, &val); 796 break; 797 798 case I2C_SLAVE_STOP: 799 break; 800 } 801 } 802 } 803 804 /* Returns true if the timer should be restarted, false if not. */ 805 static irqreturn_t i2c_imx_slave_handle(struct imx_i2c_struct *i2c_imx, 806 unsigned int status, unsigned int ctl) 807 { 808 u8 value = 0; 809 810 if (status & I2SR_IAL) { /* Arbitration lost */ 811 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 812 if (!(status & I2SR_IAAS)) 813 return IRQ_HANDLED; 814 } 815 816 if (!(status & I2SR_IBB)) { 817 /* No master on the bus, that could mean a stop condition. */ 818 i2c_imx_slave_finish_op(i2c_imx); 819 return IRQ_HANDLED; 820 } 821 822 if (!(status & I2SR_ICF)) 823 /* Data transfer still in progress, ignore this. */ 824 goto out; 825 826 if (status & I2SR_IAAS) { /* Addressed as a slave */ 827 i2c_imx_slave_finish_op(i2c_imx); 828 if (status & I2SR_SRW) { /* Master wants to read from us*/ 829 dev_dbg(&i2c_imx->adapter.dev, "read requested"); 830 i2c_imx_slave_event(i2c_imx, 831 I2C_SLAVE_READ_REQUESTED, &value); 832 833 /* Slave transmit */ 834 ctl |= I2CR_MTX; 835 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 836 837 /* Send data */ 838 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 839 } else { /* Master wants to write to us */ 840 dev_dbg(&i2c_imx->adapter.dev, "write requested"); 841 i2c_imx_slave_event(i2c_imx, 842 I2C_SLAVE_WRITE_REQUESTED, &value); 843 844 /* Slave receive */ 845 ctl &= ~I2CR_MTX; 846 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 847 /* Dummy read */ 848 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 849 } 850 } else if (!(ctl & I2CR_MTX)) { /* Receive mode */ 851 value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 852 i2c_imx_slave_event(i2c_imx, 853 I2C_SLAVE_WRITE_RECEIVED, &value); 854 } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */ 855 ctl |= I2CR_MTX; 856 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 857 858 i2c_imx_slave_event(i2c_imx, 859 I2C_SLAVE_READ_PROCESSED, &value); 860 861 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 862 } else { /* Transmit mode received NAK, operation is done */ 863 ctl &= ~I2CR_MTX; 864 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 865 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 866 867 /* flag the last byte as processed */ 868 i2c_imx_slave_event(i2c_imx, 869 I2C_SLAVE_READ_PROCESSED, &value); 870 871 i2c_imx_slave_finish_op(i2c_imx); 872 return IRQ_HANDLED; 873 } 874 875 out: 876 /* 877 * No need to check the return value here. If it returns 0 or 878 * 1, then everything is fine. If it returns -1, then the 879 * timer is running in the handler. This will still work, 880 * though it may be redone (or already have been done) by the 881 * timer function. 882 */ 883 hrtimer_try_to_cancel(&i2c_imx->slave_timer); 884 hrtimer_forward_now(&i2c_imx->slave_timer, I2C_IMX_CHECK_DELAY); 885 hrtimer_restart(&i2c_imx->slave_timer); 886 return IRQ_HANDLED; 887 } 888 889 static enum hrtimer_restart i2c_imx_slave_timeout(struct hrtimer *t) 890 { 891 struct imx_i2c_struct *i2c_imx = container_of(t, struct imx_i2c_struct, 892 slave_timer); 893 unsigned int ctl, status; 894 unsigned long flags; 895 896 spin_lock_irqsave(&i2c_imx->slave_lock, flags); 897 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 898 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 899 i2c_imx_slave_handle(i2c_imx, status, ctl); 900 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags); 901 return HRTIMER_NORESTART; 902 } 903 904 static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx) 905 { 906 int temp; 907 908 /* Set slave addr. */ 909 imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR); 910 911 i2c_imx_reset_regs(i2c_imx); 912 913 /* Enable module */ 914 temp = i2c_imx->hwdata->i2cr_ien_opcode; 915 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 916 917 /* Enable interrupt from i2c module */ 918 temp |= I2CR_IIEN; 919 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 920 921 i2c_imx_enable_bus_idle(i2c_imx); 922 } 923 924 static int i2c_imx_reg_slave(struct i2c_client *client) 925 { 926 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 927 int ret; 928 929 if (i2c_imx->slave) 930 return -EBUSY; 931 932 i2c_imx->slave = client; 933 i2c_imx->last_slave_event = I2C_SLAVE_STOP; 934 935 /* Resume */ 936 ret = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent); 937 if (ret < 0) { 938 dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller"); 939 return ret; 940 } 941 942 i2c_imx_slave_init(i2c_imx); 943 944 return 0; 945 } 946 947 static int i2c_imx_unreg_slave(struct i2c_client *client) 948 { 949 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 950 int ret; 951 952 if (!i2c_imx->slave) 953 return -EINVAL; 954 955 /* Reset slave address. */ 956 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 957 958 i2c_imx_reset_regs(i2c_imx); 959 960 i2c_imx->slave = NULL; 961 962 /* Suspend */ 963 ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent); 964 if (ret < 0) 965 dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller"); 966 967 return ret; 968 } 969 970 static inline int i2c_imx_isr_acked(struct imx_i2c_struct *i2c_imx) 971 { 972 i2c_imx->isr_result = 0; 973 974 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 975 i2c_imx->state = IMX_I2C_STATE_FAILED; 976 i2c_imx->isr_result = -ENXIO; 977 wake_up(&i2c_imx->queue); 978 } 979 980 return i2c_imx->isr_result; 981 } 982 983 static inline int i2c_imx_isr_write(struct imx_i2c_struct *i2c_imx) 984 { 985 int result; 986 987 result = i2c_imx_isr_acked(i2c_imx); 988 if (result) 989 return result; 990 991 if (i2c_imx->msg->len == i2c_imx->msg_buf_idx) 992 return 0; 993 994 imx_i2c_write_reg(i2c_imx->msg->buf[i2c_imx->msg_buf_idx++], i2c_imx, IMX_I2C_I2DR); 995 996 return 1; 997 } 998 999 static inline int i2c_imx_isr_read(struct imx_i2c_struct *i2c_imx) 1000 { 1001 int result; 1002 unsigned int temp; 1003 1004 result = i2c_imx_isr_acked(i2c_imx); 1005 if (result) 1006 return result; 1007 1008 /* setup bus to read data */ 1009 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1010 temp &= ~I2CR_MTX; 1011 if ((i2c_imx->msg->len - 1) || (i2c_imx->msg->flags & I2C_M_RECV_LEN)) 1012 temp &= ~I2CR_TXAK; 1013 1014 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1015 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 1016 1017 return 0; 1018 } 1019 1020 static inline void i2c_imx_isr_read_continue(struct imx_i2c_struct *i2c_imx) 1021 { 1022 unsigned int temp; 1023 1024 if ((i2c_imx->msg->len - 1) == i2c_imx->msg_buf_idx) { 1025 if (i2c_imx->is_lastmsg) { 1026 /* 1027 * It must generate STOP before read I2DR to prevent 1028 * controller from generating another clock cycle 1029 */ 1030 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1031 if (!(temp & I2CR_MSTA)) 1032 i2c_imx->stopped = 1; 1033 temp &= ~(I2CR_MSTA | I2CR_MTX); 1034 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1035 } else { 1036 /* 1037 * For i2c master receiver repeat restart operation like: 1038 * read -> repeat MSTA -> read/write 1039 * The controller must set MTX before read the last byte in 1040 * the first read operation, otherwise the first read cost 1041 * one extra clock cycle. 1042 */ 1043 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1044 temp |= I2CR_MTX; 1045 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1046 } 1047 } else if (i2c_imx->msg_buf_idx == (i2c_imx->msg->len - 2)) { 1048 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1049 temp |= I2CR_TXAK; 1050 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1051 } 1052 1053 i2c_imx->msg->buf[i2c_imx->msg_buf_idx++] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1054 } 1055 1056 static inline void i2c_imx_isr_read_block_data_len(struct imx_i2c_struct *i2c_imx) 1057 { 1058 u8 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1059 1060 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) { 1061 i2c_imx->isr_result = -EPROTO; 1062 i2c_imx->state = IMX_I2C_STATE_FAILED; 1063 wake_up(&i2c_imx->queue); 1064 } 1065 i2c_imx->msg->len += len; 1066 i2c_imx->msg->buf[i2c_imx->msg_buf_idx++] = len; 1067 } 1068 1069 static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned int status) 1070 { 1071 /* 1072 * This state machine handles I2C reception and transmission in non-DMA 1073 * mode. We must process all the data in the ISR to reduce the delay 1074 * between two consecutive messages. If the data is not processed in 1075 * the ISR, SMBus devices may timeout, leading to a bus error. 1076 */ 1077 switch (i2c_imx->state) { 1078 case IMX_I2C_STATE_DMA: 1079 i2c_imx->i2csr = status; 1080 wake_up(&i2c_imx->queue); 1081 break; 1082 1083 case IMX_I2C_STATE_READ: 1084 if (i2c_imx_isr_read(i2c_imx)) 1085 break; 1086 i2c_imx->state = IMX_I2C_STATE_READ_CONTINUE; 1087 break; 1088 1089 case IMX_I2C_STATE_READ_CONTINUE: 1090 i2c_imx_isr_read_continue(i2c_imx); 1091 if (i2c_imx->msg_buf_idx == i2c_imx->msg->len) { 1092 i2c_imx->state = IMX_I2C_STATE_DONE; 1093 wake_up(&i2c_imx->queue); 1094 } 1095 break; 1096 1097 case IMX_I2C_STATE_READ_BLOCK_DATA: 1098 if (i2c_imx_isr_read(i2c_imx)) 1099 break; 1100 i2c_imx->state = IMX_I2C_STATE_READ_BLOCK_DATA_LEN; 1101 break; 1102 1103 case IMX_I2C_STATE_READ_BLOCK_DATA_LEN: 1104 i2c_imx_isr_read_block_data_len(i2c_imx); 1105 i2c_imx->state = IMX_I2C_STATE_READ_CONTINUE; 1106 break; 1107 1108 case IMX_I2C_STATE_WRITE: 1109 if (i2c_imx_isr_write(i2c_imx)) 1110 break; 1111 i2c_imx->state = IMX_I2C_STATE_DONE; 1112 wake_up(&i2c_imx->queue); 1113 break; 1114 1115 default: 1116 i2c_imx->i2csr = status; 1117 i2c_imx->state = IMX_I2C_STATE_FAILED; 1118 i2c_imx->isr_result = -EINVAL; 1119 wake_up(&i2c_imx->queue); 1120 } 1121 1122 return IRQ_HANDLED; 1123 } 1124 1125 static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 1126 { 1127 struct imx_i2c_struct *i2c_imx = dev_id; 1128 unsigned int ctl, status; 1129 unsigned long flags; 1130 1131 spin_lock_irqsave(&i2c_imx->slave_lock, flags); 1132 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1133 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1134 1135 if (status & I2SR_IIF) { 1136 i2c_imx_clear_irq(i2c_imx, I2SR_IIF); 1137 if (i2c_imx->slave) { 1138 if (!(ctl & I2CR_MSTA)) { 1139 irqreturn_t ret; 1140 1141 ret = i2c_imx_slave_handle(i2c_imx, 1142 status, ctl); 1143 spin_unlock_irqrestore(&i2c_imx->slave_lock, 1144 flags); 1145 return ret; 1146 } 1147 i2c_imx_slave_finish_op(i2c_imx); 1148 } 1149 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags); 1150 return i2c_imx_master_isr(i2c_imx, status); 1151 } 1152 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags); 1153 1154 return IRQ_NONE; 1155 } 1156 1157 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx, 1158 struct i2c_msg *msgs) 1159 { 1160 int result; 1161 unsigned long time_left; 1162 unsigned int temp = 0; 1163 unsigned long orig_jiffies = jiffies; 1164 struct imx_i2c_dma *dma = i2c_imx->dma; 1165 struct device *dev = &i2c_imx->adapter.dev; 1166 1167 i2c_imx->state = IMX_I2C_STATE_DMA; 1168 1169 dma->chan_using = dma->chan_tx; 1170 dma->dma_transfer_dir = DMA_MEM_TO_DEV; 1171 dma->dma_data_dir = DMA_TO_DEVICE; 1172 dma->dma_len = msgs->len - 1; 1173 result = i2c_imx_dma_xfer(i2c_imx, msgs); 1174 if (result) 1175 return result; 1176 1177 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1178 temp |= I2CR_DMAEN; 1179 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1180 1181 /* 1182 * Write slave address. 1183 * The first byte must be transmitted by the CPU. 1184 */ 1185 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1186 time_left = wait_for_completion_timeout( 1187 &i2c_imx->dma->cmd_complete, 1188 msecs_to_jiffies(DMA_TIMEOUT)); 1189 if (time_left == 0) { 1190 dmaengine_terminate_sync(dma->chan_using); 1191 return -ETIMEDOUT; 1192 } 1193 1194 /* Waiting for transfer complete. */ 1195 while (1) { 1196 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1197 if (temp & I2SR_ICF) 1198 break; 1199 if (time_after(jiffies, orig_jiffies + 1200 msecs_to_jiffies(DMA_TIMEOUT))) { 1201 dev_dbg(dev, "<%s> Timeout\n", __func__); 1202 return -ETIMEDOUT; 1203 } 1204 schedule(); 1205 } 1206 1207 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1208 temp &= ~I2CR_DMAEN; 1209 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1210 1211 /* The last data byte must be transferred by the CPU. */ 1212 imx_i2c_write_reg(msgs->buf[msgs->len-1], 1213 i2c_imx, IMX_I2C_I2DR); 1214 result = i2c_imx_trx_complete(i2c_imx, false); 1215 if (result) 1216 return result; 1217 1218 return i2c_imx_acked(i2c_imx); 1219 } 1220 1221 static int i2c_imx_prepare_read(struct imx_i2c_struct *i2c_imx, 1222 struct i2c_msg *msgs, bool use_dma) 1223 { 1224 int result; 1225 unsigned int temp = 0; 1226 1227 /* write slave address */ 1228 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1229 result = i2c_imx_trx_complete(i2c_imx, !use_dma); 1230 if (result) 1231 return result; 1232 result = i2c_imx_acked(i2c_imx); 1233 if (result) 1234 return result; 1235 1236 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); 1237 1238 /* setup bus to read data */ 1239 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1240 temp &= ~I2CR_MTX; 1241 1242 /* 1243 * Reset the I2CR_TXAK flag initially for SMBus block read since the 1244 * length is unknown 1245 */ 1246 if (msgs->len - 1) 1247 temp &= ~I2CR_TXAK; 1248 if (use_dma) 1249 temp |= I2CR_DMAEN; 1250 1251 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1252 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 1253 1254 return 0; 1255 } 1256 1257 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx, 1258 struct i2c_msg *msgs, bool is_lastmsg) 1259 { 1260 int result; 1261 unsigned long time_left; 1262 unsigned int temp; 1263 unsigned long orig_jiffies = jiffies; 1264 struct imx_i2c_dma *dma = i2c_imx->dma; 1265 struct device *dev = &i2c_imx->adapter.dev; 1266 1267 i2c_imx->state = IMX_I2C_STATE_DMA; 1268 1269 result = i2c_imx_prepare_read(i2c_imx, msgs, true); 1270 if (result) 1271 return result; 1272 1273 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 1274 1275 dma->chan_using = dma->chan_rx; 1276 dma->dma_transfer_dir = DMA_DEV_TO_MEM; 1277 dma->dma_data_dir = DMA_FROM_DEVICE; 1278 /* The last two data bytes must be transferred by the CPU. */ 1279 dma->dma_len = msgs->len - 2; 1280 result = i2c_imx_dma_xfer(i2c_imx, msgs); 1281 if (result) 1282 return result; 1283 1284 time_left = wait_for_completion_timeout( 1285 &i2c_imx->dma->cmd_complete, 1286 msecs_to_jiffies(DMA_TIMEOUT)); 1287 if (time_left == 0) { 1288 dmaengine_terminate_sync(dma->chan_using); 1289 return -ETIMEDOUT; 1290 } 1291 1292 /* waiting for transfer complete. */ 1293 while (1) { 1294 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1295 if (temp & I2SR_ICF) 1296 break; 1297 if (time_after(jiffies, orig_jiffies + 1298 msecs_to_jiffies(DMA_TIMEOUT))) { 1299 dev_dbg(dev, "<%s> Timeout\n", __func__); 1300 return -ETIMEDOUT; 1301 } 1302 schedule(); 1303 } 1304 1305 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1306 temp &= ~I2CR_DMAEN; 1307 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1308 1309 /* read n-1 byte data */ 1310 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1311 temp |= I2CR_TXAK; 1312 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1313 1314 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1315 /* read n byte data */ 1316 result = i2c_imx_trx_complete(i2c_imx, false); 1317 if (result) 1318 return result; 1319 1320 if (is_lastmsg) { 1321 /* 1322 * It must generate STOP before read I2DR to prevent 1323 * controller from generating another clock cycle 1324 */ 1325 dev_dbg(dev, "<%s> clear MSTA\n", __func__); 1326 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1327 if (!(temp & I2CR_MSTA)) 1328 i2c_imx->stopped = 1; 1329 temp &= ~(I2CR_MSTA | I2CR_MTX); 1330 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1331 if (!i2c_imx->stopped) 1332 i2c_imx_bus_busy(i2c_imx, 0, false); 1333 } else { 1334 /* 1335 * For i2c master receiver repeat restart operation like: 1336 * read -> repeat MSTA -> read/write 1337 * The controller must set MTX before read the last byte in 1338 * the first read operation, otherwise the first read cost 1339 * one extra clock cycle. 1340 */ 1341 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1342 temp |= I2CR_MTX; 1343 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1344 } 1345 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1346 1347 return 0; 1348 } 1349 1350 static int i2c_imx_atomic_write(struct imx_i2c_struct *i2c_imx, 1351 struct i2c_msg *msgs) 1352 { 1353 int i, result; 1354 1355 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 1356 __func__, i2c_8bit_addr_from_msg(msgs)); 1357 1358 /* write slave address */ 1359 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1360 result = i2c_imx_trx_complete(i2c_imx, true); 1361 if (result) 1362 return result; 1363 result = i2c_imx_acked(i2c_imx); 1364 if (result) 1365 return result; 1366 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); 1367 1368 /* write data */ 1369 for (i = 0; i < msgs->len; i++) { 1370 dev_dbg(&i2c_imx->adapter.dev, 1371 "<%s> write byte: B%d=0x%X\n", 1372 __func__, i, msgs->buf[i]); 1373 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); 1374 result = i2c_imx_trx_complete(i2c_imx, true); 1375 if (result) 1376 return result; 1377 result = i2c_imx_acked(i2c_imx); 1378 if (result) 1379 return result; 1380 } 1381 return 0; 1382 } 1383 1384 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) 1385 { 1386 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 1387 __func__, i2c_8bit_addr_from_msg(msgs)); 1388 1389 i2c_imx->state = IMX_I2C_STATE_WRITE; 1390 i2c_imx->msg = msgs; 1391 i2c_imx->msg_buf_idx = 0; 1392 1393 /* 1394 * By writing the device address we start the state machine in the ISR. 1395 * The ISR will report when it is done or when it fails. 1396 */ 1397 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1398 wait_event_timeout(i2c_imx->queue, 1399 i2c_imx->state == IMX_I2C_STATE_DONE || 1400 i2c_imx->state == IMX_I2C_STATE_FAILED, 1401 (msgs->len + 1) * HZ / 10); 1402 if (i2c_imx->state == IMX_I2C_STATE_FAILED) { 1403 dev_dbg(&i2c_imx->adapter.dev, "<%s> write failed with %d\n", 1404 __func__, i2c_imx->isr_result); 1405 return i2c_imx->isr_result; 1406 } 1407 if (i2c_imx->state != IMX_I2C_STATE_DONE) { 1408 dev_err(&i2c_imx->adapter.dev, "<%s> write timedout\n", __func__); 1409 return -ETIMEDOUT; 1410 } 1411 return 0; 1412 } 1413 1414 static int i2c_imx_atomic_read(struct imx_i2c_struct *i2c_imx, 1415 struct i2c_msg *msgs, bool is_lastmsg) 1416 { 1417 int i, result; 1418 unsigned int temp; 1419 int block_data = msgs->flags & I2C_M_RECV_LEN; 1420 1421 result = i2c_imx_prepare_read(i2c_imx, msgs, false); 1422 if (result) 1423 return result; 1424 1425 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 1426 1427 /* read data */ 1428 for (i = 0; i < msgs->len; i++) { 1429 u8 len = 0; 1430 1431 result = i2c_imx_trx_complete(i2c_imx, true); 1432 if (result) 1433 return result; 1434 /* 1435 * First byte is the length of remaining packet 1436 * in the SMBus block data read. Add it to 1437 * msgs->len. 1438 */ 1439 if ((!i) && block_data) { 1440 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1441 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) 1442 return -EPROTO; 1443 dev_dbg(&i2c_imx->adapter.dev, 1444 "<%s> read length: 0x%X\n", 1445 __func__, len); 1446 msgs->len += len; 1447 } 1448 if (i == (msgs->len - 1)) { 1449 if (is_lastmsg) { 1450 /* 1451 * It must generate STOP before read I2DR to prevent 1452 * controller from generating another clock cycle 1453 */ 1454 dev_dbg(&i2c_imx->adapter.dev, 1455 "<%s> clear MSTA\n", __func__); 1456 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1457 if (!(temp & I2CR_MSTA)) 1458 i2c_imx->stopped = 1; 1459 temp &= ~(I2CR_MSTA | I2CR_MTX); 1460 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1461 if (!i2c_imx->stopped) 1462 i2c_imx_bus_busy(i2c_imx, 0, true); 1463 } else { 1464 /* 1465 * For i2c master receiver repeat restart operation like: 1466 * read -> repeat MSTA -> read/write 1467 * The controller must set MTX before read the last byte in 1468 * the first read operation, otherwise the first read cost 1469 * one extra clock cycle. 1470 */ 1471 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1472 temp |= I2CR_MTX; 1473 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1474 } 1475 } else if (i == (msgs->len - 2)) { 1476 dev_dbg(&i2c_imx->adapter.dev, 1477 "<%s> set TXAK\n", __func__); 1478 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1479 temp |= I2CR_TXAK; 1480 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1481 } 1482 if ((!i) && block_data) 1483 msgs->buf[0] = len; 1484 else 1485 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1486 dev_dbg(&i2c_imx->adapter.dev, 1487 "<%s> read byte: B%d=0x%X\n", 1488 __func__, i, msgs->buf[i]); 1489 } 1490 return 0; 1491 } 1492 1493 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, 1494 bool is_lastmsg) 1495 { 1496 int block_data = msgs->flags & I2C_M_RECV_LEN; 1497 1498 dev_dbg(&i2c_imx->adapter.dev, 1499 "<%s> write slave address: addr=0x%x\n", 1500 __func__, i2c_8bit_addr_from_msg(msgs)); 1501 1502 i2c_imx->is_lastmsg = is_lastmsg; 1503 1504 if (block_data) 1505 i2c_imx->state = IMX_I2C_STATE_READ_BLOCK_DATA; 1506 else 1507 i2c_imx->state = IMX_I2C_STATE_READ; 1508 i2c_imx->msg = msgs; 1509 i2c_imx->msg_buf_idx = 0; 1510 1511 /* 1512 * By writing the device address we start the state machine in the ISR. 1513 * The ISR will report when it is done or when it fails. 1514 */ 1515 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1516 wait_event_timeout(i2c_imx->queue, 1517 i2c_imx->state == IMX_I2C_STATE_DONE || 1518 i2c_imx->state == IMX_I2C_STATE_FAILED, 1519 (msgs->len + 1) * HZ / 10); 1520 if (i2c_imx->state == IMX_I2C_STATE_FAILED) { 1521 dev_dbg(&i2c_imx->adapter.dev, "<%s> read failed with %d\n", 1522 __func__, i2c_imx->isr_result); 1523 return i2c_imx->isr_result; 1524 } 1525 if (i2c_imx->state != IMX_I2C_STATE_DONE) { 1526 dev_err(&i2c_imx->adapter.dev, "<%s> read timedout\n", __func__); 1527 return -ETIMEDOUT; 1528 } 1529 if (!i2c_imx->stopped) 1530 return i2c_imx_bus_busy(i2c_imx, 0, false); 1531 1532 return 0; 1533 } 1534 1535 static int i2c_imx_xfer_common(struct i2c_adapter *adapter, 1536 struct i2c_msg *msgs, int num, bool atomic) 1537 { 1538 unsigned int i, temp; 1539 int result; 1540 bool is_lastmsg = false; 1541 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1542 int use_dma = 0; 1543 1544 /* Start I2C transfer */ 1545 result = i2c_imx_start(i2c_imx, atomic); 1546 if (result) { 1547 /* 1548 * Bus recovery uses gpiod_get_value_cansleep() which is not 1549 * allowed within atomic context. 1550 */ 1551 if (!atomic && i2c_imx->adapter.bus_recovery_info) { 1552 i2c_recover_bus(&i2c_imx->adapter); 1553 result = i2c_imx_start(i2c_imx, atomic); 1554 } 1555 } 1556 1557 if (result) 1558 goto fail0; 1559 1560 /* read/write data */ 1561 for (i = 0; i < num; i++) { 1562 if (i == num - 1) 1563 is_lastmsg = true; 1564 1565 if (i) { 1566 dev_dbg(&i2c_imx->adapter.dev, 1567 "<%s> repeated start\n", __func__); 1568 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1569 temp |= I2CR_RSTA; 1570 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1571 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 1572 if (result) 1573 goto fail0; 1574 } 1575 dev_dbg(&i2c_imx->adapter.dev, 1576 "<%s> transfer message: %d\n", __func__, i); 1577 /* write/read data */ 1578 #ifdef CONFIG_I2C_DEBUG_BUS 1579 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1580 dev_dbg(&i2c_imx->adapter.dev, 1581 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", 1582 __func__, 1583 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), 1584 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), 1585 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); 1586 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1587 dev_dbg(&i2c_imx->adapter.dev, 1588 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", 1589 __func__, 1590 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), 1591 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), 1592 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), 1593 (temp & I2SR_RXAK ? 1 : 0)); 1594 #endif 1595 1596 use_dma = i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD && 1597 msgs[i].flags & I2C_M_DMA_SAFE; 1598 if (msgs[i].flags & I2C_M_RD) { 1599 int block_data = msgs->flags & I2C_M_RECV_LEN; 1600 1601 if (atomic) 1602 result = i2c_imx_atomic_read(i2c_imx, &msgs[i], is_lastmsg); 1603 else if (use_dma && !block_data) 1604 result = i2c_imx_dma_read(i2c_imx, &msgs[i], is_lastmsg); 1605 else 1606 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg); 1607 } else { 1608 if (atomic) 1609 result = i2c_imx_atomic_write(i2c_imx, &msgs[i]); 1610 else if (use_dma) 1611 result = i2c_imx_dma_write(i2c_imx, &msgs[i]); 1612 else 1613 result = i2c_imx_write(i2c_imx, &msgs[i]); 1614 } 1615 if (result) 1616 goto fail0; 1617 } 1618 1619 fail0: 1620 /* Stop I2C transfer */ 1621 i2c_imx_stop(i2c_imx, atomic); 1622 1623 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 1624 (result < 0) ? "error" : "success msg", 1625 (result < 0) ? result : num); 1626 /* After data is transferred, switch to slave mode(as a receiver) */ 1627 if (i2c_imx->slave) 1628 i2c_imx_slave_init(i2c_imx); 1629 1630 return (result < 0) ? result : num; 1631 } 1632 1633 static int i2c_imx_xfer(struct i2c_adapter *adapter, 1634 struct i2c_msg *msgs, int num) 1635 { 1636 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1637 int result; 1638 1639 result = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent); 1640 if (result < 0) 1641 return result; 1642 1643 result = i2c_imx_xfer_common(adapter, msgs, num, false); 1644 1645 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent); 1646 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent); 1647 1648 return result; 1649 } 1650 1651 static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter, 1652 struct i2c_msg *msgs, int num) 1653 { 1654 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1655 int result; 1656 1657 result = clk_enable(i2c_imx->clk); 1658 if (result) 1659 return result; 1660 1661 result = i2c_imx_xfer_common(adapter, msgs, num, true); 1662 1663 clk_disable(i2c_imx->clk); 1664 1665 return result; 1666 } 1667 1668 /* 1669 * We switch SCL and SDA to their GPIO function and do some bitbanging 1670 * for bus recovery. These alternative pinmux settings can be 1671 * described in the device tree by a separate pinctrl state "gpio". If 1672 * this is missing this is not a big problem, the only implication is 1673 * that we can't do bus recovery. 1674 */ 1675 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx, 1676 struct platform_device *pdev) 1677 { 1678 struct i2c_bus_recovery_info *bri = &i2c_imx->rinfo; 1679 1680 bri->pinctrl = devm_pinctrl_get(&pdev->dev); 1681 if (IS_ERR(bri->pinctrl)) 1682 return PTR_ERR(bri->pinctrl); 1683 1684 i2c_imx->adapter.bus_recovery_info = bri; 1685 1686 return 0; 1687 } 1688 1689 static u32 i2c_imx_func(struct i2c_adapter *adapter) 1690 { 1691 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 1692 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1693 } 1694 1695 static const struct i2c_algorithm i2c_imx_algo = { 1696 .xfer = i2c_imx_xfer, 1697 .xfer_atomic = i2c_imx_xfer_atomic, 1698 .functionality = i2c_imx_func, 1699 .reg_slave = i2c_imx_reg_slave, 1700 .unreg_slave = i2c_imx_unreg_slave, 1701 }; 1702 1703 static int i2c_imx_probe(struct platform_device *pdev) 1704 { 1705 struct imx_i2c_struct *i2c_imx; 1706 struct resource *res; 1707 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev); 1708 void __iomem *base; 1709 int irq, ret; 1710 dma_addr_t phy_addr; 1711 const struct imx_i2c_hwdata *match; 1712 1713 irq = platform_get_irq(pdev, 0); 1714 if (irq < 0) 1715 return dev_err_probe(&pdev->dev, irq, "can't get IRQ\n"); 1716 1717 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1718 if (IS_ERR(base)) 1719 return dev_err_probe(&pdev->dev, PTR_ERR(base), "can't get IO memory\n"); 1720 1721 phy_addr = (dma_addr_t)res->start; 1722 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL); 1723 if (!i2c_imx) 1724 return -ENOMEM; 1725 1726 spin_lock_init(&i2c_imx->slave_lock); 1727 hrtimer_setup(&i2c_imx->slave_timer, i2c_imx_slave_timeout, CLOCK_MONOTONIC, 1728 HRTIMER_MODE_ABS); 1729 1730 match = device_get_match_data(&pdev->dev); 1731 if (match) 1732 i2c_imx->hwdata = match; 1733 else 1734 i2c_imx->hwdata = (struct imx_i2c_hwdata *) 1735 platform_get_device_id(pdev)->driver_data; 1736 1737 /* Setup i2c_imx driver structure */ 1738 strscpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); 1739 i2c_imx->adapter.owner = THIS_MODULE; 1740 i2c_imx->adapter.algo = &i2c_imx_algo; 1741 i2c_imx->adapter.dev.parent = &pdev->dev; 1742 i2c_imx->adapter.nr = pdev->id; 1743 i2c_imx->adapter.dev.of_node = pdev->dev.of_node; 1744 i2c_imx->base = base; 1745 ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev)); 1746 1747 /* Get I2C clock */ 1748 i2c_imx->clk = devm_clk_get_enabled(&pdev->dev, NULL); 1749 if (IS_ERR(i2c_imx->clk)) 1750 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_imx->clk), 1751 "can't get I2C clock\n"); 1752 1753 /* Init queue */ 1754 init_waitqueue_head(&i2c_imx->queue); 1755 1756 /* Set up adapter data */ 1757 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); 1758 1759 /* Set up platform driver data */ 1760 platform_set_drvdata(pdev, i2c_imx); 1761 1762 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT); 1763 pm_runtime_use_autosuspend(&pdev->dev); 1764 pm_runtime_set_active(&pdev->dev); 1765 pm_runtime_enable(&pdev->dev); 1766 1767 ret = pm_runtime_get_sync(&pdev->dev); 1768 if (ret < 0) 1769 goto rpm_disable; 1770 1771 /* Request IRQ */ 1772 ret = request_irq(irq, i2c_imx_isr, IRQF_SHARED | IRQF_NO_SUSPEND, 1773 pdev->name, i2c_imx); 1774 if (ret) { 1775 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 1776 goto rpm_disable; 1777 } 1778 1779 /* 1780 * We use the single-master property for backward compatibility. 1781 * By default multi master mode is enabled. 1782 */ 1783 i2c_imx->multi_master = !of_property_read_bool(pdev->dev.of_node, "single-master"); 1784 1785 /* Set up clock divider */ 1786 i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ; 1787 ret = of_property_read_u32(pdev->dev.of_node, 1788 "clock-frequency", &i2c_imx->bitrate); 1789 if (ret < 0 && pdata && pdata->bitrate) 1790 i2c_imx->bitrate = pdata->bitrate; 1791 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call; 1792 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb); 1793 ret = i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk)); 1794 if (ret < 0) { 1795 dev_err(&pdev->dev, "can't get I2C clock\n"); 1796 goto clk_notifier_unregister; 1797 } 1798 1799 i2c_imx_reset_regs(i2c_imx); 1800 1801 /* Init optional bus recovery function */ 1802 ret = i2c_imx_init_recovery_info(i2c_imx, pdev); 1803 /* Give it another chance if pinctrl used is not ready yet */ 1804 if (ret == -EPROBE_DEFER) 1805 goto clk_notifier_unregister; 1806 1807 /* 1808 * DMA mode should be optional for I2C, when encountering DMA errors, 1809 * no need to exit I2C probe. Only print warning to show DMA error and 1810 * use PIO mode directly to ensure I2C bus available as much as possible. 1811 */ 1812 ret = i2c_imx_dma_request(i2c_imx, phy_addr); 1813 if (ret) { 1814 if (ret == -EPROBE_DEFER) { 1815 dev_err_probe(&pdev->dev, ret, "can't get DMA channels\n"); 1816 goto clk_notifier_unregister; 1817 } else if (ret == -ENODEV) { 1818 dev_dbg(&pdev->dev, "Only use PIO mode\n"); 1819 } else { 1820 dev_warn(&pdev->dev, "Failed to setup DMA (%pe), only use PIO mode\n", 1821 ERR_PTR(ret)); 1822 } 1823 } 1824 1825 /* Add I2C adapter */ 1826 ret = i2c_add_numbered_adapter(&i2c_imx->adapter); 1827 if (ret < 0) 1828 goto clk_notifier_unregister; 1829 1830 pm_runtime_mark_last_busy(&pdev->dev); 1831 pm_runtime_put_autosuspend(&pdev->dev); 1832 1833 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq); 1834 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res); 1835 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 1836 i2c_imx->adapter.name); 1837 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 1838 1839 return 0; /* Return OK */ 1840 1841 clk_notifier_unregister: 1842 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1843 free_irq(irq, i2c_imx); 1844 rpm_disable: 1845 pm_runtime_put_noidle(&pdev->dev); 1846 pm_runtime_disable(&pdev->dev); 1847 pm_runtime_set_suspended(&pdev->dev); 1848 pm_runtime_dont_use_autosuspend(&pdev->dev); 1849 return ret; 1850 } 1851 1852 static void i2c_imx_remove(struct platform_device *pdev) 1853 { 1854 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 1855 int irq, ret; 1856 1857 ret = pm_runtime_get_sync(&pdev->dev); 1858 1859 hrtimer_cancel(&i2c_imx->slave_timer); 1860 1861 /* remove adapter */ 1862 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 1863 i2c_del_adapter(&i2c_imx->adapter); 1864 1865 if (i2c_imx->dma) 1866 i2c_imx_dma_free(i2c_imx); 1867 1868 if (ret >= 0) { 1869 /* setup chip registers to defaults */ 1870 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 1871 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); 1872 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); 1873 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); 1874 } 1875 1876 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1877 irq = platform_get_irq(pdev, 0); 1878 if (irq >= 0) 1879 free_irq(irq, i2c_imx); 1880 1881 pm_runtime_put_noidle(&pdev->dev); 1882 pm_runtime_disable(&pdev->dev); 1883 } 1884 1885 static int i2c_imx_runtime_suspend(struct device *dev) 1886 { 1887 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1888 1889 clk_disable(i2c_imx->clk); 1890 return pinctrl_pm_select_sleep_state(dev); 1891 } 1892 1893 static int i2c_imx_runtime_resume(struct device *dev) 1894 { 1895 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1896 int ret; 1897 1898 ret = pinctrl_pm_select_default_state(dev); 1899 if (ret) 1900 return ret; 1901 1902 ret = clk_enable(i2c_imx->clk); 1903 if (ret) 1904 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret); 1905 1906 return ret; 1907 } 1908 1909 static int i2c_imx_suspend(struct device *dev) 1910 { 1911 /* 1912 * Some I2C devices may need the I2C controller to remain active 1913 * during resume_noirq() or suspend_noirq(). If the controller is 1914 * autosuspended, there is no way to wake it up once runtime PM is 1915 * disabled (in suspend_late()). 1916 * 1917 * During system resume, the I2C controller will be available only 1918 * after runtime PM is re-enabled (in resume_early()). However, this 1919 * may be too late for some devices. 1920 * 1921 * Wake up the controller in the suspend() callback while runtime PM 1922 * is still enabled. The I2C controller will remain available until 1923 * the suspend_noirq() callback (pm_runtime_force_suspend()) is 1924 * called. During resume, the I2C controller can be restored by the 1925 * resume_noirq() callback (pm_runtime_force_resume()). 1926 * 1927 * Finally, the resume() callback re-enables autosuspend, ensuring 1928 * the I2C controller remains available until the system enters 1929 * suspend_noirq() and from resume_noirq(). 1930 */ 1931 return pm_runtime_resume_and_get(dev); 1932 } 1933 1934 static int i2c_imx_resume(struct device *dev) 1935 { 1936 pm_runtime_mark_last_busy(dev); 1937 pm_runtime_put_autosuspend(dev); 1938 1939 return 0; 1940 } 1941 1942 static const struct dev_pm_ops i2c_imx_pm_ops = { 1943 NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1944 pm_runtime_force_resume) 1945 SYSTEM_SLEEP_PM_OPS(i2c_imx_suspend, i2c_imx_resume) 1946 RUNTIME_PM_OPS(i2c_imx_runtime_suspend, i2c_imx_runtime_resume, NULL) 1947 }; 1948 1949 static struct platform_driver i2c_imx_driver = { 1950 .probe = i2c_imx_probe, 1951 .remove = i2c_imx_remove, 1952 .driver = { 1953 .name = DRIVER_NAME, 1954 .pm = pm_ptr(&i2c_imx_pm_ops), 1955 .of_match_table = i2c_imx_dt_ids, 1956 .acpi_match_table = i2c_imx_acpi_ids, 1957 }, 1958 .id_table = imx_i2c_devtype, 1959 }; 1960 1961 static int __init i2c_adap_imx_init(void) 1962 { 1963 return platform_driver_register(&i2c_imx_driver); 1964 } 1965 subsys_initcall(i2c_adap_imx_init); 1966 1967 static void __exit i2c_adap_imx_exit(void) 1968 { 1969 platform_driver_unregister(&i2c_imx_driver); 1970 } 1971 module_exit(i2c_adap_imx_exit); 1972 1973 MODULE_LICENSE("GPL"); 1974 MODULE_AUTHOR("Darius Augulis"); 1975 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); 1976 MODULE_ALIAS("platform:" DRIVER_NAME); 1977