1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2002 Motorola GSG-China 4 * 5 * Author: 6 * Darius Augulis, Teltonika Inc. 7 * 8 * Desc.: 9 * Implementation of I2C Adapter/Algorithm Driver 10 * for I2C Bus integrated in Freescale i.MX/MXC processors 11 * 12 * Derived from Motorola GSG China I2C example driver 13 * 14 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de 15 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de 16 * Copyright (C) 2007 RightHand Technologies, Inc. 17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 18 * 19 * Copyright 2013 Freescale Semiconductor, Inc. 20 * Copyright 2020, 2024 NXP 21 * 22 */ 23 24 #include <linux/acpi.h> 25 #include <linux/clk.h> 26 #include <linux/completion.h> 27 #include <linux/delay.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/dmaengine.h> 30 #include <linux/dmapool.h> 31 #include <linux/err.h> 32 #include <linux/errno.h> 33 #include <linux/gpio/consumer.h> 34 #include <linux/i2c.h> 35 #include <linux/init.h> 36 #include <linux/interrupt.h> 37 #include <linux/io.h> 38 #include <linux/iopoll.h> 39 #include <linux/kernel.h> 40 #include <linux/spinlock.h> 41 #include <linux/hrtimer.h> 42 #include <linux/module.h> 43 #include <linux/of.h> 44 #include <linux/of_dma.h> 45 #include <linux/pinctrl/consumer.h> 46 #include <linux/platform_data/i2c-imx.h> 47 #include <linux/platform_device.h> 48 #include <linux/pm_runtime.h> 49 #include <linux/sched.h> 50 #include <linux/slab.h> 51 52 /* This will be the driver name the kernel reports */ 53 #define DRIVER_NAME "imx-i2c" 54 55 #define I2C_IMX_CHECK_DELAY 30000 /* Time to check for bus idle, in NS */ 56 57 /* 58 * Enable DMA if transfer byte size is bigger than this threshold. 59 * As the hardware request, it must bigger than 4 bytes.\ 60 * I have set '16' here, maybe it's not the best but I think it's 61 * the appropriate. 62 */ 63 #define DMA_THRESHOLD 16 64 #define DMA_TIMEOUT 1000 65 66 /* IMX I2C registers: 67 * the I2C register offset is different between SoCs, 68 * to provide support for all these chips, split the 69 * register offset into a fixed base address and a 70 * variable shift value, then the full register offset 71 * will be calculated by 72 * reg_off = ( reg_base_addr << reg_shift) 73 */ 74 #define IMX_I2C_IADR 0x00 /* i2c slave address */ 75 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ 76 #define IMX_I2C_I2CR 0x02 /* i2c control */ 77 #define IMX_I2C_I2SR 0x03 /* i2c status */ 78 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */ 79 80 /* 81 * All of the layerscape series SoCs support IBIC register. 82 */ 83 #define IMX_I2C_IBIC 0x05 /* i2c bus interrupt config */ 84 85 #define IMX_I2C_REGSHIFT 2 86 #define VF610_I2C_REGSHIFT 0 87 #define S32G_I2C_REGSHIFT 0 88 89 /* Bits of IMX I2C registers */ 90 #define I2SR_RXAK 0x01 91 #define I2SR_IIF 0x02 92 #define I2SR_SRW 0x04 93 #define I2SR_IAL 0x10 94 #define I2SR_IBB 0x20 95 #define I2SR_IAAS 0x40 96 #define I2SR_ICF 0x80 97 #define I2CR_DMAEN 0x02 98 #define I2CR_RSTA 0x04 99 #define I2CR_TXAK 0x08 100 #define I2CR_MTX 0x10 101 #define I2CR_MSTA 0x20 102 #define I2CR_IIEN 0x40 103 #define I2CR_IEN 0x80 104 #define IBIC_BIIE 0x80 /* Bus idle interrupt enable */ 105 106 /* register bits different operating codes definition: 107 * 1) I2SR: Interrupt flags clear operation differ between SoCs: 108 * - write zero to clear(w0c) INT flag on i.MX, 109 * - but write one to clear(w1c) INT flag on Vybrid. 110 * 2) I2CR: I2C module enable operation also differ between SoCs: 111 * - set I2CR_IEN bit enable the module on i.MX, 112 * - but clear I2CR_IEN bit enable the module on Vybrid. 113 */ 114 #define I2SR_CLR_OPCODE_W0C 0x0 115 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) 116 #define I2CR_IEN_OPCODE_0 0x0 117 #define I2CR_IEN_OPCODE_1 I2CR_IEN 118 119 #define I2C_PM_TIMEOUT 10 /* ms */ 120 121 /* 122 * sorted list of clock divider, register value pairs 123 * taken from table 26-5, p.26-9, Freescale i.MX 124 * Integrated Portable System Processor Reference Manual 125 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 126 * 127 * Duplicated divider values removed from list 128 */ 129 struct imx_i2c_clk_pair { 130 u16 div; 131 u16 val; 132 }; 133 134 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = { 135 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 136 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 137 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 138 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 139 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 140 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 141 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 142 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 143 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 144 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 145 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 146 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 147 { 3072, 0x1E }, { 3840, 0x1F } 148 }; 149 150 /* Vybrid VF610 clock divider, register value pairs */ 151 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = { 152 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 153 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 154 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 155 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 156 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 157 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 158 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 159 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 160 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 161 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 162 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 163 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 164 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 165 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 166 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 167 }; 168 169 /* S32G2/S32G3 clock divider, register value pairs */ 170 static struct imx_i2c_clk_pair s32g2_i2c_clk_div[] = { 171 { 34, 0x00 }, { 36, 0x01 }, { 38, 0x02 }, { 40, 0x03 }, 172 { 42, 0x04 }, { 44, 0x05 }, { 46, 0x06 }, { 48, 0x09 }, 173 { 52, 0x0A }, { 54, 0x07 }, { 56, 0x0B }, { 60, 0x0C }, 174 { 64, 0x0D }, { 68, 0x40 }, { 72, 0x0E }, { 76, 0x42 }, 175 { 80, 0x12 }, { 84, 0x0F }, { 88, 0x13 }, { 96, 0x14 }, 176 { 104, 0x15 }, { 108, 0x47 }, { 112, 0x19 }, { 120, 0x16 }, 177 { 128, 0x1A }, { 136, 0x80 }, { 144, 0x17 }, { 152, 0x82 }, 178 { 160, 0x1C }, { 168, 0x84 }, { 176, 0x1D }, { 192, 0x21 }, 179 { 208, 0x1E }, { 216, 0x87 }, { 224, 0x22 }, { 240, 0x56 }, 180 { 256, 0x1F }, { 288, 0x24 }, { 320, 0x25 }, { 336, 0x8F }, 181 { 352, 0x93 }, { 356, 0x5D }, { 358, 0x98 }, { 384, 0x26 }, 182 { 416, 0x56 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 183 { 576, 0x2C }, { 640, 0x2D }, { 704, 0x9D }, { 768, 0x2E }, 184 { 832, 0x9D }, { 896, 0x32 }, { 960, 0x2F }, { 1024, 0x33 }, 185 { 1152, 0x34 }, { 1280, 0x35 }, { 1536, 0x36 }, { 1792, 0x3A }, 186 { 1920, 0x37 }, { 2048, 0x3B }, { 2304, 0x74 }, { 2560, 0x3D }, 187 { 3072, 0x3E }, { 3584, 0x7A }, { 3840, 0x3F }, { 4096, 0x7B }, 188 { 4608, 0x7C }, { 5120, 0x7D }, { 6144, 0x7E }, { 7168, 0xBA }, 189 { 7680, 0x7F }, { 8192, 0xBB }, { 9216, 0xBC }, { 10240, 0xBD }, 190 { 12288, 0xBE }, { 15360, 0xBF }, 191 }; 192 193 enum imx_i2c_type { 194 IMX1_I2C, 195 IMX21_I2C, 196 S32G_I2C, 197 VF610_I2C, 198 }; 199 200 struct imx_i2c_hwdata { 201 enum imx_i2c_type devtype; 202 unsigned int regshift; 203 struct imx_i2c_clk_pair *clk_div; 204 unsigned int ndivs; 205 unsigned int i2sr_clr_opcode; 206 unsigned int i2cr_ien_opcode; 207 /* 208 * Errata ERR007805 or e7805: 209 * I2C: When the I2C clock speed is configured for 400 kHz, 210 * the SCL low period violates the I2C spec of 1.3 uS min. 211 */ 212 bool has_err007805; 213 }; 214 215 struct imx_i2c_dma { 216 struct dma_chan *chan_tx; 217 struct dma_chan *chan_rx; 218 struct dma_chan *chan_using; 219 struct completion cmd_complete; 220 dma_addr_t dma_buf; 221 unsigned int dma_len; 222 enum dma_transfer_direction dma_transfer_dir; 223 enum dma_data_direction dma_data_dir; 224 }; 225 226 enum imx_i2c_state { 227 IMX_I2C_STATE_DONE, 228 IMX_I2C_STATE_FAILED, 229 IMX_I2C_STATE_WRITE, 230 IMX_I2C_STATE_DMA, 231 IMX_I2C_STATE_READ, 232 IMX_I2C_STATE_READ_CONTINUE, 233 IMX_I2C_STATE_READ_BLOCK_DATA, 234 IMX_I2C_STATE_READ_BLOCK_DATA_LEN, 235 }; 236 237 struct imx_i2c_struct { 238 struct i2c_adapter adapter; 239 struct clk *clk; 240 struct notifier_block clk_change_nb; 241 void __iomem *base; 242 wait_queue_head_t queue; 243 unsigned long i2csr; 244 unsigned int disable_delay; 245 int stopped; 246 unsigned int ifdr; /* IMX_I2C_IFDR */ 247 unsigned int cur_clk; 248 unsigned int bitrate; 249 const struct imx_i2c_hwdata *hwdata; 250 struct i2c_bus_recovery_info rinfo; 251 252 struct imx_i2c_dma *dma; 253 struct i2c_client *slave; 254 enum i2c_slave_event last_slave_event; 255 256 struct i2c_msg *msg; 257 unsigned int msg_buf_idx; 258 int isr_result; 259 bool is_lastmsg; 260 enum imx_i2c_state state; 261 262 bool multi_master; 263 264 /* For checking slave events. */ 265 spinlock_t slave_lock; 266 struct hrtimer slave_timer; 267 }; 268 269 static const struct imx_i2c_hwdata imx1_i2c_hwdata = { 270 .devtype = IMX1_I2C, 271 .regshift = IMX_I2C_REGSHIFT, 272 .clk_div = imx_i2c_clk_div, 273 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 274 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 275 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 276 277 }; 278 279 static const struct imx_i2c_hwdata imx21_i2c_hwdata = { 280 .devtype = IMX21_I2C, 281 .regshift = IMX_I2C_REGSHIFT, 282 .clk_div = imx_i2c_clk_div, 283 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 284 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 285 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 286 287 }; 288 289 static const struct imx_i2c_hwdata imx6_i2c_hwdata = { 290 .devtype = IMX21_I2C, 291 .regshift = IMX_I2C_REGSHIFT, 292 .clk_div = imx_i2c_clk_div, 293 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 294 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 295 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 296 .has_err007805 = true, 297 }; 298 299 static struct imx_i2c_hwdata vf610_i2c_hwdata = { 300 .devtype = VF610_I2C, 301 .regshift = VF610_I2C_REGSHIFT, 302 .clk_div = vf610_i2c_clk_div, 303 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div), 304 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 305 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 306 }; 307 308 static const struct imx_i2c_hwdata s32g2_i2c_hwdata = { 309 .devtype = S32G_I2C, 310 .regshift = S32G_I2C_REGSHIFT, 311 .clk_div = s32g2_i2c_clk_div, 312 .ndivs = ARRAY_SIZE(s32g2_i2c_clk_div), 313 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 314 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 315 }; 316 317 static const struct platform_device_id imx_i2c_devtype[] = { 318 { 319 .name = "imx1-i2c", 320 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata, 321 }, { 322 .name = "imx21-i2c", 323 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata, 324 }, { 325 /* sentinel */ 326 } 327 }; 328 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); 329 330 static const struct of_device_id i2c_imx_dt_ids[] = { 331 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, }, 332 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, }, 333 { .compatible = "fsl,imx6q-i2c", .data = &imx6_i2c_hwdata, }, 334 { .compatible = "fsl,imx6sl-i2c", .data = &imx6_i2c_hwdata, }, 335 { .compatible = "fsl,imx6sll-i2c", .data = &imx6_i2c_hwdata, }, 336 { .compatible = "fsl,imx6sx-i2c", .data = &imx6_i2c_hwdata, }, 337 { .compatible = "fsl,imx6ul-i2c", .data = &imx6_i2c_hwdata, }, 338 { .compatible = "fsl,imx7d-i2c", .data = &imx6_i2c_hwdata, }, 339 { .compatible = "fsl,imx7s-i2c", .data = &imx6_i2c_hwdata, }, 340 { .compatible = "fsl,imx8mm-i2c", .data = &imx6_i2c_hwdata, }, 341 { .compatible = "fsl,imx8mn-i2c", .data = &imx6_i2c_hwdata, }, 342 { .compatible = "fsl,imx8mp-i2c", .data = &imx6_i2c_hwdata, }, 343 { .compatible = "fsl,imx8mq-i2c", .data = &imx6_i2c_hwdata, }, 344 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, }, 345 { .compatible = "nxp,s32g2-i2c", .data = &s32g2_i2c_hwdata, }, 346 { /* sentinel */ } 347 }; 348 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); 349 350 static const struct acpi_device_id i2c_imx_acpi_ids[] = { 351 {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata}, 352 { } 353 }; 354 MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids); 355 356 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) 357 { 358 return i2c_imx->hwdata->devtype == IMX1_I2C; 359 } 360 361 static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx) 362 { 363 return i2c_imx->hwdata->devtype == VF610_I2C; 364 } 365 366 static inline void imx_i2c_write_reg(unsigned int val, 367 struct imx_i2c_struct *i2c_imx, unsigned int reg) 368 { 369 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 370 } 371 372 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, 373 unsigned int reg) 374 { 375 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 376 } 377 378 static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits) 379 { 380 unsigned int temp; 381 382 /* 383 * i2sr_clr_opcode is the value to clear all interrupts. Here we want to 384 * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits> 385 * toggled. This is required because i.MX needs W0C and Vybrid uses W1C. 386 */ 387 temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits; 388 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 389 } 390 391 /* Set up i2c controller register and i2c status register to default value. */ 392 static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx) 393 { 394 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 395 i2c_imx, IMX_I2C_I2CR); 396 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 397 } 398 399 /* Functions for DMA support */ 400 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, 401 dma_addr_t phy_addr) 402 { 403 struct imx_i2c_dma *dma; 404 struct dma_slave_config dma_sconfig; 405 struct device *dev = &i2c_imx->adapter.dev; 406 int ret; 407 408 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 409 if (!dma) 410 return; 411 412 dma->chan_tx = dma_request_chan(dev, "tx"); 413 if (IS_ERR(dma->chan_tx)) { 414 ret = PTR_ERR(dma->chan_tx); 415 if (ret != -ENODEV && ret != -EPROBE_DEFER) 416 dev_err(dev, "can't request DMA tx channel (%d)\n", ret); 417 goto fail_al; 418 } 419 420 dma_sconfig.dst_addr = phy_addr + 421 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 422 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 423 dma_sconfig.dst_maxburst = 1; 424 dma_sconfig.direction = DMA_MEM_TO_DEV; 425 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig); 426 if (ret < 0) { 427 dev_err(dev, "can't configure tx channel (%d)\n", ret); 428 goto fail_tx; 429 } 430 431 dma->chan_rx = dma_request_chan(dev, "rx"); 432 if (IS_ERR(dma->chan_rx)) { 433 ret = PTR_ERR(dma->chan_rx); 434 if (ret != -ENODEV && ret != -EPROBE_DEFER) 435 dev_err(dev, "can't request DMA rx channel (%d)\n", ret); 436 goto fail_tx; 437 } 438 439 dma_sconfig.src_addr = phy_addr + 440 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 441 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 442 dma_sconfig.src_maxburst = 1; 443 dma_sconfig.direction = DMA_DEV_TO_MEM; 444 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig); 445 if (ret < 0) { 446 dev_err(dev, "can't configure rx channel (%d)\n", ret); 447 goto fail_rx; 448 } 449 450 i2c_imx->dma = dma; 451 init_completion(&dma->cmd_complete); 452 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n", 453 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); 454 455 return; 456 457 fail_rx: 458 dma_release_channel(dma->chan_rx); 459 fail_tx: 460 dma_release_channel(dma->chan_tx); 461 fail_al: 462 devm_kfree(dev, dma); 463 } 464 465 static void i2c_imx_dma_callback(void *arg) 466 { 467 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg; 468 struct imx_i2c_dma *dma = i2c_imx->dma; 469 470 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf, 471 dma->dma_len, dma->dma_data_dir); 472 complete(&dma->cmd_complete); 473 } 474 475 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx, 476 struct i2c_msg *msgs) 477 { 478 struct imx_i2c_dma *dma = i2c_imx->dma; 479 struct dma_async_tx_descriptor *txdesc; 480 struct device *dev = &i2c_imx->adapter.dev; 481 struct device *chan_dev = dma->chan_using->device->dev; 482 483 dma->dma_buf = dma_map_single(chan_dev, msgs->buf, 484 dma->dma_len, dma->dma_data_dir); 485 if (dma_mapping_error(chan_dev, dma->dma_buf)) { 486 dev_err(dev, "DMA mapping failed\n"); 487 goto err_map; 488 } 489 490 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf, 491 dma->dma_len, dma->dma_transfer_dir, 492 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 493 if (!txdesc) { 494 dev_err(dev, "Not able to get desc for DMA xfer\n"); 495 goto err_desc; 496 } 497 498 reinit_completion(&dma->cmd_complete); 499 txdesc->callback = i2c_imx_dma_callback; 500 txdesc->callback_param = i2c_imx; 501 if (dma_submit_error(dmaengine_submit(txdesc))) { 502 dev_err(dev, "DMA submit failed\n"); 503 goto err_submit; 504 } 505 506 dma_async_issue_pending(dma->chan_using); 507 return 0; 508 509 err_submit: 510 dmaengine_terminate_sync(dma->chan_using); 511 err_desc: 512 dma_unmap_single(chan_dev, dma->dma_buf, 513 dma->dma_len, dma->dma_data_dir); 514 err_map: 515 return -EINVAL; 516 } 517 518 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx) 519 { 520 struct imx_i2c_dma *dma = i2c_imx->dma; 521 522 dma->dma_buf = 0; 523 dma->dma_len = 0; 524 525 dma_release_channel(dma->chan_tx); 526 dma->chan_tx = NULL; 527 528 dma_release_channel(dma->chan_rx); 529 dma->chan_rx = NULL; 530 531 dma->chan_using = NULL; 532 } 533 534 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic) 535 { 536 bool multi_master = i2c_imx->multi_master; 537 unsigned long orig_jiffies = jiffies; 538 unsigned int temp; 539 540 while (1) { 541 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 542 543 /* check for arbitration lost */ 544 if (multi_master && (temp & I2SR_IAL)) { 545 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 546 return -EAGAIN; 547 } 548 549 if (for_busy && (!multi_master || (temp & I2SR_IBB))) { 550 i2c_imx->stopped = 0; 551 break; 552 } 553 if (!for_busy && !(temp & I2SR_IBB)) { 554 i2c_imx->stopped = 1; 555 break; 556 } 557 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 558 dev_dbg(&i2c_imx->adapter.dev, 559 "<%s> I2C bus is busy\n", __func__); 560 return -ETIMEDOUT; 561 } 562 if (atomic) 563 udelay(100); 564 else 565 schedule(); 566 } 567 568 return 0; 569 } 570 571 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic) 572 { 573 if (atomic) { 574 void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift); 575 unsigned int regval; 576 577 /* 578 * The formula for the poll timeout is documented in the RM 579 * Rev.5 on page 1878: 580 * T_min = 10/F_scl 581 * Set the value hard as it is done for the non-atomic use-case. 582 * Use 10 kHz for the calculation since this is the minimum 583 * allowed SMBus frequency. Also add an offset of 100us since it 584 * turned out that the I2SR_IIF bit isn't set correctly within 585 * the minimum timeout in polling mode. 586 */ 587 readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100); 588 i2c_imx->i2csr = regval; 589 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 590 } else { 591 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); 592 } 593 594 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { 595 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); 596 return -ETIMEDOUT; 597 } 598 599 /* In multi-master mode check for arbitration lost */ 600 if (i2c_imx->multi_master && (i2c_imx->i2csr & I2SR_IAL)) { 601 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__); 602 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 603 604 i2c_imx->i2csr = 0; 605 return -EAGAIN; 606 } 607 608 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); 609 i2c_imx->i2csr = 0; 610 return 0; 611 } 612 613 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) 614 { 615 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 616 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); 617 return -ENXIO; /* No ACK */ 618 } 619 620 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); 621 return 0; 622 } 623 624 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 625 unsigned int i2c_clk_rate) 626 { 627 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; 628 unsigned int div; 629 int i; 630 631 if (i2c_imx->hwdata->has_err007805 && i2c_imx->bitrate > 384000) { 632 dev_dbg(&i2c_imx->adapter.dev, 633 "SoC errata ERR007805 or e7805 applies, bus frequency limited from %d Hz to 384000 Hz.\n", 634 i2c_imx->bitrate); 635 i2c_imx->bitrate = 384000; 636 } 637 638 /* Divider value calculation */ 639 if (i2c_imx->cur_clk == i2c_clk_rate) 640 return; 641 642 i2c_imx->cur_clk = i2c_clk_rate; 643 644 div = DIV_ROUND_UP(i2c_clk_rate, i2c_imx->bitrate); 645 if (div < i2c_clk_div[0].div) 646 i = 0; 647 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) 648 i = i2c_imx->hwdata->ndivs - 1; 649 else 650 for (i = 0; i2c_clk_div[i].div < div; i++) 651 ; 652 653 /* Store divider value */ 654 i2c_imx->ifdr = i2c_clk_div[i].val; 655 656 /* 657 * There dummy delay is calculated. 658 * It should be about one I2C clock period long. 659 * This delay is used in I2C bus disable function 660 * to fix chip hardware bug. 661 */ 662 i2c_imx->disable_delay = DIV_ROUND_UP(500000U * i2c_clk_div[i].div, 663 i2c_clk_rate / 2); 664 665 #ifdef CONFIG_I2C_DEBUG_BUS 666 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n", 667 i2c_clk_rate, div); 668 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n", 669 i2c_clk_div[i].val, i2c_clk_div[i].div); 670 #endif 671 } 672 673 static int i2c_imx_clk_notifier_call(struct notifier_block *nb, 674 unsigned long action, void *data) 675 { 676 struct clk_notifier_data *ndata = data; 677 struct imx_i2c_struct *i2c_imx = container_of(nb, 678 struct imx_i2c_struct, 679 clk_change_nb); 680 681 if (action & POST_RATE_CHANGE) 682 i2c_imx_set_clk(i2c_imx, ndata->new_rate); 683 684 return NOTIFY_OK; 685 } 686 687 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic) 688 { 689 unsigned int temp = 0; 690 int result; 691 692 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); 693 /* Enable I2C controller */ 694 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 695 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR); 696 697 /* Wait controller to be stable */ 698 if (atomic) 699 udelay(50); 700 else 701 usleep_range(50, 150); 702 703 /* Start I2C transaction */ 704 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 705 temp |= I2CR_MSTA; 706 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 707 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 708 if (result) 709 return result; 710 711 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; 712 if (atomic) 713 temp &= ~I2CR_IIEN; /* Disable interrupt */ 714 715 temp &= ~I2CR_DMAEN; 716 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 717 return result; 718 } 719 720 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic) 721 { 722 unsigned int temp = 0; 723 724 if (!i2c_imx->stopped) { 725 /* Stop I2C transaction */ 726 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 727 if (!(temp & I2CR_MSTA)) 728 i2c_imx->stopped = 1; 729 temp &= ~(I2CR_MSTA | I2CR_MTX); 730 if (i2c_imx->dma) 731 temp &= ~I2CR_DMAEN; 732 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 733 } 734 if (is_imx1_i2c(i2c_imx)) { 735 /* 736 * This delay caused by an i.MXL hardware bug. 737 * If no (or too short) delay, no "STOP" bit will be generated. 738 */ 739 udelay(i2c_imx->disable_delay); 740 } 741 742 if (!i2c_imx->stopped) 743 i2c_imx_bus_busy(i2c_imx, 0, atomic); 744 745 /* Disable I2C controller */ 746 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN; 747 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 748 } 749 750 /* 751 * Enable bus idle interrupts 752 * Note: IBIC register will be cleared after disabled i2c module. 753 * All of layerscape series SoCs support IBIC register. 754 */ 755 static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx) 756 { 757 if (is_vf610_i2c(i2c_imx)) { 758 unsigned int temp; 759 760 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC); 761 temp |= IBIC_BIIE; 762 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC); 763 } 764 } 765 766 static void i2c_imx_slave_event(struct imx_i2c_struct *i2c_imx, 767 enum i2c_slave_event event, u8 *val) 768 { 769 i2c_slave_event(i2c_imx->slave, event, val); 770 i2c_imx->last_slave_event = event; 771 } 772 773 static void i2c_imx_slave_finish_op(struct imx_i2c_struct *i2c_imx) 774 { 775 u8 val = 0; 776 777 while (i2c_imx->last_slave_event != I2C_SLAVE_STOP) { 778 switch (i2c_imx->last_slave_event) { 779 case I2C_SLAVE_READ_REQUESTED: 780 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_READ_PROCESSED, 781 &val); 782 break; 783 784 case I2C_SLAVE_WRITE_REQUESTED: 785 case I2C_SLAVE_READ_PROCESSED: 786 case I2C_SLAVE_WRITE_RECEIVED: 787 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_STOP, &val); 788 break; 789 790 case I2C_SLAVE_STOP: 791 break; 792 } 793 } 794 } 795 796 /* Returns true if the timer should be restarted, false if not. */ 797 static irqreturn_t i2c_imx_slave_handle(struct imx_i2c_struct *i2c_imx, 798 unsigned int status, unsigned int ctl) 799 { 800 u8 value = 0; 801 802 if (status & I2SR_IAL) { /* Arbitration lost */ 803 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 804 if (!(status & I2SR_IAAS)) 805 return IRQ_HANDLED; 806 } 807 808 if (!(status & I2SR_IBB)) { 809 /* No master on the bus, that could mean a stop condition. */ 810 i2c_imx_slave_finish_op(i2c_imx); 811 return IRQ_HANDLED; 812 } 813 814 if (!(status & I2SR_ICF)) 815 /* Data transfer still in progress, ignore this. */ 816 goto out; 817 818 if (status & I2SR_IAAS) { /* Addressed as a slave */ 819 i2c_imx_slave_finish_op(i2c_imx); 820 if (status & I2SR_SRW) { /* Master wants to read from us*/ 821 dev_dbg(&i2c_imx->adapter.dev, "read requested"); 822 i2c_imx_slave_event(i2c_imx, 823 I2C_SLAVE_READ_REQUESTED, &value); 824 825 /* Slave transmit */ 826 ctl |= I2CR_MTX; 827 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 828 829 /* Send data */ 830 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 831 } else { /* Master wants to write to us */ 832 dev_dbg(&i2c_imx->adapter.dev, "write requested"); 833 i2c_imx_slave_event(i2c_imx, 834 I2C_SLAVE_WRITE_REQUESTED, &value); 835 836 /* Slave receive */ 837 ctl &= ~I2CR_MTX; 838 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 839 /* Dummy read */ 840 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 841 } 842 } else if (!(ctl & I2CR_MTX)) { /* Receive mode */ 843 value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 844 i2c_imx_slave_event(i2c_imx, 845 I2C_SLAVE_WRITE_RECEIVED, &value); 846 } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */ 847 ctl |= I2CR_MTX; 848 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 849 850 i2c_imx_slave_event(i2c_imx, 851 I2C_SLAVE_READ_PROCESSED, &value); 852 853 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 854 } else { /* Transmit mode received NAK, operation is done */ 855 ctl &= ~I2CR_MTX; 856 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 857 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 858 859 /* flag the last byte as processed */ 860 i2c_imx_slave_event(i2c_imx, 861 I2C_SLAVE_READ_PROCESSED, &value); 862 863 i2c_imx_slave_finish_op(i2c_imx); 864 return IRQ_HANDLED; 865 } 866 867 out: 868 /* 869 * No need to check the return value here. If it returns 0 or 870 * 1, then everything is fine. If it returns -1, then the 871 * timer is running in the handler. This will still work, 872 * though it may be redone (or already have been done) by the 873 * timer function. 874 */ 875 hrtimer_try_to_cancel(&i2c_imx->slave_timer); 876 hrtimer_forward_now(&i2c_imx->slave_timer, I2C_IMX_CHECK_DELAY); 877 hrtimer_restart(&i2c_imx->slave_timer); 878 return IRQ_HANDLED; 879 } 880 881 static enum hrtimer_restart i2c_imx_slave_timeout(struct hrtimer *t) 882 { 883 struct imx_i2c_struct *i2c_imx = container_of(t, struct imx_i2c_struct, 884 slave_timer); 885 unsigned int ctl, status; 886 unsigned long flags; 887 888 spin_lock_irqsave(&i2c_imx->slave_lock, flags); 889 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 890 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 891 i2c_imx_slave_handle(i2c_imx, status, ctl); 892 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags); 893 return HRTIMER_NORESTART; 894 } 895 896 static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx) 897 { 898 int temp; 899 900 /* Set slave addr. */ 901 imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR); 902 903 i2c_imx_reset_regs(i2c_imx); 904 905 /* Enable module */ 906 temp = i2c_imx->hwdata->i2cr_ien_opcode; 907 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 908 909 /* Enable interrupt from i2c module */ 910 temp |= I2CR_IIEN; 911 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 912 913 i2c_imx_enable_bus_idle(i2c_imx); 914 } 915 916 static int i2c_imx_reg_slave(struct i2c_client *client) 917 { 918 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 919 int ret; 920 921 if (i2c_imx->slave) 922 return -EBUSY; 923 924 i2c_imx->slave = client; 925 i2c_imx->last_slave_event = I2C_SLAVE_STOP; 926 927 /* Resume */ 928 ret = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent); 929 if (ret < 0) { 930 dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller"); 931 return ret; 932 } 933 934 i2c_imx_slave_init(i2c_imx); 935 936 return 0; 937 } 938 939 static int i2c_imx_unreg_slave(struct i2c_client *client) 940 { 941 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 942 int ret; 943 944 if (!i2c_imx->slave) 945 return -EINVAL; 946 947 /* Reset slave address. */ 948 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 949 950 i2c_imx_reset_regs(i2c_imx); 951 952 i2c_imx->slave = NULL; 953 954 /* Suspend */ 955 ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent); 956 if (ret < 0) 957 dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller"); 958 959 return ret; 960 } 961 962 static inline int i2c_imx_isr_acked(struct imx_i2c_struct *i2c_imx) 963 { 964 i2c_imx->isr_result = 0; 965 966 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 967 i2c_imx->state = IMX_I2C_STATE_FAILED; 968 i2c_imx->isr_result = -ENXIO; 969 wake_up(&i2c_imx->queue); 970 } 971 972 return i2c_imx->isr_result; 973 } 974 975 static inline int i2c_imx_isr_write(struct imx_i2c_struct *i2c_imx) 976 { 977 int result; 978 979 result = i2c_imx_isr_acked(i2c_imx); 980 if (result) 981 return result; 982 983 if (i2c_imx->msg->len == i2c_imx->msg_buf_idx) 984 return 0; 985 986 imx_i2c_write_reg(i2c_imx->msg->buf[i2c_imx->msg_buf_idx++], i2c_imx, IMX_I2C_I2DR); 987 988 return 1; 989 } 990 991 static inline int i2c_imx_isr_read(struct imx_i2c_struct *i2c_imx) 992 { 993 int result; 994 unsigned int temp; 995 996 result = i2c_imx_isr_acked(i2c_imx); 997 if (result) 998 return result; 999 1000 /* setup bus to read data */ 1001 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1002 temp &= ~I2CR_MTX; 1003 if (i2c_imx->msg->len - 1) 1004 temp &= ~I2CR_TXAK; 1005 1006 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1007 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 1008 1009 return 0; 1010 } 1011 1012 static inline void i2c_imx_isr_read_continue(struct imx_i2c_struct *i2c_imx) 1013 { 1014 unsigned int temp; 1015 1016 if ((i2c_imx->msg->len - 1) == i2c_imx->msg_buf_idx) { 1017 if (i2c_imx->is_lastmsg) { 1018 /* 1019 * It must generate STOP before read I2DR to prevent 1020 * controller from generating another clock cycle 1021 */ 1022 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1023 if (!(temp & I2CR_MSTA)) 1024 i2c_imx->stopped = 1; 1025 temp &= ~(I2CR_MSTA | I2CR_MTX); 1026 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1027 } else { 1028 /* 1029 * For i2c master receiver repeat restart operation like: 1030 * read -> repeat MSTA -> read/write 1031 * The controller must set MTX before read the last byte in 1032 * the first read operation, otherwise the first read cost 1033 * one extra clock cycle. 1034 */ 1035 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1036 temp |= I2CR_MTX; 1037 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1038 } 1039 } else if (i2c_imx->msg_buf_idx == (i2c_imx->msg->len - 2)) { 1040 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1041 temp |= I2CR_TXAK; 1042 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1043 } 1044 1045 i2c_imx->msg->buf[i2c_imx->msg_buf_idx++] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1046 } 1047 1048 static inline void i2c_imx_isr_read_block_data_len(struct imx_i2c_struct *i2c_imx) 1049 { 1050 u8 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1051 1052 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) { 1053 i2c_imx->isr_result = -EPROTO; 1054 i2c_imx->state = IMX_I2C_STATE_FAILED; 1055 wake_up(&i2c_imx->queue); 1056 } 1057 i2c_imx->msg->len += len; 1058 } 1059 1060 static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned int status) 1061 { 1062 /* 1063 * This state machine handles I2C reception and transmission in non-DMA 1064 * mode. We must process all the data in the ISR to reduce the delay 1065 * between two consecutive messages. If the data is not processed in 1066 * the ISR, SMBus devices may timeout, leading to a bus error. 1067 */ 1068 switch (i2c_imx->state) { 1069 case IMX_I2C_STATE_DMA: 1070 i2c_imx->i2csr = status; 1071 wake_up(&i2c_imx->queue); 1072 break; 1073 1074 case IMX_I2C_STATE_READ: 1075 if (i2c_imx_isr_read(i2c_imx)) 1076 break; 1077 i2c_imx->state = IMX_I2C_STATE_READ_CONTINUE; 1078 break; 1079 1080 case IMX_I2C_STATE_READ_CONTINUE: 1081 i2c_imx_isr_read_continue(i2c_imx); 1082 if (i2c_imx->msg_buf_idx == i2c_imx->msg->len) { 1083 i2c_imx->state = IMX_I2C_STATE_DONE; 1084 wake_up(&i2c_imx->queue); 1085 } 1086 break; 1087 1088 case IMX_I2C_STATE_READ_BLOCK_DATA: 1089 if (i2c_imx_isr_read(i2c_imx)) 1090 break; 1091 i2c_imx->state = IMX_I2C_STATE_READ_BLOCK_DATA_LEN; 1092 break; 1093 1094 case IMX_I2C_STATE_READ_BLOCK_DATA_LEN: 1095 i2c_imx_isr_read_block_data_len(i2c_imx); 1096 i2c_imx->state = IMX_I2C_STATE_READ_CONTINUE; 1097 break; 1098 1099 case IMX_I2C_STATE_WRITE: 1100 if (i2c_imx_isr_write(i2c_imx)) 1101 break; 1102 i2c_imx->state = IMX_I2C_STATE_DONE; 1103 wake_up(&i2c_imx->queue); 1104 break; 1105 1106 default: 1107 i2c_imx->i2csr = status; 1108 i2c_imx->state = IMX_I2C_STATE_FAILED; 1109 i2c_imx->isr_result = -EINVAL; 1110 wake_up(&i2c_imx->queue); 1111 } 1112 1113 return IRQ_HANDLED; 1114 } 1115 1116 static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 1117 { 1118 struct imx_i2c_struct *i2c_imx = dev_id; 1119 unsigned int ctl, status; 1120 unsigned long flags; 1121 1122 spin_lock_irqsave(&i2c_imx->slave_lock, flags); 1123 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1124 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1125 1126 if (status & I2SR_IIF) { 1127 i2c_imx_clear_irq(i2c_imx, I2SR_IIF); 1128 if (i2c_imx->slave) { 1129 if (!(ctl & I2CR_MSTA)) { 1130 irqreturn_t ret; 1131 1132 ret = i2c_imx_slave_handle(i2c_imx, 1133 status, ctl); 1134 spin_unlock_irqrestore(&i2c_imx->slave_lock, 1135 flags); 1136 return ret; 1137 } 1138 i2c_imx_slave_finish_op(i2c_imx); 1139 } 1140 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags); 1141 return i2c_imx_master_isr(i2c_imx, status); 1142 } 1143 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags); 1144 1145 return IRQ_NONE; 1146 } 1147 1148 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx, 1149 struct i2c_msg *msgs) 1150 { 1151 int result; 1152 unsigned long time_left; 1153 unsigned int temp = 0; 1154 unsigned long orig_jiffies = jiffies; 1155 struct imx_i2c_dma *dma = i2c_imx->dma; 1156 struct device *dev = &i2c_imx->adapter.dev; 1157 1158 i2c_imx->state = IMX_I2C_STATE_DMA; 1159 1160 dma->chan_using = dma->chan_tx; 1161 dma->dma_transfer_dir = DMA_MEM_TO_DEV; 1162 dma->dma_data_dir = DMA_TO_DEVICE; 1163 dma->dma_len = msgs->len - 1; 1164 result = i2c_imx_dma_xfer(i2c_imx, msgs); 1165 if (result) 1166 return result; 1167 1168 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1169 temp |= I2CR_DMAEN; 1170 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1171 1172 /* 1173 * Write slave address. 1174 * The first byte must be transmitted by the CPU. 1175 */ 1176 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1177 time_left = wait_for_completion_timeout( 1178 &i2c_imx->dma->cmd_complete, 1179 msecs_to_jiffies(DMA_TIMEOUT)); 1180 if (time_left == 0) { 1181 dmaengine_terminate_sync(dma->chan_using); 1182 return -ETIMEDOUT; 1183 } 1184 1185 /* Waiting for transfer complete. */ 1186 while (1) { 1187 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1188 if (temp & I2SR_ICF) 1189 break; 1190 if (time_after(jiffies, orig_jiffies + 1191 msecs_to_jiffies(DMA_TIMEOUT))) { 1192 dev_dbg(dev, "<%s> Timeout\n", __func__); 1193 return -ETIMEDOUT; 1194 } 1195 schedule(); 1196 } 1197 1198 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1199 temp &= ~I2CR_DMAEN; 1200 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1201 1202 /* The last data byte must be transferred by the CPU. */ 1203 imx_i2c_write_reg(msgs->buf[msgs->len-1], 1204 i2c_imx, IMX_I2C_I2DR); 1205 result = i2c_imx_trx_complete(i2c_imx, false); 1206 if (result) 1207 return result; 1208 1209 return i2c_imx_acked(i2c_imx); 1210 } 1211 1212 static int i2c_imx_prepare_read(struct imx_i2c_struct *i2c_imx, 1213 struct i2c_msg *msgs, bool use_dma) 1214 { 1215 int result; 1216 unsigned int temp = 0; 1217 1218 /* write slave address */ 1219 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1220 result = i2c_imx_trx_complete(i2c_imx, !use_dma); 1221 if (result) 1222 return result; 1223 result = i2c_imx_acked(i2c_imx); 1224 if (result) 1225 return result; 1226 1227 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); 1228 1229 /* setup bus to read data */ 1230 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1231 temp &= ~I2CR_MTX; 1232 1233 /* 1234 * Reset the I2CR_TXAK flag initially for SMBus block read since the 1235 * length is unknown 1236 */ 1237 if (msgs->len - 1) 1238 temp &= ~I2CR_TXAK; 1239 if (use_dma) 1240 temp |= I2CR_DMAEN; 1241 1242 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1243 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 1244 1245 return 0; 1246 } 1247 1248 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx, 1249 struct i2c_msg *msgs, bool is_lastmsg) 1250 { 1251 int result; 1252 unsigned long time_left; 1253 unsigned int temp; 1254 unsigned long orig_jiffies = jiffies; 1255 struct imx_i2c_dma *dma = i2c_imx->dma; 1256 struct device *dev = &i2c_imx->adapter.dev; 1257 1258 i2c_imx->state = IMX_I2C_STATE_DMA; 1259 1260 result = i2c_imx_prepare_read(i2c_imx, msgs, true); 1261 if (result) 1262 return result; 1263 1264 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 1265 1266 dma->chan_using = dma->chan_rx; 1267 dma->dma_transfer_dir = DMA_DEV_TO_MEM; 1268 dma->dma_data_dir = DMA_FROM_DEVICE; 1269 /* The last two data bytes must be transferred by the CPU. */ 1270 dma->dma_len = msgs->len - 2; 1271 result = i2c_imx_dma_xfer(i2c_imx, msgs); 1272 if (result) 1273 return result; 1274 1275 time_left = wait_for_completion_timeout( 1276 &i2c_imx->dma->cmd_complete, 1277 msecs_to_jiffies(DMA_TIMEOUT)); 1278 if (time_left == 0) { 1279 dmaengine_terminate_sync(dma->chan_using); 1280 return -ETIMEDOUT; 1281 } 1282 1283 /* waiting for transfer complete. */ 1284 while (1) { 1285 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1286 if (temp & I2SR_ICF) 1287 break; 1288 if (time_after(jiffies, orig_jiffies + 1289 msecs_to_jiffies(DMA_TIMEOUT))) { 1290 dev_dbg(dev, "<%s> Timeout\n", __func__); 1291 return -ETIMEDOUT; 1292 } 1293 schedule(); 1294 } 1295 1296 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1297 temp &= ~I2CR_DMAEN; 1298 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1299 1300 /* read n-1 byte data */ 1301 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1302 temp |= I2CR_TXAK; 1303 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1304 1305 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1306 /* read n byte data */ 1307 result = i2c_imx_trx_complete(i2c_imx, false); 1308 if (result) 1309 return result; 1310 1311 if (is_lastmsg) { 1312 /* 1313 * It must generate STOP before read I2DR to prevent 1314 * controller from generating another clock cycle 1315 */ 1316 dev_dbg(dev, "<%s> clear MSTA\n", __func__); 1317 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1318 if (!(temp & I2CR_MSTA)) 1319 i2c_imx->stopped = 1; 1320 temp &= ~(I2CR_MSTA | I2CR_MTX); 1321 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1322 if (!i2c_imx->stopped) 1323 i2c_imx_bus_busy(i2c_imx, 0, false); 1324 } else { 1325 /* 1326 * For i2c master receiver repeat restart operation like: 1327 * read -> repeat MSTA -> read/write 1328 * The controller must set MTX before read the last byte in 1329 * the first read operation, otherwise the first read cost 1330 * one extra clock cycle. 1331 */ 1332 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1333 temp |= I2CR_MTX; 1334 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1335 } 1336 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1337 1338 return 0; 1339 } 1340 1341 static int i2c_imx_atomic_write(struct imx_i2c_struct *i2c_imx, 1342 struct i2c_msg *msgs) 1343 { 1344 int i, result; 1345 1346 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 1347 __func__, i2c_8bit_addr_from_msg(msgs)); 1348 1349 /* write slave address */ 1350 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1351 result = i2c_imx_trx_complete(i2c_imx, true); 1352 if (result) 1353 return result; 1354 result = i2c_imx_acked(i2c_imx); 1355 if (result) 1356 return result; 1357 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); 1358 1359 /* write data */ 1360 for (i = 0; i < msgs->len; i++) { 1361 dev_dbg(&i2c_imx->adapter.dev, 1362 "<%s> write byte: B%d=0x%X\n", 1363 __func__, i, msgs->buf[i]); 1364 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); 1365 result = i2c_imx_trx_complete(i2c_imx, true); 1366 if (result) 1367 return result; 1368 result = i2c_imx_acked(i2c_imx); 1369 if (result) 1370 return result; 1371 } 1372 return 0; 1373 } 1374 1375 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) 1376 { 1377 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 1378 __func__, i2c_8bit_addr_from_msg(msgs)); 1379 1380 i2c_imx->state = IMX_I2C_STATE_WRITE; 1381 i2c_imx->msg = msgs; 1382 i2c_imx->msg_buf_idx = 0; 1383 1384 /* 1385 * By writing the device address we start the state machine in the ISR. 1386 * The ISR will report when it is done or when it fails. 1387 */ 1388 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1389 wait_event_timeout(i2c_imx->queue, 1390 i2c_imx->state == IMX_I2C_STATE_DONE || 1391 i2c_imx->state == IMX_I2C_STATE_FAILED, 1392 (msgs->len + 1) * HZ / 10); 1393 if (i2c_imx->state == IMX_I2C_STATE_FAILED) { 1394 dev_dbg(&i2c_imx->adapter.dev, "<%s> write failed with %d\n", 1395 __func__, i2c_imx->isr_result); 1396 return i2c_imx->isr_result; 1397 } 1398 if (i2c_imx->state != IMX_I2C_STATE_DONE) { 1399 dev_err(&i2c_imx->adapter.dev, "<%s> write timedout\n", __func__); 1400 return -ETIMEDOUT; 1401 } 1402 return 0; 1403 } 1404 1405 static int i2c_imx_atomic_read(struct imx_i2c_struct *i2c_imx, 1406 struct i2c_msg *msgs, bool is_lastmsg) 1407 { 1408 int i, result; 1409 unsigned int temp; 1410 int block_data = msgs->flags & I2C_M_RECV_LEN; 1411 1412 result = i2c_imx_prepare_read(i2c_imx, msgs, false); 1413 if (result) 1414 return result; 1415 1416 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 1417 1418 /* read data */ 1419 for (i = 0; i < msgs->len; i++) { 1420 u8 len = 0; 1421 1422 result = i2c_imx_trx_complete(i2c_imx, true); 1423 if (result) 1424 return result; 1425 /* 1426 * First byte is the length of remaining packet 1427 * in the SMBus block data read. Add it to 1428 * msgs->len. 1429 */ 1430 if ((!i) && block_data) { 1431 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1432 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) 1433 return -EPROTO; 1434 dev_dbg(&i2c_imx->adapter.dev, 1435 "<%s> read length: 0x%X\n", 1436 __func__, len); 1437 msgs->len += len; 1438 } 1439 if (i == (msgs->len - 1)) { 1440 if (is_lastmsg) { 1441 /* 1442 * It must generate STOP before read I2DR to prevent 1443 * controller from generating another clock cycle 1444 */ 1445 dev_dbg(&i2c_imx->adapter.dev, 1446 "<%s> clear MSTA\n", __func__); 1447 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1448 if (!(temp & I2CR_MSTA)) 1449 i2c_imx->stopped = 1; 1450 temp &= ~(I2CR_MSTA | I2CR_MTX); 1451 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1452 if (!i2c_imx->stopped) 1453 i2c_imx_bus_busy(i2c_imx, 0, true); 1454 } else { 1455 /* 1456 * For i2c master receiver repeat restart operation like: 1457 * read -> repeat MSTA -> read/write 1458 * The controller must set MTX before read the last byte in 1459 * the first read operation, otherwise the first read cost 1460 * one extra clock cycle. 1461 */ 1462 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1463 temp |= I2CR_MTX; 1464 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1465 } 1466 } else if (i == (msgs->len - 2)) { 1467 dev_dbg(&i2c_imx->adapter.dev, 1468 "<%s> set TXAK\n", __func__); 1469 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1470 temp |= I2CR_TXAK; 1471 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1472 } 1473 if ((!i) && block_data) 1474 msgs->buf[0] = len; 1475 else 1476 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 1477 dev_dbg(&i2c_imx->adapter.dev, 1478 "<%s> read byte: B%d=0x%X\n", 1479 __func__, i, msgs->buf[i]); 1480 } 1481 return 0; 1482 } 1483 1484 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, 1485 bool is_lastmsg) 1486 { 1487 int block_data = msgs->flags & I2C_M_RECV_LEN; 1488 1489 dev_dbg(&i2c_imx->adapter.dev, 1490 "<%s> write slave address: addr=0x%x\n", 1491 __func__, i2c_8bit_addr_from_msg(msgs)); 1492 1493 i2c_imx->is_lastmsg = is_lastmsg; 1494 1495 if (block_data) 1496 i2c_imx->state = IMX_I2C_STATE_READ_BLOCK_DATA; 1497 else 1498 i2c_imx->state = IMX_I2C_STATE_READ; 1499 i2c_imx->msg = msgs; 1500 i2c_imx->msg_buf_idx = 0; 1501 1502 /* 1503 * By writing the device address we start the state machine in the ISR. 1504 * The ISR will report when it is done or when it fails. 1505 */ 1506 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 1507 wait_event_timeout(i2c_imx->queue, 1508 i2c_imx->state == IMX_I2C_STATE_DONE || 1509 i2c_imx->state == IMX_I2C_STATE_FAILED, 1510 (msgs->len + 1) * HZ / 10); 1511 if (i2c_imx->state == IMX_I2C_STATE_FAILED) { 1512 dev_dbg(&i2c_imx->adapter.dev, "<%s> read failed with %d\n", 1513 __func__, i2c_imx->isr_result); 1514 return i2c_imx->isr_result; 1515 } 1516 if (i2c_imx->state != IMX_I2C_STATE_DONE) { 1517 dev_err(&i2c_imx->adapter.dev, "<%s> read timedout\n", __func__); 1518 return -ETIMEDOUT; 1519 } 1520 if (!i2c_imx->stopped) 1521 return i2c_imx_bus_busy(i2c_imx, 0, false); 1522 1523 return 0; 1524 } 1525 1526 static int i2c_imx_xfer_common(struct i2c_adapter *adapter, 1527 struct i2c_msg *msgs, int num, bool atomic) 1528 { 1529 unsigned int i, temp; 1530 int result; 1531 bool is_lastmsg = false; 1532 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1533 int use_dma = 0; 1534 1535 /* Start I2C transfer */ 1536 result = i2c_imx_start(i2c_imx, atomic); 1537 if (result) { 1538 /* 1539 * Bus recovery uses gpiod_get_value_cansleep() which is not 1540 * allowed within atomic context. 1541 */ 1542 if (!atomic && i2c_imx->adapter.bus_recovery_info) { 1543 i2c_recover_bus(&i2c_imx->adapter); 1544 result = i2c_imx_start(i2c_imx, atomic); 1545 } 1546 } 1547 1548 if (result) 1549 goto fail0; 1550 1551 /* read/write data */ 1552 for (i = 0; i < num; i++) { 1553 if (i == num - 1) 1554 is_lastmsg = true; 1555 1556 if (i) { 1557 dev_dbg(&i2c_imx->adapter.dev, 1558 "<%s> repeated start\n", __func__); 1559 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1560 temp |= I2CR_RSTA; 1561 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 1562 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 1563 if (result) 1564 goto fail0; 1565 } 1566 dev_dbg(&i2c_imx->adapter.dev, 1567 "<%s> transfer message: %d\n", __func__, i); 1568 /* write/read data */ 1569 #ifdef CONFIG_I2C_DEBUG_BUS 1570 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 1571 dev_dbg(&i2c_imx->adapter.dev, 1572 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", 1573 __func__, 1574 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), 1575 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), 1576 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); 1577 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1578 dev_dbg(&i2c_imx->adapter.dev, 1579 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", 1580 __func__, 1581 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), 1582 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), 1583 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), 1584 (temp & I2SR_RXAK ? 1 : 0)); 1585 #endif 1586 1587 use_dma = i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD && 1588 msgs[i].flags & I2C_M_DMA_SAFE; 1589 if (msgs[i].flags & I2C_M_RD) { 1590 int block_data = msgs->flags & I2C_M_RECV_LEN; 1591 1592 if (atomic) 1593 result = i2c_imx_atomic_read(i2c_imx, &msgs[i], is_lastmsg); 1594 else if (use_dma && !block_data) 1595 result = i2c_imx_dma_read(i2c_imx, &msgs[i], is_lastmsg); 1596 else 1597 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg); 1598 } else { 1599 if (atomic) 1600 result = i2c_imx_atomic_write(i2c_imx, &msgs[i]); 1601 else if (use_dma) 1602 result = i2c_imx_dma_write(i2c_imx, &msgs[i]); 1603 else 1604 result = i2c_imx_write(i2c_imx, &msgs[i]); 1605 } 1606 if (result) 1607 goto fail0; 1608 } 1609 1610 fail0: 1611 /* Stop I2C transfer */ 1612 i2c_imx_stop(i2c_imx, atomic); 1613 1614 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 1615 (result < 0) ? "error" : "success msg", 1616 (result < 0) ? result : num); 1617 /* After data is transferred, switch to slave mode(as a receiver) */ 1618 if (i2c_imx->slave) 1619 i2c_imx_slave_init(i2c_imx); 1620 1621 return (result < 0) ? result : num; 1622 } 1623 1624 static int i2c_imx_xfer(struct i2c_adapter *adapter, 1625 struct i2c_msg *msgs, int num) 1626 { 1627 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1628 int result; 1629 1630 result = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent); 1631 if (result < 0) 1632 return result; 1633 1634 result = i2c_imx_xfer_common(adapter, msgs, num, false); 1635 1636 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent); 1637 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent); 1638 1639 return result; 1640 } 1641 1642 static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter, 1643 struct i2c_msg *msgs, int num) 1644 { 1645 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1646 int result; 1647 1648 result = clk_enable(i2c_imx->clk); 1649 if (result) 1650 return result; 1651 1652 result = i2c_imx_xfer_common(adapter, msgs, num, true); 1653 1654 clk_disable(i2c_imx->clk); 1655 1656 return result; 1657 } 1658 1659 /* 1660 * We switch SCL and SDA to their GPIO function and do some bitbanging 1661 * for bus recovery. These alternative pinmux settings can be 1662 * described in the device tree by a separate pinctrl state "gpio". If 1663 * this is missing this is not a big problem, the only implication is 1664 * that we can't do bus recovery. 1665 */ 1666 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx, 1667 struct platform_device *pdev) 1668 { 1669 struct i2c_bus_recovery_info *bri = &i2c_imx->rinfo; 1670 1671 bri->pinctrl = devm_pinctrl_get(&pdev->dev); 1672 if (IS_ERR(bri->pinctrl)) 1673 return PTR_ERR(bri->pinctrl); 1674 1675 i2c_imx->adapter.bus_recovery_info = bri; 1676 1677 return 0; 1678 } 1679 1680 static u32 i2c_imx_func(struct i2c_adapter *adapter) 1681 { 1682 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 1683 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1684 } 1685 1686 static const struct i2c_algorithm i2c_imx_algo = { 1687 .master_xfer = i2c_imx_xfer, 1688 .master_xfer_atomic = i2c_imx_xfer_atomic, 1689 .functionality = i2c_imx_func, 1690 .reg_slave = i2c_imx_reg_slave, 1691 .unreg_slave = i2c_imx_unreg_slave, 1692 }; 1693 1694 static int i2c_imx_probe(struct platform_device *pdev) 1695 { 1696 struct imx_i2c_struct *i2c_imx; 1697 struct resource *res; 1698 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev); 1699 void __iomem *base; 1700 int irq, ret; 1701 dma_addr_t phy_addr; 1702 const struct imx_i2c_hwdata *match; 1703 1704 irq = platform_get_irq(pdev, 0); 1705 if (irq < 0) 1706 return irq; 1707 1708 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1709 if (IS_ERR(base)) 1710 return PTR_ERR(base); 1711 1712 phy_addr = (dma_addr_t)res->start; 1713 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL); 1714 if (!i2c_imx) 1715 return -ENOMEM; 1716 1717 spin_lock_init(&i2c_imx->slave_lock); 1718 hrtimer_init(&i2c_imx->slave_timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); 1719 i2c_imx->slave_timer.function = i2c_imx_slave_timeout; 1720 1721 match = device_get_match_data(&pdev->dev); 1722 if (match) 1723 i2c_imx->hwdata = match; 1724 else 1725 i2c_imx->hwdata = (struct imx_i2c_hwdata *) 1726 platform_get_device_id(pdev)->driver_data; 1727 1728 /* Setup i2c_imx driver structure */ 1729 strscpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); 1730 i2c_imx->adapter.owner = THIS_MODULE; 1731 i2c_imx->adapter.algo = &i2c_imx_algo; 1732 i2c_imx->adapter.dev.parent = &pdev->dev; 1733 i2c_imx->adapter.nr = pdev->id; 1734 i2c_imx->adapter.dev.of_node = pdev->dev.of_node; 1735 i2c_imx->base = base; 1736 ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev)); 1737 1738 /* Get I2C clock */ 1739 i2c_imx->clk = devm_clk_get_enabled(&pdev->dev, NULL); 1740 if (IS_ERR(i2c_imx->clk)) 1741 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_imx->clk), 1742 "can't get I2C clock\n"); 1743 1744 /* Init queue */ 1745 init_waitqueue_head(&i2c_imx->queue); 1746 1747 /* Set up adapter data */ 1748 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); 1749 1750 /* Set up platform driver data */ 1751 platform_set_drvdata(pdev, i2c_imx); 1752 1753 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT); 1754 pm_runtime_use_autosuspend(&pdev->dev); 1755 pm_runtime_set_active(&pdev->dev); 1756 pm_runtime_enable(&pdev->dev); 1757 1758 ret = pm_runtime_get_sync(&pdev->dev); 1759 if (ret < 0) 1760 goto rpm_disable; 1761 1762 /* Request IRQ */ 1763 ret = request_irq(irq, i2c_imx_isr, IRQF_SHARED, pdev->name, i2c_imx); 1764 if (ret) { 1765 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 1766 goto rpm_disable; 1767 } 1768 1769 /* 1770 * We use the single-master property for backward compatibility. 1771 * By default multi master mode is enabled. 1772 */ 1773 i2c_imx->multi_master = !of_property_read_bool(pdev->dev.of_node, "single-master"); 1774 1775 /* Set up clock divider */ 1776 i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ; 1777 ret = of_property_read_u32(pdev->dev.of_node, 1778 "clock-frequency", &i2c_imx->bitrate); 1779 if (ret < 0 && pdata && pdata->bitrate) 1780 i2c_imx->bitrate = pdata->bitrate; 1781 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call; 1782 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb); 1783 i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk)); 1784 1785 i2c_imx_reset_regs(i2c_imx); 1786 1787 /* Init optional bus recovery function */ 1788 ret = i2c_imx_init_recovery_info(i2c_imx, pdev); 1789 /* Give it another chance if pinctrl used is not ready yet */ 1790 if (ret == -EPROBE_DEFER) 1791 goto clk_notifier_unregister; 1792 1793 /* Add I2C adapter */ 1794 ret = i2c_add_numbered_adapter(&i2c_imx->adapter); 1795 if (ret < 0) 1796 goto clk_notifier_unregister; 1797 1798 pm_runtime_mark_last_busy(&pdev->dev); 1799 pm_runtime_put_autosuspend(&pdev->dev); 1800 1801 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq); 1802 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res); 1803 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 1804 i2c_imx->adapter.name); 1805 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 1806 1807 /* Init DMA config if supported */ 1808 i2c_imx_dma_request(i2c_imx, phy_addr); 1809 1810 return 0; /* Return OK */ 1811 1812 clk_notifier_unregister: 1813 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1814 free_irq(irq, i2c_imx); 1815 rpm_disable: 1816 pm_runtime_put_noidle(&pdev->dev); 1817 pm_runtime_disable(&pdev->dev); 1818 pm_runtime_set_suspended(&pdev->dev); 1819 pm_runtime_dont_use_autosuspend(&pdev->dev); 1820 return ret; 1821 } 1822 1823 static void i2c_imx_remove(struct platform_device *pdev) 1824 { 1825 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 1826 int irq, ret; 1827 1828 ret = pm_runtime_get_sync(&pdev->dev); 1829 1830 hrtimer_cancel(&i2c_imx->slave_timer); 1831 1832 /* remove adapter */ 1833 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 1834 i2c_del_adapter(&i2c_imx->adapter); 1835 1836 if (i2c_imx->dma) 1837 i2c_imx_dma_free(i2c_imx); 1838 1839 if (ret >= 0) { 1840 /* setup chip registers to defaults */ 1841 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 1842 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); 1843 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); 1844 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); 1845 } 1846 1847 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1848 irq = platform_get_irq(pdev, 0); 1849 if (irq >= 0) 1850 free_irq(irq, i2c_imx); 1851 1852 pm_runtime_put_noidle(&pdev->dev); 1853 pm_runtime_disable(&pdev->dev); 1854 } 1855 1856 static int i2c_imx_runtime_suspend(struct device *dev) 1857 { 1858 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1859 1860 clk_disable(i2c_imx->clk); 1861 1862 return 0; 1863 } 1864 1865 static int i2c_imx_runtime_resume(struct device *dev) 1866 { 1867 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1868 int ret; 1869 1870 ret = clk_enable(i2c_imx->clk); 1871 if (ret) 1872 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret); 1873 1874 return ret; 1875 } 1876 1877 static const struct dev_pm_ops i2c_imx_pm_ops = { 1878 RUNTIME_PM_OPS(i2c_imx_runtime_suspend, i2c_imx_runtime_resume, NULL) 1879 }; 1880 1881 static struct platform_driver i2c_imx_driver = { 1882 .probe = i2c_imx_probe, 1883 .remove = i2c_imx_remove, 1884 .driver = { 1885 .name = DRIVER_NAME, 1886 .pm = pm_ptr(&i2c_imx_pm_ops), 1887 .of_match_table = i2c_imx_dt_ids, 1888 .acpi_match_table = i2c_imx_acpi_ids, 1889 }, 1890 .id_table = imx_i2c_devtype, 1891 }; 1892 1893 static int __init i2c_adap_imx_init(void) 1894 { 1895 return platform_driver_register(&i2c_imx_driver); 1896 } 1897 subsys_initcall(i2c_adap_imx_init); 1898 1899 static void __exit i2c_adap_imx_exit(void) 1900 { 1901 platform_driver_unregister(&i2c_imx_driver); 1902 } 1903 module_exit(i2c_adap_imx_exit); 1904 1905 MODULE_LICENSE("GPL"); 1906 MODULE_AUTHOR("Darius Augulis"); 1907 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); 1908 MODULE_ALIAS("platform:" DRIVER_NAME); 1909